[llvm-branch-commits] [compiler-rt] 6b358fb - [win/asan] GetInstructionSize: Add some more instructions. (#214707)
Tobias Hieta via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Sep 5 00:12:23 PDT 2026
Author: bernhardu
Date: 2026-09-05T09:11:52+02:00
New Revision: 6b358fb914eefe2193c708dd6eebb17c25443f9e
URL: https://github.com/llvm/llvm-project/commit/6b358fb914eefe2193c708dd6eebb17c25443f9e
DIFF: https://github.com/llvm/llvm-project/commit/6b358fb914eefe2193c708dd6eebb17c25443f9e.diff
LOG: [win/asan] GetInstructionSize: Add some more instructions. (#214707)
Below instructions can be found in wine-11.14 Debian packages.
```
8D 45 XX : lea eax, [ebp + XX]
66 0f ef c0 : pxor xmm0, xmm0
41 B9 XX XX XX XX : mov r9d, XX XX XX XX
45 84 c9 : test r9b,r9b
```
This patch also adds `80 3A XX` to tests (followup of 3ca5b7dc4f) and
fixes the sorting of test lists.
```
==484==interception_win: unhandled instruction at 0x7bcb2264: 8d 45 f8 83 ec 18 8b 5d
ntdll.dll`RtlExitUserThread:
0x7bcb2264 <+4>: 8d 45 f8 lea eax, [ebp - 0x8]
==484==interception_win: unhandled instruction at 0x7a5f2fe1: 66 0f ef c0 89 e5 53 83
ucrtbase.dll`memset:
0x7a5f2fe1 <+1>: 66 0f ef c0 pxor xmm0, xmm0
==760==interception_win: unhandled instruction at 0x6fffffbe6b25: 41 b9 04 00 00 00 ba 0c
ntdll.dll`RtlExitUserThread:
0x6fffffbe6b25 <+5>: 41 b9 04 00 00 00 movl $0x4, %r9d
==760==interception_win: unhandled instruction at 0x6fffffc342a4: 45 84 c9 74 45 0f 1f 80
ntdll.dll`strpbrk:
0x6fffffc342a4 <+4>: 45 84 c9 testb %r9b, %r9b
```
(cherry picked from commit 5af1c55f938ff025718129f64e8e41136496ff05)
Added:
Modified:
compiler-rt/lib/interception/interception_win.cpp
compiler-rt/lib/interception/tests/interception_win_test.cpp
Removed:
################################################################################
diff --git a/compiler-rt/lib/interception/interception_win.cpp b/compiler-rt/lib/interception/interception_win.cpp
index 19bccb3566d72..86a622ed48b50 100644
--- a/compiler-rt/lib/interception/interception_win.cpp
+++ b/compiler-rt/lib/interception/interception_win.cpp
@@ -685,6 +685,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0x758B: // 8B 75 XX : mov XX(%ebp), esp
case 0xE483: // 83 E4 XX : and esp, XX
case 0xEC83: // 83 EC XX : sub esp, XX
+ case 0x458D: // 8D 45 XX : lea eax, [ebp + XX]
case 0xC1F6: // F6 C1 XX : test cl, XX
return 3;
@@ -705,6 +706,11 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
return 7;
}
+ switch (*(u32*)(address)) {
+ case 0xc0ef0f66: // 66 0f ef c0 : pxor xmm0, xmm0
+ return 4;
+ }
+
switch (0x000000FF & *(u32 *)address) {
case 0xc2: // C2 XX XX : ret XX (needed for registering weak functions)
return 3;
@@ -771,6 +777,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
*rel_offset = 2;
FALLTHROUGH;
case 0xB841: // 41 B8 XX XX XX XX : mov r8d, XX XX XX XX
+ case 0xB941: // 41 B9 XX XX XX XX : mov r9d, XX XX XX XX
return 6;
case 0x7E81: // 81 7E YY XX XX XX XX cmp DWORD PTR [rsi+YY], XX XX XX XX
@@ -844,6 +851,7 @@ static size_t GetInstructionSize(uptr address, size_t* rel_offset = nullptr) {
case 0xd23345: // 45 33 d2 : xor r10d, r10d
case 0xdb3345: // 45 33 db : xor r11d, r11d
case 0xc08445: // 45 84 c0 : test r8b,r8b
+ case 0xc98445: // 45 84 c9 : test r9b,r9b
case 0xd28445: // 45 84 d2 : test r10b,r10b
case 0xdb8548: // 48 85 db : test rbx, rbx
case 0xdb854d: // 4d 85 db : test r11, r11
diff --git a/compiler-rt/lib/interception/tests/interception_win_test.cpp b/compiler-rt/lib/interception/tests/interception_win_test.cpp
index e3dc4cfbe9b2c..054d5405971dd 100644
--- a/compiler-rt/lib/interception/tests/interception_win_test.cpp
+++ b/compiler-rt/lib/interception/tests/interception_win_test.cpp
@@ -841,11 +841,11 @@ const struct InstructionSizeData {
{ 1, {0xCC}, 0, "CC : int 3 i.e. registering weak functions)"},
{ 2, {0x31, 0xC0}, 0, "31 C0 : xor eax, eax"},
{ 2, {0x31, 0xC9}, 0, "31 C9 : xor ecx, ecx"},
- { 2, {0x33, 0xFF}, 0, "33 FF : xor edi, edi"},
{ 2, {0x31, 0xD2}, 0, "31 D2 : xor edx, edx"},
{ 2, {0x33, 0xC0}, 0, "33 C0 : xor eax, eax"},
{ 2, {0x33, 0xC9}, 0, "33 C9 : xor ecx, ecx"},
{ 2, {0x33, 0xD2}, 0, "33 D2 : xor edx, edx"},
+ { 2, {0x33, 0xFF}, 0, "33 FF : xor edi, edi"},
{ 2, {0x66, 0x90}, 0, "66 90 : xchg %ax,%ax (Two-byte NOP)"},
{ 2, {0x6A, 0x71}, 0, "6A XX : push XX"},
{ 2, {0x84, 0xC0}, 0, "84 C0 : test al,al"},
@@ -860,12 +860,15 @@ const struct InstructionSizeData {
{ 2, {0x8B, 0xEC}, 0, "8B EC : mov ebp, esp"},
{ 2, {0x8B, 0xFF}, 0, "8B FF : mov edi, edi"},
{ 3, {0x80, 0x39, 0x72}, 0, "80 39 XX : cmp BYTE PTR [rcx], XX"},
+ { 3, {0x80, 0x3A, 0x72}, 0, "80 3A XX : cmp BYTE PTR [rdx], XX"},
{ 3, {0x83, 0xE4, 0x72}, 0, "83 E4 XX : and esp, XX"},
{ 3, {0x83, 0xEC, 0x72}, 0, "83 EC XX : sub esp, XX"},
{ 3, {0x8B, 0x4D, 0x72}, 0, "8B 4D XX : mov XX(%ebp), ecx"},
{ 3, {0x8B, 0x55, 0x72}, 0, "8B 55 XX : mov XX(%ebp), edx"},
{ 3, {0x8B, 0x75, 0x72}, 0, "8B 75 XX : mov XX(%ebp), esp"},
+ { 3, {0x8D, 0x45, 0x72}, 0, "8D 45 XX : lea eax, [ebp + XX]"},
{ 3, {0xc2, 0x71, 0x72}, 0, "C2 XX XX : ret XX (needed for registering weak functions)"},
+ { 4, {0x66, 0x0f, 0xef, 0xc0}, 0, "66 0f ef c0 : pxor xmm0, xmm0"},
{ 4, {0x8D, 0x4C, 0x24, 0x73}, 0, "8D 4C 24 XX : lea ecx, [esp + XX]"},
{ 4, {0xFF, 0x74, 0x24, 0x73}, 0, "FF 74 24 XX : push qword ptr [rsp + XX]"},
{ 5, {0x68, 0x71, 0x72, 0x73, 0x74}, 0, "68 XX XX XX XX : push imm32"},
@@ -911,6 +914,7 @@ const struct InstructionSizeData {
{ 3, {0x45, 0x33, 0xd2}, 0, "45 33 d2 : xor r10d, r10d"},
{ 3, {0x45, 0x33, 0xdb}, 0, "45 33 db : xor r11d, r11d"},
{ 3, {0x45, 0x84, 0xc0}, 0, "45 84 c0 : test r8b,r8b"},
+ { 3, {0x45, 0x84, 0xc9}, 0, "45 84 c9 : test r9b,r9b"},
{ 3, {0x45, 0x84, 0xd2}, 0, "45 84 d2 : test r10b,r10b"},
{ 3, {0x48, 0x29, 0xd1}, 0, "48 29 d1 : sub rcx, rdx"},
{ 3, {0x48, 0x2b, 0xca}, 0, "48 2b ca : sub rcx, rdx"},
@@ -1007,6 +1011,7 @@ const struct InstructionSizeData {
{ 5, {0x83, 0x44, 0x72, 0x73, 0x74}, 0, "83 44 72 XX YY : add DWORD PTR [rdx+rsi*2+XX],YY"},
{ 5, {0x83, 0x64, 0x24, 0x73, 0x74}, 0, "83 64 24 XX YY : and DWORD PTR [rsp+XX], YY"},
{ 6, {0x41, 0xB8, 0x72, 0x73, 0x74, 0x75}, 0, "41 B8 XX XX XX XX : mov r8d, XX XX XX XX"},
+ { 6, {0x41, 0xB9, 0x72, 0x73, 0x74, 0x75}, 0, "41 B9 XX XX XX XX : mov r9d, XX XX XX XX"},
{ 6, {0x48, 0x83, 0x64, 0x24, 0x74, 0x75}, 0, "48 83 64 24 XX YY : and QWORD PTR [rsp + XX], YY"},
{ 6, {0x66, 0x81, 0x78, 0x73, 0x74, 0x75}, 0, "66 81 78 XX YY YY : cmp WORD PTR [rax+XX], YY YY"},
{ 6, {0x66, 0x81, 0x79, 0x73, 0x74, 0x75}, 0, "66 81 79 XX YY YY : cmp WORD PTR [rcx+XX], YY YY"},
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