[llvm-branch-commits] [llvm] b01d7c4 - [RISCV] Add patterns to select vmerge.vxm/vim for bf16 and f16 vectors. (#219640)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 1 14:54:30 PDT 2026
Author: Craig Topper
Date: 2026-08-31T13:12:44-07:00
New Revision: b01d7c4c3b2af0cf306d67a5cec147302e58becf
URL: https://github.com/llvm/llvm-project/commit/b01d7c4c3b2af0cf306d67a5cec147302e58becf
DIFF: https://github.com/llvm/llvm-project/commit/b01d7c4c3b2af0cf306d67a5cec147302e58becf.diff
LOG: [RISCV] Add patterns to select vmerge.vxm/vim for bf16 and f16 vectors. (#219640)
With zvfhmin/zvfbfmin, vfmv.v.f isn't supported so we can end up with a
bitcast from vmv.v.x.
Assisted-by: Claude
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
llvm/test/CodeGen/RISCV/rvv/select-bf16.ll
llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll
llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 3c8ab6bad5452..8b1c9ac98ec16 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1534,6 +1534,30 @@ foreach fvti = AllFloatAndBF16Vectors in {
(fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
}
+// Match vselect with a splat that is a bitcast integer splat of the
+// floating-point type (e.g. when the scalar type doesn't have native
+// FP splat support, such as f16 or bf16).
+foreach fvti = !listconcat(AllFP16Vectors, AllBF16Vectors) in {
+ defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ let Predicates = GetVTypePredicates<ivti>.Predicates in {
+ def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
+ (fvti.Vector (bitconvert
+ (ivti.Vector (SplatPat XLenVT:$rs1)))),
+ fvti.RegClass:$rs2)),
+ (!cast<Instruction>("PseudoVMERGE_VXM_"#fvti.LMul.MX)
+ (fvti.Vector (IMPLICIT_DEF)),
+ fvti.RegClass:$rs2, GPR:$rs1, (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
+
+ def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm),
+ (fvti.Vector (bitconvert
+ (ivti.Vector (SplatPat_simm5 simm5:$rs1)))),
+ fvti.RegClass:$rs2)),
+ (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
+ (fvti.Vector (IMPLICIT_DEF)),
+ fvti.RegClass:$rs2, simm5:$rs1, (fvti.Mask VMV0:$vm), fvti.AVL, fvti.Log2SEW)>;
+ }
+}
+
// 13.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm : VPatConvertFP2ISDNode_V<any_fp_to_sint, "PseudoVFCVT_RTZ_X_F_V">;
defm : VPatConvertFP2ISDNode_V<any_fp_to_uint, "PseudoVFCVT_RTZ_XU_F_V">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 19ec518e3ace3..60461026da761 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2665,6 +2665,34 @@ foreach fvti = AllFloatAndBF16Vectors in {
}
}
+// Match vmerge with a splat that is a bitcast integer splat of the
+// floating-point type (e.g. when the scalar type doesn't have native
+// FP splat support, such as f16 or bf16).
+foreach fvti = !listconcat(AllFP16Vectors, AllBF16Vectors) in {
+ defvar ivti = GetIntVTypeInfo<fvti>.Vti;
+ let Predicates = GetVTypePredicates<ivti>.Predicates in {
+ def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
+ (fvti.Vector (bitconvert
+ (ivti.Vector (SplatPat XLenVT:$rs1)))),
+ fvti.RegClass:$rs2,
+ fvti.RegClass:$passthru,
+ VLOpFrag)),
+ (!cast<Instruction>("PseudoVMERGE_VXM_"#fvti.LMul.MX)
+ fvti.RegClass:$passthru, fvti.RegClass:$rs2, GPR:$rs1, (fvti.Mask VMV0:$vm),
+ GPR:$vl, fvti.Log2SEW)>;
+
+ def : Pat<(fvti.Vector (riscv_vmerge_vl (fvti.Mask VMV0:$vm),
+ (fvti.Vector (bitconvert
+ (ivti.Vector (SplatPat_simm5 simm5:$rs1)))),
+ fvti.RegClass:$rs2,
+ fvti.RegClass:$passthru,
+ VLOpFrag)),
+ (!cast<Instruction>("PseudoVMERGE_VIM_"#fvti.LMul.MX)
+ fvti.RegClass:$passthru, fvti.RegClass:$rs2, simm5:$rs1, (fvti.Mask VMV0:$vm),
+ GPR:$vl, fvti.Log2SEW)>;
+ }
+}
+
foreach fvti = AllFloatAndBF16Vectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
let Predicates = GetVTypePredicates<ivti>.Predicates in {
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
index 5d021d2e0e031..a96fcc814b75a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-i2fp.ll
@@ -529,47 +529,27 @@ define void @ui2fp_v2i64_v2bf16(ptr %x, ptr %y) {
}
define <2 x bfloat> @si2fp_v2i1_v2bf16(<2 x i1> %x) {
-; ZVFBFMIN-LABEL: si2fp_v2i1_v2bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: si2fp_v2i1_v2bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: si2fp_v2i1_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x bfloat>
ret <2 x bfloat> %z
}
define <2 x bfloat> @ui2fp_v2i1_v2bf16(<2 x i1> %x) {
-; ZVFBFMIN-LABEL: ui2fp_v2i1_v2bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: ui2fp_v2i1_v2bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: ui2fp_v2i1_v2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x bfloat>
ret <2 x bfloat> %z
}
@@ -627,47 +607,27 @@ define void @ui2fp_v8i64_v8bf16(ptr %x, ptr %y) {
}
define <8 x bfloat> @si2fp_v8i1_v8bf16(<8 x i1> %x) {
-; ZVFBFMIN-LABEL: si2fp_v8i1_v8bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: si2fp_v8i1_v8bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: si2fp_v8i1_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x bfloat>
ret <8 x bfloat> %z
}
define <8 x bfloat> @ui2fp_v8i1_v8bf16(<8 x i1> %x) {
-; ZVFBFMIN-LABEL: ui2fp_v8i1_v8bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: ui2fp_v8i1_v8bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: ui2fp_v8i1_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x bfloat>
ret <8 x bfloat> %z
}
@@ -941,47 +901,27 @@ define void @ui2fp_v2i64_v2f16(ptr %x, ptr %y) {
}
define <2 x half> @si2fp_v2i1_v2f16(<2 x i1> %x) {
-; ZVFH-LABEL: si2fp_v2i1_v2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: si2fp_v2i1_v2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: si2fp_v2i1_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = sitofp <2 x i1> %x to <2 x half>
ret <2 x half> %z
}
define <2 x half> @ui2fp_v2i1_v2f16(<2 x i1> %x) {
-; ZVFH-LABEL: ui2fp_v2i1_v2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: ui2fp_v2i1_v2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: ui2fp_v2i1_v2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = uitofp <2 x i1> %x to <2 x half>
ret <2 x half> %z
}
@@ -1019,47 +959,27 @@ define void @ui2fp_v8i64_v8f16(ptr %x, ptr %y) {
}
define <8 x half> @si2fp_v8i1_v8f16(<8 x i1> %x) {
-; ZVFH-LABEL: si2fp_v8i1_v8f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: si2fp_v8i1_v8f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: si2fp_v8i1_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = sitofp <8 x i1> %x to <8 x half>
ret <8 x half> %z
}
define <8 x half> @ui2fp_v8i1_v8f16(<8 x i1> %x) {
-; ZVFH-LABEL: ui2fp_v8i1_v8f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: ui2fp_v8i1_v8f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: ui2fp_v8i1_v8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%z = uitofp <8 x i1> %x to <8 x half>
ret <8 x half> %z
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
index 640ea801c0232..df122353e196b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-select-bf16.ll
@@ -133,8 +133,7 @@ define <8 x bfloat> @vselect_vf_v8bf16(bfloat %a, <8 x bfloat> %vb, <8 x i1> %cc
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: fmv.x.h a0, fa0
; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v9, a0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; ZVFBFMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vselect_vf_v8bf16:
@@ -153,8 +152,7 @@ define <16 x bfloat> @vselect_vf_v16bf16(bfloat %a, <16 x bfloat> %vb, <16 x i1>
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: fmv.x.h a0, fa0
; ZVFBFMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v10, a0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
+; ZVFBFMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vselect_vf_v16bf16:
@@ -169,18 +167,11 @@ define <16 x bfloat> @vselect_vf_v16bf16(bfloat %a, <16 x bfloat> %vb, <16 x i1>
}
define <8 x bfloat> @vselect_vfpzero_v8bf16(<8 x bfloat> %vb, <8 x i1> %cc) {
-; ZVFBFMIN-LABEL: vselect_vfpzero_v8bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v9, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vselect_vfpzero_v8bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFBFA-NEXT: vmerge.vim v8, v8, 0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vselect_vfpzero_v8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: ret
%vsel = select <8 x i1> %cc, <8 x bfloat> splat (bfloat 0.0), <8 x bfloat> %vb
ret <8 x bfloat> %vsel
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
index 844e0213989bc..232a1acf3b4dd 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge-bf16.ll
@@ -23,10 +23,8 @@ define <2 x bfloat> @vpmerge_vf_v2bf16(bfloat %a, <2 x bfloat> %vb, <2 x i1> %m,
; CHECK-LABEL: vpmerge_vf_v2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <2 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <2 x bfloat> %elt.head, <2 x bfloat> poison, <2 x i32> zeroinitializer
@@ -49,10 +47,8 @@ define <4 x bfloat> @vpmerge_vf_v4bf16(bfloat %a, <4 x bfloat> %vb, <4 x i1> %m,
; CHECK-LABEL: vpmerge_vf_v4bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <4 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <4 x bfloat> %elt.head, <4 x bfloat> poison, <4 x i32> zeroinitializer
@@ -75,10 +71,8 @@ define <8 x bfloat> @vpmerge_vf_v8bf16(bfloat %a, <8 x bfloat> %vb, <8 x i1> %m,
; CHECK-LABEL: vpmerge_vf_v8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a1
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <8 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <8 x bfloat> %elt.head, <8 x bfloat> poison, <8 x i32> zeroinitializer
@@ -101,10 +95,8 @@ define <16 x bfloat> @vpmerge_vf_v16bf16(bfloat %a, <16 x bfloat> %vb, <16 x i1>
; CHECK-LABEL: vpmerge_vf_v16bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.x v10, a1
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <16 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <16 x bfloat> %elt.head, <16 x bfloat> poison, <16 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
index 4f02539c1a057..7df63a0eaddda 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vpmerge.ll
@@ -991,10 +991,8 @@ define <2 x half> @vpmerge_vf_v2f16(half %a, <2 x half> %vb, <2 x i1> %m, i32 ze
; ZVFHMIN-LABEL: vpmerge_vf_v2f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v9, a1
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <2 x half> poison, half %a, i32 0
%va = shufflevector <2 x half> %elt.head, <2 x half> poison, <2 x i32> zeroinitializer
@@ -1023,10 +1021,8 @@ define <4 x half> @vpmerge_vf_v4f16(half %a, <4 x half> %vb, <4 x i1> %m, i32 ze
; ZVFHMIN-LABEL: vpmerge_vf_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v9, a1
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <4 x half> poison, half %a, i32 0
%va = shufflevector <4 x half> %elt.head, <4 x half> poison, <4 x i32> zeroinitializer
@@ -1055,10 +1051,8 @@ define <8 x half> @vpmerge_vf_v8f16(half %a, <8 x half> %vb, <8 x i1> %m, i32 ze
; ZVFHMIN-LABEL: vpmerge_vf_v8f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 8, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v9, a1
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <8 x half> poison, half %a, i32 0
%va = shufflevector <8 x half> %elt.head, <8 x half> poison, <8 x i32> zeroinitializer
@@ -1087,10 +1081,8 @@ define <16 x half> @vpmerge_vf_v16f16(half %a, <16 x half> %vb, <16 x i1> %m, i3
; ZVFHMIN-LABEL: vpmerge_vf_v16f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; ZVFHMIN-NEXT: vsetivli zero, 16, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v10, a1
; ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, ma
-; ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
+; ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; ZVFHMIN-NEXT: ret
%elt.head = insertelement <16 x half> poison, half %a, i32 0
%va = shufflevector <16 x half> %elt.head, <16 x half> poison, <16 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/select-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/select-bf16.ll
index 26d9f0f646e00..3ef69129e8e6c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/select-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/select-bf16.ll
@@ -193,8 +193,7 @@ define <vscale x 4 x bfloat> @vselect_vf_nxv4bf16(bfloat %a, <vscale x 4 x bfloa
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: fmv.x.h a0, fa0
; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v9, a0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; ZVFBFMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vselect_vf_nxv4bf16:
@@ -213,8 +212,7 @@ define <vscale x 8 x bfloat> @vselect_vf_nxv8bf16(bfloat %a, <vscale x 8 x bfloa
; ZVFBFMIN: # %bb.0:
; ZVFBFMIN-NEXT: fmv.x.h a0, fa0
; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v10, a0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v10, v0
+; ZVFBFMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; ZVFBFMIN-NEXT: ret
;
; ZVFBFA-LABEL: vselect_vf_nxv8bf16:
@@ -229,18 +227,11 @@ define <vscale x 8 x bfloat> @vselect_vf_nxv8bf16(bfloat %a, <vscale x 8 x bfloa
}
define <vscale x 4 x bfloat> @vselect_vfpzero_nxv4bf16(<vscale x 4 x bfloat> %vb, <vscale x 4 x i1> %cc) {
-; ZVFBFMIN-LABEL: vselect_vfpzero_nxv4bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v8, v9, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vselect_vfpzero_nxv4bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFA-NEXT: vmerge.vim v8, v8, 0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vselect_vfpzero_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: ret
%vsel = select <vscale x 4 x i1> %cc, <vscale x 4 x bfloat> splat (bfloat 0.0), <vscale x 4 x bfloat> %vb
ret <vscale x 4 x bfloat> %vsel
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
index 75cd70e1729e1..09f0b7de631a4 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vitofp-sdnode.ll
@@ -19,277 +19,157 @@
; RUN: --check-prefixes=CHECK,RV64,ZVFHMIN,ZVFBFA
define <vscale x 1 x bfloat> @vsitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
-; ZVFBFMIN-LABEL: vsitofp_nxv1i1_nxv1bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vsitofp_nxv1i1_nxv1bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv1i1_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 1 x bfloat> @vuitofp_nxv1i1_nxv1bf16(<vscale x 1 x i1> %va) {
-; ZVFBFMIN-LABEL: vuitofp_nxv1i1_nxv1bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vuitofp_nxv1i1_nxv1bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv1i1_nxv1bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x bfloat>
ret <vscale x 1 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vsitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
-; ZVFBFMIN-LABEL: vsitofp_nxv2i1_nxv2bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vsitofp_nxv2i1_nxv2bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv2i1_nxv2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 2 x bfloat> @vuitofp_nxv2i1_nxv2bf16(<vscale x 2 x i1> %va) {
-; ZVFBFMIN-LABEL: vuitofp_nxv2i1_nxv2bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vuitofp_nxv2i1_nxv2bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv2i1_nxv2bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x bfloat>
ret <vscale x 2 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vsitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
-; ZVFBFMIN-LABEL: vsitofp_nxv4i1_nxv4bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vsitofp_nxv4i1_nxv4bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv4i1_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 4 x bfloat> @vuitofp_nxv4i1_nxv4bf16(<vscale x 4 x i1> %va) {
-; ZVFBFMIN-LABEL: vuitofp_nxv4i1_nxv4bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v9, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vuitofp_nxv4i1_nxv4bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv4i1_nxv4bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x bfloat>
ret <vscale x 4 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vsitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
-; ZVFBFMIN-LABEL: vsitofp_nxv8i1_nxv8bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v10, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vsitofp_nxv8i1_nxv8bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv8i1_nxv8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 8 x bfloat> @vuitofp_nxv8i1_nxv8bf16(<vscale x 8 x i1> %va) {
-; ZVFBFMIN-LABEL: vuitofp_nxv8i1_nxv8bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v10, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vuitofp_nxv8i1_nxv8bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv8i1_nxv8bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x bfloat>
ret <vscale x 8 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vsitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va) {
-; ZVFBFMIN-LABEL: vsitofp_nxv16i1_nxv16bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v12, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vsitofp_nxv16i1_nxv16bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv16i1_nxv16bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 16 x bfloat> @vuitofp_nxv16i1_nxv16bf16(<vscale x 16 x i1> %va) {
-; ZVFBFMIN-LABEL: vuitofp_nxv16i1_nxv16bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v12, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vuitofp_nxv16i1_nxv16bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv16i1_nxv16bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x bfloat>
ret <vscale x 16 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vsitofp_nxv32i1_nxv32bf16(<vscale x 32 x i1> %va) {
-; ZVFBFMIN-LABEL: vsitofp_nxv32i1_nxv32bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 1048572
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v16, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vsitofp_nxv32i1_nxv32bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 1048572
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv32i1_nxv32bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 1048572
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 32 x i1> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
define <vscale x 32 x bfloat> @vuitofp_nxv32i1_nxv32bf16(<vscale x 32 x i1> %va) {
-; ZVFBFMIN-LABEL: vuitofp_nxv32i1_nxv32bf16:
-; ZVFBFMIN: # %bb.0:
-; ZVFBFMIN-NEXT: lui a0, 4
-; ZVFBFMIN-NEXT: addi a0, a0, -128
-; ZVFBFMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFBFMIN-NEXT: vmv.v.x v8, a0
-; ZVFBFMIN-NEXT: vmv.v.i v16, 0
-; ZVFBFMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFBFMIN-NEXT: ret
-;
-; ZVFBFA-LABEL: vuitofp_nxv32i1_nxv32bf16:
-; ZVFBFA: # %bb.0:
-; ZVFBFA-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; ZVFBFA-NEXT: vmv.v.i v8, 0
-; ZVFBFA-NEXT: lui a0, 4
-; ZVFBFA-NEXT: addi a0, a0, -128
-; ZVFBFA-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFBFA-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv32i1_nxv32bf16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: lui a0, 4
+; CHECK-NEXT: addi a0, a0, -128
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 32 x i1> %va to <vscale x 32 x bfloat>
ret <vscale x 32 x bfloat> %evec
}
@@ -1177,47 +1057,27 @@ define <vscale x 8 x bfloat> @vuitofp_nxv8i64_nxv8bf16(<vscale x 8 x i64> %va) {
}
define <vscale x 1 x half> @vsitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
-; ZVFH-LABEL: vsitofp_nxv1i1_nxv1f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vsitofp_nxv1i1_nxv1f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv1i1_nxv1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
}
define <vscale x 1 x half> @vuitofp_nxv1i1_nxv1f16(<vscale x 1 x i1> %va) {
-; ZVFH-LABEL: vuitofp_nxv1i1_nxv1f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vuitofp_nxv1i1_nxv1f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv1i1_nxv1f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 1 x i1> %va to <vscale x 1 x half>
ret <vscale x 1 x half> %evec
}
@@ -1291,47 +1151,27 @@ define <vscale x 1 x double> @vuitofp_nxv1i1_nxv1f64(<vscale x 1 x i1> %va) {
}
define <vscale x 2 x half> @vsitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
-; ZVFH-LABEL: vsitofp_nxv2i1_nxv2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vsitofp_nxv2i1_nxv2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv2i1_nxv2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
}
define <vscale x 2 x half> @vuitofp_nxv2i1_nxv2f16(<vscale x 2 x i1> %va) {
-; ZVFH-LABEL: vuitofp_nxv2i1_nxv2f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vuitofp_nxv2i1_nxv2f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv2i1_nxv2f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 2 x i1> %va to <vscale x 2 x half>
ret <vscale x 2 x half> %evec
}
@@ -1405,47 +1245,27 @@ define <vscale x 2 x double> @vuitofp_nxv2i1_nxv2f64(<vscale x 2 x i1> %va) {
}
define <vscale x 4 x half> @vsitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
-; ZVFH-LABEL: vsitofp_nxv4i1_nxv4f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vsitofp_nxv4i1_nxv4f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv4i1_nxv4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
}
define <vscale x 4 x half> @vuitofp_nxv4i1_nxv4f16(<vscale x 4 x i1> %va) {
-; ZVFH-LABEL: vuitofp_nxv4i1_nxv4f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m1, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vuitofp_nxv4i1_nxv4f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v9, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v9, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv4i1_nxv4f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 4 x i1> %va to <vscale x 4 x half>
ret <vscale x 4 x half> %evec
}
@@ -1519,47 +1339,27 @@ define <vscale x 4 x double> @vuitofp_nxv4i1_nxv4f64(<vscale x 4 x i1> %va) {
}
define <vscale x 8 x half> @vsitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
-; ZVFH-LABEL: vsitofp_nxv8i1_nxv8f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vsitofp_nxv8i1_nxv8f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v10, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv8i1_nxv8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
}
define <vscale x 8 x half> @vuitofp_nxv8i1_nxv8f16(<vscale x 8 x i1> %va) {
-; ZVFH-LABEL: vuitofp_nxv8i1_nxv8f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vuitofp_nxv8i1_nxv8f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v10, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v10, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv8i1_nxv8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 8 x i1> %va to <vscale x 8 x half>
ret <vscale x 8 x half> %evec
}
@@ -1633,47 +1433,27 @@ define <vscale x 8 x double> @vuitofp_nxv8i1_nxv8f64(<vscale x 8 x i1> %va) {
}
define <vscale x 16 x half> @vsitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
-; ZVFH-LABEL: vsitofp_nxv16i1_nxv16f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vsitofp_nxv16i1_nxv16f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v12, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv16i1_nxv16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
}
define <vscale x 16 x half> @vuitofp_nxv16i1_nxv16f16(<vscale x 16 x i1> %va) {
-; ZVFH-LABEL: vuitofp_nxv16i1_nxv16f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m4, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vuitofp_nxv16i1_nxv16f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v12, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v12, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv16i1_nxv16f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 16 x i1> %va to <vscale x 16 x half>
ret <vscale x 16 x half> %evec
}
@@ -1703,47 +1483,27 @@ define <vscale x 16 x float> @vuitofp_nxv16i1_nxv16f32(<vscale x 16 x i1> %va) {
}
define <vscale x 32 x half> @vsitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
-; ZVFH-LABEL: vsitofp_nxv32i1_nxv32f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, -17
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vsitofp_nxv32i1_nxv32f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, -17
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v16, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vsitofp_nxv32i1_nxv32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, -17
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = sitofp <vscale x 32 x i1> %va to <vscale x 32 x half>
ret <vscale x 32 x half> %evec
}
define <vscale x 32 x half> @vuitofp_nxv32i1_nxv32f16(<vscale x 32 x i1> %va) {
-; ZVFH-LABEL: vuitofp_nxv32i1_nxv32f16:
-; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli a0, zero, e16, m8, ta, ma
-; ZVFH-NEXT: vmv.v.i v8, 0
-; ZVFH-NEXT: li a0, 15
-; ZVFH-NEXT: slli a0, a0, 10
-; ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; ZVFH-NEXT: ret
-;
-; ZVFHMIN-LABEL: vuitofp_nxv32i1_nxv32f16:
-; ZVFHMIN: # %bb.0:
-; ZVFHMIN-NEXT: li a0, 15
-; ZVFHMIN-NEXT: slli a0, a0, 10
-; ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; ZVFHMIN-NEXT: vmv.v.x v8, a0
-; ZVFHMIN-NEXT: vmv.v.i v16, 0
-; ZVFHMIN-NEXT: vmerge.vvm v8, v16, v8, v0
-; ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vuitofp_nxv32i1_nxv32f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
+; CHECK-NEXT: li a0, 15
+; CHECK-NEXT: slli a0, a0, 10
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%evec = uitofp <vscale x 32 x i1> %va to <vscale x 32 x half>
ret <vscale x 32 x half> %evec
}
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
index 8a1a3cdd90d72..a85acb5835e1c 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode-bf16.ll
@@ -23,10 +23,8 @@ define <vscale x 1 x bfloat> @vpmerge_vf_nxv1bf16(bfloat %a, <vscale x 1 x bfloa
; CHECK-LABEL: vpmerge_vf_nxv1bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 1 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 1 x bfloat> %elt.head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
@@ -49,10 +47,8 @@ define <vscale x 2 x bfloat> @vpmerge_vf_nxv2bf16(bfloat %a, <vscale x 2 x bfloa
; CHECK-LABEL: vpmerge_vf_nxv2bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, mf2, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 2 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 2 x bfloat> %elt.head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
@@ -75,10 +71,8 @@ define <vscale x 4 x bfloat> @vpmerge_vf_nxv4bf16(bfloat %a, <vscale x 4 x bfloa
; CHECK-LABEL: vpmerge_vf_nxv4bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, m1, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 4 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 4 x bfloat> %elt.head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
@@ -101,10 +95,8 @@ define <vscale x 8 x bfloat> @vpmerge_vf_nxv8bf16(bfloat %a, <vscale x 8 x bfloa
; CHECK-LABEL: vpmerge_vf_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.x v10, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, m2, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
+; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 8 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 8 x bfloat> %elt.head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
@@ -127,10 +119,8 @@ define <vscale x 16 x bfloat> @vpmerge_vf_nxv16bf16(bfloat %a, <vscale x 16 x bf
; CHECK-LABEL: vpmerge_vf_nxv16bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; CHECK-NEXT: vmv.v.x v12, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, m4, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
+; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 16 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 16 x bfloat> %elt.head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
@@ -153,10 +143,8 @@ define <vscale x 32 x bfloat> @vpmerge_vf_nxv32bf16(bfloat %a, <vscale x 32 x bf
; CHECK-LABEL: vpmerge_vf_nxv32bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a1, fa0
-; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; CHECK-NEXT: vmv.v.x v16, a1
-; CHECK-NEXT: vsetvli zero, zero, e16, m8, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: vsetvli zero, a0, e16, m8, tu, ma
+; CHECK-NEXT: vmerge.vxm v8, v8, a1, v0
; CHECK-NEXT: ret
%elt.head = insertelement <vscale x 32 x bfloat> poison, bfloat %a, i32 0
%va = shufflevector <vscale x 32 x bfloat> %elt.head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
index 8a355bd0feb83..a249f50d161c9 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vpmerge-sdnode.ll
@@ -1190,19 +1190,15 @@ define <vscale x 1 x half> @vpmerge_vf_nxv1f16(half %a, <vscale x 1 x half> %vb,
; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv1f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV32ZVFHMIN-NEXT: vmv.v.x v9, a1
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
-; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; RV32ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv1f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
-; RV64ZVFHMIN-NEXT: vmv.v.x v9, a1
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf4, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
+; RV64ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV64ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 1 x half> poison, half %a, i32 0
%va = shufflevector <vscale x 1 x half> %elt.head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -1237,19 +1233,15 @@ define <vscale x 2 x half> @vpmerge_vf_nxv2f16(half %a, <vscale x 2 x half> %vb,
; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv2f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV32ZVFHMIN-NEXT: vmv.v.x v9, a1
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, tu, ma
-; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; RV32ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv2f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; RV64ZVFHMIN-NEXT: vmv.v.x v9, a1
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, mf2, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
+; RV64ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV64ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 2 x half> poison, half %a, i32 0
%va = shufflevector <vscale x 2 x half> %elt.head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
@@ -1284,19 +1276,15 @@ define <vscale x 4 x half> @vpmerge_vf_nxv4f16(half %a, <vscale x 4 x half> %vb,
; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv4f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; RV32ZVFHMIN-NEXT: vmv.v.x v9, a1
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, tu, ma
-; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; RV32ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv4f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, ta, ma
-; RV64ZVFHMIN-NEXT: vmv.v.x v9, a1
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m1, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m1, tu, ma
+; RV64ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV64ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 4 x half> poison, half %a, i32 0
%va = shufflevector <vscale x 4 x half> %elt.head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
@@ -1331,19 +1319,15 @@ define <vscale x 8 x half> @vpmerge_vf_nxv8f16(half %a, <vscale x 8 x half> %vb,
; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv8f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; RV32ZVFHMIN-NEXT: vmv.v.x v10, a1
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
-; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; RV32ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv8f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, ta, ma
-; RV64ZVFHMIN-NEXT: vmv.v.x v10, a1
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m2, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m2, tu, ma
+; RV64ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV64ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 8 x half> poison, half %a, i32 0
%va = shufflevector <vscale x 8 x half> %elt.head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -1378,19 +1362,15 @@ define <vscale x 16 x half> @vpmerge_vf_nxv16f16(half %a, <vscale x 16 x half> %
; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv16f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; RV32ZVFHMIN-NEXT: vmv.v.x v12, a1
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, tu, ma
-; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v12, v0
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; RV32ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv16f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, ta, ma
-; RV64ZVFHMIN-NEXT: vmv.v.x v12, a1
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m4, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v12, v0
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m4, tu, ma
+; RV64ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV64ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 16 x half> poison, half %a, i32 0
%va = shufflevector <vscale x 16 x half> %elt.head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
@@ -1425,19 +1405,15 @@ define <vscale x 32 x half> @vpmerge_vf_nxv32f16(half %a, <vscale x 32 x half> %
; RV32ZVFHMIN-LABEL: vpmerge_vf_nxv32f16:
; RV32ZVFHMIN: # %bb.0:
; RV32ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; RV32ZVFHMIN-NEXT: vmv.v.x v16, a1
-; RV32ZVFHMIN-NEXT: vsetvli zero, zero, e16, m8, tu, ma
-; RV32ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0
+; RV32ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, tu, ma
+; RV32ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV32ZVFHMIN-NEXT: ret
;
; RV64ZVFHMIN-LABEL: vpmerge_vf_nxv32f16:
; RV64ZVFHMIN: # %bb.0:
; RV64ZVFHMIN-NEXT: fmv.x.h a1, fa0
-; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, ta, ma
-; RV64ZVFHMIN-NEXT: vmv.v.x v16, a1
-; RV64ZVFHMIN-NEXT: vsetvli zero, zero, e16, m8, tu, ma
-; RV64ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0
+; RV64ZVFHMIN-NEXT: vsetvli zero, a0, e16, m8, tu, ma
+; RV64ZVFHMIN-NEXT: vmerge.vxm v8, v8, a1, v0
; RV64ZVFHMIN-NEXT: ret
%elt.head = insertelement <vscale x 32 x half> poison, half %a, i32 0
%va = shufflevector <vscale x 32 x half> %elt.head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll
index b793531e34069..a794f2fb2052a 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-bf16.ll
@@ -23,8 +23,7 @@ define <vscale x 1 x bfloat> @vfmerge_fv_nxv1bf16(<vscale x 1 x bfloat> %va, bfl
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a0, fa0
; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%head = insertelement <vscale x 1 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 1 x bfloat> %head, <vscale x 1 x bfloat> poison, <vscale x 1 x i32> zeroinitializer
@@ -47,8 +46,7 @@ define <vscale x 2 x bfloat> @vfmerge_fv_nxv2bf16(<vscale x 2 x bfloat> %va, bfl
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a0, fa0
; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%head = insertelement <vscale x 2 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 2 x bfloat> %head, <vscale x 2 x bfloat> poison, <vscale x 2 x i32> zeroinitializer
@@ -71,8 +69,7 @@ define <vscale x 4 x bfloat> @vfmerge_fv_nxv4bf16(<vscale x 4 x bfloat> %va, bfl
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a0, fa0
; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-NEXT: vmv.v.x v9, a0
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%head = insertelement <vscale x 4 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 4 x bfloat> %head, <vscale x 4 x bfloat> poison, <vscale x 4 x i32> zeroinitializer
@@ -95,8 +92,7 @@ define <vscale x 8 x bfloat> @vfmerge_fv_nxv8bf16(<vscale x 8 x bfloat> %va, bfl
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a0, fa0
; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.x v10, a0
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%head = insertelement <vscale x 8 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 8 x bfloat> %head, <vscale x 8 x bfloat> poison, <vscale x 8 x i32> zeroinitializer
@@ -108,8 +104,7 @@ define <vscale x 8 x bfloat> @vfmerge_zv_nxv8bf16(<vscale x 8 x bfloat> %va, <vs
; CHECK-LABEL: vfmerge_zv_nxv8bf16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-NEXT: vmv.v.i v10, 0
-; CHECK-NEXT: vmerge.vvm v8, v8, v10, v0
+; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
; CHECK-NEXT: ret
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x bfloat> splat (bfloat zeroinitializer), <vscale x 8 x bfloat> %va
ret <vscale x 8 x bfloat> %vc
@@ -148,8 +143,7 @@ define <vscale x 16 x bfloat> @vfmerge_fv_nxv16bf16(<vscale x 16 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a0, fa0
; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; CHECK-NEXT: vmv.v.x v12, a0
-; CHECK-NEXT: vmerge.vvm v8, v8, v12, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%head = insertelement <vscale x 16 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 16 x bfloat> %head, <vscale x 16 x bfloat> poison, <vscale x 16 x i32> zeroinitializer
@@ -172,8 +166,7 @@ define <vscale x 32 x bfloat> @vfmerge_fv_nxv32bf16(<vscale x 32 x bfloat> %va,
; CHECK: # %bb.0:
; CHECK-NEXT: fmv.x.h a0, fa0
; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-NEXT: vmv.v.x v16, a0
-; CHECK-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%head = insertelement <vscale x 32 x bfloat> poison, bfloat %b, i32 0
%splat = shufflevector <vscale x 32 x bfloat> %head, <vscale x 32 x bfloat> poison, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
index e267c98c59efd..109a6575feada 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vselect-fp.ll
@@ -29,8 +29,7 @@ define <vscale x 1 x half> @vfmerge_fv_nxv1f16(<vscale x 1 x half> %va, half %b,
; CHECK-ZVFHMIN: # %bb.0:
; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0
; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf4, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVFHMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 1 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 1 x half> %head, <vscale x 1 x half> poison, <vscale x 1 x i32> zeroinitializer
@@ -59,8 +58,7 @@ define <vscale x 2 x half> @vfmerge_fv_nxv2f16(<vscale x 2 x half> %va, half %b,
; CHECK-ZVFHMIN: # %bb.0:
; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0
; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVFHMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 2 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 2 x half> %head, <vscale x 2 x half> poison, <vscale x 2 x i32> zeroinitializer
@@ -89,8 +87,7 @@ define <vscale x 4 x half> @vfmerge_fv_nxv4f16(<vscale x 4 x half> %va, half %b,
; CHECK-ZVFHMIN: # %bb.0:
; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0
; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m1, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.x v9, a0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-ZVFHMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 4 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 4 x half> %head, <vscale x 4 x half> poison, <vscale x 4 x i32> zeroinitializer
@@ -119,8 +116,7 @@ define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b,
; CHECK-ZVFHMIN: # %bb.0:
; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0
; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.x v10, a0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
+; CHECK-ZVFHMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 8 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 8 x half> %head, <vscale x 8 x half> poison, <vscale x 8 x i32> zeroinitializer
@@ -129,37 +125,22 @@ define <vscale x 8 x half> @vfmerge_fv_nxv8f16(<vscale x 8 x half> %va, half %b,
}
define <vscale x 8 x half> @vfmerge_zv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_zv_nxv8f16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-ZVFH-NEXT: vmerge.vim v8, v8, 0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_zv_nxv8f16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: vsetvli a0, zero, e16, m2, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.i v10, 0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_zv_nxv8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmerge.vim v8, v8, 0, v0
+; CHECK-NEXT: ret
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> splat (half zeroinitializer), <vscale x 8 x half> %va
ret <vscale x 8 x half> %vc
}
define <vscale x 8 x half> @vfmerge_nzv_nxv8f16(<vscale x 8 x half> %va, <vscale x 8 x i1> %cond) {
-; CHECK-ZVFH-LABEL: vfmerge_nzv_nxv8f16:
-; CHECK-ZVFH: # %bb.0:
-; CHECK-ZVFH-NEXT: lui a0, 1048568
-; CHECK-ZVFH-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-ZVFH-NEXT: vmerge.vxm v8, v8, a0, v0
-; CHECK-ZVFH-NEXT: ret
-;
-; CHECK-ZVFHMIN-LABEL: vfmerge_nzv_nxv8f16:
-; CHECK-ZVFHMIN: # %bb.0:
-; CHECK-ZVFHMIN-NEXT: lui a0, 1048568
-; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m2, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.x v10, a0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v10, v0
-; CHECK-ZVFHMIN-NEXT: ret
+; CHECK-LABEL: vfmerge_nzv_nxv8f16:
+; CHECK: # %bb.0:
+; CHECK-NEXT: lui a0, 1048568
+; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
+; CHECK-NEXT: ret
%vc = select <vscale x 8 x i1> %cond, <vscale x 8 x half> splat (half -0.0), <vscale x 8 x half> %va
ret <vscale x 8 x half> %vc
}
@@ -203,8 +184,7 @@ define <vscale x 16 x half> @vfmerge_fv_nxv16f16(<vscale x 16 x half> %va, half
; CHECK-ZVFHMIN: # %bb.0:
; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0
; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m4, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.x v12, a0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v12, v0
+; CHECK-ZVFHMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 16 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 16 x half> %head, <vscale x 16 x half> poison, <vscale x 16 x i32> zeroinitializer
@@ -233,8 +213,7 @@ define <vscale x 32 x half> @vfmerge_fv_nxv32f16(<vscale x 32 x half> %va, half
; CHECK-ZVFHMIN: # %bb.0:
; CHECK-ZVFHMIN-NEXT: fmv.x.h a0, fa0
; CHECK-ZVFHMIN-NEXT: vsetvli a1, zero, e16, m8, ta, ma
-; CHECK-ZVFHMIN-NEXT: vmv.v.x v16, a0
-; CHECK-ZVFHMIN-NEXT: vmerge.vvm v8, v8, v16, v0
+; CHECK-ZVFHMIN-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-ZVFHMIN-NEXT: ret
%head = insertelement <vscale x 32 x half> poison, half %b, i32 0
%splat = shufflevector <vscale x 32 x half> %head, <vscale x 32 x half> poison, <vscale x 32 x i32> zeroinitializer
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
index b4961d2b06c82..cd43a6576d261 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsitofp-vp-mask.ll
@@ -5,12 +5,11 @@
define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: lui a0, 1048572
; CHECK-NEXT: addi a0, a0, -128
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -19,12 +18,11 @@ define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vs
define <vscale x 2 x bfloat> @vsitofp_nxv2bf16_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vsitofp_nxv2bf16_nxv2i1_unmasked:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: lui a0, 1048572
; CHECK-NEXT: addi a0, a0, -128
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.sitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x bfloat> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
index 272b32c3d769f..4db1643572133 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vuitofp-vp-mask.ll
@@ -5,12 +5,11 @@
define <vscale x 2 x bfloat> @vuitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2bf16_nxv2i1:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: lui a0, 4
; CHECK-NEXT: addi a0, a0, -128
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.uitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> %m, i32 %evl)
ret <vscale x 2 x bfloat> %v
@@ -19,12 +18,11 @@ define <vscale x 2 x bfloat> @vuitofp_nxv2bf16_nxv2i1(<vscale x 2 x i1> %va, <vs
define <vscale x 2 x bfloat> @vuitofp_nxv2bf16_nxv2i1_unmasked(<vscale x 2 x i1> %va, i32 zeroext %evl) {
; CHECK-LABEL: vuitofp_nxv2bf16_nxv2i1_unmasked:
; CHECK: # %bb.0:
+; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
+; CHECK-NEXT: vmv.v.i v8, 0
; CHECK-NEXT: lui a0, 4
; CHECK-NEXT: addi a0, a0, -128
-; CHECK-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
-; CHECK-NEXT: vmv.v.x v8, a0
-; CHECK-NEXT: vmv.v.i v9, 0
-; CHECK-NEXT: vmerge.vvm v8, v9, v8, v0
+; CHECK-NEXT: vmerge.vxm v8, v8, a0, v0
; CHECK-NEXT: ret
%v = call <vscale x 2 x bfloat> @llvm.vp.uitofp.nxv2bf16.nxv2i1(<vscale x 2 x i1> %va, <vscale x 2 x i1> splat (i1 true), i32 %evl)
ret <vscale x 2 x bfloat> %v
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