[llvm-branch-commits] [llvm] [AMDGPU] Verify VGPR tuple alignment from the operand register class (PR #219230)

[Matt Arsenault via llvm-branch-commits]

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@@ -3016,6 +3016,93 @@ unsigned getRegBitWidth(const MCRegisterClass &RC) {
   return getRegBitWidth(RC.getID());
 }
 
+int getUnalignedEquivalentRC(unsigned RCID) {
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arsenm wrote:

You probably could get away with inspecting subclasses 

https://github.com/llvm/llvm-project/pull/219230