[llvm-branch-commits] [llvm] [AMDGPU] Promote sgpr16 copy in sdag and gisel (PR #218000)
Guo Chen via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Sep 1 07:54:45 PDT 2026
https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/218000
>From e36563cc60dad5e5cc78c614ac88bc9494632937 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Sun, 9 Aug 2026 18:44:24 -0400
Subject: [PATCH 1/4] Legalize sgpr16 copy in gisel
---
.../AMDGPU/AMDGPUInstructionSelector.cpp | 45 ++
.../Target/AMDGPU/AMDGPUInstructionSelector.h | 1 +
llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll | 205 +++---
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll | 2 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll | 4 +-
.../AMDGPU/GlobalISel/fp-int-conversions.ll | 4 +-
.../AMDGPU/GlobalISel/insertelement.i8.ll | 6 +-
.../llvm.amdgcn.raw.buffer.load.tfe.ll | 20 +-
.../llvm.amdgcn.struct.buffer.load.tfe.ll | 20 +-
.../AMDGPU/GlobalISel/load-uniform-in-vgpr.ll | 96 ++-
.../CodeGen/AMDGPU/GlobalISel/load-uniform.ll | 95 +--
.../GlobalISel/merge-values-s16-true16.ll | 9 +-
...alize-amdgcn.ptr.s.buffer.load.subdword.ll | 6 +-
...klegalize-amdgcn.s.buffer.load.subdword.ll | 6 +-
.../AMDGPU/GlobalISel/store-local.128.ll | 64 +-
.../AMDGPU/GlobalISel/store-local.96.ll | 54 +-
.../AMDGPU/GlobalISel/strict_fma.f16.ll | 16 +-
llvm/test/CodeGen/AMDGPU/bitreverse.ll | 83 +--
.../CodeGen/AMDGPU/dagcombine-fmul-sel.ll | 601 ++++++++++++------
llvm/test/CodeGen/AMDGPU/fmaximum.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fmaxnum.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fminimum.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fminnum.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fp_to_sint.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fp_to_uint.ll | 2 +-
llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll | 16 +-
llvm/test/CodeGen/AMDGPU/fptrunc.ll | 222 ++-----
.../isel-amdgpu-cs-chain-preserve-cc.ll | 18 +-
.../test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll | 3 +-
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll | 16 +-
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 2 +-
.../llvm.amdgcn.ptr.s.buffer.load-gfx12.ll | 4 +-
.../AMDGPU/llvm.amdgcn.raw.buffer.load.ll | 2 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll | 96 +--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll | 79 +--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll | 78 +--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll | 78 +--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll | 79 +--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll | 108 ++--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll | 79 +--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll | 79 +--
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll | 109 ++--
.../CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll | 2 +-
.../test/CodeGen/AMDGPU/llvm.fptrunc.round.ll | 43 +-
llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/minimummaximum.ll | 39 +-
llvm/test/CodeGen/AMDGPU/minmax.ll | 197 ++----
47 files changed, 1236 insertions(+), 1468 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index 893c7cce1a0f0..bb8d9a825d8ba 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -216,6 +216,47 @@ bool AMDGPUInstructionSelector::selectCOPY(MachineInstr &I) const {
continue;
RBI.constrainGenericRegister(MO.getReg(), *RC, *MRI);
}
+
+ // Crossbank s16 copy between sgpr and vgpr
+ // sgpr(s16) = COPY vgpr(s16)
+ // =>
+ // vgpr32 = REG_SEQUENCE vgpr16
+ // sreg32 = readfirstlane vgpr32
+ //
+ // vgpr(s16) = COPY sgpr(s16)
+ // =>
+ // vgpr32 = COPY sreg32
+ // vgpr16 = COPY vgpr32.lo16
+
+ LLT DstTy = MRI->getType(DstReg);
+ bool IsS16Copy = DstTy == LLT::scalar(16);
+ if (Subtarget->useRealTrue16Insts() && IsS16Copy && !SrcReg.isPhysical() &&
+ !DstReg.isPhysical()) {
+ if (isSGPR(DstReg) && isVGPR(SrcReg)) {
+ Register Reg16 = MRI->createVirtualRegister(&AMDGPU::VGPR_16RegClass);
+ Register Reg32 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(*BB, &I, DL, TII.get(AMDGPU::IMPLICIT_DEF), Reg16);
+ BuildMI(*BB, &I, DL, TII.get(AMDGPU::REG_SEQUENCE), Reg32)
+ .addReg(SrcReg)
+ .addImm(AMDGPU::lo16)
+ .addReg(Reg16)
+ .addImm(AMDGPU::hi16);
+ BuildMI(*BB, &I, DL, TII.get(AMDGPU::V_READFIRSTLANE_B32), DstReg)
+ .addReg(Reg32);
+ I.eraseFromParent();
+ return true;
+ }
+
+ if (isSGPR(SrcReg) && isVGPR(DstReg)) {
+ Register Reg32 = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), Reg32).addReg(SrcReg);
+ BuildMI(*BB, &I, DL, TII.get(AMDGPU::COPY), DstReg)
+ .addReg(Reg32, {}, AMDGPU::lo16);
+ I.eraseFromParent();
+ return true;
+ }
+ }
+
return true;
}
@@ -3063,6 +3104,10 @@ bool AMDGPUInstructionSelector::isSGPR(Register Reg) const {
return RBI.getRegBank(Reg, *MRI, TRI)->getID() == AMDGPU::SGPRRegBankID;
}
+bool AMDGPUInstructionSelector::isVGPR(Register Reg) const {
+ return RBI.getRegBank(Reg, *MRI, TRI)->getID() == AMDGPU::VGPRRegBankID;
+}
+
bool AMDGPUInstructionSelector::isInstrUniform(const MachineInstr &MI) const {
if (!MI.hasOneMemOperand())
return false;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
index ce3a090651d0e..deb3539aebe0c 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.h
@@ -70,6 +70,7 @@ class AMDGPUInstructionSelector final : public InstructionSelector {
};
bool isSGPR(Register Reg) const;
+ bool isVGPR(Register Reg) const;
bool isInstrUniform(const MachineInstr &MI) const;
bool isVCC(Register Reg, const MachineRegisterInfo &MRI) const;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
index 5738dd30112c5..08be2ad4a8f26 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/bswap.ll
@@ -2,8 +2,8 @@
; RUN: llc -global-isel -mtriple=amdgpu7.01-amd-amdpal -o - %s | FileCheck -check-prefix=GFX7 %s
; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-amdpal -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-amdpal -o - %s | FileCheck -check-prefix=GFX9 %s
-; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefix=GFX10 %s
-; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefix=GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-amdpal -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s
+; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-amdpal -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s
define amdgpu_ps i32 @s_bswap_i32(i32 inreg %src) {
; GFX7-LABEL: s_bswap_i32:
@@ -31,11 +31,11 @@ define amdgpu_ps i32 @s_bswap_i32(i32 inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s0, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s0, 0x10203
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call i32 @llvm.bswap.i32(i32 %src)
ret i32 %bswap
}
@@ -64,11 +64,11 @@ define i32 @v_bswap_i32(i32 %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0x10203
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call i32 @llvm.bswap.i32(i32 %src)
ret i32 %bswap
}
@@ -109,13 +109,13 @@ define amdgpu_ps <2 x i32> @s_bswap_v2i32(<2 x i32> inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s0, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, s1, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s0, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, s1, 0x10203
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src)
ret <2 x i32> %bswap
}
@@ -149,12 +149,12 @@ define <2 x i32> @v_bswap_v2i32(<2 x i32> %src) {
; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_v2i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x10203
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_v2i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, v1, 0x10203
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i32> @llvm.bswap.v2i32(<2 x i32> %src)
ret <2 x i32> %bswap
}
@@ -195,13 +195,13 @@ define amdgpu_ps i64 @s_bswap_i64(i64 inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s1, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, s0, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s1, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, s0, 0x10203
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call i64 @llvm.bswap.i64(i64 %src)
ret i64 %bswap
}
@@ -238,13 +238,13 @@ define i64 @v_bswap_i64(i64 %src) {
; GFX9-NEXT: v_mov_b32_e32 v0, v2
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v2, 0, v1, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, v0, 0x10203
-; GFX10-NEXT: v_mov_b32_e32 v0, v2
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v2, 0, v1, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, v0, 0x10203
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v2
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call i64 @llvm.bswap.i64(i64 %src)
ret i64 %bswap
}
@@ -305,17 +305,17 @@ define amdgpu_ps <2 x i64> @s_bswap_v2i64(<2 x i64> inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_v2i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s1, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, s0, 0x10203
-; GFX10-NEXT: v_perm_b32 v2, 0, s3, 0x10203
-; GFX10-NEXT: v_perm_b32 v3, 0, s2, 0x10203
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: v_readfirstlane_b32 s1, v1
-; GFX10-NEXT: v_readfirstlane_b32 s2, v2
-; GFX10-NEXT: v_readfirstlane_b32 s3, v3
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_v2i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s1, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, s0, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v2, 0, s3, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v3, 0, s2, 0x10203
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v1
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v2
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v3
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src)
ret <2 x i64> %bswap
}
@@ -365,16 +365,16 @@ define <2 x i64> @v_bswap_v2i64(<2 x i64> %src) {
; GFX9-NEXT: v_mov_b32_e32 v2, v5
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_v2i64:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v4, 0, v1, 0x10203
-; GFX10-NEXT: v_perm_b32 v5, 0, v3, 0x10203
-; GFX10-NEXT: v_perm_b32 v1, 0, v0, 0x10203
-; GFX10-NEXT: v_perm_b32 v3, 0, v2, 0x10203
-; GFX10-NEXT: v_mov_b32_e32 v0, v4
-; GFX10-NEXT: v_mov_b32_e32 v2, v5
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_v2i64:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v4, 0, v1, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v5, 0, v3, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, v0, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v3, 0, v2, 0x10203
+; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v4
+; GFX10PLUS-NEXT: v_mov_b32_e32 v2, v5
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %src)
ret <2 x i64> %bswap
}
@@ -408,6 +408,13 @@ define amdgpu_ps i16 @s_bswap_i16(i16 inreg %src) {
; GFX10-NEXT: v_perm_b32 v0, 0, s0, 0xc0c0001
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: ; return to shader part epilog
+;
+; GFX11-LABEL: s_bswap_i16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX11-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-NEXT: ; return to shader part epilog
%bswap = call i16 @llvm.bswap.i16(i16 %src)
ret i16 %bswap
}
@@ -435,11 +442,11 @@ define i16 @v_bswap_i16(i16 %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
ret i16 %bswap
}
@@ -476,11 +483,11 @@ define amdgpu_ps i32 @s_bswap_v2i16(<2 x i16> inreg %src) {
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: ; return to shader part epilog
;
-; GFX10-LABEL: s_bswap_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: v_perm_b32 v0, 0, s0, 0x2030001
-; GFX10-NEXT: v_readfirstlane_b32 s0, v0
-; GFX10-NEXT: ; return to shader part epilog
+; GFX10PLUS-LABEL: s_bswap_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, s0, 0x2030001
+; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0
+; GFX10PLUS-NEXT: ; return to shader part epilog
%bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src)
%cast = bitcast <2 x i16> %bswap to i32
ret i32 %cast
@@ -510,11 +517,11 @@ define i32 @v_bswap_i16_zext_to_i32(i16 %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i16_zext_to_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i16_zext_to_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = zext i16 %bswap to i32
ret i32 %zext
@@ -546,12 +553,12 @@ define i32 @v_bswap_i16_sext_to_i32(i16 %src) {
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i16_sext_to_i32:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
-; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i16_sext_to_i32:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0xc0c0001
+; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call i16 @llvm.bswap.i16(i16 %src)
%zext = sext i16 %bswap to i32
ret i32 %zext
@@ -586,11 +593,11 @@ define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {
; GFX9-NEXT: v_perm_b32 v0, 0, v0, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_v2i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x2030001
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_v2i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0x2030001
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call <2 x i16> @llvm.bswap.v2i16(<2 x i16> %src)
ret <2 x i16> %bswap
}
@@ -630,12 +637,12 @@ define <3 x i16> @v_bswap_v3i16(<3 x i16> %src) {
; GFX9-NEXT: v_perm_b32 v1, 0, v1, s4
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_v3i16:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v0, 0, v0, 0x2030001
-; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x2030001
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_v3i16:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v0, 0, v0, 0x2030001
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, v1, 0x2030001
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%bswap = call <3 x i16> @llvm.bswap.v3i16(<3 x i16> %src)
ret <3 x i16> %bswap
}
@@ -672,13 +679,13 @@ define i64 @v_bswap_i48(i64 %src) {
; GFX9-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX10-LABEL: v_bswap_i48:
-; GFX10: ; %bb.0:
-; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: v_perm_b32 v1, 0, v1, 0x10203
-; GFX10-NEXT: v_perm_b32 v2, 0, v0, 0x10203
-; GFX10-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
-; GFX10-NEXT: s_setpc_b64 s[30:31]
+; GFX10PLUS-LABEL: v_bswap_i48:
+; GFX10PLUS: ; %bb.0:
+; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10PLUS-NEXT: v_perm_b32 v1, 0, v1, 0x10203
+; GFX10PLUS-NEXT: v_perm_b32 v2, 0, v0, 0x10203
+; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 16, v[1:2]
+; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]
%trunc = trunc i64 %src to i48
%bswap = call i48 @llvm.bswap.i48(i48 %trunc)
%zext = zext i48 %bswap to i64
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
index 7505234fae8d2..e6a93c653cedf 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
@@ -1526,7 +1526,7 @@ define amdgpu_ps half @fma_s16_uniform(half inreg %a, half inreg %b, half inreg
;
; GFX11-TRUE16-LABEL: fma_s16_uniform:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, s1, s0, v0.l
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
index 0baba45e541a1..81ddff1dd2a4f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fmed3.ll
@@ -12,7 +12,7 @@ define amdgpu_ps half @fmed3_s16_uniform(half inreg %a, half inreg %b, half inre
;
; GFX12-LABEL: fmed3_s16_uniform:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT: v_med3_num_f16 v0.l, s0, s1, v0.l
; GFX12-NEXT: ; return to shader part epilog
@@ -31,7 +31,7 @@ define amdgpu_ps half @fmed3_s16_uniform_salu_use(half inreg %a, half inreg %b,
;
; GFX12-LABEL: fmed3_s16_uniform_salu_use:
; GFX12: ; %bb.0:
-; GFX12-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-NEXT: v_mov_b32_e32 v0, s2
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-NEXT: v_med3_num_f16 v0.l, s0, s1, v0.l
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
index 26fab4aeb914f..42e534ccae809 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fp-int-conversions.ll
@@ -531,7 +531,7 @@ define amdgpu_ps void @s_uitofp_i32_to_f16(i32 inreg %x, ptr addrspace(1) %out)
; GFX12: ; %bb.0:
; GFX12: s_cvt_f32_u32 s0, s0
; GFX12: s_cvt_f16_f32 s0, s0
-; GFX12: v_mov_b16_e32 v2.l, s0
+; GFX12: v_mov_b32_e32 v2, s0
%result = uitofp i32 %x to half
store half %result, ptr addrspace(1) %out
ret void
@@ -552,7 +552,7 @@ define amdgpu_ps void @s_sitofp_i32_to_f16(i32 inreg %x, ptr addrspace(1) %out)
; GFX12: ; %bb.0:
; GFX12: s_cvt_f32_i32 s0, s0
; GFX12: s_cvt_f16_f32 s0, s0
-; GFX12: v_mov_b16_e32 v2.l, s0
+; GFX12: v_mov_b32_e32 v2, s0
%result = sitofp i32 %x to half
store half %result, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
index 620cba152f5a2..373f80379998d 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll
@@ -90,10 +90,10 @@ define amdgpu_ps void @insertelement_s_v2i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0
; GFX11-TRUE16-NEXT: s_mov_b32 m0, s5
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-TRUE16-NEXT: global_load_u16 v0, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8
@@ -103,8 +103,8 @@ define amdgpu_ps void @insertelement_s_v2i8_s_s(ptr addrspace(4) inreg %ptr, i8
; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8
; GFX11-TRUE16-NEXT: s_or_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: global_store_b16 v[1:2], v0, off
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s0
+; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: insertelement_s_v2i8_s_s:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
index 0d0ab1388c0d6..548d8986f96c6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.tfe.ll
@@ -265,8 +265,9 @@ define amdgpu_ps void @raw_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX11-TRUE16-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
; GFX11-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX11-TRUE16-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX11-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
- ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+ ; GFX11-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
+ ; GFX11-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]].lo16
+ ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
; GFX11-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX11-TRUE16-NEXT: S_ENDPGM 0
;
@@ -313,8 +314,9 @@ define amdgpu_ps void @raw_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX12-TRUE16-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
; GFX12-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX12-TRUE16-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX12-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
- ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+ ; GFX12-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
+ ; GFX12-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]].lo16
+ ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
; GFX12-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX12-TRUE16-NEXT: S_ENDPGM 0
;
@@ -470,8 +472,9 @@ define amdgpu_ps void @raw_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX11-TRUE16-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_OFFSET]].sub1
; GFX11-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX11-TRUE16-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX11-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
- ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+ ; GFX11-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
+ ; GFX11-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]].lo16
+ ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
; GFX11-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX11-TRUE16-NEXT: S_ENDPGM 0
;
@@ -518,8 +521,9 @@ define amdgpu_ps void @raw_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX12-TRUE16-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET]].sub1
; GFX12-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY8]], implicit $exec
; GFX12-TRUE16-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX12-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_16 = COPY [[COPY10]]
- ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY11]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+ ; GFX12-TRUE16-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[COPY10]]
+ ; GFX12-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]].lo16
+ ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
; GFX12-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX12-TRUE16-NEXT: S_ENDPGM 0
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
index 81a44835c2c1e..bf40610169806 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.tfe.ll
@@ -277,8 +277,9 @@ define amdgpu_ps void @raw_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX11-TRUE16-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
; GFX11-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX11-TRUE16-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX11-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
- ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+ ; GFX11-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
+ ; GFX11-TRUE16-NEXT: [[COPY13:%[0-9]+]]:vgpr_16 = COPY [[COPY12]].lo16
+ ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
; GFX11-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX11-TRUE16-NEXT: S_ENDPGM 0
;
@@ -328,8 +329,9 @@ define amdgpu_ps void @raw_buffer_load_i16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX12-TRUE16-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
; GFX12-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX12-TRUE16-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX12-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
- ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
+ ; GFX12-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
+ ; GFX12-TRUE16-NEXT: [[COPY13:%[0-9]+]]:vgpr_16 = COPY [[COPY12]].lo16
+ ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (i16) into %ir.data_addr, addrspace 1)
; GFX12-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX12-TRUE16-NEXT: S_ENDPGM 0
;
@@ -493,8 +495,9 @@ define amdgpu_ps void @raw_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX11-TRUE16-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_IDXEN]].sub1
; GFX11-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX11-TRUE16-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX11-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
- ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+ ; GFX11-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
+ ; GFX11-TRUE16-NEXT: [[COPY13:%[0-9]+]]:vgpr_16 = COPY [[COPY12]].lo16
+ ; GFX11-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
; GFX11-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX11-TRUE16-NEXT: S_ENDPGM 0
;
@@ -544,8 +547,9 @@ define amdgpu_ps void @raw_buffer_load_f16_tfe(<4 x i32> inreg %rsrc, ptr addrsp
; GFX12-TRUE16-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN]].sub1
; GFX12-TRUE16-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY9]], implicit $exec
; GFX12-TRUE16-NEXT: [[COPY11:%[0-9]+]]:sreg_32 = COPY [[V_READFIRSTLANE_B32_]]
- ; GFX12-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_16 = COPY [[COPY11]]
- ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY12]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
+ ; GFX12-TRUE16-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY11]]
+ ; GFX12-TRUE16-NEXT: [[COPY13:%[0-9]+]]:vgpr_16 = COPY [[COPY12]].lo16
+ ; GFX12-TRUE16-NEXT: GLOBAL_STORE_SHORT_t16 [[REG_SEQUENCE1]], [[COPY13]], 0, 0, implicit $exec :: (store (f16) into %ir.data_addr, addrspace 1)
; GFX12-TRUE16-NEXT: GLOBAL_STORE_DWORD [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (store (i32) into %ir.tfe_addr, addrspace 1)
; GFX12-TRUE16-NEXT: S_ENDPGM 0
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
index 730443a56b003..16cbe0d79c773 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform-in-vgpr.ll
@@ -39,7 +39,7 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx12(ptr addrspace(1) inreg %ptr
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -69,7 +69,7 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx12(ptr addrspace(1) inreg %ptr
; GFX12-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-True16-NEXT: s_add_co_i32 s0, s0, s1
; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-True16-NEXT: s_endpgm
;
@@ -123,7 +123,7 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx11(ptr addrspace(1) inreg %ptr
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -152,7 +152,7 @@ define amdgpu_ps void @load_uniform_P1_i16_b16_gfx11(ptr addrspace(1) inreg %ptr
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
; GFX12-True16-NEXT: s_add_co_i32 s0, s2, s0
; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-True16-NEXT: s_endpgm
;
@@ -205,7 +205,7 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx12(ptr addrspace(1) i
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -235,7 +235,7 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx12(ptr addrspace(1) i
; GFX12-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-True16-NEXT: s_add_co_i32 s0, s0, s1
; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-True16-NEXT: s_endpgm
;
@@ -289,7 +289,7 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx11(ptr addrspace(1) i
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -318,7 +318,7 @@ define amdgpu_ps void @load_uniform_P1_i16_anyextending_gfx11(ptr addrspace(1) i
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
; GFX12-True16-NEXT: s_add_co_i32 s0, s2, s0
; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-True16-NEXT: s_endpgm
;
@@ -1260,7 +1260,7 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx12(ptr addrspace(4) inreg %ptr
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -1290,7 +1290,7 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx12(ptr addrspace(4) inreg %ptr
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
; GFX12-True16-NEXT: s_add_co_i32 s0, s1, s0
; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-True16-NEXT: s_endpgm
;
@@ -1342,7 +1342,7 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx11(ptr addrspace(4) inreg %ptr
; GFX11-True16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-True16-NEXT: s_add_i32 s0, s1, s0
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -1360,29 +1360,17 @@ define amdgpu_ps void @load_uniform_P4_i16_b16_gfx11(ptr addrspace(4) inreg %ptr
; GFX11-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NoTrue16-NEXT: s_endpgm
;
-; GFX12-True16-LABEL: load_uniform_P4_i16_b16_gfx11:
-; GFX12-True16: ; %bb.0:
-; GFX12-True16-NEXT: s_clause 0x1
-; GFX12-True16-NEXT: s_load_u16 s2, s[0:1], 0x0
-; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-True16-NEXT: s_wait_kmcnt 0x0
-; GFX12-True16-NEXT: s_add_co_i32 s0, s2, s0
-; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-True16-NEXT: s_endpgm
-;
-; GFX12-NoTrue16-LABEL: load_uniform_P4_i16_b16_gfx11:
-; GFX12-NoTrue16: ; %bb.0:
-; GFX12-NoTrue16-NEXT: s_clause 0x1
-; GFX12-NoTrue16-NEXT: s_load_u16 s2, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0
-; GFX12-NoTrue16-NEXT: s_add_co_i32 s0, s2, s0
-; GFX12-NoTrue16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NoTrue16-NEXT: s_endpgm
+; GFX12-LABEL: load_uniform_P4_i16_b16_gfx11:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_add_co_i32 s0, s2, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(4) %ptra
%b = load volatile i16, ptr addrspace(4) %ptra, align 4
%sum = add i16 %a, %b
@@ -1421,7 +1409,7 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx12(ptr addrspace(4) i
; GFX11-True16-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-True16-NEXT: s_add_i32 s0, s0, s1
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -1451,7 +1439,7 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx12(ptr addrspace(4) i
; GFX12-True16-NEXT: s_wait_kmcnt 0x0
; GFX12-True16-NEXT: s_add_co_i32 s0, s1, s0
; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-True16-NEXT: s_endpgm
;
@@ -1503,7 +1491,7 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx11(ptr addrspace(4) i
; GFX11-True16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-True16-NEXT: s_add_i32 s0, s1, s0
; GFX11-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-True16-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-True16-NEXT: v_mov_b32_e32 v2, s0
; GFX11-True16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-True16-NEXT: s_endpgm
;
@@ -1521,29 +1509,17 @@ define amdgpu_ps void @load_uniform_P4_i16_anyextending_gfx11(ptr addrspace(4) i
; GFX11-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NoTrue16-NEXT: s_endpgm
;
-; GFX12-True16-LABEL: load_uniform_P4_i16_anyextending_gfx11:
-; GFX12-True16: ; %bb.0:
-; GFX12-True16-NEXT: s_clause 0x1
-; GFX12-True16-NEXT: s_load_u16 s2, s[0:1], 0x0
-; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-True16-NEXT: s_wait_kmcnt 0x0
-; GFX12-True16-NEXT: s_add_co_i32 s0, s2, s0
-; GFX12-True16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-True16-NEXT: s_endpgm
-;
-; GFX12-NoTrue16-LABEL: load_uniform_P4_i16_anyextending_gfx11:
-; GFX12-NoTrue16: ; %bb.0:
-; GFX12-NoTrue16-NEXT: s_clause 0x1
-; GFX12-NoTrue16-NEXT: s_load_u16 s2, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0
-; GFX12-NoTrue16-NEXT: s_add_co_i32 s0, s2, s0
-; GFX12-NoTrue16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NoTrue16-NEXT: s_endpgm
+; GFX12-LABEL: load_uniform_P4_i16_anyextending_gfx11:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_clause 0x1
+; GFX12-NEXT: s_load_u16 s2, s[0:1], 0x0
+; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: s_add_co_i32 s0, s2, s0
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(4) %ptra
%b = load volatile i16, ptr addrspace(4) %ptra, align 4
%sum = add i16 %a, %b
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
index 5dd0626feec2c..33e325dc228ad 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-uniform.ll
@@ -16,21 +16,13 @@ define amdgpu_ps void @load_uniform_P1_i16_gfx12(ptr addrspace(1) inreg %ptra, p
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
-; GFX12-True16-LABEL: load_uniform_P1_i16_gfx12:
-; GFX12-True16: ; %bb.0:
-; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-True16-NEXT: s_wait_kmcnt 0x0
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-True16-NEXT: s_endpgm
-;
-; GFX12-NoTrue16-LABEL: load_uniform_P1_i16_gfx12:
-; GFX12-NoTrue16: ; %bb.0:
-; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0
-; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NoTrue16-NEXT: s_endpgm
+; GFX12-LABEL: load_uniform_P1_i16_gfx12:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(1) %ptra
store i16 %a, ptr addrspace(1) %out
ret void
@@ -44,25 +36,17 @@ define amdgpu_ps void @load_uniform_P1_i16_align4_widen_mmo_gfx11(ptr addrspace(
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
-; GFX12-True16-LABEL: load_uniform_P1_i16_align4_widen_mmo_gfx11:
-; GFX12-True16: ; %bb.0:
-; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-True16-NEXT: s_wait_kmcnt 0x0
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-True16-NEXT: s_endpgm
-;
-; GFX12-NoTrue16-LABEL: load_uniform_P1_i16_align4_widen_mmo_gfx11:
-; GFX12-NoTrue16: ; %bb.0:
-; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0
-; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NoTrue16-NEXT: s_endpgm
+; GFX12-LABEL: load_uniform_P1_i16_align4_widen_mmo_gfx11:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(1) %ptra, align 4
store i16 %a, ptr addrspace(1) %out
ret void
@@ -312,21 +296,13 @@ define amdgpu_ps void @load_uniform_P4_i16_gfx12(ptr addrspace(4) inreg %ptra, p
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
-; GFX12-True16-LABEL: load_uniform_P4_i16_gfx12:
-; GFX12-True16: ; %bb.0:
-; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-True16-NEXT: s_wait_kmcnt 0x0
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-True16-NEXT: s_endpgm
-;
-; GFX12-NoTrue16-LABEL: load_uniform_P4_i16_gfx12:
-; GFX12-NoTrue16: ; %bb.0:
-; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0
-; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NoTrue16-NEXT: s_endpgm
+; GFX12-LABEL: load_uniform_P4_i16_gfx12:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(4) %ptra
store i16 %a, ptr addrspace(1) %out
ret void
@@ -337,25 +313,17 @@ define amdgpu_ps void @load_uniform_P4_i16_align4_widen_mmo_gfx11(ptr addrspace(
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
-; GFX12-True16-LABEL: load_uniform_P4_i16_align4_widen_mmo_gfx11:
-; GFX12-True16: ; %bb.0:
-; GFX12-True16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-True16-NEXT: s_wait_kmcnt 0x0
-; GFX12-True16-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-True16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-True16-NEXT: s_endpgm
-;
-; GFX12-NoTrue16-LABEL: load_uniform_P4_i16_align4_widen_mmo_gfx11:
-; GFX12-NoTrue16: ; %bb.0:
-; GFX12-NoTrue16-NEXT: s_load_u16 s0, s[0:1], 0x0
-; GFX12-NoTrue16-NEXT: s_wait_kmcnt 0x0
-; GFX12-NoTrue16-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-NoTrue16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NoTrue16-NEXT: s_endpgm
+; GFX12-LABEL: load_uniform_P4_i16_align4_widen_mmo_gfx11:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_load_u16 s0, s[0:1], 0x0
+; GFX12-NEXT: s_wait_kmcnt 0x0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
%a = load i16, ptr addrspace(4) %ptra, align 4
store i16 %a, ptr addrspace(1) %out
ret void
@@ -594,3 +562,6 @@ define amdgpu_ps void @load_uniform_P4_v16i32(ptr addrspace(4) inreg %ptra, ptr
store <16 x i32> %a, ptr addrspace(1) %out
ret void
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX12-NoTrue16: {{.*}}
+; GFX12-True16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
index fc1be777b09a3..9dd8a1f9b5c59 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/merge-values-s16-true16.ll
@@ -29,19 +29,20 @@ define amdgpu_kernel void @store_i136_divergent(ptr %p) {
; GFX1150: ; %bb.0:
; GFX1150-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
; GFX1150-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x3ff, v0
-; GFX1150-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-NEXT: v_mov_b32_e32 v6, 0
+; GFX1150-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1150-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX1150-NEXT: v_mov_b16_e32 v0.h, 0
; GFX1150-NEXT: v_and_b16 v0.l, 0xff, v0.l
; GFX1150-NEXT: v_lshlrev_b16 v4.l, 8, v1.l
-; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-NEXT: v_mov_b16_e32 v1.l, v0.h
+; GFX1150-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1150-NEXT: v_mov_b16_e32 v1.h, v0.h
; GFX1150-NEXT: v_or_b16 v0.l, v0.l, v4.l
; GFX1150-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1150-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0
+; GFX1150-NEXT: v_mov_b32_e32 v5, s1
+; GFX1150-NEXT: v_mov_b16_e32 v1.l, v6.l
+; GFX1150-NEXT: v_mov_b32_e32 v4, s0
; GFX1150-NEXT: s_clause 0x1
; GFX1150-NEXT: flat_store_b128 v[4:5], v[0:3]
; GFX1150-NEXT: flat_store_b8 v[4:5], v6 offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll
index e3f267238dd95..221461c47f56a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.ptr.s.buffer.load.subdword.ll
@@ -41,11 +41,10 @@ define amdgpu_ps void @ptr_s_buffer_load_i16_sgpr_rsrc_sgpr_offset(ptr addrspace
; GFX12-LABEL: ptr_s_buffer_load_i16_sgpr_rsrc_sgpr_offset:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_mov_b32 s8, s5
; GFX12-NEXT: s_mov_b32 s9, s6
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
; GFX12-NEXT: global_store_b16 v1, v0, s[8:9]
; GFX12-NEXT: s_endpgm
%val = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
@@ -58,11 +57,10 @@ define amdgpu_ps void @ptr_s_buffer_load_u16_sgpr_rsrc_sgpr_offset(ptr addrspace
; GFX12-LABEL: ptr_s_buffer_load_u16_sgpr_rsrc_sgpr_offset:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_mov_b32 s8, s5
; GFX12-NEXT: s_mov_b32 s9, s6
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
; GFX12-NEXT: global_store_b16 v1, v0, s[8:9]
; GFX12-NEXT: s_endpgm
%val = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %rsrc, i32 %soffset, i32 0), !invariant.load !0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
index 42779b9803ece..e72f9a1d44f91 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbanklegalize-amdgcn.s.buffer.load.subdword.ll
@@ -41,11 +41,10 @@ define amdgpu_ps void @s_buffer_load_i16_sgpr_rsrc_sgpr_offset(<4 x i32> inreg %
; GFX12-LABEL: s_buffer_load_i16_sgpr_rsrc_sgpr_offset:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_mov_b32 s8, s5
; GFX12-NEXT: s_mov_b32 s9, s6
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
; GFX12-NEXT: global_store_b16 v1, v0, s[8:9]
; GFX12-NEXT: s_endpgm
%val = call i16 @llvm.amdgcn.s.buffer.load.i16(<4 x i32> %rsrc, i32 %soffset, i32 0)
@@ -58,11 +57,10 @@ define amdgpu_ps void @s_buffer_load_u16_sgpr_rsrc_sgpr_offset(<4 x i32> inreg %
; GFX12-LABEL: s_buffer_load_u16_sgpr_rsrc_sgpr_offset:
; GFX12: ; %bb.0:
; GFX12-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0
-; GFX12-NEXT: v_mov_b32_e32 v1, 0
; GFX12-NEXT: s_mov_b32 s8, s5
; GFX12-NEXT: s_mov_b32 s9, s6
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX12-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s0
; GFX12-NEXT: global_store_b16 v1, v0, s[8:9]
; GFX12-NEXT: s_endpgm
%val = call i16 @llvm.amdgcn.s.buffer.load.u16(<4 x i32> %rsrc, i32 %soffset, i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
index 439d9f7912b30..2587d868e8676 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.128.ll
@@ -239,53 +239,47 @@ define amdgpu_kernel void @store_lds_v4i32_align1(ptr addrspace(3) %out, <4 x i3
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_and_b32 s6, 0xffff, s0
; GFX11-NEXT: s_lshr_b32 s5, s0, 16
-; GFX11-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s4
; GFX11-NEXT: s_lshr_b32 s0, s0, 24
+; GFX11-NEXT: s_lshr_b32 s4, s1, 16
; GFX11-NEXT: s_and_b32 s7, 0xffff, s1
; GFX11-NEXT: s_lshr_b32 s6, s6, 8
-; GFX11-NEXT: v_mov_b32_e32 v5, s4
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX11-NEXT: s_lshr_b32 s0, s7, 8
-; GFX11-NEXT: v_mov_b16_e32 v3.l, s6
-; GFX11-NEXT: v_mov_b16_e32 v1.h, s5
-; GFX11-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-NEXT: v_mov_b16_e32 v0.h, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s2
; GFX11-NEXT: s_lshr_b32 s1, s1, 24
+; GFX11-NEXT: v_dual_mov_b32 v4, s5 :: v_dual_mov_b32 v5, s0
+; GFX11-NEXT: s_lshr_b32 s0, s7, 8
+; GFX11-NEXT: v_dual_mov_b32 v6, s4 :: v_dual_mov_b32 v7, s6
; GFX11-NEXT: s_and_b32 s9, 0xffff, s2
-; GFX11-NEXT: v_mov_b16_e32 v4.l, s0
+; GFX11-NEXT: v_dual_mov_b32 v8, s1 :: v_dual_mov_b32 v9, s0
; GFX11-NEXT: s_lshr_b32 s0, s2, 24
-; GFX11-NEXT: v_mov_b16_e32 v2.h, s4
-; GFX11-NEXT: v_mov_b16_e32 v3.h, s1
; GFX11-NEXT: s_lshr_b32 s1, s9, 8
-; GFX11-NEXT: ds_store_b8 v5, v0
-; GFX11-NEXT: ds_store_b8 v5, v3 offset:1
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v1 offset:2
-; GFX11-NEXT: ds_store_b8 v5, v2 offset:3
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v0 offset:4
-; GFX11-NEXT: ds_store_b8 v5, v4 offset:5
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v2 offset:6
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v3 offset:7
-; GFX11-NEXT: v_mov_b16_e32 v1.h, s0
+; GFX11-NEXT: ds_store_b8 v1, v0
+; GFX11-NEXT: ds_store_b8 v1, v7 offset:1
+; GFX11-NEXT: ds_store_b8 v1, v4 offset:2
+; GFX11-NEXT: ds_store_b8 v1, v5 offset:3
+; GFX11-NEXT: ds_store_b8 v1, v2 offset:4
+; GFX11-NEXT: ds_store_b8 v1, v9 offset:5
+; GFX11-NEXT: ds_store_b8 v1, v6 offset:6
+; GFX11-NEXT: ds_store_b8 v1, v8 offset:7
+; GFX11-NEXT: v_mov_b32_e32 v4, s0
; GFX11-NEXT: s_and_b32 s0, 0xffff, s3
; GFX11-NEXT: s_lshr_b32 s8, s2, 16
-; GFX11-NEXT: v_mov_b16_e32 v1.l, s2
-; GFX11-NEXT: v_mov_b16_e32 v0.l, s1
+; GFX11-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v5, s3
; GFX11-NEXT: s_lshr_b32 s0, s0, 8
-; GFX11-NEXT: v_mov_b16_e32 v0.h, s8
; GFX11-NEXT: s_lshr_b32 s1, s3, 16
-; GFX11-NEXT: v_mov_b16_e32 v2.h, s0
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v7, s1
+; GFX11-NEXT: v_mov_b32_e32 v6, s0
; GFX11-NEXT: s_lshr_b32 s0, s3, 24
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s3
-; GFX11-NEXT: v_mov_b16_e32 v3.l, s1
-; GFX11-NEXT: v_mov_b16_e32 v3.h, s0
-; GFX11-NEXT: ds_store_b8 v5, v1 offset:8
-; GFX11-NEXT: ds_store_b8 v5, v0 offset:9
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v0 offset:10
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v1 offset:11
-; GFX11-NEXT: ds_store_b8 v5, v2 offset:12
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v2 offset:13
-; GFX11-NEXT: ds_store_b8 v5, v3 offset:14
-; GFX11-NEXT: ds_store_b8_d16_hi v5, v3 offset:15
+; GFX11-NEXT: v_mov_b32_e32 v8, s0
+; GFX11-NEXT: ds_store_b8 v1, v3 offset:8
+; GFX11-NEXT: ds_store_b8 v1, v0 offset:9
+; GFX11-NEXT: ds_store_b8 v1, v2 offset:10
+; GFX11-NEXT: ds_store_b8 v1, v4 offset:11
+; GFX11-NEXT: ds_store_b8 v1, v5 offset:12
+; GFX11-NEXT: ds_store_b8 v1, v6 offset:13
+; GFX11-NEXT: ds_store_b8 v1, v7 offset:14
+; GFX11-NEXT: ds_store_b8 v1, v8 offset:15
; GFX11-NEXT: s_endpgm
store <4 x i32> %x, ptr addrspace(3) %out, align 1
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
index 3b6106b915e03..43d39edc824d4 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/store-local.96.ll
@@ -60,7 +60,6 @@ define amdgpu_kernel void @store_lds_v3i32(ptr addrspace(3) %out, <3 x i32> %x)
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: ds_store_b96 v3, v[0:2]
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -223,45 +222,38 @@ define amdgpu_kernel void @store_lds_v3i32_align1(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_load_b32 s3, s[4:5], 0x0
; GFX11-NEXT: s_and_b32 s5, 0xffff, s0
-; GFX11-NEXT: s_lshr_b32 s4, s0, 16
+; GFX11-NEXT: s_lshr_b32 s7, s2, 16
; GFX11-NEXT: s_lshr_b32 s5, s5, 8
-; GFX11-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-NEXT: v_mov_b32_e32 v6, s3
+; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s3
; GFX11-NEXT: s_lshr_b32 s0, s0, 24
; GFX11-NEXT: s_lshr_b32 s3, s1, 16
; GFX11-NEXT: s_and_b32 s6, 0xffff, s1
-; GFX11-NEXT: v_mov_b16_e32 v0.h, s1
+; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v3, s2
; GFX11-NEXT: s_lshr_b32 s1, s1, 24
; GFX11-NEXT: s_and_b32 s8, 0xffff, s2
-; GFX11-NEXT: v_mov_b16_e32 v4.l, s5
-; GFX11-NEXT: v_mov_b16_e32 v1.h, s4
-; GFX11-NEXT: s_lshr_b32 s7, s2, 16
-; GFX11-NEXT: v_mov_b16_e32 v1.l, s2
+; GFX11-NEXT: v_dual_mov_b32 v8, s7 :: v_dual_mov_b32 v9, s5
+; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s0
; GFX11-NEXT: s_lshr_b32 s2, s2, 24
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
; GFX11-NEXT: s_lshr_b32 s0, s6, 8
-; GFX11-NEXT: v_mov_b16_e32 v3.l, s1
+; GFX11-NEXT: v_dual_mov_b32 v6, s3 :: v_dual_mov_b32 v7, s1
; GFX11-NEXT: s_lshr_b32 s1, s8, 8
-; GFX11-NEXT: v_mov_b16_e32 v2.h, s3
-; GFX11-NEXT: v_mov_b16_e32 v3.h, s7
-; GFX11-NEXT: v_mov_b16_e32 v4.h, s2
-; GFX11-NEXT: v_mov_b16_e32 v5.l, s0
-; GFX11-NEXT: v_mov_b16_e32 v5.h, s1
-; GFX11-NEXT: ds_store_b8 v6, v0
-; GFX11-NEXT: ds_store_b8 v6, v4 offset:1
-; GFX11-NEXT: ds_store_b8_d16_hi v6, v1 offset:2
-; GFX11-NEXT: ds_store_b8 v6, v2 offset:3
-; GFX11-NEXT: ds_store_b8_d16_hi v6, v0 offset:4
-; GFX11-NEXT: ds_store_b8 v6, v5 offset:5
-; GFX11-NEXT: ds_store_b8_d16_hi v6, v2 offset:6
-; GFX11-NEXT: ds_store_b8 v6, v3 offset:7
-; GFX11-NEXT: ds_store_b8 v6, v1 offset:8
-; GFX11-NEXT: ds_store_b8_d16_hi v6, v5 offset:9
-; GFX11-NEXT: ds_store_b8_d16_hi v6, v3 offset:10
-; GFX11-NEXT: ds_store_b8_d16_hi v6, v4 offset:11
+; GFX11-NEXT: v_dual_mov_b32 v10, s2 :: v_dual_mov_b32 v11, s0
+; GFX11-NEXT: v_mov_b32_e32 v12, s1
+; GFX11-NEXT: ds_store_b8 v1, v0
+; GFX11-NEXT: ds_store_b8 v1, v9 offset:1
+; GFX11-NEXT: ds_store_b8 v1, v4 offset:2
+; GFX11-NEXT: ds_store_b8 v1, v5 offset:3
+; GFX11-NEXT: ds_store_b8 v1, v2 offset:4
+; GFX11-NEXT: ds_store_b8 v1, v11 offset:5
+; GFX11-NEXT: ds_store_b8 v1, v6 offset:6
+; GFX11-NEXT: ds_store_b8 v1, v7 offset:7
+; GFX11-NEXT: ds_store_b8 v1, v3 offset:8
+; GFX11-NEXT: ds_store_b8 v1, v12 offset:9
+; GFX11-NEXT: ds_store_b8 v1, v8 offset:10
+; GFX11-NEXT: ds_store_b8 v1, v10 offset:11
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align1:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -426,7 +418,6 @@ define amdgpu_kernel void @store_lds_v3i32_align2(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: ds_store_b16 v1, v4 offset:8
; GFX11-NEXT: ds_store_b16 v1, v6 offset:10
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align2:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -522,7 +513,6 @@ define amdgpu_kernel void @store_lds_v3i32_align4(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: ds_store_2addr_b32 v1, v0, v2 offset1:1
; GFX11-NEXT: ds_store_b32 v1, v3 offset:8
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align4:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dword s6, s[4:5], 0x0
@@ -597,7 +587,6 @@ define amdgpu_kernel void @store_lds_v3i32_align8(ptr addrspace(3) %out, <3 x i3
; GFX11-NEXT: ds_store_2addr_b32 v1, v0, v2 offset1:1
; GFX11-NEXT: ds_store_b32 v1, v3 offset:8
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
@@ -671,7 +660,6 @@ define amdgpu_kernel void @store_lds_v3i32_align16(ptr addrspace(3) %out, <3 x i
; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3
; GFX11-NEXT: ds_store_b96 v3, v[0:2]
; GFX11-NEXT: s_endpgm
-;
; GFX6-LABEL: store_lds_v3i32_align16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x4
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
index b833480c267f0..b4b93614a03a6 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/strict_fma.f16.ll
@@ -39,7 +39,7 @@ define void @v_constained_fma_f16_fpexcept_strict_uni(half inreg %x, half inreg
; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_uni:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_f16 v2.l, s0, s1, v2.l
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -55,7 +55,7 @@ define void @v_constained_fma_f16_fpexcept_strict_uni(half inreg %x, half inreg
; GFX12-NEXT: s_fmac_f16 s2, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s2
+; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%val = call half @llvm.experimental.constrained.fma.f16(half %x, half %y, half %z, metadata !"round.tonearest", metadata !"fpexcept.strict")
@@ -511,7 +511,7 @@ define void @v_constained_fma_f16_fpexcept_strict_fneg_uni(half inreg %x, half i
; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_uni:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s1
+; GFX11-NEXT: v_mov_b32_e32 v2, s1
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_f16 v2.l, s0, v2.l, -s2
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -529,7 +529,7 @@ define void @v_constained_fma_f16_fpexcept_strict_fneg_uni(half inreg %x, half i
; GFX12-NEXT: s_fmac_f16 s2, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s2
+; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.z = fneg half %z
@@ -622,7 +622,7 @@ define void @v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni(half inreg %x, h
; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_f16 v2.l, -s0, -s1, v2.l
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -641,7 +641,7 @@ define void @v_constained_fma_f16_fpexcept_strict_fneg_fneg_uni(half inreg %x, h
; GFX12-NEXT: s_fmac_f16 s2, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s2
+; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.x = fneg half %x
@@ -736,7 +736,7 @@ define void @v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni(half inreg %x, h
; GFX11-LABEL: v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s2
+; GFX11-NEXT: v_mov_b32_e32 v2, s2
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_fma_f16 v2.l, |s0|, |s1|, v2.l
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
@@ -755,7 +755,7 @@ define void @v_constained_fma_f16_fpexcept_strict_fabs_fabs_uni(half inreg %x, h
; GFX12-NEXT: s_fmac_f16 s2, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s2
+; GFX12-NEXT: v_mov_b32_e32 v2, s2
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_setpc_b64 s[30:31]
%neg.x = call half @llvm.fabs.f16(half %x) #0
diff --git a/llvm/test/CodeGen/AMDGPU/bitreverse.ll b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
index a0eb268fe6d51..5554bbe44b4f1 100644
--- a/llvm/test/CodeGen/AMDGPU/bitreverse.ll
+++ b/llvm/test/CodeGen/AMDGPU/bitreverse.ll
@@ -72,33 +72,19 @@ define amdgpu_kernel void @s_brev_i16(ptr addrspace(1) noalias %out, i16 %val) #
; GFX11-FLAT-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1]
; GFX11-FLAT-NEXT: s_endpgm
;
-; GFX11-GISEL-TRUE16-LABEL: s_brev_i16:
-; GFX11-GISEL-TRUE16: ; %bb.0:
-; GFX11-GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX11-GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: s_brev_b32 s2, s2
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX11-GISEL-FAKE16-LABEL: s_brev_i16:
-; GFX11-GISEL-FAKE16: ; %bb.0:
-; GFX11-GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX11-GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX11-GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: s_brev_b32 s2, s2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-GISEL-FAKE16-NEXT: s_endpgm
+; GFX11-GISEL-LABEL: s_brev_i16:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_clause 0x1
+; GFX11-GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX11-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_brev_b32 s2, s2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-GISEL-NEXT: s_endpgm
%brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
store i16 %brev, ptr addrspace(1) %out
ret void
@@ -175,35 +161,20 @@ define amdgpu_kernel void @v_brev_i16(ptr addrspace(1) noalias %out, ptr addrspa
; GFX11-FLAT-NEXT: global_store_d16_hi_b16 v1, v0, s[0:1]
; GFX11-FLAT-NEXT: s_endpgm
;
-; GFX11-GISEL-TRUE16-LABEL: v_brev_i16:
-; GFX11-GISEL-TRUE16: ; %bb.0:
-; GFX11-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: global_load_u16 v0, v1, s[2:3]
-; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-GISEL-TRUE16-NEXT: s_brev_b32 s2, s2
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX11-GISEL-FAKE16-LABEL: v_brev_i16:
-; GFX11-GISEL-FAKE16: ; %bb.0:
-; GFX11-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, 0
-; GFX11-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: global_load_u16 v1, v0, s[2:3]
-; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-GISEL-FAKE16-NEXT: v_readfirstlane_b32 s2, v1
-; GFX11-GISEL-FAKE16-NEXT: s_brev_b32 s2, s2
-; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-GISEL-FAKE16-NEXT: s_lshr_b32 s2, s2, 16
-; GFX11-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, s2
-; GFX11-GISEL-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-GISEL-FAKE16-NEXT: s_endpgm
+; GFX11-GISEL-LABEL: v_brev_i16:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: global_load_u16 v1, v0, s[2:3]
+; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v1
+; GFX11-GISEL-NEXT: s_brev_b32 s2, s2
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX11-GISEL-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-GISEL-NEXT: s_endpgm
%val = load i16, ptr addrspace(1) %valptr
%brev = call i16 @llvm.bitreverse.i16(i16 %val) #1
store i16 %brev, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
index e1c26a02f9a5d..c9de2001e024a 100644
--- a/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
+++ b/llvm/test/CodeGen/AMDGPU/dagcombine-fmul-sel.ll
@@ -2875,25 +2875,46 @@ define bfloat @fmul_select_bf16_test1(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test1:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0x3f80 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4000, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test1:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test1:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x3f80 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x4000, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat 2.000000e+00, bfloat 1.000000e+00
%ldexp = fmul bfloat %x, %y
@@ -3041,25 +3062,46 @@ define bfloat @fmul_select_bf16_test2(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test2:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0x3f80 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x3f00, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test2:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x3f00 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test2:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x3f80 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x3f00, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat 5.000000e-01, bfloat 1.000000e+00
%ldexp = fmul bfloat %x, %y
@@ -3300,36 +3342,38 @@ define <2 x bfloat> @fmul_select_v2bf16_test3(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2bf16_test3:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v5, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v5, 0x4000
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v6, 0x3f80
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, v5, 0x4000, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, v5, 0x4000, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v1 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-GISEL-TRUE16-NEXT: v_dual_cndmask_b32 v1, v6, v5 :: v_dual_mul_f32 v2, v3, v2
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v2, v3, v2
-; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v2
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3605,36 +3649,38 @@ define <2 x bfloat> @fmul_select_v2bf16_test4(<2 x bfloat> %x, <2 x i32> %bool.a
; GFX11-GISEL-TRUE16-LABEL: fmul_select_v2bf16_test4:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v5, 0x3f80
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v5, 0x3f00
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v6, 0x3f80
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v2, v4
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4)
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v2, v5, 0x3f00, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v2, v6, v5, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v3
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.h
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e64 v1, v5, 0x3f00, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-TRUE16-NEXT: v_dual_mul_f32 v0, v0, v1 :: v_dual_lshlrev_b32 v3, 16, v3
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-GISEL-TRUE16-NEXT: v_dual_cndmask_b32 v1, v6, v5 :: v_dual_mul_f32 v2, v3, v2
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v2, v3, v2
-; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v2, 16, 1
; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v2
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
-; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v2, 0x7fff
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3818,25 +3864,46 @@ define bfloat @fmul_select_bf16_test5(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test5:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4000, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test5:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x4000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0x4100
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test5:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x4000, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat 2.000000e+00, bfloat 8.000000e+00
%ldexp = fmul bfloat %x, %y
@@ -3986,25 +4053,46 @@ define bfloat @fmul_select_bf16_test6(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test6:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0x4040 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc100, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test6:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0xc100 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0x4040
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test6:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x4040 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0xc100, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat -8.000000e+00, bfloat 3.000000e+00
%ldexp = fmul bfloat %x, %y
@@ -4153,25 +4241,46 @@ define bfloat @fmul_select_bf16_test7(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test7:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0xc080 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x4100, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test7:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x4100 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc080
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test7:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0xc080 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x4100, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat 8.000000e+00, bfloat -4.000000e+00
%ldexp = fmul bfloat %x, %y
@@ -4314,24 +4423,45 @@ define bfloat @fmul_select_bf16_test8(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test8:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test8:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x8000 :: v_dual_mov_b32 v4, 0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test8:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x8000, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat -0.000000e+00, bfloat 0.000000e+00
%ldexp = fmul bfloat %x, %y
@@ -4481,25 +4611,46 @@ define bfloat @fmul_select_bf16_test9(bfloat %x, i32 %bool.arg1, i32 %bool.arg2)
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test9:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0xc200 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xc180, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test9:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0xc180 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0xc200
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test9:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0xc200 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0xc180, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat -1.600000e+01, bfloat -3.200000e+01
%ldexp = fmul bfloat %x, %y
@@ -4649,25 +4800,46 @@ define bfloat @fmul_select_bf16_test10_sel_log2val_pos65_pos56(bfloat %x, i32 %b
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0xdb80 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0xe000, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0xe000 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0xdb80
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test10_sel_log2val_pos65_pos56:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0xdb80 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0xe000, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat 0xRE000, bfloat 0xRDB80
%ldexp = fmul bfloat %x, %y
@@ -4817,36 +4989,49 @@ define bfloat @fmul_select_bf16_test11_sel_log2val_neg22_pos25(bfloat %x, i32 %b
; GFX11-SDAG-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
; GFX11-SDAG-FAKE16-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-GISEL-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
-; GFX11-GISEL: ; %bb.0:
-; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-NEXT: v_dual_mov_b32 v3, 0x4c00 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-GISEL-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, v3, 0x3480, vcc_lo
-; GFX11-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_mul_f32_e32 v0, v0, v1
-; GFX11-GISEL-NEXT: v_bfe_u32 v1, v0, 16, 1
-; GFX11-GISEL-NEXT: v_or_b32_e32 v2, 0x400000, v0
-; GFX11-GISEL-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
-; GFX11-GISEL-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
+; GFX11-GISEL-TRUE16-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
+; GFX11-GISEL-TRUE16: ; %bb.0:
+; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-TRUE16-NEXT: v_dual_mov_b32 v3, 0x3480 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v4, 0x4c00
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-GISEL-FAKE16-LABEL: fmul_select_bf16_test11_sel_log2val_neg22_pos25:
+; GFX11-GISEL-FAKE16: ; %bb.0:
+; GFX11-GISEL-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-GISEL-FAKE16-NEXT: v_dual_mov_b32 v3, 0x4c00 :: v_dual_lshlrev_b32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, v1, v2
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e64 v1, v3, 0x3480, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-GISEL-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1
+; GFX11-GISEL-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0
+; GFX11-GISEL-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, 0, v0
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff
+; GFX11-GISEL-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo
+; GFX11-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-GISEL-FAKE16-NEXT: s_setpc_b64 s[30:31]
%bool = icmp eq i32 %bool.arg1, %bool.arg2
%y = select i1 %bool, bfloat 0xR3480, bfloat 0xR4C00
%ldexp = fmul bfloat %x, %y
ret bfloat %ldexp
}
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; GFX10: {{.*}}
-; GFX11: {{.*}}
-; GFX11-GISEL-FAKE16: {{.*}}
-; GFX11-GISEL-TRUE16: {{.*}}
-; GFX11-SDAG: {{.*}}
-; GFX7: {{.*}}
-; GFX9: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index 213d6ffeb9f00..6e2c47ac62c24 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -1530,7 +1530,7 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-TRUE16-NEXT: s_maximum_f16 s2, s2, s3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
index 25090bf693552..a183ea4ad2a73 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
@@ -1943,7 +1943,7 @@ define amdgpu_kernel void @test_fmax_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
@@ -2064,7 +2064,7 @@ define amdgpu_kernel void @test_fmax_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 094dd76e0f945..2156fc6f2397c 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -1530,7 +1530,7 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
; GFX12-GISEL-TRUE16-NEXT: s_minimum_f16 s2, s2, s3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll
index 06fb492792ae8..86329738d2520 100644
--- a/llvm/test/CodeGen/AMDGPU/fminnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll
@@ -1856,7 +1856,7 @@ define amdgpu_kernel void @test_fmin_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
@@ -1977,7 +1977,7 @@ define amdgpu_kernel void @test_fmin_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-GISEL-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
index 2618c670b8c23..61798f566c890 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_sint.ll
@@ -1298,7 +1298,7 @@ define amdgpu_kernel void @fp_to_sint_f32_i16(ptr addrspace(1) %out, float %in)
; GFX11-GISEL-NEXT: v_cvt_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
index 2fb9e0b764391..a0a37b4c02a42 100644
--- a/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
+++ b/llvm/test/CodeGen/AMDGPU/fp_to_uint.ll
@@ -1069,7 +1069,7 @@ define amdgpu_kernel void @fp_to_uint_f32_to_i16(ptr addrspace(1) %out, float %i
; GFX11-GISEL-NEXT: v_cvt_u32_f32_e32 v0, s2
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v0
-; GFX11-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-GISEL-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
index 36b3ea7492078..ef21fd1c90cb7 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.f16.ll
@@ -258,7 +258,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
@@ -533,7 +533,7 @@ define amdgpu_kernel void @fptrunc_f32_to_f16_afn(ptr addrspace(1) %r,
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
@@ -1201,7 +1201,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX11-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000
; GFX11-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-GISEL-TRUE16-NEXT: s_endpgm
@@ -1463,7 +1463,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000
; GFX1250-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
@@ -1801,7 +1801,7 @@ define amdgpu_kernel void @fptrunc_f64_to_f16_afn(
; GFX1250-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
@@ -4466,7 +4466,7 @@ define amdgpu_kernel void @fneg_fptrunc_f32_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
@@ -4748,7 +4748,7 @@ define amdgpu_kernel void @fabs_fptrunc_f32_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
@@ -5030,7 +5030,7 @@ define amdgpu_kernel void @fneg_fabs_fptrunc_f32_to_f16(
; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 0 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: s_cvt_f16_f32 s2, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX1250-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX1250-GISEL-TRUE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/fptrunc.ll b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
index 685fc615812dc..fb85ae0bef264 100644
--- a/llvm/test/CodeGen/AMDGPU/fptrunc.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptrunc.ll
@@ -479,173 +479,61 @@ define amdgpu_kernel void @fptrunc_f64_to_f16(ptr addrspace(1) %out, double %in)
; GFX11-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-SDAG-NEXT: s_endpgm
;
-; GFX11-SAFE-GISEL-LABEL: fptrunc_f64_to_f16:
-; GFX11-SAFE-GISEL: ; %bb.0:
-; GFX11-SAFE-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-SAFE-GISEL-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-SAFE-GISEL-NEXT: s_bfe_u32 s4, s3, 0xb0014
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s5, s3, 8
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff
-; GFX11-SAFE-GISEL-NEXT: s_addk_i32 s4, 0xfc10
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s5, s5, 0xffe
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s6, s2
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s5, s2
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_sub_i32 s6, 1, s4
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s8, s2, 0x1000
-; GFX11-SAFE-GISEL-NEXT: s_max_i32 s6, s6, 0
-; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s7, s4, 12
-; GFX11-SAFE-GISEL-NEXT: s_min_i32 s6, s6, 13
-; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s5, s5, 9
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s9, s8, s6
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s2, s7
-; GFX11-SAFE-GISEL-NEXT: s_lshl_b32 s6, s9, s6
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s5, s5, 0x7c00
-; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, s8
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s6, s9, s6
-; GFX11-SAFE-GISEL-NEXT: s_cmp_lt_i32 s4, 1
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, s6, s2
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s6, s2, 7
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s2, s2, 2
-; GFX11-SAFE-GISEL-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s6, s7, s6
-; GFX11-SAFE-GISEL-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_add_i32 s2, s2, s6
-; GFX11-SAFE-GISEL-NEXT: s_cmp_gt_i32 s4, 30
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
-; GFX11-SAFE-GISEL-NEXT: s_cmpk_eq_i32 s4, 0x40f
-; GFX11-SAFE-GISEL-NEXT: s_cselect_b32 s2, s5, s2
-; GFX11-SAFE-GISEL-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-SAFE-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-SAFE-GISEL-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX11-SAFE-GISEL-NEXT: s_or_b32 s2, s3, s2
-; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-SAFE-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-SAFE-GISEL-NEXT: s_mov_b32 s2, -1
-; GFX11-SAFE-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-SAFE-GISEL-NEXT: s_endpgm
-;
-; GFX11-UNSAFE-GISEL-TRUE16-LABEL: fptrunc_f64_to_f16:
-; GFX11-UNSAFE-GISEL-TRUE16: ; %bb.0:
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_bfe_u32 s4, s3, 0xb0014
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s5, s3, 8
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s6, s3, 0x1ff
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_addk_i32 s4, 0xfc10
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s5, s5, 0xffe
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s6, s2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s5, s2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_sub_i32 s6, 1, s4
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s8, s2, 0x1000
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_max_i32 s6, s6, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshl_b32 s7, s4, 12
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_min_i32 s6, s6, 13
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshl_b32 s5, s5, 9
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s9, s8, s6
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s2, s7
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshl_b32 s6, s9, s6
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s5, s5, 0x7c00
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, s8
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s6, s9, s6
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_lt_i32 s4, 1
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, s6, s2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s6, s2, 7
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s2, s2, 2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s6, s7, s6
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_add_i32 s2, s2, s6
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmp_gt_i32 s4, 30
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, 0x7c00, s2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cmpk_eq_i32 s4, 0x40f
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_cselect_b32 s2, s5, s2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-UNSAFE-GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX11-UNSAFE-GISEL-FAKE16-LABEL: fptrunc_f64_to_f16:
-; GFX11-UNSAFE-GISEL-FAKE16: ; %bb.0:
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_bfe_u32 s4, s3, 0xb0014
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s5, s3, 8
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s6, s3, 0x1ff
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_addk_i32 s4, 0xfc10
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s5, s5, 0xffe
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s6, s2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s5, s2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s5, 1, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_sub_i32 s6, 1, s4
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s8, s2, 0x1000
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_max_i32 s6, s6, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshl_b32 s7, s4, 12
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_min_i32 s6, s6, 13
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshl_b32 s5, s5, 9
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s9, s8, s6
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s2, s7
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshl_b32 s6, s9, s6
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s5, s5, 0x7c00
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, s8
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s6, s9, s6
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_lt_i32 s4, 1
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, s6, s2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s6, s2, 7
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s2, s2, 2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_eq_u32 s6, 3
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s7, 1, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s6, 5
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s6, s7, s6
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_lg_u32 s6, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s6, 1, 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_add_i32 s2, s2, s6
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmp_gt_i32 s4, 30
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, 0x7c00, s2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cmpk_eq_i32 s4, 0x40f
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_cselect_b32 s2, s5, s2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_and_b32 s3, s3, 0x8000
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_or_b32 s2, s3, s2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_mov_b32 s3, 0x31016000
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_mov_b32 s2, -1
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
-; GFX11-UNSAFE-GISEL-FAKE16-NEXT: s_endpgm
+; GFX11-GISEL-LABEL: fptrunc_f64_to_f16:
+; GFX11-GISEL: ; %bb.0:
+; GFX11-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX11-GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-GISEL-NEXT: s_bfe_u32 s4, s3, 0xb0014
+; GFX11-GISEL-NEXT: s_lshr_b32 s5, s3, 8
+; GFX11-GISEL-NEXT: s_and_b32 s6, s3, 0x1ff
+; GFX11-GISEL-NEXT: s_addk_i32 s4, 0xfc10
+; GFX11-GISEL-NEXT: s_and_b32 s5, s5, 0xffe
+; GFX11-GISEL-NEXT: s_or_b32 s2, s6, s2
+; GFX11-GISEL-NEXT: s_cselect_b32 s2, 1, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_or_b32 s2, s5, s2
+; GFX11-GISEL-NEXT: s_cselect_b32 s5, 1, 0
+; GFX11-GISEL-NEXT: s_sub_i32 s6, 1, s4
+; GFX11-GISEL-NEXT: s_or_b32 s8, s2, 0x1000
+; GFX11-GISEL-NEXT: s_max_i32 s6, s6, 0
+; GFX11-GISEL-NEXT: s_lshl_b32 s7, s4, 12
+; GFX11-GISEL-NEXT: s_min_i32 s6, s6, 13
+; GFX11-GISEL-NEXT: s_lshl_b32 s5, s5, 9
+; GFX11-GISEL-NEXT: s_lshr_b32 s9, s8, s6
+; GFX11-GISEL-NEXT: s_or_b32 s2, s2, s7
+; GFX11-GISEL-NEXT: s_lshl_b32 s6, s9, s6
+; GFX11-GISEL-NEXT: s_or_b32 s5, s5, 0x7c00
+; GFX11-GISEL-NEXT: s_cmp_lg_u32 s6, s8
+; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_or_b32 s6, s9, s6
+; GFX11-GISEL-NEXT: s_cmp_lt_i32 s4, 1
+; GFX11-GISEL-NEXT: s_cselect_b32 s2, s6, s2
+; GFX11-GISEL-NEXT: s_and_b32 s6, s2, 7
+; GFX11-GISEL-NEXT: s_lshr_b32 s2, s2, 2
+; GFX11-GISEL-NEXT: s_cmp_eq_u32 s6, 3
+; GFX11-GISEL-NEXT: s_cselect_b32 s7, 1, 0
+; GFX11-GISEL-NEXT: s_cmp_gt_i32 s6, 5
+; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_or_b32 s6, s7, s6
+; GFX11-GISEL-NEXT: s_cmp_lg_u32 s6, 0
+; GFX11-GISEL-NEXT: s_cselect_b32 s6, 1, 0
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_add_i32 s2, s2, s6
+; GFX11-GISEL-NEXT: s_cmp_gt_i32 s4, 30
+; GFX11-GISEL-NEXT: s_cselect_b32 s2, 0x7c00, s2
+; GFX11-GISEL-NEXT: s_cmpk_eq_i32 s4, 0x40f
+; GFX11-GISEL-NEXT: s_cselect_b32 s2, s5, s2
+; GFX11-GISEL-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX11-GISEL-NEXT: s_and_b32 s3, s3, 0x8000
+; GFX11-GISEL-NEXT: s_or_b32 s2, s3, s2
+; GFX11-GISEL-NEXT: s_mov_b32 s3, 0x31016000
+; GFX11-GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX11-GISEL-NEXT: s_mov_b32 s2, -1
+; GFX11-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-GISEL-NEXT: s_endpgm
%result = fptrunc double %in to half
%result_i16 = bitcast half %result to i16
store i16 %result_i16, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
index f51d7f5a2fff8..e3165c1b88093 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-preserve-cc.ll
@@ -742,10 +742,11 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_half(half inre
; GISEL-GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
; GISEL-GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
; GISEL-GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
- ; GISEL-GFX11-TRUE16-NEXT: [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY3]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[DEF]]
- ; GISEL-GFX11-TRUE16-NEXT: FLAT_STORE_SHORT_t16 [[COPY4]], [[V_ADD_F16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (f16) into `ptr poison`)
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY4:%[0-9]+]]:vgpr_16 = COPY [[COPY3]].lo16
+ ; GISEL-GFX11-TRUE16-NEXT: [[V_ADD_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_ADD_F16_t16_e64 0, [[COPY4]], 0, [[COPY2]], 0, 0, 0, implicit $mode, implicit $exec
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+ ; GISEL-GFX11-TRUE16-NEXT: FLAT_STORE_SHORT_t16 [[COPY5]], [[V_ADD_F16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (f16) into `ptr poison`)
; GISEL-GFX11-TRUE16-NEXT: S_ENDPGM 0
;
; GISEL-GFX11-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_half
@@ -950,10 +951,11 @@ define amdgpu_cs_chain_preserve void @amdgpu_cs_chain_preserve_cc_i16(i16 inreg
; GISEL-GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
; GISEL-GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
; GISEL-GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY]]
- ; GISEL-GFX11-TRUE16-NEXT: [[V_ADD_NC_U16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_NC_U16_t16_e64 0, [[COPY3]], 0, [[COPY2]], 0, 0, implicit $exec
- ; GISEL-GFX11-TRUE16-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[DEF]]
- ; GISEL-GFX11-TRUE16-NEXT: FLAT_STORE_SHORT_t16 [[COPY4]], [[V_ADD_NC_U16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (i16) into `ptr poison`)
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]]
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY4:%[0-9]+]]:vgpr_16 = COPY [[COPY3]].lo16
+ ; GISEL-GFX11-TRUE16-NEXT: [[V_ADD_NC_U16_t16_e64_:%[0-9]+]]:vgpr_16 = V_ADD_NC_U16_t16_e64 0, [[COPY4]], 0, [[COPY2]], 0, 0, implicit $exec
+ ; GISEL-GFX11-TRUE16-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[DEF]]
+ ; GISEL-GFX11-TRUE16-NEXT: FLAT_STORE_SHORT_t16 [[COPY5]], [[V_ADD_NC_U16_t16_e64_]], 0, 0, implicit $exec, implicit $flat_scr :: (store (i16) into `ptr poison`)
; GISEL-GFX11-TRUE16-NEXT: S_ENDPGM 0
;
; GISEL-GFX11-FAKE16-LABEL: name: amdgpu_cs_chain_preserve_cc_i16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
index 3b5000fc4443d..3fb6d9d1bf244 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
@@ -325,7 +325,8 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-TRUE16-NEXT: v_nop
; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
; GFX1250-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
index b0c68735831af..97c83fd2f9545 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
@@ -286,8 +286,12 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
; GFX1250-GISEL-REAL16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-REAL16-NEXT: v_nop
; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.h, v0 byte_sel:3
-; GFX1250-GISEL-REAL16-NEXT: v_mov_b16_e32 v0.l, 0
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_bf8_byte3_hi:
@@ -531,8 +535,12 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
; GFX1250-GISEL-REAL16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-REAL16-NEXT: v_nop
; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.h, v0 byte_sel:3
-; GFX1250-GISEL-REAL16-NEXT: v_mov_b16_e32 v0.l, 0
+; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b16_e32 v1.h, v0.l
+; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v0, v1
; GFX1250-GISEL-REAL16-NEXT: ; return to shader part epilog
;
; GFX1250-GISEL-FAKE16-LABEL: test_cvt_f16_fp8_byte3_hi:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
index e284f99fa05b6..452b83a7fbd36 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
@@ -166,7 +166,7 @@ define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(
;
; GISEL-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
; GISEL-GFX11-TRUE16: ; %bb.0: ; %entry
-; GISEL-GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1
+; GISEL-GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s1
; GISEL-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GISEL-GFX11-TRUE16-NEXT: v_dot2_bf16_bf16 v2.l, s0, 0x3f803f80, v2.l
; GISEL-GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll
index 1a05c8ff127f5..a772ce5f8f8ee 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.ptr.s.buffer.load-gfx12.ll
@@ -95,7 +95,7 @@ define amdgpu_kernel void @ptr_s_buffer_load_i16(ptr addrspace(1) %out, ptr addr
; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1200-GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s6 offset:0x0
; GFX1200-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1200-GISEL-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX1200-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1200-GISEL-NEXT: global_store_b16 v1, v0, s[4:5]
; GFX1200-GISEL-NEXT: s_endpgm
;
@@ -128,7 +128,7 @@ define amdgpu_kernel void @ptr_s_buffer_load_i16(ptr addrspace(1) %out, ptr addr
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX1250-GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s8 offset:0x0 nv
; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0
-; GFX1250-GISEL-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, s0
; GFX1250-GISEL-NEXT: global_store_b16 v1, v0, s[6:7]
; GFX1250-GISEL-NEXT: s_endpgm
%load = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %rsrc, i32 %offset, i32 0), !invariant.load !0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
index bdfe37fb28463..1969ae6a47e7e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.buffer.load.ll
@@ -1350,7 +1350,7 @@ define amdgpu_ps void @raw_buffer_load_f16(<4 x i32> inreg %rsrc, ptr addrspace(
; GFX12-GISEL-TRUE16-NEXT: buffer_load_u16 v1, off, s[0:3], null
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v1
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, s0
; GFX12-GISEL-TRUE16-NEXT: ds_store_b16 v0, v1
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
main_body:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
index 4d367c1eb3c06..c4a8301c05dd5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.add.ll
@@ -183,21 +183,21 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_sext_i32_i16 s3, s6
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_sext_i32_i16 s3, s6
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -215,53 +215,21 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_sext_i32_i16 s3, s6
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_sext_i32_i16 s2, s2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_mul_i32 s2, s2, s3
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
; GFX12DAGISEL-LABEL: uniform_value_i16:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
@@ -5156,5 +5124,9 @@ attributes #0 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1132DAGISEL-FAKE16: {{.*}}
; GFX1132DAGISEL-TRUE16: {{.*}}
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
; GFX1164DAGISEL-FAKE16: {{.*}}
; GFX1164DAGISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
index c876aa657338d..9d5aa73de8324 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.and.ll
@@ -126,18 +126,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -151,44 +151,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.and.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -4045,3 +4019,8 @@ endif:
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
index 7bc7f987bb2d4..65af1f6d6596c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.max.ll
@@ -126,18 +126,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_sext_i32_i16 s2, s2
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -151,44 +151,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_sext_i32_i16 s2, s2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.max.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -4220,5 +4194,9 @@ attributes #0 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1132DAGISEL-FAKE16: {{.*}}
; GFX1132DAGISEL-TRUE16: {{.*}}
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
; GFX1164DAGISEL-FAKE16: {{.*}}
; GFX1164DAGISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
index 6f472a6e18584..f42da8cd7df37 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.min.ll
@@ -126,18 +126,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_sext_i32_i16 s2, s2
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -151,44 +151,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_sext_i32_i16 s2, s2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.min.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -4220,5 +4194,9 @@ attributes #0 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1132DAGISEL-FAKE16: {{.*}}
; GFX1132DAGISEL-TRUE16: {{.*}}
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
; GFX1164DAGISEL-FAKE16: {{.*}}
; GFX1164DAGISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
index 1f3d19668f86b..75a6c7d580573 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.or.ll
@@ -126,18 +126,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -151,44 +151,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.or.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -4046,3 +4020,8 @@ endif:
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
index ae2dcfac5a4d0..58e47554ff89e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.sub.ll
@@ -195,23 +195,23 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_sext_i32_i16 s4, s6
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: s_sub_i32 s3, 0, s4
-; GFX1164GISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_sext_i32_i16 s4, s6
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_sub_i32 s3, 0, s4
+; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -230,59 +230,23 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: s_sub_i32 s2, 0, s2
-; GFX1132GISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_sext_i32_i16 s4, s6
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: s_sub_i32 s3, 0, s4
-; GFX1164GISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_sext_i32_i16 s2, s2
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: s_sub_i32 s2, 0, s2
-; GFX1132GISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_sext_i32_i16 s2, s2
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_sub_i32 s2, 0, s2
+; GFX1132GISEL-NEXT: s_mul_i32 s2, s2, s3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
; GFX12DAGISEL-LABEL: uniform_value_i16:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
@@ -5287,5 +5251,9 @@ attributes #0 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX1132DAGISEL-FAKE16: {{.*}}
; GFX1132DAGISEL-TRUE16: {{.*}}
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
; GFX1164DAGISEL-FAKE16: {{.*}}
; GFX1164DAGISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
index 69b24c6f1b17a..5f12243bd0cec 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umax.ll
@@ -126,18 +126,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -151,44 +151,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
; GFX11GISEL-LABEL: uniform_value_i16:
; GFX11GISEL: ; %bb.0: ; %entry
; GFX11GISEL-NEXT: s_clause 0x1
@@ -4387,3 +4361,8 @@ endif:
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
index 7a3a939891089..12357cc9e8726 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.umin.ll
@@ -126,18 +126,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -151,44 +151,18 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.umin.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -4191,3 +4165,8 @@ endif:
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
index 7d6c296515733..8e4d7708091b3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.xor.ll
@@ -195,23 +195,23 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1164DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1164DAGISEL-NEXT: s_endpgm
;
-; GFX1164GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1164GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1164GISEL-FAKE16-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX1164GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-FAKE16-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-FAKE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 1
-; GFX1164GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-FAKE16-NEXT: s_and_b32 s3, s6, 0xffff
-; GFX1164GISEL-FAKE16-NEXT: s_mul_i32 s2, s3, s2
-; GFX1164GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1164GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-FAKE16-NEXT: s_endpgm
+; GFX1164GISEL-LABEL: uniform_value_i16:
+; GFX1164GISEL: ; %bb.0: ; %entry
+; GFX1164GISEL-NEXT: s_clause 0x1
+; GFX1164GISEL-NEXT: s_load_b32 s6, s[4:5], 0x2c
+; GFX1164GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1164GISEL-NEXT: s_mov_b64 s[2:3], exec
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1164GISEL-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: s_and_b32 s2, s2, 1
+; GFX1164GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1164GISEL-NEXT: s_and_b32 s3, s6, 0xffff
+; GFX1164GISEL-NEXT: s_mul_i32 s2, s3, s2
+; GFX1164GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1164GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1164GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1164GISEL-NEXT: s_endpgm
;
; GFX1132DAGISEL-LABEL: uniform_value_i16:
; GFX1132DAGISEL: ; %bb.0: ; %entry
@@ -230,59 +230,23 @@ define amdgpu_kernel void @uniform_value_i16(ptr addrspace(1) %out, i16 %in) {
; GFX1132DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX1132DAGISEL-NEXT: s_endpgm
;
-; GFX1132GISEL-FAKE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-FAKE16: ; %bb.0: ; %entry
-; GFX1132GISEL-FAKE16-NEXT: s_clause 0x1
-; GFX1132GISEL-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-FAKE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-FAKE16-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s3, s3, 1
-; GFX1132GISEL-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-FAKE16-NEXT: s_mul_i32 s2, s2, s3
-; GFX1132GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX1132GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-FAKE16-NEXT: s_endpgm
-;
-; GFX1164GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1164GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1164GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1164GISEL-TRUE16-NEXT: s_load_b32 s6, s[4:5], 0x2c
-; GFX1164GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1164GISEL-TRUE16-NEXT: s_mov_b64 s[2:3], exec
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1164GISEL-TRUE16-NEXT: s_bcnt1_i32_b64 s2, s[2:3]
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 1
-; GFX1164GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1164GISEL-TRUE16-NEXT: s_and_b32 s3, s6, 0xffff
-; GFX1164GISEL-TRUE16-NEXT: s_mul_i32 s2, s3, s2
-; GFX1164GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1164GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1164GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1164GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX1132GISEL-TRUE16-LABEL: uniform_value_i16:
-; GFX1132GISEL-TRUE16: ; %bb.0: ; %entry
-; GFX1132GISEL-TRUE16-NEXT: s_clause 0x1
-; GFX1132GISEL-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x2c
-; GFX1132GISEL-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
-; GFX1132GISEL-TRUE16-NEXT: s_mov_b32 s3, exec_lo
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX1132GISEL-TRUE16-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s3, s3, 1
-; GFX1132GISEL-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX1132GISEL-TRUE16-NEXT: s_and_b32 s2, s2, 0xffff
-; GFX1132GISEL-TRUE16-NEXT: s_mul_i32 s2, s2, s3
-; GFX1132GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1132GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1132GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX1132GISEL-TRUE16-NEXT: s_endpgm
+; GFX1132GISEL-LABEL: uniform_value_i16:
+; GFX1132GISEL: ; %bb.0: ; %entry
+; GFX1132GISEL-NEXT: s_clause 0x1
+; GFX1132GISEL-NEXT: s_load_b32 s2, s[4:5], 0x2c
+; GFX1132GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
+; GFX1132GISEL-NEXT: s_mov_b32 s3, exec_lo
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX1132GISEL-NEXT: s_bcnt1_i32_b32 s3, s3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: s_and_b32 s3, s3, 1
+; GFX1132GISEL-NEXT: s_waitcnt lgkmcnt(0)
+; GFX1132GISEL-NEXT: s_and_b32 s2, s2, 0xffff
+; GFX1132GISEL-NEXT: s_mul_i32 s2, s2, s3
+; GFX1132GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX1132GISEL-NEXT: v_mov_b32_e32 v0, s2
+; GFX1132GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX1132GISEL-NEXT: s_endpgm
entry:
%result = call i16 @llvm.amdgcn.wave.reduce.xor.i16(i16 %in, i32 1)
store i16 %result, ptr addrspace(1) %out
@@ -4841,3 +4805,8 @@ entry:
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX1132GISEL-FAKE16: {{.*}}
+; GFX1132GISEL-TRUE16: {{.*}}
+; GFX1164GISEL-FAKE16: {{.*}}
+; GFX1164GISEL-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
index e5979d8c99b60..d2199772c1b25 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.rsq.f16.ll
@@ -159,7 +159,7 @@ define amdgpu_kernel void @rsq_f16(
; GISEL-GFX12-TRUE16-NEXT: v_s_rsq_f16 s2, s2
; GISEL-GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GISEL-GFX12-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
-; GISEL-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GISEL-GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s2, -1
; GISEL-GFX12-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GISEL-GFX12-TRUE16-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
index 2ab76c99095f8..c29a124706d13 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
@@ -693,20 +693,35 @@ define amdgpu_gs void @s_fptrunc_round_f32_to_f16_upward_multiple_calls(float in
; GISEL-NEXT: global_store_short v[0:1], v2, off
; GISEL-NEXT: s_endpgm
;
-; GFX12-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls:
-; GFX12: ; %bb.0:
-; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
-; GFX12-NEXT: s_cvt_f16_f32 s0, s0
-; GFX12-NEXT: s_cvt_f16_f32 s2, s1
-; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 2
-; GFX12-NEXT: s_cvt_f16_f32 s1, s1
-; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
-; GFX12-NEXT: s_add_f16 s0, s0, s2
-; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
-; GFX12-NEXT: s_add_f16 s0, s1, s0
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
+; GFX12-SDAG-NEXT: s_cvt_f16_f32 s0, s0
+; GFX12-SDAG-NEXT: s_cvt_f16_f32 s2, s1
+; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 2
+; GFX12-SDAG-NEXT: s_cvt_f16_f32 s1, s1
+; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
+; GFX12-SDAG-NEXT: s_add_f16 s0, s0, s2
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
+; GFX12-SDAG-NEXT: s_add_f16 s0, s1, s0
+; GFX12-SDAG-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-SDAG-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-SDAG-NEXT: s_endpgm
+;
+; GFX12-GISEL-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
+; GFX12-GISEL-NEXT: s_cvt_f16_f32 s0, s0
+; GFX12-GISEL-NEXT: s_cvt_f16_f32 s2, s1
+; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 2
+; GFX12-GISEL-NEXT: s_cvt_f16_f32 s1, s1
+; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
+; GFX12-GISEL-NEXT: s_add_f16 s0, s0, s2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
+; GFX12-GISEL-NEXT: s_add_f16 s0, s1, s0
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-GISEL-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-GISEL-NEXT: s_endpgm
%res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")
%res2 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.upward")
%res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.downward")
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
index bcaba060b812f..4e82a8f68366d 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.sqrt.f16.ll
@@ -146,7 +146,7 @@ define amdgpu_kernel void @sqrt_f16(
; GFX12-TRUE16-GISEL-NEXT: v_s_sqrt_f16 s2, s2
; GFX12-TRUE16-GISEL-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(TRANS32_DEP_1)
-; GFX12-TRUE16-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-TRUE16-GISEL-NEXT: s_mov_b32 s2, -1
; GFX12-TRUE16-GISEL-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-TRUE16-GISEL-NEXT: s_endpgm
diff --git a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
index 10f6984276d69..32091c78120a1 100644
--- a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
@@ -228,11 +228,10 @@ define amdgpu_ps void @s_test_minmax_f16(half inreg %a, half inreg %b, half inre
;
; GFX1170-GISEL-TRUE16-LABEL: s_test_minmax_f16:
; GFX1170-GISEL-TRUE16: ; %bb.0:
-; GFX1170-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1170-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1170-GISEL-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; GFX1170-GISEL-TRUE16-NEXT: s_mov_b32 s6, s3
; GFX1170-GISEL-TRUE16-NEXT: s_mov_b32 s7, s4
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_maximumminimum_f16 v0.l, s0, s1, v0.l
; GFX1170-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
; GFX1170-GISEL-TRUE16-NEXT: s_endpgm
@@ -270,29 +269,17 @@ define amdgpu_ps void @s_test_minmax_f16(half inreg %a, half inreg %b, half inre
; GFX12-SDAG-FAKE16-NEXT: global_store_b16 v0, v1, s[4:5]
; GFX12-SDAG-FAKE16-NEXT: s_endpgm
;
-; GFX12-GISEL-TRUE16-LABEL: s_test_minmax_f16:
-; GFX12-GISEL-TRUE16: ; %bb.0:
-; GFX12-GISEL-TRUE16-NEXT: s_maximum_f16 s0, s0, s1
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GISEL-TRUE16-NEXT: s_mov_b32 s6, s3
-; GFX12-GISEL-TRUE16-NEXT: s_mov_b32 s7, s4
-; GFX12-GISEL-TRUE16-NEXT: s_minimum_f16 s0, s0, s2
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GFX12-GISEL-TRUE16-NEXT: s_endpgm
-;
-; GFX12-GISEL-FAKE16-LABEL: s_test_minmax_f16:
-; GFX12-GISEL-FAKE16: ; %bb.0:
-; GFX12-GISEL-FAKE16-NEXT: s_maximum_f16 s0, s0, s1
-; GFX12-GISEL-FAKE16-NEXT: s_mov_b32 s6, s3
-; GFX12-GISEL-FAKE16-NEXT: s_mov_b32 s7, s4
-; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-GISEL-FAKE16-NEXT: s_minimum_f16 s0, s0, s2
-; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX12-GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GFX12-GISEL-FAKE16-NEXT: s_endpgm
+; GFX12-GISEL-LABEL: s_test_minmax_f16:
+; GFX12-GISEL: ; %bb.0:
+; GFX12-GISEL-NEXT: s_maximum_f16 s0, s0, s1
+; GFX12-GISEL-NEXT: s_mov_b32 s6, s3
+; GFX12-GISEL-NEXT: s_mov_b32 s7, s4
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-GISEL-NEXT: s_minimum_f16 s0, s0, s2
+; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
+; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GFX12-GISEL-NEXT: global_store_b16 v1, v0, s[6:7]
+; GFX12-GISEL-NEXT: s_endpgm
%smax = call half @llvm.maximum.f16(half %a, half %b)
%sminmax = call half @llvm.minimum.f16(half %smax, half %c)
store half %sminmax, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index 93c9e67bda589..e24f50f91bf1b 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -113,10 +113,9 @@ define amdgpu_ps void @s_test_minmax_i32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; SDAG-GFX1250-LABEL: s_test_minmax_i32:
; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-NEXT: v_nop
-; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-NEXT: s_max_i32 s0, s0, s1
; SDAG-GFX1250-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-NEXT: s_min_i32 s0, s0, s2
@@ -127,10 +126,9 @@ define amdgpu_ps void @s_test_minmax_i32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; GISEL-GFX1250-LABEL: s_test_minmax_i32:
; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-GFX1250-NEXT: v_nop
-; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-NEXT: s_max_i32 s0, s0, s1
; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
; GISEL-GFX1250-NEXT: s_min_i32 s0, s0, s2
@@ -384,10 +382,9 @@ define amdgpu_ps void @s_test_minmax_u32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; SDAG-GFX1250-LABEL: s_test_minmax_u32:
; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-NEXT: v_nop
-; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-NEXT: s_max_u32 s0, s0, s1
; SDAG-GFX1250-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-NEXT: s_min_u32 s0, s0, s2
@@ -398,10 +395,9 @@ define amdgpu_ps void @s_test_minmax_u32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; GISEL-GFX1250-LABEL: s_test_minmax_u32:
; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-GFX1250-NEXT: v_nop
-; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-NEXT: s_max_u32 s0, s0, s1
; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
; GISEL-GFX1250-NEXT: s_min_u32 s0, s0, s2
@@ -698,10 +694,9 @@ define amdgpu_ps void @s_test_minmax_f32_ieee_false(float inreg %a, float inreg
;
; SDAG-GFX1250-LABEL: s_test_minmax_f32_ieee_false:
; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-NEXT: v_nop
-; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1250-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-NEXT: s_mov_b32 s4, s3
@@ -711,10 +706,9 @@ define amdgpu_ps void @s_test_minmax_f32_ieee_false(float inreg %a, float inreg
;
; GISEL-GFX1250-LABEL: s_test_minmax_f32_ieee_false:
; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-GFX1250-NEXT: v_nop
-; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-NEXT: s_max_num_f32 s0, s0, s1
; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
; GISEL-GFX1250-NEXT: s_mov_b32 s7, s4
@@ -747,10 +741,9 @@ define amdgpu_ps float @test_minmax_commuted_f32_ieee_false(float %a, float %b,
;
; GFX1250-LABEL: test_minmax_commuted_f32_ieee_false:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%max = call float @llvm.maxnum.f32(float %a, float %b)
@@ -855,10 +848,9 @@ define amdgpu_ps float @test_maxmin_commuted_f32_ieee_false(float %a, float %b,
;
; GFX1250-LABEL: test_maxmin_commuted_f32_ieee_false:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GFX1250-NEXT: v_nop
-; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-NEXT: v_minmax_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%min = call float @llvm.minnum.f32(float %a, float %b)
@@ -1011,37 +1003,33 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
;
; SDAG-GFX1250-TRUE16-LABEL: test_minmax_f16_ieee_false:
; SDAG-GFX1250-TRUE16: ; %bb.0:
-; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-TRUE16-NEXT: v_nop
-; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; SDAG-GFX1250-FAKE16-LABEL: test_minmax_f16_ieee_false:
; SDAG-GFX1250-FAKE16: ; %bb.0:
-; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-FAKE16-NEXT: v_nop
-; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-TRUE16-LABEL: test_minmax_f16_ieee_false:
; GISEL-GFX1250-TRUE16: ; %bb.0:
-; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-GFX1250-TRUE16-NEXT: v_nop
-; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-FAKE16-LABEL: test_minmax_f16_ieee_false:
; GISEL-GFX1250-FAKE16: ; %bb.0:
-; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-GFX1250-FAKE16-NEXT: v_nop
-; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: ; return to shader part epilog
%max = call half @llvm.maxnum.f16(half %a, half %b)
@@ -1071,8 +1059,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; GISEL-GFX11-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX11-TRUE16: ; %bb.0:
-; GISEL-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GISEL-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; GISEL-GFX11-TRUE16-NEXT: s_mov_b32 s6, s3
; GISEL-GFX11-TRUE16-NEXT: s_mov_b32 s7, s4
; GISEL-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, s0, s1, v0.l
@@ -1107,27 +1094,16 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
; SDAG-GFX1170-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
; SDAG-GFX1170-FAKE16-NEXT: s_endpgm
;
-; GISEL-GFX1170-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
-; GISEL-GFX1170-TRUE16: ; %bb.0:
-; GISEL-GFX1170-TRUE16-NEXT: s_max_f16 s0, s0, s1
-; GISEL-GFX1170-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1170-TRUE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1170-TRUE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1170-TRUE16-NEXT: s_min_f16 s0, s0, s2
-; GISEL-GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GISEL-GFX1170-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GISEL-GFX1170-TRUE16-NEXT: s_endpgm
-;
-; GISEL-GFX1170-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
-; GISEL-GFX1170-FAKE16: ; %bb.0:
-; GISEL-GFX1170-FAKE16-NEXT: s_max_f16 s0, s0, s1
-; GISEL-GFX1170-FAKE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1170-FAKE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1170-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1170-FAKE16-NEXT: s_min_f16 s0, s0, s2
-; GISEL-GFX1170-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX1170-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GISEL-GFX1170-FAKE16-NEXT: s_endpgm
+; GISEL-GFX1170-LABEL: s_test_minmax_f16_ieee_false:
+; GISEL-GFX1170: ; %bb.0:
+; GISEL-GFX1170-NEXT: s_max_f16 s0, s0, s1
+; GISEL-GFX1170-NEXT: s_mov_b32 s6, s3
+; GISEL-GFX1170-NEXT: s_mov_b32 s7, s4
+; GISEL-GFX1170-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX1170-NEXT: s_min_f16 s0, s0, s2
+; GISEL-GFX1170-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX1170-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX1170-NEXT: s_endpgm
;
; SDAG-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX12-TRUE16: ; %bb.0:
@@ -1148,34 +1124,22 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
; SDAG-GFX12-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
; SDAG-GFX12-FAKE16-NEXT: s_endpgm
;
-; GISEL-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
-; GISEL-GFX12-TRUE16: ; %bb.0:
-; GISEL-GFX12-TRUE16-NEXT: s_max_num_f16 s0, s0, s1
-; GISEL-GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX12-TRUE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX12-TRUE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GISEL-GFX12-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GISEL-GFX12-TRUE16-NEXT: s_endpgm
-;
-; GISEL-GFX12-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
-; GISEL-GFX12-FAKE16: ; %bb.0:
-; GISEL-GFX12-FAKE16-NEXT: s_max_num_f16 s0, s0, s1
-; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX12-FAKE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX12-FAKE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX12-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GISEL-GFX12-FAKE16-NEXT: s_endpgm
+; GISEL-GFX12-LABEL: s_test_minmax_f16_ieee_false:
+; GISEL-GFX12: ; %bb.0:
+; GISEL-GFX12-NEXT: s_max_num_f16 s0, s0, s1
+; GISEL-GFX12-NEXT: s_mov_b32 s6, s3
+; GISEL-GFX12-NEXT: s_mov_b32 s7, s4
+; GISEL-GFX12-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX12-NEXT: s_min_num_f16 s0, s0, s2
+; GISEL-GFX12-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX12-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX12-NEXT: s_endpgm
;
; SDAG-GFX1250-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX1250-TRUE16: ; %bb.0:
-; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-TRUE16-NEXT: v_nop
-; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; SDAG-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s5, s4
@@ -1186,10 +1150,9 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; SDAG-GFX1250-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX1250-FAKE16: ; %bb.0:
-; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-FAKE16-NEXT: v_nop
-; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1250-FAKE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-FAKE16-NEXT: s_mov_b32 s4, s3
@@ -1197,35 +1160,19 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
; SDAG-GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[4:5]
; SDAG-GFX1250-FAKE16-NEXT: s_endpgm
;
-; GISEL-GFX1250-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
-; GISEL-GFX1250-TRUE16: ; %bb.0:
-; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GISEL-GFX1250-TRUE16-NEXT: v_nop
-; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GISEL-GFX1250-TRUE16-NEXT: s_max_num_f16 s0, s0, s1
-; GISEL-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1250-TRUE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1250-TRUE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GISEL-GFX1250-TRUE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GISEL-GFX1250-TRUE16-NEXT: s_endpgm
-;
-; GISEL-GFX1250-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
-; GISEL-GFX1250-FAKE16: ; %bb.0:
-; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
-; GISEL-GFX1250-FAKE16-NEXT: v_nop
-; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GISEL-GFX1250-FAKE16-NEXT: s_max_num_f16 s0, s0, s1
-; GISEL-GFX1250-FAKE16-NEXT: s_mov_b32 s6, s3
-; GISEL-GFX1250-FAKE16-NEXT: s_mov_b32 s7, s4
-; GISEL-GFX1250-FAKE16-NEXT: v_mov_b32_e32 v1, 0
-; GISEL-GFX1250-FAKE16-NEXT: s_min_num_f16 s0, s0, s2
-; GISEL-GFX1250-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GISEL-GFX1250-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
-; GISEL-GFX1250-FAKE16-NEXT: s_endpgm
+; GISEL-GFX1250-LABEL: s_test_minmax_f16_ieee_false:
+; GISEL-GFX1250: ; %bb.0:
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
+; GISEL-GFX1250-NEXT: v_nop
+; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-NEXT: s_max_num_f16 s0, s0, s1
+; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
+; GISEL-GFX1250-NEXT: s_mov_b32 s7, s4
+; GISEL-GFX1250-NEXT: v_mov_b32_e32 v1, 0
+; GISEL-GFX1250-NEXT: s_min_num_f16 s0, s0, s2
+; GISEL-GFX1250-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-GFX1250-NEXT: global_store_b16 v1, v0, s[6:7]
+; GISEL-GFX1250-NEXT: s_endpgm
%smax = call half @llvm.maxnum.f16(half %a, half %b)
%sminmax = call half @llvm.minnum.f16(half %smax, half %c)
store half %sminmax, ptr addrspace(1) %out
@@ -1464,37 +1411,33 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) {
;
; SDAG-GFX1250-TRUE16-LABEL: test_maxmin_f16_ieee_false:
; SDAG-GFX1250-TRUE16: ; %bb.0:
-; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-TRUE16-NEXT: v_nop
-; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; SDAG-GFX1250-FAKE16-LABEL: test_maxmin_f16_ieee_false:
; SDAG-GFX1250-FAKE16: ; %bb.0:
-; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; SDAG-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; SDAG-GFX1250-FAKE16-NEXT: v_nop
-; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; SDAG-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-TRUE16-LABEL: test_maxmin_f16_ieee_false:
; GISEL-GFX1250-TRUE16: ; %bb.0:
-; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-GFX1250-TRUE16-NEXT: v_nop
-; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-FAKE16-LABEL: test_maxmin_f16_ieee_false:
; GISEL-GFX1250-FAKE16: ; %bb.0:
-; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GISEL-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
; GISEL-GFX1250-FAKE16-NEXT: v_nop
-; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GISEL-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: ; return to shader part epilog
%min = call half @llvm.minnum.f16(half %a, half %b)
>From 1e722795c469662069a92edebf2ae593c68265af Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Sun, 23 Aug 2026 19:13:00 -0400
Subject: [PATCH 2/4] Legalize sgpr16 in sdag
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 145 +
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 2 +
...zero-and-sign-extending-uniform-in-vgpr.ll | 12 +-
.../load-zero-and-sign-extending-uniform.ll | 16 +-
.../CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll | 2576 ++++-----
.../CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll | 240 +-
llvm/test/CodeGen/AMDGPU/fabs.bf16.ll | 165 +-
llvm/test/CodeGen/AMDGPU/fabs.f16.ll | 70 +-
.../float-to-arbitrary-fp-fp8-f16-hw.ll | 30 +-
.../AMDGPU/float-to-arbitrary-fp-fp8-hw.ll | 264 +-
.../AMDGPU/float-to-arbitrary-fp-widen.ll | 2909 +++++-----
llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll | 5 +-
llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll | 198 +-
llvm/test/CodeGen/AMDGPU/fmaxnum.ll | 12 +-
llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll | 23 +-
llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll | 198 +-
llvm/test/CodeGen/AMDGPU/fminnum.ll | 12 +-
llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll | 78 +-
llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll | 78 +-
llvm/test/CodeGen/AMDGPU/fneg.bf16.ll | 70 +-
llvm/test/CodeGen/AMDGPU/fneg.f16.ll | 70 +-
llvm/test/CodeGen/AMDGPU/fpext.f16.ll | 24 +-
llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll | 433 +-
llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll | 277 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 284 +-
.../test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll | 1 -
.../CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll | 2 -
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll | 10 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll | 5 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll | 5 +-
.../CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll | 7 +-
llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll | 144 +-
.../test/CodeGen/AMDGPU/llvm.fptrunc.round.ll | 43 +-
llvm/test/CodeGen/AMDGPU/load-constant-i1.ll | 178 +-
llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll | 4917 ++++++++---------
llvm/test/CodeGen/AMDGPU/minimummaximum.ll | 32 +-
llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll | 4917 ++++++++---------
llvm/test/CodeGen/AMDGPU/minmax.ll | 95 +-
...-to-valu-pseudo-scalar-trans-f16-true16.ll | 80 +-
llvm/test/CodeGen/AMDGPU/sad.ll | 4 +-
40 files changed, 8651 insertions(+), 9980 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 8db3aeb65a6bc..ba539628a14b4 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -4781,6 +4781,149 @@ bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode *N) const {
->isMemOpHasNoClobberedMemOperand(N)));
}
+const TargetRegisterClass *AMDGPUDAGToDAGISel::getDefRegClass(SDNode *N) const {
+ if (!N->isMachineOpcode())
+ return nullptr;
+
+ LLVM_DEBUG(dbgs() << "GetDefRegClass:\n"; N->dump(CurDAG); dbgs() << "\n");
+
+ const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+ const TargetRegisterClass *DstRC = nullptr;
+ switch (N->getMachineOpcode()) {
+ case TargetOpcode::COPY:
+ DstRC = getOperandRegClass(N, 0);
+ break;
+ case TargetOpcode::EXTRACT_SUBREG: {
+ SDNode *Src = N->getOperand(0).getNode();
+ if (!Src->isMachineOpcode())
+ return nullptr;
+ const TargetRegisterClass *SrcRC = getDefRegClass(Src);
+ if (!SrcRC)
+ return nullptr;
+ unsigned SubIdx = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+ DstRC = TRI->getSubClassWithSubReg(SrcRC, SubIdx);
+ } break;
+ case TargetOpcode::REG_SEQUENCE: {
+ unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
+ DstRC = TRI->getRegClass(RCID);
+ } break;
+ case TargetOpcode::COPY_TO_REGCLASS: {
+ unsigned RCID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
+ DstRC = TRI->getRegClass(RCID);
+ } break;
+ default:
+ const MCInstrDesc &Desc = TII->get(N->getMachineOpcode());
+ DstRC = TII->getRegClass(Desc, 0);
+ }
+ return DstRC;
+}
+
+bool AMDGPUDAGToDAGISel::PromoteSGPR16(MachineSDNode *N) {
+ if (!CurDAG->getTarget().getTargetTriple().isAMDGCN() ||
+ !Subtarget->useRealTrue16Insts() || !N->isMachineOpcode())
+ return false;
+
+ const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+
+ LLVM_DEBUG(dbgs() << "XXXXXXXXXXXXX:\n"; N->dump(CurDAG); dbgs() << "\n");
+
+ EVT VT = N->getValueType(0);
+ if (VT != MVT::i16 && VT != MVT::f16 && VT != MVT::bf16)
+ return false;
+
+ // Get Def RC
+ const TargetRegisterClass *DstRC = getDefRegClass(N);
+ if (!DstRC) {
+ LLVM_DEBUG(dbgs() << "FALED:\n");
+ return false;
+ }
+
+ bool IsSGPR32 = TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_32RegClass);
+ bool IsVGPR16 = TRI->getCommonSubClass(DstRC, &AMDGPU::VGPR_16RegClass);
+
+ LLVM_DEBUG(dbgs() << "IsSGPR32:" << IsSGPR32 << "\n");
+ LLVM_DEBUG(dbgs() << "IsVGPR16:" << IsVGPR16 << "\n");
+
+ SmallVector<std::pair<SDNode *, unsigned>, 4> ToFix;
+
+ for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); UI != UE;
+ ++UI) {
+ SDNode *User = UI->getUser();
+ unsigned OperandNo = UI->getOperandNo();
+
+ LLVM_DEBUG(dbgs() << "User:" << OperandNo << "\n"; User->dump(CurDAG);
+ dbgs() << "\n");
+ const TargetRegisterClass *UserRC = getOperandRegClass(User, OperandNo);
+
+ // Cross bank 16bit Def-Use that requires a fix
+ if ((IsSGPR32 && TRI->getCommonSubClass(UserRC, &AMDGPU::VGPR_16RegClass) &&
+ !TRI->getCommonSubClass(UserRC, &AMDGPU::SGPR_32RegClass)) ||
+ (IsVGPR16 && TRI->getCommonSubClass(UserRC, &AMDGPU::SGPR_32RegClass) &&
+ !TRI->getCommonSubClass(UserRC, &AMDGPU::VGPR_16RegClass))) {
+
+ LLVM_DEBUG(dbgs() << "Found To Fix OperandNo:" << "\n");
+ ToFix.emplace_back(User, OperandNo);
+ }
+ }
+
+ if (!ToFix.size())
+ return false;
+
+ SDLoc DL(N);
+ SDValue NewValue;
+ if (IsSGPR32) {
+ // t0: sgpr_32 = ...
+ // ... = t0: vgpr_16
+ // to
+ // t0: sgpr_32 = ...
+ // t1: vgpr_32 = COPY_REGCLASS t0
+ // t2: vgpr_16 = EXTRACT_SUBREG t1, lo16
+ // ... = t2: vgpr_16
+ SDValue RCImm =
+ CurDAG->getTargetConstant(AMDGPU::VGPR_32RegClassID, DL, MVT::i32);
+ SDValue SubRegIdx = CurDAG->getTargetConstant(AMDGPU::lo16, DL, MVT::i32);
+ SDValue CopyToReg =
+ SDValue(CurDAG->getMachineNode(AMDGPU::COPY_TO_REGCLASS, DL, VT,
+ SDValue(N, 0), RCImm),
+ 0);
+ NewValue = SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
+ VT, CopyToReg, SubRegIdx),
+ 0);
+ } else if (IsVGPR16) {
+ // t0: vgpr_16 = ...
+ // ... = t0: sgpr_32
+ // to
+ // t0: vgpr_16 = ...
+ // t1: vgpr_32 = REG_SEQUENCE t0
+ // t2: sgpr_32 = COPY_TO_REGCLASS t1
+ // ... = t2: sgpr_32
+ SDValue SubIdx0 = CurDAG->getTargetConstant(AMDGPU::lo16, DL, MVT::i32);
+ SDValue SubIdx1 = CurDAG->getTargetConstant(AMDGPU::hi16, DL, MVT::i32);
+ SDValue Undef = SDValue(
+ CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i16), 0);
+ SDValue VRegRCImm =
+ CurDAG->getTargetConstant(AMDGPU::VGPR_32RegClassID, DL, MVT::i32);
+ const SDValue Ops[] = {VRegRCImm, SDValue(N, 0), SubIdx0, Undef, SubIdx1};
+ SDValue RegSeq = SDValue(
+ CurDAG->getMachineNode(TargetOpcode::REG_SEQUENCE, DL, MVT::i32, Ops),
+ 0);
+ SDValue SRegRCImm =
+ CurDAG->getTargetConstant(AMDGPU::SGPR_32RegClassID, DL, MVT::i32);
+ NewValue = SDValue(CurDAG->getMachineNode(AMDGPU::COPY_TO_REGCLASS, DL, VT,
+ RegSeq, SRegRCImm),
+ 0);
+ }
+
+ for (auto &[User, OperandNo] : ToFix) {
+ SmallVector<SDValue, 8> NewOps(User->op_begin(), User->op_end());
+ NewOps[OperandNo] = NewValue;
+ CurDAG->UpdateNodeOperands(User, NewOps);
+ }
+ CurDAG->RemoveDeadNodes();
+
+ return true;
+}
+
void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
const AMDGPUTargetLowering& Lowering =
*static_cast<const AMDGPUTargetLowering*>(getTargetLowering());
@@ -4796,6 +4939,8 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
if (!MachineNode)
continue;
+ IsModified = PromoteSGPR16(MachineNode);
+
SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
if (ResNode != Node) {
if (ResNode)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index 2bcfe530b3947..99dfe399dd406 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -312,6 +312,8 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
void SelectINTRINSIC_VOID(SDNode *N);
void SelectWAVE_ADDRESS(SDNode *N);
void SelectSTACKRESTORE(SDNode *N);
+ bool PromoteSGPR16(MachineSDNode *N);
+ const TargetRegisterClass *getDefRegClass(SDNode *N) const;
protected:
// Include the pieces autogenerated from the target description.
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
index b57ebb2b5887f..bae7ec74587e0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform-in-vgpr.ll
@@ -283,7 +283,7 @@ define amdgpu_ps void @sextload_and_zextload_P1_i8_to_i16_not_uniform_mmo(ptr ad
; GFX11-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-NEXT: s_add_i32 s0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
@@ -298,7 +298,7 @@ define amdgpu_ps void @sextload_and_zextload_P1_i8_to_i16_not_uniform_mmo(ptr ad
; GFX12-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
%a = load volatile i8, ptr addrspace(1) %ptra
@@ -325,7 +325,7 @@ define amdgpu_ps void @sextload_and_zextload_P1_i8_to_i16_clobbered(ptr addrspac
; GFX11-NEXT: v_readfirstlane_b32 s1, v3
; GFX11-NEXT: s_add_i32 s0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
@@ -343,7 +343,7 @@ define amdgpu_ps void @sextload_and_zextload_P1_i8_to_i16_clobbered(ptr addrspac
; GFX12-NEXT: v_readfirstlane_b32 s1, v3
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
store i16 0, ptr addrspace(1) %out
@@ -448,7 +448,7 @@ define amdgpu_ps void @sextload_and_zextload_P3_i8_to_i16(ptr addrspace(3) inreg
; GFX11-NEXT: v_readfirstlane_b32 s1, v2
; GFX11-NEXT: s_add_i32 s0, s0, s1
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v1, s0
; GFX11-NEXT: ds_store_b16 v0, v1
; GFX11-NEXT: s_endpgm
;
@@ -463,7 +463,7 @@ define amdgpu_ps void @sextload_and_zextload_P3_i8_to_i16(ptr addrspace(3) inreg
; GFX12-NEXT: v_readfirstlane_b32 s1, v2
; GFX12-NEXT: s_add_co_i32 s0, s0, s1
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX12-NEXT: v_mov_b32_e32 v1, s0
; GFX12-NEXT: ds_store_b16 v0, v1
; GFX12-NEXT: s_endpgm
%a = load i8, ptr addrspace(3) %ptra
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
index eaaf2da3805e3..94c05bd1a3886 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/load-zero-and-sign-extending-uniform.ll
@@ -125,7 +125,7 @@ define amdgpu_ps void @sextload_P1_i8_to_i16(ptr addrspace(1) inreg %ptra, ptr a
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: s_add_i32 s0, s0, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
@@ -135,7 +135,7 @@ define amdgpu_ps void @sextload_P1_i8_to_i16(ptr addrspace(1) inreg %ptra, ptr a
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_co_i32 s0, s0, s0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
%a = load i8, ptr addrspace(1) %ptra
@@ -268,7 +268,7 @@ define amdgpu_ps void @zextload_P1_i8_to_i16(ptr addrspace(1) inreg %ptra, ptr a
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: s_add_i32 s0, s0, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
@@ -278,7 +278,7 @@ define amdgpu_ps void @zextload_P1_i8_to_i16(ptr addrspace(1) inreg %ptra, ptr a
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_co_i32 s0, s0, s0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
%a = load i8, ptr addrspace(1) %ptra
@@ -297,7 +297,7 @@ define amdgpu_ps void @sextload_P4_i8_to_i16(ptr addrspace(4) inreg %ptra, ptr a
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: s_add_i32 s0, s0, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
@@ -307,7 +307,7 @@ define amdgpu_ps void @sextload_P4_i8_to_i16(ptr addrspace(4) inreg %ptra, ptr a
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_co_i32 s0, s0, s0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
%a = load i8, ptr addrspace(4) %ptra
@@ -326,7 +326,7 @@ define amdgpu_ps void @zextload_P4_i8_to_i16(ptr addrspace(4) inreg %ptra, ptr a
; GFX11-NEXT: v_readfirstlane_b32 s0, v2
; GFX11-NEXT: s_add_i32 s0, s0, s0
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX11-NEXT: v_mov_b32_e32 v2, s0
; GFX11-NEXT: global_store_b16 v[0:1], v2, off
; GFX11-NEXT: s_endpgm
;
@@ -336,7 +336,7 @@ define amdgpu_ps void @zextload_P4_i8_to_i16(ptr addrspace(4) inreg %ptra, ptr a
; GFX12-NEXT: s_wait_kmcnt 0x0
; GFX12-NEXT: s_add_co_i32 s0, s0, s0
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-NEXT: v_mov_b16_e32 v2.l, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
; GFX12-NEXT: global_store_b16 v[0:1], v2, off
; GFX12-NEXT: s_endpgm
%a = load i8, ptr addrspace(4) %ptra
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
index 2b1650e429b86..8c92ae4a47279 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.1024bit.ll
@@ -20533,10 +20533,10 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
@@ -20553,10 +20553,10 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -20574,10 +20574,10 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
@@ -20586,32 +20586,32 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -20652,8 +20652,8 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
@@ -20710,35 +20710,35 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v179, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v145, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v144, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
@@ -20746,9 +20746,9 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
@@ -20764,13 +20764,13 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -20786,9 +20786,9 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -20901,11 +20901,11 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v162
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v149
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
@@ -20914,24 +20914,24 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v179
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
@@ -20960,22 +20960,22 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v18, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v20, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v144
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -21012,7 +21012,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
@@ -21020,7 +21020,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -21057,7 +21057,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
@@ -21065,9 +21065,9 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -21075,7 +21075,7 @@ define inreg <32 x i32> @bitcast_v128i8_to_v32i32_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -56543,10 +56543,10 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
@@ -56563,10 +56563,10 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -56584,10 +56584,10 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
@@ -56596,32 +56596,32 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -56662,8 +56662,8 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
@@ -56720,35 +56720,35 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v179, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v145, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v144, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
@@ -56756,9 +56756,9 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
@@ -56774,13 +56774,13 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -56796,9 +56796,9 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -56911,11 +56911,11 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v162
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v149
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
@@ -56924,24 +56924,24 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v179
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
@@ -56970,22 +56970,22 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v18, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v20, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v144
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -57022,7 +57022,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
@@ -57030,7 +57030,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -57067,7 +57067,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
@@ -57075,9 +57075,9 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -57085,7 +57085,7 @@ define inreg <32 x float> @bitcast_v128i8_to_v32f32_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -90558,10 +90558,10 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
@@ -90578,10 +90578,10 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -90599,10 +90599,10 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
@@ -90611,32 +90611,32 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -90677,8 +90677,8 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
@@ -90735,35 +90735,35 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v179, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v145, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v144, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
@@ -90771,9 +90771,9 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
@@ -90789,13 +90789,13 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -90811,9 +90811,9 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -90926,11 +90926,11 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v162
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v149
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
@@ -90939,24 +90939,24 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v179
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
@@ -90985,22 +90985,22 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v18, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v20, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v144
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -91037,7 +91037,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
@@ -91045,7 +91045,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -91082,7 +91082,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
@@ -91090,9 +91090,9 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -91100,7 +91100,7 @@ define inreg <16 x i64> @bitcast_v128i8_to_v16i64_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -123584,10 +123584,10 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:312
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:308
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:300
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:296
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:288
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:284
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:280
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:276
@@ -123604,10 +123604,10 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:232
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:228
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:220
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:216
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:208
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:204
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:200
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:196
@@ -123625,10 +123625,10 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:152
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:148
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:140
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:136
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:128
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:124
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:120
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:116
@@ -123637,32 +123637,32 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:104
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:100
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:92
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:80
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:76
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:48
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:36
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -123703,8 +123703,8 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v182, v178, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v162, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v150, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v165, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v149, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s18, s19, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v119, v115, 0xc0c0004
@@ -123761,35 +123761,35 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, s8, s7, v10
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
-; GFX11-TRUE16-NEXT: v_perm_b32 v12, v180, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v12, v179, v176, 0xc0c0004
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v179, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, s4, v180, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v15
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v181, v177, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, v13, v14
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, v163, v151, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, v162, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v13, v15, v16
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v167, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v164, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v15, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v146, v134, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v145, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v17, v18
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v160, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v19
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v147, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v17, v18
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v129, v118, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v17, v19, v20
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v145, v133, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v144, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v132, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
@@ -123797,9 +123797,9 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v19, v20
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v114, v112, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v19, v21, v22
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v128, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v117, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v20, v21, v22
@@ -123815,13 +123815,13 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v23, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v96, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v27
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v84, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v24
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v25, v26
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v66, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v25, v27, v28
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v81, v69, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v80, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v29
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v67, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v30, 16, v26
@@ -123837,9 +123837,9 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v29, v30
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v29, v31, v183
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v183, 16, v40
-; GFX11-TRUE16-NEXT: v_perm_b32 v40, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v40, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v41, 16, v30
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v31, v183
@@ -123952,11 +123952,11 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v13, 0xffff, v13
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v163
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v162
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v8
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v161
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v150
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v149
; GFX11-TRUE16-NEXT: s_add_i32 s4, s4, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v15, v15, v166, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v8, v9
@@ -123965,24 +123965,24 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s10, s9, v10
; GFX11-TRUE16-NEXT: v_perm_b32 v10, s6, s5, v10
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v179, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v162, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, s4, v180, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v11
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v12
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v160, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v161, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v151, 0xc0c0004
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v10
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v11, v12
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v13, v14
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 3, v182
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v181
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v180
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v179
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v15
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v17
; GFX11-TRUE16-NEXT: v_perm_b32 v12, v12, v178, 0xc0c0004
@@ -124011,22 +124011,22 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_or_b32_e32 v15, v18, v19
; GFX11-TRUE16-NEXT: v_or_b32_e32 v16, v20, v21
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v146
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v144
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v135
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 3, v132
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 3, v129
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 3, v128
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 3, v119
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v117
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 3, v116
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 3, v114
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v144, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v146, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v134, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v133, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v131, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v21, v21, v130, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v118, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v116, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v24, v24, v115, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v113, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v112, 0xc0c0004
@@ -124063,7 +124063,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 3, v85
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 3, v84
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 3, v80
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 3, v70
; GFX11-TRUE16-NEXT: v_perm_b32 v22, v22, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v23, v23, v98, 0xc0c0004
@@ -124071,7 +124071,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v25, v25, v87, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v26, v26, v86, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v81, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v29, v29, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v69, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v68, 0xc0c0004
@@ -124108,7 +124108,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 3, v49
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 3, v36
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 3, v34
; GFX11-TRUE16-NEXT: v_perm_b32 v27, v27, v64, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v28, v28, v54, 0xc0c0004
@@ -124116,9 +124116,9 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v30, v30, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v31, v31, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v38, v49, v38, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v36, v48, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v37, v48, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v35, v39, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v33, v37, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v33, v36, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v32, v34, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v27
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v28
@@ -124126,7 +124126,7 @@ define inreg <16 x double> @bitcast_v128i8_to_v16f64_scalar(<128 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v30
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v31
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v38
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v37
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v33
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v32
@@ -149052,119 +149052,119 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:260
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
@@ -149172,10 +149172,10 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB89_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v181
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s14, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s8, 8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v176
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
@@ -149185,139 +149185,139 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v177
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v178
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s44, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v180
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v164
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v150
; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s73, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s56, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s12, 8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v167
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v147
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v160
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v165
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v151, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v166, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v162, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v49, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v81, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v55, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v96, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v65, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v101, v70, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v69, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v99, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v112, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v80
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v37
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v129
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v84
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v50
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v102
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v131, v103, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v98
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v64
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v83
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v130
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v67
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v115
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v66
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v118
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v86
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v133, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v134
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v113
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v97
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v144
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v119
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v128
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v82
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v132
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v145, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v135, v114, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -149333,234 +149333,234 @@ define inreg <64 x bfloat> @bitcast_v128i8_to_v64bf16_scalar(<128 x i8> inreg %a
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB89_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v166
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v119
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v144
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v128
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v133, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v97, 0x300, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v115
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v179
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v162
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v129, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v102, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v149
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v133
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v132, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v167
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v144
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v86, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v130
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v131
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v101, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v87
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v87, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v129
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v80
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v112
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v69
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v135
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v99
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v65
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v101
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v55
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v130
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v96
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v103
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v66
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v97
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v162
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v166
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v50
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v167
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v164
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v114
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v180
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v68
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v178
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, s40, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, s26, s27, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v69, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s26, s27, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v69, s2, s3, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v70, s18, s19, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v83, s2, s3, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v84, s18, s19, v1
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v71, s16, s17, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s0, s1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v54
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v67
+; GFX11-TRUE16-NEXT: v_perm_b32 v85, s16, s17, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v87, s0, s1, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v69
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v70
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v80, 0x300, v80
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v83, 0x300, v83
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v84
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v96, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v80
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v85.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v87.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.h, v132.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v102.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v87
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v84.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v96.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v81.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v71.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v65.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v50.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v97.l
; GFX11-TRUE16-NEXT: .LBB89_5: ; %end
; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
@@ -175469,119 +175469,119 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:260
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
@@ -175589,10 +175589,10 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB93_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v181
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s14, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s8, 8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v176
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
@@ -175602,139 +175602,139 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v177
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v178
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s44, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v180
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v164
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v150
; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s73, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s56, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s12, 8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v167
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v147
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v160
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v165
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v151, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v166, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v162, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v49, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v81, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v55, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v96, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v65, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v101, v70, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v69, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v99, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v112, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v80
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v37
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v129
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v84
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v50
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v102
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v131, v103, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v98
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v64
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v83
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v130
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v67
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v115
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v66
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v118
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v86
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v133, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v134
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v113
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v97
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v144
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v119
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v128
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v82
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v132
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v145, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v135, v114, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -175750,234 +175750,234 @@ define inreg <64 x half> @bitcast_v128i8_to_v64f16_scalar(<128 x i8> inreg %a, i
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB93_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v166
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v119
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v144
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v128
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v133, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v97, 0x300, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v115
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v179
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v162
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v129, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v102, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v149
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v133
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v132, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v167
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v144
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v86, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v130
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v131
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v101, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v87
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v87, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v129
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v80
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v112
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v69
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v135
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v99
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v65
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v101
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v55
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v130
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v96
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v103
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v66
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v97
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v162
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v166
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v50
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v167
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v164
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v114
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v180
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v68
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v178
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, s40, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, s26, s27, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v69, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s26, s27, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v69, s2, s3, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v70, s18, s19, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v83, s2, s3, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v84, s18, s19, v1
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v71, s16, s17, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s0, s1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v54
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v67
+; GFX11-TRUE16-NEXT: v_perm_b32 v85, s16, s17, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v87, s0, s1, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v69
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v70
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v80, 0x300, v80
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v83, 0x300, v83
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v84
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v96, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v80
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v85.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v87.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.h, v132.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v102.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v87
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v84.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v96.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v81.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v71.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v65.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v50.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v97.l
; GFX11-TRUE16-NEXT: .LBB93_5: ; %end
; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
@@ -196297,119 +196297,119 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: ; meta instruction
; GFX11-TRUE16-NEXT: scratch_store_b32 off, v41, s32 offset:320
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:312
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:308
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:304
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:300
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:296
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:292
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:288
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:284
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:280
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:276
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:272
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32 offset:268
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:264
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:260
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:256
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:252
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:248
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:244
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:240
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:236
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:232
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:228
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:224
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:220
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:216
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:212
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:208
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:204
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:200
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:196
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:192
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:188
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:312
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v119, off, s32 offset:308
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:304
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:300
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v82, off, s32 offset:296
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v128, off, s32 offset:292
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v132, off, s32 offset:288
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v144, off, s32 offset:284
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:280
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:276
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v117, off, s32 offset:272
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:268
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32 offset:264
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:260
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:256
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:252
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:248
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v102, off, s32 offset:244
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:240
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v133, off, s32 offset:236
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v64, off, s32 offset:232
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:228
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:224
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:220
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:216
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v87, off, s32 offset:212
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:208
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v131, off, s32 offset:204
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:200
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:196
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:192
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v129, off, s32 offset:188
; GFX11-TRUE16-NEXT: s_clause 0x1f
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:184
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v118, off, s32 offset:180
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v115, off, s32 offset:176
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:172
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:168
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v113, off, s32 offset:164
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v100, off, s32 offset:160
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:156
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:152
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v98, off, s32 offset:148
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:144
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v135, off, s32 offset:140
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:136
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v84, off, s32 offset:132
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:128
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v145, off, s32 offset:124
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:120
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:116
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v80, off, s32 offset:112
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v130, off, s32 offset:108
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:104
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:100
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v67, off, s32 offset:96
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:92
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:88
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v66, off, s32 offset:84
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:80
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v103, off, s32 offset:76
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:72
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:68
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:64
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v97, off, s32 offset:60
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v54, off, s32 offset:184
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v85, off, s32 offset:180
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v71, off, s32 offset:176
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v116, off, s32 offset:172
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:168
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v69, off, s32 offset:164
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:160
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v112, off, s32 offset:156
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:152
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:148
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:144
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:140
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:136
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v55, off, s32 offset:132
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:128
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v101, off, s32 offset:124
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:120
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:116
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:112
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:108
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:104
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:100
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:96
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v81, off, s32 offset:92
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:88
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:84
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v148, off, s32 offset:80
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v161, off, s32 offset:76
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v146, off, s32 offset:72
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v151, off, s32 offset:68
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v149, off, s32 offset:64
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v162, off, s32 offset:60
; GFX11-TRUE16-NEXT: s_clause 0xf
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:52
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v65, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v99, off, s32 offset:44
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v83, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v147, off, s32 offset:56
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v160, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v163, off, s32 offset:48
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v166, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v150, off, s32 offset:40
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v164, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v165, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v167, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32 offset:316
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v70, off, s32 offset:24
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v114, off, s32 offset:20
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v96, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v134, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v68, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v86, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v177, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v180, off, s32 offset:20
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v179, off, s32 offset:16
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v182, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v176, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v178, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v181, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v29
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v28
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v27
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v26
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v25
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v24
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v23
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v22
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v21
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v20
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v19
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v18
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v17
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v16
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v15
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v14
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v13
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v12
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s46, v28
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s47, v27
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v26
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s12, v25
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s56, v24
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s57, v23
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s73, v22
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v21
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v20
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s42, v19
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v18
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v17
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s43, v16
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s44, v15
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s62, v14
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v13
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s13, v12
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s58, v11
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s72, v10
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v9
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s14, v8
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v7
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v6
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s8, v5
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v4
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s63, v10
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v9
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s15, v8
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s40, v7
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s59, v6
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s7, v5
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s41, v4
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s45, v3
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s61, v2
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s60, v2
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s9, v0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s10, v0
; GFX11-TRUE16-NEXT: s_mov_b32 s75, 0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(7)
; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v31
@@ -196417,10 +196417,10 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB97_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v86
-; GFX11-TRUE16-NEXT: s_and_b32 s76, s43, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s11, 8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, 0xc0c0004 :: v_dual_lshlrev_b32 v13, 8, v181
+; GFX11-TRUE16-NEXT: s_and_b32 s76, s14, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s77, s8, 8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v176
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s2, s3, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s22, s23, v8
@@ -196430,139 +196430,139 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s20, s21, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s9, s4, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s10, s4, v8
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s40, s8, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s14, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s41, s7, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s15, s6, v8
; GFX11-TRUE16-NEXT: s_or_b32 s76, s76, s77
; GFX11-TRUE16-NEXT: v_perm_b32 v1, s16, s17, v8
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s12, s6, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v70
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s76 :: v_dual_lshlrev_b32 v15, 8, v177
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s61, s45, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v6, s60, s15, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v6, s59, s40, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v7, s72, s58, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v7, s63, s58, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v9.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v9, s59, s44, v8
+; GFX11-TRUE16-NEXT: v_perm_b32 v9, s61, s42, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v68
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s41, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s10, 8
-; GFX11-TRUE16-NEXT: v_perm_b32 v11, s73, s42, v8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v178
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s11, 8
+; GFX11-TRUE16-NEXT: v_perm_b32 v11, s72, s47, v8
; GFX11-TRUE16-NEXT: s_or_b32 s88, s88, s89
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v12
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s88
; GFX11-TRUE16-NEXT: s_and_b32 s88, s74, 0xff
-; GFX11-TRUE16-NEXT: s_and_b32 s77, s63, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s57, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s56, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s5, 8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v114
+; GFX11-TRUE16-NEXT: s_and_b32 s77, s62, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s76, s44, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s43, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s9, 8
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v180
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s88, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v32
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v164
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v150
; GFX11-TRUE16-NEXT: s_or_b32 s76, s77, s76
; GFX11-TRUE16-NEXT: s_or_b32 s77, s78, s79
-; GFX11-TRUE16-NEXT: s_and_b32 s78, s62, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s47, 8
-; GFX11-TRUE16-NEXT: s_and_b32 s88, s46, 0xff
-; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s13, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s78, s73, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s57, 8
+; GFX11-TRUE16-NEXT: s_and_b32 s88, s56, 0xff
+; GFX11-TRUE16-NEXT: s_lshl_b32 s89, s12, 8
; GFX11-TRUE16-NEXT: s_or_b32 s78, s78, s79
; GFX11-TRUE16-NEXT: s_or_b32 s79, s88, s89
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v83
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v33
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v167
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 8, v147
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s76, s76, s77
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v50
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xff, v160
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s78, s79
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v165
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
-; GFX11-TRUE16-NEXT: v_perm_b32 v13, v134, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v13, v182, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v15, v16
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v14, v17
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v99, v65, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v151, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v166, v163, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v66, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v16, v97, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v16, v162, v149, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v71, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v103, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v53, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v161, v148, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v69, v36, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v18, v116, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v49, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v18, v81, v48, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v84, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v130, v80, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v55, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v96, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v98, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v145, v112, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v65, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v101, v70, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v10.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v10, v113, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v21, v135, v81, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v10, v69, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v21, v99, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v8.l
-; GFX11-TRUE16-NEXT: v_perm_b32 v22, v147, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v8, v118, v85, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v22, v112, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v8, v85, v54, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v117
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v64
-; GFX11-TRUE16-NEXT: v_perm_b32 v23, v151, v115, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v80
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 8, v37
+; GFX11-TRUE16-NEXT: v_perm_b32 v23, v116, v71, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v164
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v119
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v131
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v129
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 8, v84
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xff, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v50
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v149
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v28, 0xff, v102
; GFX11-TRUE16-NEXT: v_or_b32_e32 v24, v8, v25
-; GFX11-TRUE16-NEXT: v_perm_b32 v25, v176, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v25, v131, v103, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v26, v27
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v144
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v128
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v98
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 8, v64
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 8, v83
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v167
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v101
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v130
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v67
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v26
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v160
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v102
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v30, 0xff, v115
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v66
; GFX11-TRUE16-NEXT: v_or_b32_e32 v26, v8, v27
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v28, v29
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v162
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v132
-; GFX11-TRUE16-NEXT: v_perm_b32 v27, v177, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v118
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 8, v86
+; GFX11-TRUE16-NEXT: v_perm_b32 v27, v133, v100, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v8.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v179
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v150
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v134
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 8, v113
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v28
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v30, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v133
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v182
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v97
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v40, 0xff, v144
; GFX11-TRUE16-NEXT: v_or_b32_e32 v28, v8, v29
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v166
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xff, v119
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v165
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v129
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xff, v128
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 8, v82
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_or_b32_e32 v41, v29, v31
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v178
-; GFX11-TRUE16-NEXT: v_perm_b32 v29, v181, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v31, 8, v132
+; GFX11-TRUE16-NEXT: v_perm_b32 v29, v145, v117, 0xc0c0004
; GFX11-TRUE16-NEXT: v_or_b32_e32 v183, v8, v10
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v30.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v30, v40, v31
-; GFX11-TRUE16-NEXT: v_perm_b32 v31, v180, v161, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v31, v135, v114, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v183.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v41.l
@@ -196578,234 +196578,234 @@ define inreg <64 x i16> @bitcast_v128i8_to_v64i16_scalar(<128 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB97_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v180
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v166
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v182
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v165
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v181
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v161, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v133, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v178, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v135
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v119
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v144
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v128
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v114, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v97, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v132, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v31, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v133, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v129, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v160
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v97, 0x300, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v115
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v30, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v179
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v162
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v129, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v102, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v117, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v1, v66, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v29, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v150, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v132, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v177
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v102, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v149
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v113, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v133
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v102
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v28, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v132, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v146, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v167
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v101, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v144
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v176
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v86, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v130
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v67, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v131
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v27, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v128, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v101, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v87, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v148, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v131
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v83, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v103, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v87
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v26, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v164
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v87, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v129
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v25, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v82, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v117
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v119, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v118
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v82, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v64, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v50, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v80
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v84, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v37, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v24, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v115, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v85, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v147
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v64, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v113
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v71, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v54, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v112
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v69
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v23, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v85, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v100, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v135
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v55, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v98
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v145
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v68, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v99
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v38, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v65
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v101
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v22, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v81, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v52, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v112, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v84
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v55
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v21, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v130
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v96
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v69
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v80, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v116
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v36, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v52, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v81
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v67, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v103
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v36, 0x300, v0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v66
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v161
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v54, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v97
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v35, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v99
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v148, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v162
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v151
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v166
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v48, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v35, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v65, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v50
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v2, v149, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v146, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v163, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v160
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v83
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v34, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v167
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v33, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v39, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v147, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v164
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v165, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v134
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v114
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v33, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v182
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v180
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v2, v150, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v96, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v1, v3, v179, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v68
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v70, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v32, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v178
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v4, v177, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v49, 0x300, v0
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v86, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s74, v181, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 0x300, v1
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v37, 0xc0c0004
-; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v38, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s73, s42, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s62, s47, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v37, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s59, s44, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v176, 0xc0c0004
+; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v51, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v52, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s61, s42, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s12, s12, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s72, s58, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s63, s58, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s43, s11, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s56, s5, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, s12, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, s13, s5, v1
+; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
; GFX11-TRUE16-NEXT: s_add_i32 s60, s60, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s28, s28, 3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s41, s10, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v5, s46, s13, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v50, 0x300, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s60, s15, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v4, s61, s45, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v0
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s46, s11, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v5, s56, s12, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v65, 0x300, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v4
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s59, s40, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v4, s60, s45, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s28, s29, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s9, s9, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s62, s62, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s10, s10, 3
; GFX11-TRUE16-NEXT: s_add_i32 s20, s20, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v39, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s63, s57, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v48, 0x300, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v53, 0x300, v3
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s62, s44, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v55, 0x300, v5
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 0x300, v4
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, s9, s4, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, s10, s4, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s20, s21, v1
-; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
-; GFX11-TRUE16-NEXT: s_add_i32 s40, s40, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s15, s15, 3
+; GFX11-TRUE16-NEXT: s_add_i32 s41, s41, 3
; GFX11-TRUE16-NEXT: s_add_i32 s26, s26, 3
; GFX11-TRUE16-NEXT: s_add_i32 s22, s22, 3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 3
; GFX11-TRUE16-NEXT: s_add_i32 s18, s18, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, 0x300, v3
-; GFX11-TRUE16-NEXT: v_perm_b32 v3, s14, s7, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v54, s40, s8, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v67, s26, s27, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v68, 0x300, v2
+; GFX11-TRUE16-NEXT: v_perm_b32 v3, s15, s6, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v69, s41, s7, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v80, s26, s27, v1
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v2
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, s22, s23, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v69, s2, s3, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v70, s18, s19, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v83, s2, s3, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v84, s18, s19, v1
; GFX11-TRUE16-NEXT: s_add_i32 s24, s24, 3
; GFX11-TRUE16-NEXT: s_add_i32 s16, s16, 3
; GFX11-TRUE16-NEXT: s_add_i32 s0, s0, 3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v66, 0x300, v3
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v71, 0x300, v3
; GFX11-TRUE16-NEXT: v_perm_b32 v3, s24, s25, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v71, s16, s17, v1
-; GFX11-TRUE16-NEXT: v_perm_b32 v80, s0, s1, v1
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v54, 0x300, v54
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v67, 0x300, v67
+; GFX11-TRUE16-NEXT: v_perm_b32 v85, s16, s17, v1
+; GFX11-TRUE16-NEXT: v_perm_b32 v87, s0, s1, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v69, 0x300, v69
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v70, 0x300, v70
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v81, 0x300, v0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v80, 0x300, v80
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v83, 0x300, v83
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v84, 0x300, v84
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v96, 0x300, v0
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 0x300, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v71
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v80
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v69.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v70.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v68.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v54.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v66.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v50.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v48.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v32.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v34.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v51.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v85.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v64.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v82.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v87.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v101.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v28.h, v132.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v102.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v30.h, v129.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v31.h, v133.l
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 0x300, v85
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 0x300, v87
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v83.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v84.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v96.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v80.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v81.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v69.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v71.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v70.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.h, v68.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v65.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.h, v55.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v53.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v52.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v51.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v49.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v48.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.h, v39.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.h, v33.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.h, v35.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.h, v32.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.h, v34.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.h, v36.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.h, v38.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.h, v54.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.h, v37.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.h, v50.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.h, v64.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.h, v67.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.h, v86.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.h, v66.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.h, v82.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.h, v97.l
; GFX11-TRUE16-NEXT: .LBB97_5: ; %end
; GFX11-TRUE16-NEXT: s_clause 0x1 ; 8-byte Folded Reload
; GFX11-TRUE16-NEXT: scratch_load_b32 v41, off, s32 offset:320
diff --git a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
index 7a26f3497f492..fe78e8a8c0764 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgcn.bitcast.512bit.ll
@@ -14931,19 +14931,19 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -14985,11 +14985,11 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -15042,7 +15042,7 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
@@ -15164,11 +15164,11 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -15176,11 +15176,11 @@ define inreg <16 x i32> @bitcast_v64i8_to_v16i32_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -30126,19 +30126,19 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -30180,11 +30180,11 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -30237,7 +30237,7 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
@@ -30359,11 +30359,11 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -30371,11 +30371,11 @@ define inreg <16 x float> @bitcast_v64i8_to_v16f32_scalar(<64 x i8> inreg %a, i3
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -44199,19 +44199,19 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -44253,11 +44253,11 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -44310,7 +44310,7 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
@@ -44432,11 +44432,11 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -44444,11 +44444,11 @@ define inreg <8 x i64> @bitcast_v64i8_to_v8i64_scalar(<64 x i8> inreg %a, i32 in
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -57690,19 +57690,19 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:56
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:40
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:32
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:16
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:12
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:12
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32 offset:8
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:4
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s4, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s5, v29
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s6, v28
@@ -57744,11 +57744,11 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v37, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v33, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v52, v49, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v51, v49, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v19, v38, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s22, s23, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_perm_b32 v20, v36, v32, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v20, v35, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
@@ -57801,7 +57801,7 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s8, s7, v11
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v14, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v11, v11, v12
@@ -57923,11 +57923,11 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v13, 3, v53
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v14, v15
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v52
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 3, v51
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v17, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 3, v37
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v19, 3, v35
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v20, 3, v33
; GFX11-TRUE16-NEXT: s_add_i32 s8, s8, 3
; GFX11-TRUE16-NEXT: s_add_i32 s6, s6, 3
@@ -57935,11 +57935,11 @@ define inreg <8 x double> @bitcast_v64i8_to_v8f64_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v12, s8, s7, v11
; GFX11-TRUE16-NEXT: v_perm_b32 v11, s6, s5, v11
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v51, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, s4, v52, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v13, v50, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v14, v14, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v16, v16, v39, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v17, v17, v36, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v18, v18, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v19, v19, v32, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v20, v20, v31, 0xc0c0004
@@ -71889,20 +71889,20 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
@@ -71971,7 +71971,7 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v49
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
@@ -71987,8 +71987,8 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v39
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
@@ -71998,23 +71998,23 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v38
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v36
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v35
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v34
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
@@ -72029,20 +72029,20 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB99_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v35
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
@@ -72050,13 +72050,13 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
@@ -72068,7 +72068,7 @@ define inreg <32 x i16> @bitcast_v64i8_to_v32i16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
@@ -84678,20 +84678,20 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
@@ -84760,7 +84760,7 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v49
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
@@ -84776,8 +84776,8 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v39
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
@@ -84787,23 +84787,23 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v38
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v36
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v35
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v34
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
@@ -84818,20 +84818,20 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB107_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v35
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
@@ -84839,13 +84839,13 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
@@ -84857,7 +84857,7 @@ define inreg <32 x half> @bitcast_v64i8_to_v32f16_scalar(<64 x i8> inreg %a, i32
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
@@ -95369,20 +95369,20 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0xf
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v32, off, s32 offset:56
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:52
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:52
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v33, off, s32 offset:48
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:44
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:44
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v31, off, s32 offset:40
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v37, off, s32 offset:36
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v35, off, s32 offset:32
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:28
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v36, off, s32 offset:36
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:32
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:28
; GFX11-TRUE16-NEXT: scratch_load_b32 v54, off, s32 offset:60
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:24
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v49, off, s32 offset:24
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v52, off, s32 offset:20
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v51, off, s32 offset:16
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v53, off, s32 offset:12
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v34, off, s32 offset:8
-; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v38, off, s32 offset:4
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v39, off, s32 offset:8
+; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v48, off, s32 offset:4
; GFX11-TRUE16-NEXT: scratch_load_d16_b16 v50, off, s32
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s74, v30
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s11, v29
@@ -95451,7 +95451,7 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v9, s13, s5, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s28, s29, v8
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v48
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v10, s77 :: v_dual_lshlrev_b32 v15, 8, v49
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l
; GFX11-TRUE16-NEXT: v_perm_b32 v5, s60, s45, v8
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v6.l
@@ -95467,8 +95467,8 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_or_b32 s77, s77, s78
; GFX11-TRUE16-NEXT: s_or_b32 s78, s79, s88
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v38
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v34
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 8, v39
; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s77, s77, s78
; GFX11-TRUE16-NEXT: s_and_b32 s78, s46, 0xff
; GFX11-TRUE16-NEXT: s_lshl_b32 s79, s11, 8
@@ -95478,23 +95478,23 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s78
; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v52
; GFX11-TRUE16-NEXT: s_and_b32 s78, s74, 0xff
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v49
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xff, v38
; GFX11-TRUE16-NEXT: v_or_b32_e32 v12, s78, v13
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.h, v10.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v37
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xff, v36
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 8, v31
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.h, v8.l
; GFX11-TRUE16-NEXT: v_or_b32_e32 v8, v14, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v36
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xff, v35
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 8, v32
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v35
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 8, v34
; GFX11-TRUE16-NEXT: v_or_b32_e32 v10, v10, v13
; GFX11-TRUE16-NEXT: v_perm_b32 v13, v53, v51, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.h, v8.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s76
; GFX11-TRUE16-NEXT: v_or_b32_e32 v18, v14, v15
; GFX11-TRUE16-NEXT: v_or_b32_e32 v14, v16, v17
-; GFX11-TRUE16-NEXT: v_perm_b32 v15, v39, v33, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v15, v37, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.h, v10.l
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, s77
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.h, v18.l
@@ -95509,20 +95509,20 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s75, 1
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB111_5
; GFX11-TRUE16-NEXT: ; %bb.4: ; %cmp.true
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v36
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v1, 3, v35
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(3)
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, 3, v53
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v39
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v0, 3, v37
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v36
; GFX11-TRUE16-NEXT: s_add_i32 s74, s74, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v1, v32, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v49
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, 3, v38
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, 3, v52
; GFX11-TRUE16-NEXT: s_add_i32 s61, s61, 3
; GFX11-TRUE16-NEXT: s_add_i32 s72, s72, 3
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v16, 0x300, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v1, v4, v51, 0xc0c0004
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v35, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v2, v34, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s73, s73, 3
; GFX11-TRUE16-NEXT: s_add_i32 s63, s63, 3
; GFX11-TRUE16-NEXT: s_add_i32 s14, s14, 3
@@ -95530,13 +95530,13 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0xc0c0004
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v0, v33, 0xc0c0004
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, 0x300, v2
-; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v48, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v2, v5, v49, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s43, s43, 3
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s73, s57, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, 0x300, v0
; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v31, 0xc0c0004
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v38
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v3, 3, v48
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v18, 0x300, v2
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s72, s47, v1
; GFX11-TRUE16-NEXT: s_add_i32 s13, s13, 3
@@ -95548,7 +95548,7 @@ define inreg <32 x bfloat> @bitcast_v64i8_to_v32bf16_scalar(<64 x i8> inreg %a,
; GFX11-TRUE16-NEXT: v_perm_b32 v2, s14, s8, v1
; GFX11-TRUE16-NEXT: v_perm_b32 v4, s43, s9, v1
; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, 0x300, v0
-; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v34, 0xc0c0004
+; GFX11-TRUE16-NEXT: v_perm_b32 v0, v3, v39, 0xc0c0004
; GFX11-TRUE16-NEXT: s_add_i32 s46, s46, 3
; GFX11-TRUE16-NEXT: s_add_i32 s56, s56, 3
; GFX11-TRUE16-NEXT: s_add_i32 s59, s59, 3
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
index be4d3e4c0fcdb..d8e116317087b 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.bf16.ll
@@ -51,30 +51,17 @@ define amdgpu_kernel void @s_fabs_free_bf16(ptr addrspace(1) %out, i16 %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fabs_free_bf16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fabs_free_bf16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fabs_free_bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%bc= bitcast i16 %in to bfloat
%fabs = call bfloat @llvm.fabs.bf16(bfloat %bc)
store bfloat %fabs, ptr addrspace(1) %out
@@ -123,30 +110,17 @@ define amdgpu_kernel void @s_fabs_bf16(ptr addrspace(1) %out, bfloat %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fabs_bf16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fabs_bf16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fabs_bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%fabs = call bfloat @llvm.fabs.bf16(bfloat %in)
store bfloat %fabs, ptr addrspace(1) %out
ret void
@@ -616,37 +590,37 @@ define amdgpu_kernel void @v_fabs_fold_self_v2bf16(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v2, v0, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v2.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0x7fff, v0.l
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_dual_mul_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, v0, v3
+; GFX11-TRUE16-NEXT: v_dual_mul_f32 v0, v2, v0 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v1, v1, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
-; GFX11-TRUE16-NEXT: global_store_b32 v2, v1, s[0:1]
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: global_store_b32 v2, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_fabs_fold_self_v2bf16:
@@ -804,38 +778,39 @@ define amdgpu_kernel void @v_fabs_fold_v2bf16(ptr addrspace(1) %out, ptr addrspa
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 2, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_b32 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_b32 v0, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_and_b32 s2, s4, 0xffff0000
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v1, s2, v1
; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s4, 16
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v0, s2, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v0, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
-; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v1, 16, 1
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v1
-; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v0, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v1, 0x7fff
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, v3, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX11-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v3, v5, vcc_lo
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v0.l
-; GFX11-TRUE16-NEXT: global_store_b32 v2, v1, s[0:1]
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l
+; GFX11-TRUE16-NEXT: global_store_b32 v2, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_fabs_fold_v2bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
index 2cb7c5d869082..026168b78e8a0 100644
--- a/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fabs.f16.ll
@@ -51,30 +51,17 @@ define amdgpu_kernel void @s_fabs_free_f16(ptr addrspace(1) %out, i16 %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fabs_free_f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fabs_free_f16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fabs_free_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%bc= bitcast i16 %in to half
%fabs = call half @llvm.fabs.f16(half %bc)
store half %fabs, ptr addrspace(1) %out
@@ -123,30 +110,17 @@ define amdgpu_kernel void @s_fabs_f16(ptr addrspace(1) %out, half %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fabs_f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fabs_f16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0x7fff
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fabs_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_and_b32 s2, s2, 0x7fff
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%fabs = call half @llvm.fabs.f16(half %in)
store half %fabs, ptr addrspace(1) %out
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
index d4288ae2362e7..cd48c0dc3bd5a 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-f16-hw.ll
@@ -1082,15 +1082,12 @@ define <4 x i8> @to_fp8_v4f16(<4 x half> %x) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v2.h, v1
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v2.l, v0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v0, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v2.l, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX1250-TRUE16-NEXT: v_dual_lshrrev_b32 v1, 8, v0 :: v_dual_lshrrev_b32 v3, 24, v3
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_fp8_v4f16:
@@ -1350,15 +1347,12 @@ define <4 x i8> @to_bf8_v4f16(<4 x half> %x) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v2.h, v1
-; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v2.l, v0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v0, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v2
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v0
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v2.l, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX1250-TRUE16-NEXT: v_dual_lshrrev_b32 v1, 8, v0 :: v_dual_lshrrev_b32 v3, 24, v3
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
; GFX1250-FAKE16-LABEL: to_bf8_v4f16:
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
index 547724a407ca8..fe0b62e662f61 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-fp8-hw.ll
@@ -2617,178 +2617,183 @@ define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v4, v1
; GFX1200-NEXT: v_frexp_mant_f32_e32 v5, v1
-; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v6, v0
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v7, v0
; GFX1200-NEXT: s_mov_b32 s1, 0x7fffff
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v7, v0
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v6, v0
; GFX1200-NEXT: v_sub_nc_u32_e32 v8, 7, v4
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_and_or_b32 v13, v5, s1, 0x800000
-; GFX1200-NEXT: v_sub_nc_u32_e32 v11, 7, v6
-; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v5
-; GFX1200-NEXT: v_and_or_b32 v17, v7, s1, 0x800000
+; GFX1200-NEXT: v_and_or_b32 v12, v5, s1, 0x800000
+; GFX1200-NEXT: v_and_b32_e32 v13, 0x7ffff, v5
+; GFX1200-NEXT: v_sub_nc_u32_e32 v15, 7, v7
+; GFX1200-NEXT: v_and_or_b32 v17, v6, s1, 0x800000
; GFX1200-NEXT: v_min_u32_e32 v8, 31, v8
-; GFX1200-NEXT: v_bfe_u32 v15, v5, 20, 3
-; GFX1200-NEXT: v_min_u32_e32 v11, 31, v11
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
+; GFX1200-NEXT: v_bfe_u32 v14, v5, 20, 3
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
+; GFX1200-NEXT: v_min_u32_e32 v15, 31, v15
; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 19, v5
; GFX1200-NEXT: v_sub_nc_u32_e64 v16, v8, 1 clamp
-; GFX1200-NEXT: v_lshrrev_b32_e32 v22, v8, v13
-; GFX1200-NEXT: v_sub_nc_u32_e64 v18, v11, 1 clamp
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b32_e32 v23, v11, v17
-; GFX1200-NEXT: v_bfe_u32 v20, v13, 0, v16
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, v16, v13
-; GFX1200-NEXT: v_bfe_u32 v21, v17, 0, v18
-; GFX1200-NEXT: v_and_or_b32 v14, v15, 1, v14
-; GFX1200-NEXT: v_lshrrev_b32_e32 v17, v18, v17
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
+; GFX1200-NEXT: v_lshrrev_b32_e32 v22, v8, v12
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u32_e64 v21, v15, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u32_e64 s0, 0, v15
+; GFX1200-NEXT: v_bfe_u32 v20, v12, 0, v16
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, v16, v12
+; GFX1200-NEXT: v_and_or_b32 v13, v14, 1, v13
+; GFX1200-NEXT: v_bfe_u32 v24, v17, 0, v21
; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v10, v3
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v9, v3
-; GFX1200-NEXT: v_and_b32_e32 v5, v5, v14
-; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v12, v2
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v20
+; GFX1200-NEXT: v_and_b32_e32 v18, 0x7ffff, v6
+; GFX1200-NEXT: v_and_b32_e32 v5, v5, v13
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, v21, v17
+; GFX1200-NEXT: v_sub_nc_u32_e32 v23, 7, v10
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
-; GFX1200-NEXT: v_sub_nc_u32_e32 v14, 7, v10
-; GFX1200-NEXT: v_add_nc_u32_e32 v5, v15, v5
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v24
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, v14, v5
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v9, v3
+; GFX1200-NEXT: v_min_u32_e32 v23, 31, v23
; GFX1200-NEXT: v_and_or_b32 v16, v22, 1, v20
+; GFX1200-NEXT: v_lshrrev_b32_e32 v20, v15, v17
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v24, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
-; GFX1200-NEXT: v_min_u32_e32 v14, 31, v14
-; GFX1200-NEXT: v_and_or_b32 v20, v9, s1, 0x800000
-; GFX1200-NEXT: v_and_b32_e32 v13, v13, v16
-; GFX1200-NEXT: v_and_b32_e32 v19, 0x7ffff, v7
-; GFX1200-NEXT: v_and_or_b32 v18, v23, 1, v21
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v13, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v11
-; GFX1200-NEXT: v_and_b32_e32 v16, v17, v18
-; GFX1200-NEXT: v_sub_nc_u32_e32 v13, 7, v12
-; GFX1200-NEXT: v_lshrrev_b32_e32 v18, v14, v20
-; GFX1200-NEXT: v_add_nc_u32_e32 v8, v22, v8
-; GFX1200-NEXT: v_bfe_u32 v22, v9, 20, 3
+; GFX1200-NEXT: v_sub_nc_u32_e64 v14, v23, 1 clamp
+; GFX1200-NEXT: v_and_b32_e32 v12, v12, v16
+; GFX1200-NEXT: v_frexp_exp_i32_f32_e32 v11, v2
+; GFX1200-NEXT: v_and_or_b32 v16, v20, 1, v24
+; GFX1200-NEXT: v_bfe_u32 v19, v6, 20, 3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v11, 0, v16, vcc_lo
+; GFX1200-NEXT: v_dual_cndmask_b32 v8, 0, v12 :: v_dual_and_b32 v21, 0x7ffff, v9
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
-; GFX1200-NEXT: v_sub_nc_u32_e64 v16, v14, 1 clamp
-; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
-; GFX1200-NEXT: v_min_u32_e32 v13, 31, v13
+; GFX1200-NEXT: v_and_b32_e32 v13, v13, v16
+; GFX1200-NEXT: v_and_or_b32 v12, v9, s1, 0x800000
+; GFX1200-NEXT: v_lshrrev_b32_e32 v6, 19, v6
+; GFX1200-NEXT: v_add_nc_u32_e32 v8, v22, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, v13, s0
; GFX1200-NEXT: v_add_co_ci_u32_e64 v4, null, 14, v4, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v18
+; GFX1200-NEXT: v_frexp_mant_f32_e32 v18, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_lshl_or_b32 v5, v4, 3, v5
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 8, s0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_lshl_or_b32 v5, v4, 3, v5
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b32_e32 v22, 0x7ffff, v18
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_or_b32_e32 v8, v15, v8
-; GFX1200-NEXT: v_add_nc_u32_e32 v11, v23, v11
-; GFX1200-NEXT: v_bfe_u32 v15, v20, 0, v16
-; GFX1200-NEXT: v_lshrrev_b32_e32 v16, v16, v20
-; GFX1200-NEXT: v_sub_nc_u32_e64 v20, v13, 1 clamp
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v11
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, v11, 0, vcc_lo
+; GFX1200-NEXT: v_add_nc_u32_e32 v13, v20, v13
+; GFX1200-NEXT: v_bfe_u32 v15, v12, 0, v14
+; GFX1200-NEXT: v_and_or_b32 v16, v19, 1, v16
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v13
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_and_b32_e32 v6, v6, v16
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, v13, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v17, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v4
-; GFX1200-NEXT: v_or_b32_e32 v11, v17, v11
+; GFX1200-NEXT: v_add_nc_u32_e32 v6, v19, v6
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b32_e32 v13, v17, v13
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, v5, v8, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u32_e32 v8, 7, v11
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
-; GFX1200-NEXT: v_frexp_mant_f32_e32 v15, v2
-; GFX1200-NEXT: v_and_b32_e32 v21, 0x7ffff, v9
-; GFX1200-NEXT: v_bfe_u32 v17, v7, 20, 3
-; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 19, v7
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v19
-; GFX1200-NEXT: v_and_or_b32 v19, v15, s1, 0x800000
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 19, v9
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_and_or_b32 v5, v18, 1, v5
+; GFX1200-NEXT: v_lshrrev_b32_e32 v5, v23, v12
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, v14, v12
+; GFX1200-NEXT: v_and_or_b32 v14, v18, s1, 0x800000
+; GFX1200-NEXT: v_min_u32_e32 v8, 31, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v21
-; GFX1200-NEXT: v_lshrrev_b32_e32 v23, v13, v19
-; GFX1200-NEXT: v_and_b32_e32 v5, v16, v5
-; GFX1200-NEXT: v_bfe_u32 v16, v19, 0, v20
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v21, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_or_b32 v8, v17, 1, v8
-; GFX1200-NEXT: v_lshrrev_b32_e32 v19, v20, v19
-; GFX1200-NEXT: v_bfe_u32 v20, v15, 20, 3
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16
-; GFX1200-NEXT: v_and_or_b32 v21, v22, 1, v21
-; GFX1200-NEXT: v_and_b32_e32 v7, v7, v8
+; GFX1200-NEXT: v_bfe_u32 v17, v9, 20, 3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 19, v9
+; GFX1200-NEXT: v_sub_nc_u32_e64 v20, v8, 1 clamp
+; GFX1200-NEXT: v_and_or_b32 v15, v5, 1, v15
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
-; GFX1200-NEXT: v_and_b32_e32 v14, 0x7ffff, v15
-; GFX1200-NEXT: v_and_b32_e32 v9, v9, v21
-; GFX1200-NEXT: v_lshrrev_b32_e32 v15, 19, v15
-; GFX1200-NEXT: v_and_or_b32 v16, v23, 1, v16
+; GFX1200-NEXT: v_lshrrev_b32_e32 v21, v8, v14
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b32_e32 v12, v12, v15
+; GFX1200-NEXT: v_bfe_u32 v15, v14, 0, v20
+; GFX1200-NEXT: v_and_or_b32 v16, v17, 1, v16
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, v20, v14
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v15
+; GFX1200-NEXT: v_and_b32_e32 v9, v9, v16
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v14
-; GFX1200-NEXT: v_add_nc_u32_e32 v9, v22, v9
-; GFX1200-NEXT: v_add_nc_u32_e32 v7, v17, v7
-; GFX1200-NEXT: v_and_b32_e32 v8, v19, v16
-; GFX1200-NEXT: v_add_nc_u32_e32 v5, v18, v5
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v23
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_add_nc_u32_e32 v9, v17, v9
+; GFX1200-NEXT: v_and_or_b32 v15, v21, 1, v15
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v13
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_or_b32 v14, v20, 1, v14
+; GFX1200-NEXT: v_cndmask_b32_e32 v12, 0, v12, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v22
+; GFX1200-NEXT: v_bfe_u32 v22, v18, 20, 3
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_add_nc_u32_e32 v5, v5, v12
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v20, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b32_e32 v12, v14, v15
+; GFX1200-NEXT: v_lshrrev_b32_e32 v15, 19, v18
+; GFX1200-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_or_b32 v14, v22, 1, v20
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v12, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v5
-; GFX1200-NEXT: v_and_b32_e32 v13, v15, v14
+; GFX1200-NEXT: v_and_b32_e32 v12, v15, v14
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_add_nc_u32_e32 v8, v23, v8
+; GFX1200-NEXT: v_add_nc_u32_e32 v8, v21, v8
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc_lo
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v9
-; GFX1200-NEXT: v_add_nc_u32_e32 v13, v20, v13
+; GFX1200-NEXT: v_add_nc_u32_e32 v12, v22, v12
; GFX1200-NEXT: v_cmp_lt_i32_e64 s0, 7, v8
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX1200-NEXT: v_or_b32_e32 v5, v14, v5
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v9, v9, 0, vcc_lo
; GFX1200-NEXT: v_add_co_ci_u32_e64 v10, null, 14, v10, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v13
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v12
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v8, v8, 0, s0
; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 8, s0
; GFX1200-NEXT: v_lshl_or_b32 v9, v10, 3, v9
-; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v10
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, v13, 0, vcc_lo
-; GFX1200-NEXT: v_add_co_ci_u32_e64 v12, null, 14, v12, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v7
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, v12, 0, vcc_lo
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v11, null, 14, v11, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i32_e32 vcc_lo, 7, v6
; GFX1200-NEXT: v_or_b32_e32 v8, v15, v8
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v5, v9, v5, s0
-; GFX1200-NEXT: v_lshl_or_b32 v13, v12, 3, v13
-; GFX1200-NEXT: v_cmp_gt_i32_e64 s0, 1, v12
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_lshl_or_b32 v12, v11, 3, v12
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc_lo
-; GFX1200-NEXT: v_add_co_ci_u32_e64 v6, null, 14, v6, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc_lo
+; GFX1200-NEXT: v_add_co_ci_u32_e64 v7, null, 14, v7, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v10
+; GFX1200-NEXT: v_lshl_or_b32 v6, v7, 3, v6
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v11
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v8, v12, v8, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v3
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, v13, v8, s0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_lshl_or_b32 v7, v6, 3, v7
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0, v5, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v8, 0, v8, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v7
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e32 v6, v6, v13, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v3, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0xff, v5, vcc_lo
@@ -2797,35 +2802,30 @@ define <4 x i8> @to_e5m3fnu_v4f32(<4 x float> %x) {
; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v3.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v5, 0xff, v8, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i32_e32 vcc_lo, 1, v6
-; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v5.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v6, v7, v11, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v2.l
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v5.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc_lo
; GFX1200-NEXT: v_cmp_neq_f32_e32 vcc_lo, 0, v0
+; GFX1200-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v3, 0, v6, vcc_lo
+; GFX1200-NEXT: v_cndmask_b32_e32 v6, 0, v6, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e32 v1, 0xff, v4, vcc_lo
; GFX1200-NEXT: v_cmp_o_f32_e32 vcc_lo, v0, v0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
+; GFX1200-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0xff, v3, vcc_lo
-; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b32_e32 v0, 0xff, v6, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX1200-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v3, 24, v3
-; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_e5m3fnu_v4f32:
diff --git a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
index 3aec6c15ee0c8..9f8bbef48d20f 100644
--- a/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
+++ b/llvm/test/CodeGen/AMDGPU/float-to-arbitrary-fp-widen.ll
@@ -610,13 +610,13 @@ define <5 x i8> @to_fp8_v5f16(<5 x half> %x) {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v2
; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v3.h
; GFX1200-NEXT: v_and_b16 v6.l, v3.h, 63
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v14.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v13.l
; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
@@ -624,392 +624,383 @@ define <5 x i8> @to_fp8_v5f16(<5 x half> %x) {
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v7.l
; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v14.l
-; GFX1200-NEXT: v_and_b16 v10.h, v5.h, 1
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v13.l
+; GFX1200-NEXT: v_and_b16 v11.l, v5.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_min_u16 v9.h, v9.h, 15
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.l, v8.l
; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v8.l
-; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
-; GFX1200-NEXT: v_or_b16 v10.h, v11.l, v10.h
-; GFX1200-NEXT: v_sub_nc_u16 v11.l, v9.h, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v11.l, 1
+; GFX1200-NEXT: v_min_u16 v5.l, v9.h, 15
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_sub_nc_u16 v11.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.l
; GFX1200-NEXT: v_and_b16 v9.l, v8.l, v9.l
-; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v11.l, v11.h, 1
; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, -1
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v8.h, v8.l
; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, v11.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v8.h, v8.l
+; GFX1200-NEXT: v_and_b16 v9.l, v10.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_and_b16 v5.h, v5.l, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 1
; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.h
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.h, v5.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
-; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, v13.l, v10.l
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v11.l, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v11.l, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v8.h
+; GFX1200-NEXT: v_and_b16 v5.h, v9.h, v9.l
+; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v8.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v12.l
-; GFX1200-NEXT: v_and_b16 v8.l, v9.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
+; GFX1200-NEXT: v_or_b16 v5.h, v10.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v9.l
+; GFX1200-NEXT: v_and_b16 v8.h, v8.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v10.h, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.h, v6.h, v5.h
; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
-; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v11.h, v9.h
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v6.l, v5.h
; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, s1
-; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v6.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, vcc_lo
+; GFX1200-NEXT: v_or_b16 v8.h, v9.l, v8.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
+; GFX1200-NEXT: v_or_b16 v6.l, v4.l, v6.l
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_or_b16 v8.h, v4.l, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v5.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v5.h
-; GFX1200-NEXT: v_min_u16 v5.h, v7.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v5.l, v6.l, v5.l
+; GFX1200-NEXT: v_min_u16 v6.l, v7.h, 15
+; GFX1200-NEXT: v_or_b16 v3.h, v8.h, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v6.h, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v9.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v6.l, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.l, s0
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v8.l, v3.l
; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v2
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v3.h, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v7.l, v8.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, s1
+; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s1
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v2.l, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 3, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
+; GFX1200-NEXT: v_and_b16 v7.h, v8.l, v7.h
; GFX1200-NEXT: v_or_b16 v2.h, v8.h, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v5.h, v9.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v6.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.l, v8.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v6.l, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v3.l
+; GFX1200-NEXT: v_and_b16 v3.l, v5.l, 63
+; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v5.h
+; GFX1200-NEXT: v_and_b16 v5.h, v9.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_or_b16 v3.l, v10.l, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v6.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v2.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.h
-; GFX1200-NEXT: v_and_b16 v3.h, v5.l, 1
-; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_mov_b16_e32 v4.l, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v2.h, v4.l, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.l
+; GFX1200-NEXT: v_and_b16 v3.l, v5.h, v3.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v12.l
+; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.h, v2.l, s0
-; GFX1200-NEXT: v_and_b16 v2.h, v6.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_or_b16 v3.h, v4.l, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v2.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v3.l, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v8.h, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v14.l, v14.l
-; GFX1200-NEXT: v_and_b16 v2.h, v4.l, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v3.h, 2, v6.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_and_b16 v4.l, v7.l, 1
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
-; GFX1200-NEXT: v_min_u16 v3.h, v3.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v13.l, v13.l
+; GFX1200-NEXT: v_and_b16 v2.h, v5.l, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v9.l, v5.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v3.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, v2.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: v_min_u16 v4.l, v5.l, 15
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s1
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.l, v4.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v4.l, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s0
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, v3.h, v6.h
-; GFX1200-NEXT: v_and_b16 v8.l, v6.h, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v8.l
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
+; GFX1200-NEXT: v_or_b16 v3.l, v7.l, v3.l
+; GFX1200-NEXT: v_and_b16 v7.l, v6.l, 63
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v4.l, v8.l
+; GFX1200-NEXT: v_and_b16 v8.h, v8.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_and_b16 v9.h, v9.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_b16 v10.h, v5.l, 1
-; GFX1200-NEXT: v_or_b16 v7.l, v8.h, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_and_b16 v9.l, v9.h, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_and_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.l
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v7.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.l, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v8.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v0.l
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.l
-; GFX1200-NEXT: v_or_b16 v7.h, v11.l, v10.h
+; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.h
; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 16, v0
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_and_b16 v4.h, v6.h, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.h, v6.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, 2, v8.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v6.h, s0
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v7.h
-; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
-; GFX1200-NEXT: v_or_b16 v5.l, v8.h, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.h
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
-; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.l
-; GFX1200-NEXT: v_min_u16 v5.l, v5.h, 15
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
+; GFX1200-NEXT: v_min_u16 v3.l, v6.h, 15
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.l, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v8.h, s0
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v5.h, 1
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v1.h, v9.l, v1.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 3, v6.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
-; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v10.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v11.l
-; GFX1200-NEXT: v_and_b16 v4.l, v8.l, 1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v3.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.h, v11.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v11.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v5.h, v5.l
+; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.h, -1
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v1.h, 6
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v3.l, v5.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v1.l, v5.l, v5.h
+; GFX1200-NEXT: v_or_b16 v5.h, v8.h, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v6.h, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v1.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v4.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v4.h, v5.h, v4.h
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v7.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v9.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.l, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v6.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v7.h, v9.l, 1
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.h
+; GFX1200-NEXT: v_or_b16 v1.l, v4.l, v1.l
+; GFX1200-NEXT: v_or_b16 v4.l, v3.h, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.h, s1
+; GFX1200-NEXT: v_min_u16 v2.h, v5.h, 15
+; GFX1200-NEXT: v_or_b16 v1.h, v10.l, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v9.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v11.l
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_min_u16 v1.h, v4.l, 15
-; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v7.h
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v1.h, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.l
-; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
-; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v5.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v3.h, v6.l, 63
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.l, v11.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, v2.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v1.h, v5.l, v1.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
+; GFX1200-NEXT: v_and_b16 v3.h, 0x3ff, v3.l
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, v4.h, 1
+; GFX1200-NEXT: v_and_b16 v7.l, v3.l, 63
+; GFX1200-NEXT: v_and_b16 v6.h, v5.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 7, v3.h
+; GFX1200-NEXT: v_or_b16 v6.h, v10.l, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_and_b16 v5.h, v7.h, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v1.h, v9.h
-; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 1
-; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v8.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v7.l, v3.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v2.h, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, 6, v3.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
-; GFX1200-NEXT: v_and_b16 v8.h, v10.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v6.l, v4.h
-; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v7.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v1.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v13.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v12.l, v12.l
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v5.l
+; GFX1200-NEXT: v_and_b16 v5.h, v6.l, v6.h
+; GFX1200-NEXT: v_and_b16 v6.h, v10.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s3
-; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v6.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v1.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.l, s2
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v6.l
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v6.l, v10.l, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v4.h, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v9.l, v1.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v13.l
+; GFX1200-NEXT: v_and_b16 v3.l, v3.l, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.h
; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
-; GFX1200-NEXT: v_or_b16 v0.h, v5.l, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v8.l
+; GFX1200-NEXT: v_or_b16 v5.h, v7.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.h, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s2
; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v6.l
-; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
-; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.h
-; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
-; GFX1200-NEXT: v_or_b16 v8.l, v7.h, v8.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.l
-; GFX1200-NEXT: v_or_b16 v1.h, v7.l, v1.h
-; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v3.h, v4.h, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.l, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v3.h, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s3
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 8, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v8.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v10.h, v2.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v9.h, v7.l
+; GFX1200-NEXT: v_and_b16 v3.h, 0x80, v3.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s3
+; GFX1200-NEXT: v_or_b16 v0.h, v3.h, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v6.l, 6
+; GFX1200-NEXT: v_lshlrev_b16 v6.l, 3, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, s1
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s1
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v5.h
+; GFX1200-NEXT: v_or_b16 v6.l, v3.h, v6.l
+; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX1200-NEXT: v_or_b16 v6.h, v7.l, v6.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v7.h, v7.l, v7.h
+; GFX1200-NEXT: v_or_b16 v1.h, v6.l, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s0
+; GFX1200-NEXT: v_or_b16 v2.h, v6.h, v2.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v5.h
+; GFX1200-NEXT: v_or_b16 v3.l, v7.h, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s2
-; GFX1200-NEXT: v_or_b16 v4.l, v3.l, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.l, v2.h, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, vcc_lo
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v3, v4.l
+; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v1.l
; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.h, s0
-; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.l, s1
; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v11.l, v11.l
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v3
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
+; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v0.l
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v5.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_fp8_v5f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.l, v1
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v5.h, s0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v5.l, v2
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.l, v0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v4, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[4:5]
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.l
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -1391,13 +1382,13 @@ define <6 x i8> @to_fp8_v6f16(<6 x half> %x) {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v2
; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v3.l
; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v3.h
; GFX1200-NEXT: v_and_b16 v6.l, v3.h, 63
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v14.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v13.l
; GFX1200-NEXT: v_lshrrev_b16 v3.h, 6, v3.h
; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
@@ -1405,392 +1396,383 @@ define <6 x i8> @to_fp8_v6f16(<6 x half> %x) {
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v7.l
; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v14.l
-; GFX1200-NEXT: v_and_b16 v10.h, v5.h, 1
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v13.l
+; GFX1200-NEXT: v_and_b16 v11.l, v5.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_min_u16 v9.h, v9.h, 15
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.l, v8.l
; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v5.l, v8.l
-; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
-; GFX1200-NEXT: v_or_b16 v10.h, v11.l, v10.h
-; GFX1200-NEXT: v_sub_nc_u16 v11.l, v9.h, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v10.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.h, v11.l, 1
+; GFX1200-NEXT: v_min_u16 v5.l, v9.h, 15
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_and_b16 v10.l, v6.h, 63
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v6.h
+; GFX1200-NEXT: v_sub_nc_u16 v11.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.l
; GFX1200-NEXT: v_and_b16 v9.l, v8.l, v9.l
-; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v11.l, v11.h, 1
; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, -1
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v8.h, v8.l
; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, v11.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v8.h, v8.l
+; GFX1200-NEXT: v_and_b16 v9.l, v10.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_and_b16 v5.h, v5.l, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 1
; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.h
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s0
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.h, v5.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
-; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, v13.l, v10.l
+; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v11.l, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v11.l, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
+; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v8.h
+; GFX1200-NEXT: v_and_b16 v5.h, v9.h, v9.l
+; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v8.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v12.l
-; GFX1200-NEXT: v_and_b16 v8.l, v9.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v11.h, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
+; GFX1200-NEXT: v_or_b16 v5.h, v10.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v9.l
+; GFX1200-NEXT: v_and_b16 v8.h, v8.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v10.h, v5.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.h, v6.h, v5.h
; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s0
-; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v11.h, v9.h
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v9.l, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v6.l, v5.h
; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, v5.l, s1
-; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v6.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, vcc_lo
+; GFX1200-NEXT: v_or_b16 v8.h, v9.l, v8.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
+; GFX1200-NEXT: v_or_b16 v6.l, v4.l, v6.l
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_or_b16 v8.h, v4.l, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_or_b16 v3.l, v8.l, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v5.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v5.h
-; GFX1200-NEXT: v_min_u16 v5.h, v7.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v5.l, v6.l, v5.l
+; GFX1200-NEXT: v_min_u16 v6.l, v7.h, 15
+; GFX1200-NEXT: v_or_b16 v3.h, v8.h, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v6.h, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v2.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v9.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v6.l, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.l, s0
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v8.l, v3.l
; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v2
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v3.h, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v7.l, v8.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.h, 1 clamp
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, s1
+; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, 8, s0
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.l, 1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v4.l, s1
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v3.h
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v2.l, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 3, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
+; GFX1200-NEXT: v_and_b16 v7.h, v8.l, v7.h
; GFX1200-NEXT: v_or_b16 v2.h, v8.h, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v5.h, v9.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v6.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.l, v8.h, v2.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v6.l, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v3.l
+; GFX1200-NEXT: v_and_b16 v3.l, v5.l, 63
+; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v5.h
+; GFX1200-NEXT: v_and_b16 v5.h, v9.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
+; GFX1200-NEXT: v_or_b16 v3.l, v10.l, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v6.h, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v2.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.h
-; GFX1200-NEXT: v_and_b16 v3.h, v5.l, 1
-; GFX1200-NEXT: v_and_b16 v3.l, 0xff, v3.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_mov_b16_e32 v4.l, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v2.h, v4.l, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.l
+; GFX1200-NEXT: v_and_b16 v3.l, v5.h, v3.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v12.l
+; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.h, v2.l, s0
-; GFX1200-NEXT: v_and_b16 v2.h, v6.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_or_b16 v3.h, v4.l, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, v7.l, v9.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v2.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v3.l, s0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v8.h, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v14.l, v14.l
-; GFX1200-NEXT: v_and_b16 v2.h, v4.l, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v3.h, 2, v6.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_and_b16 v4.l, v7.l, 1
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
-; GFX1200-NEXT: v_min_u16 v3.h, v3.h, 15
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s0
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v13.l, v13.l
+; GFX1200-NEXT: v_and_b16 v2.h, v5.l, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v9.l, v5.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v3.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, v2.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v1.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v4.l, v2.h
+; GFX1200-NEXT: v_min_u16 v4.l, v5.l, 15
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s1
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.l, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s0
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, v3.h, v6.h
-; GFX1200-NEXT: v_and_b16 v8.l, v6.h, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v4.l, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_b16 v10.h, v5.l, 1
-; GFX1200-NEXT: v_or_b16 v7.l, v8.h, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_and_b16 v9.l, v9.h, 1
-; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, vcc_lo
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v8.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v0.l
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
+; GFX1200-NEXT: v_or_b16 v3.l, v7.l, v3.l
+; GFX1200-NEXT: v_and_b16 v7.l, v6.l, 63
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v4.l, v8.l
+; GFX1200-NEXT: v_and_b16 v8.h, v8.l, v8.h
; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.l
-; GFX1200-NEXT: v_or_b16 v7.h, v11.l, v10.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 16, v0
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, v6.h, s0
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v7.h
-; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v4.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
-; GFX1200-NEXT: v_or_b16 v5.l, v8.h, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
-; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.h
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.h
-; GFX1200-NEXT: v_or_b16 v4.l, v5.l, v4.l
-; GFX1200-NEXT: v_min_u16 v5.l, v5.h, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, v6.h, 0, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v4.l, v2.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v5.l, 1 clamp
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v7.h
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v8.h, s0
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v5.h, 1
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 7, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v1.h, v9.l, v1.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 3, v6.l
-; GFX1200-NEXT: v_and_b16 v4.l, v9.h, v8.l
-; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v5.l, v9.h
-; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v10.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.l
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v11.l
-; GFX1200-NEXT: v_and_b16 v4.l, v8.l, 1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v3.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_and_b16 v9.h, v9.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v11.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v10.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.h, v1.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.h, v6.l, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v4.l, 2, v6.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_and_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v0.l
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v7.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.l, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v9.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.l, v11.l
-; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v3.h
-; GFX1200-NEXT: v_min_u16 v1.h, v4.l, 15
-; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v7.h
-; GFX1200-NEXT: v_and_b16 v9.l, v5.l, 63
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, v1.h, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.l
-; GFX1200-NEXT: v_and_b16 v4.l, 0x3ff, v5.l
-; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 6, v5.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v5.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
-; GFX1200-NEXT: v_or_b16 v9.h, 0x400, v4.l
-; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v8.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v1.h, v9.h
-; GFX1200-NEXT: v_and_b16 v9.l, v4.l, 1
-; GFX1200-NEXT: v_and_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
-; GFX1200-NEXT: v_and_b16 v8.h, v10.h, 1
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
+; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 16, v0
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v6.l, v4.h
-; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v9.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_and_b16 v4.h, v6.h, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v7.h, v6.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, 2, v8.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.l
+; GFX1200-NEXT: v_min_u16 v3.l, v6.h, 15
+; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v9.l, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s0
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.h, v11.l
; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_and_b16 v5.l, v5.l, v7.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v1.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.h
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v13.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v12.l, v12.l
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v5.l
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s3
-; GFX1200-NEXT: v_or_b16 v6.l, v9.l, v8.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v4.l
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s1
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v5.h, v5.l
+; GFX1200-NEXT: v_or_b16 v5.l, 0x400, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.h, -1
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v1.h, 6
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v3.l, v5.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v6.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v8.l
+; GFX1200-NEXT: v_and_b16 v1.l, v5.l, v5.h
+; GFX1200-NEXT: v_or_b16 v5.h, v8.h, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, v6.h, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v1.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v4.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v4.h, v5.h, v4.h
+; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v7.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v9.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v7.h, v9.l, 1
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v1.h
+; GFX1200-NEXT: v_or_b16 v1.l, v4.l, v1.l
+; GFX1200-NEXT: v_or_b16 v4.l, v3.h, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.h, s1
+; GFX1200-NEXT: v_min_u16 v2.h, v5.h, 15
+; GFX1200-NEXT: v_or_b16 v1.h, v10.l, v7.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v4.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v3.h, v6.l, 63
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.l, v11.l
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, v2.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v1.h, v5.l, v1.h
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 7, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.h
+; GFX1200-NEXT: v_and_b16 v3.h, 0x3ff, v3.l
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, v4.h, 1
+; GFX1200-NEXT: v_and_b16 v7.l, v3.l, 63
+; GFX1200-NEXT: v_and_b16 v6.h, v5.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s4
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s4
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.l, s2
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v6.l
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, 8, s3
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.h, v1.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, 6
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, -1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 7, v3.h
+; GFX1200-NEXT: v_or_b16 v6.h, v10.l, v6.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_and_b16 v5.h, v7.h, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v7.l, v3.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v10.h, v2.h, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, 6, v3.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_and_b16 v5.h, v6.l, v6.h
+; GFX1200-NEXT: v_and_b16 v6.h, v10.h, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v1.h, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v6.l, v10.l, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, v5.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v4.h, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v9.l, v1.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v13.l
+; GFX1200-NEXT: v_and_b16 v3.l, v3.l, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.h
; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
-; GFX1200-NEXT: v_or_b16 v0.h, v5.l, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, 6
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 3, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v8.l
+; GFX1200-NEXT: v_or_b16 v5.h, v7.l, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.h, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s2
; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 3, v6.l
-; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
-; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.h
-; GFX1200-NEXT: v_or_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.h
-; GFX1200-NEXT: v_or_b16 v8.l, v7.h, v8.l
-; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v4.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v6.l
-; GFX1200-NEXT: v_or_b16 v1.h, v7.l, v1.h
-; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
-; GFX1200-NEXT: v_or_b16 v4.l, v8.l, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.h, v0.h, vcc_lo
+; GFX1200-NEXT: v_and_b16 v3.h, v4.h, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v3.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.l, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v3.h, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s3
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, 8, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 6
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v8.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v10.h, v2.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v9.h, v7.l
+; GFX1200-NEXT: v_and_b16 v3.h, 0x80, v3.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s3
+; GFX1200-NEXT: v_or_b16 v0.h, v3.h, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v6.l, 6
+; GFX1200-NEXT: v_lshlrev_b16 v6.l, 3, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, s1
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s1
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v5.h
+; GFX1200-NEXT: v_or_b16 v6.l, v3.h, v6.l
+; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX1200-NEXT: v_or_b16 v6.h, v7.l, v6.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
+; GFX1200-NEXT: v_or_b16 v7.h, v7.l, v7.h
+; GFX1200-NEXT: v_or_b16 v1.h, v6.l, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s0
+; GFX1200-NEXT: v_or_b16 v2.h, v6.h, v2.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v5.h
+; GFX1200-NEXT: v_or_b16 v3.l, v7.h, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
+; GFX1200-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.l, v1.h, s2
-; GFX1200-NEXT: v_or_b16 v4.l, v3.l, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.l, v2.h, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v11.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, vcc_lo
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v3, v4.l
+; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v1.l
; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.h, s0
-; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v7.l, s1
; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v11.l, v11.l
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v3
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX1200-NEXT: v_or_b32_e32 v6, 0x7f7f0000, v1
+; GFX1200-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
-; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-NEXT: v_lshrrev_b64 v[7:8], 24, v[5:6]
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v0.l
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v7.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
; GFX1250-TRUE16-LABEL: to_fp8_v6f16:
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.l, v1
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.h, s0
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.l, v2
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v3.l, v0
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v0.l, v0
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v7
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v7.l
-; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v6, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v3
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[6:7]
; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
@@ -2283,513 +2265,491 @@ define <7 x i8> @to_fp8_v7f16(<7 x half> %x) {
; GFX1200-NEXT: s_wait_kmcnt 0x0
; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.l, v3.l
; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v3.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v3
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 31, v3
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v3
; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v3.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v2.l
; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v4.l
-; GFX1200-NEXT: v_and_b16 v6.l, v4.h, 63
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v13.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.l, v13.l
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
-; GFX1200-NEXT: v_min_u16 v3.h, v5.h, 15
-; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.l
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, 2, v7.h
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v4.h
+; GFX1200-NEXT: v_and_b16 v7.h, v4.h, 63
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v14.l
; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_min_u16 v9.l, v9.l, 15
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v3.h, v8.l
-; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v3.h
-; GFX1200-NEXT: v_sub_nc_u16 v3.h, v9.l, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
-; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v7.l
-; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
-; GFX1200-NEXT: v_and_b16 v9.h, v7.l, 63
-; GFX1200-NEXT: v_lshlrev_b16 v11.l, v3.h, 1
-; GFX1200-NEXT: v_and_b16 v8.h, v8.l, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 6, v7.l
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v9.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v5.h, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v8.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v11.l, -1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v3.h, v3.h, v8.h
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: v_or_b16 v8.l, v12.l, v10.l
-; GFX1200-NEXT: v_and_b16 v6.h, v8.h, v6.h
+; GFX1200-NEXT: v_min_u16 v5.h, v5.h, 15
+; GFX1200-NEXT: v_or_b16 v10.l, 0x400, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.h
+; GFX1200-NEXT: v_sub_nc_u16 v11.l, 2, v9.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.h, 1 clamp
+; GFX1200-NEXT: v_lshrrev_b16 v12.h, v5.h, v10.l
+; GFX1200-NEXT: v_and_b16 v12.l, v7.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s3
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v9.l
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, v9.l, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v3.l, v3.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v10.l
-; GFX1200-NEXT: v_and_b16 v6.h, v5.h, 1
-; GFX1200-NEXT: v_and_b16 v9.l, v8.l, 1
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.h, v6.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_min_u16 v11.l, v11.l, 15
+; GFX1200-NEXT: v_lshlrev_b16 v10.h, v8.h, 1
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.l, v14.l
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
+; GFX1200-NEXT: v_or_b16 v12.l, v13.l, v12.l
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, 2, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v10.h, v10.h, -1
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v8.l
+; GFX1200-NEXT: v_and_b16 v11.h, v8.l, 63
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 6, v8.l
+; GFX1200-NEXT: v_and_b16 v10.h, v10.l, v10.h
+; GFX1200-NEXT: v_min_u16 v9.h, v9.h, 15
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v11.h
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v8.h, v10.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.h
+; GFX1200-NEXT: v_and_b16 v10.h, v12.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s2
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v11.l
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v16, 0, 1, s2
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v2.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, v11.l, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, s1
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v4.l
-; GFX1200-NEXT: v_or_b16 v6.h, v11.l, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v4.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v8.h
-; GFX1200-NEXT: v_or_b16 v8.h, v5.l, v9.l
-; GFX1200-NEXT: v_or_b16 v9.l, v5.l, v9.h
-; GFX1200-NEXT: v_and_b16 v6.h, v7.l, v6.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s1
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v13.l
+; GFX1200-NEXT: v_or_b16 v13.l, 0x400, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v13.h, v5.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v10.h
+; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
+; GFX1200-NEXT: v_add_nc_u16 v10.l, v13.h, -1
+; GFX1200-NEXT: v_and_b16 v10.h, v7.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v13.l
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, v12.l
+; GFX1200-NEXT: v_and_b16 v10.l, v13.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, v11.l, v13.l
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, s3
-; GFX1200-NEXT: v_or_b16 v4.l, v8.h, v4.h
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, s0
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 6
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v6.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, 2, v3.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v8.l, v3.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v2.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v10.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v16.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v11.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v12.h, v7.l
+; GFX1200-NEXT: v_and_b16 v11.l, v8.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s2
+; GFX1200-NEXT: v_lshlrev_b16 v11.h, 3, v4.l
+; GFX1200-NEXT: v_or_b16 v10.l, v10.l, v10.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v7.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v4.l
+; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.l
+; GFX1200-NEXT: v_or_b16 v11.h, v5.l, v11.h
+; GFX1200-NEXT: v_and_b16 v8.l, v8.l, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v10.h, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v7.l, v7.l, 0, s2
+; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v11.l
+; GFX1200-NEXT: v_or_b16 v4.l, v11.h, v4.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; GFX1200-NEXT: v_or_b16 v10.h, v5.l, v10.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s2, v1.l, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v5.h, s0
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_or_b16 v4.h, v10.h, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.h, v8.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, v9.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v6.l
; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v4.h, s1
-; GFX1200-NEXT: v_min_u16 v4.h, v6.l, 15
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v3.h
-; GFX1200-NEXT: v_and_b16 v9.h, v6.h, 63
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.h, v5.h
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, v8.l, 1
+; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, vcc_lo
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, v4.h, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
-; GFX1200-NEXT: v_lshlrev_b16 v5.l, 7, v14.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s2
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v6.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s2
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s1
-; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v2
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_or_b16 v7.h, v5.l, v8.l
-; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 6, v6.h
-; GFX1200-NEXT: v_cndmask_b16 v4.l, 0x7f, v4.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
-; GFX1200-NEXT: v_or_b16 v3.h, v7.h, v3.h
-; GFX1200-NEXT: v_and_b16 v7.h, v8.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v10.l, v4.h, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v7.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v8.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, -1
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v3.l, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v10.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v3
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v4.h, 0, s1
+; GFX1200-NEXT: v_and_b16 v4.h, v8.h, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.l, 0x7f, v4.l, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, 8, s1
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, 7, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v9.h, v8.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v14.l, v14.l
+; GFX1200-NEXT: v_or_b16 v4.h, v5.h, v5.l
+; GFX1200-NEXT: v_and_b16 v10.l, v9.l, 1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v5.l, 3, v3.l
; GFX1200-NEXT: v_and_b16 v4.l, 0xff, v4.l
-; GFX1200-NEXT: v_or_b16 v8.h, v5.l, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, v10.l, 1
+; GFX1200-NEXT: v_or_b16 v3.h, v4.h, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v7.l, 0, s0
+; GFX1200-NEXT: v_and_b16 v7.l, v6.l, 63
+; GFX1200-NEXT: v_or_b16 v5.l, v5.h, v5.l
+; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v8.l, v8.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v8.l, v12.l
+; GFX1200-NEXT: v_or_b16 v4.h, v5.l, v4.h
+; GFX1200-NEXT: v_and_b16 v5.l, v7.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v10.l
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v9.h
-; GFX1200-NEXT: v_and_b16 v9.h, v7.h, 1
-; GFX1200-NEXT: v_or_b16 v5.h, v8.h, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
-; GFX1200-NEXT: v_or_b16 v7.l, v11.l, v9.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v14.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v8.h, v12.l, v9.h
+; GFX1200-NEXT: v_sub_nc_u16 v3.l, 2, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v4.h, v3.h, s0
+; GFX1200-NEXT: v_or_b16 v5.l, v11.l, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v5.h, v3.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v9.l
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v7.l
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, 8, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, vcc_lo
+; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
+; GFX1200-NEXT: v_and_b16 v4.h, v6.l, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v7.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v3.l, 1 clamp
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.l, vcc_lo
-; GFX1200-NEXT: v_min_u16 v4.h, v5.h, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, 0, v6.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v7.h, v6.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v14.l
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v13.l, v13.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v4.h, 1 clamp
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.l, v5.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v5.l
-; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.h, v4.h
+; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v7.l, 1
+; GFX1200-NEXT: v_and_b16 v8.h, 0x80, v8.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v4.h
+; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
-; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v7.l
-; GFX1200-NEXT: v_and_b16 v10.l, v6.l, 63
+; GFX1200-NEXT: v_cndmask_b16 v9.h, 0, 8, vcc_lo
; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, vcc_lo
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v4.h, v8.h
-; GFX1200-NEXT: v_and_b16 v7.h, v8.h, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 7, v7.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 6
-; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v9.h
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, s0
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, 0, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_or_b16 v9.h, v8.h, v9.h
+; GFX1200-NEXT: v_and_b16 v7.h, v9.l, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.l, v9.l
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, v10.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v3.l, v9.l
+; GFX1200-NEXT: v_or_b16 v5.l, v9.h, v5.l
; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v3.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.h
-; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_and_b16 v7.h, v6.l, 63
+; GFX1200-NEXT: v_add_nc_u16 v6.h, v6.h, 6
+; GFX1200-NEXT: v_and_b16 v9.h, v10.l, 1
+; GFX1200-NEXT: v_and_b16 v9.l, v5.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
-; GFX1200-NEXT: v_and_b16 v11.h, v7.l, 1
-; GFX1200-NEXT: v_or_b16 v7.h, v9.h, v7.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc_lo
-; GFX1200-NEXT: v_or_b16 v10.l, v11.l, v10.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
-; GFX1200-NEXT: v_or_b16 v5.l, v7.h, v5.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.h, v1.l
-; GFX1200-NEXT: v_or_b16 v11.l, v12.l, v11.h
-; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v10.l
-; GFX1200-NEXT: v_or_b16 v5.h, v8.l, v5.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX1200-NEXT: v_sub_nc_u16 v3.l, 2, v7.h
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v11.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v7.h, v8.h, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7f, v3.h, s1
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v9.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v13.l
+; GFX1200-NEXT: v_or_b16 v4.h, v7.h, v4.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v14, 16, v0
; GFX1200-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v5.h, s0
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v2.l
-; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, v7.l, vcc_lo
+; GFX1200-NEXT: v_or_b16 v3.l, v11.l, v9.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v1.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.h
+; GFX1200-NEXT: v_lshrrev_b32_e32 v11, 31, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, 2, v9.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, v5.l, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.l, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 7, v11.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v5.h, v3.l
+; GFX1200-NEXT: v_min_u16 v5.l, v6.h, 15
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v1.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v2.h, 0x3ff, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, v5.l, v9.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v10.h, v6.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v1.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v2
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, s0
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s0
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, v6.h, 1
+; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v2.h
+; GFX1200-NEXT: v_or_b16 v7.h, v9.h, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.h, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
-; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s1
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v9.l, v7.l
-; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v8.l
-; GFX1200-NEXT: v_cndmask_b16 v7.l, 0, 8, s1
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, 6
-; GFX1200-NEXT: v_and_b16 v8.h, v9.l, v8.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v7.l, v10.l, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v3.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 3, v2.h
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v2.h
-; GFX1200-NEXT: v_and_b16 v2.h, v6.l, 63
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
-; GFX1200-NEXT: v_or_b16 v8.h, v10.l, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, v8.h, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, v10.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
+; GFX1200-NEXT: v_and_b16 v8.h, v5.h, 63
+; GFX1200-NEXT: v_or_b16 v6.l, v7.h, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, v5.l, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, 6
+; GFX1200-NEXT: v_and_b16 v7.l, v10.h, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s1
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, 7, v2.h
+; GFX1200-NEXT: v_and_b16 v10.l, v7.h, 1
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v10.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v8.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v2.l, v2.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_or_b16 v2.l, v7.l, v5.h
-; GFX1200-NEXT: v_and_b16 v5.h, v10.h, 1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v11.l
-; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0x7f, v5.l, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v14.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_or_b16 v7.l, v9.h, v7.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s1
-; GFX1200-NEXT: v_or_b16 v5.h, v7.l, v5.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v13.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v3.l
-; GFX1200-NEXT: v_and_b16 v3.l, v8.l, 1
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v4.h, v2.l, s0
-; GFX1200-NEXT: v_and_b16 v2.h, v6.h, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v7.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.h, v13.l
-; GFX1200-NEXT: v_or_b16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0x7f, v4.h, s1
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v10.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, vcc_lo
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, s1
-; GFX1200-NEXT: v_min_u16 v5.h, v5.h, 15
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v4.h
-; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
-; GFX1200-NEXT: v_and_b16 v10.l, v4.h, 63
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v10.h, v2.h
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.h, 1 clamp
-; GFX1200-NEXT: v_or_b16 v6.l, 0x400, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v8.l, v3.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v3.l, v7.l, v3.l
+; GFX1200-NEXT: v_and_b16 v7.l, v2.h, 1
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v8.l
+; GFX1200-NEXT: v_and_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v13.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v6.l, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0, v6.h, s0
+; GFX1200-NEXT: v_or_b16 v5.l, v10.l, v7.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v13.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v13.l
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v7.h, v2.l
+; GFX1200-NEXT: v_and_b16 v5.l, v5.h, v5.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, 2, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v9.h, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v2.l
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, v5.l
+; GFX1200-NEXT: v_min_u16 v5.l, v5.h, 15
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v1.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v2.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v6.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v10.h, v5.h, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v3.l
-; GFX1200-NEXT: v_lshrrev_b16 v9.h, 8, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v5.h, 0x80, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v12.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, v7.l, 1
+; GFX1200-NEXT: v_or_b16 v7.h, v5.h, v7.h
; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s0
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_and_b16 v11.h, v8.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 6, v4.h
-; GFX1200-NEXT: v_and_b16 v9.l, v6.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.h, v6.l
-; GFX1200-NEXT: v_and_b16 v9.h, 0x80, v9.h
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_mov_b16_e32 v9.l, v11.l
-; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v8.l
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v9.l, v8.l
+; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v9.h, v9.h, -1
+; GFX1200-NEXT: v_or_b16 v2.l, v7.h, v2.l
+; GFX1200-NEXT: v_and_b16 v7.h, v6.l, 63
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, 6
+; GFX1200-NEXT: v_and_b16 v9.h, v9.l, v9.h
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v5.l, v9.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 6, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.l, v9.l
+; GFX1200-NEXT: v_and_b16 v10.h, v10.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v10.l
-; GFX1200-NEXT: v_and_b16 v10.l, v10.h, 1
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, v9.l
-; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
+; GFX1200-NEXT: v_and_b16 v9.h, v8.h, 1
+; GFX1200-NEXT: v_or_b16 v7.h, v5.h, v7.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v9.l, v0.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v8.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, 6
-; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v10.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v12.l, v15.l
-; GFX1200-NEXT: v_lshlrev_b16 v5.h, 3, v7.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v9.l
-; GFX1200-NEXT: v_or_b16 v6.h, v12.l, v11.h
-; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v5.h, v9.h, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s0
-; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v6.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v0.l
-; GFX1200-NEXT: v_or_b16 v3.l, v5.h, v3.l
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.h, v6.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v8.h, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, 2, v6.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v3.l, v2.h, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v4.h
-; GFX1200-NEXT: v_min_u16 v5.h, v8.l, 15
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s1
+; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
+; GFX1200-NEXT: v_or_b16 v2.h, v7.h, v2.h
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, 2, v9.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.l
+; GFX1200-NEXT: v_or_b16 v10.h, v12.l, v10.h
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.h, v2.l, s0
+; GFX1200-NEXT: v_min_u16 v2.h, v7.h, 15
; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v1.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v8.h, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
-; GFX1200-NEXT: v_sub_nc_u16 v8.h, v5.h, 1 clamp
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v9.h, s0
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v1.l, v1.l
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v10.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0x7f, v3.l, vcc_lo
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v2.h, 1 clamp
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v5.h, s0
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v7.l, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v5.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.l, v0.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7f, v2.l, s2
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.l, v6.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s1
+; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v7.l
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v7.h, 1
; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v1
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, 8, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v14.l, v14.l
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v8.l
-; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_lshlrev_b16 v10.l, 7, v10.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 7, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v6.h, v8.l
+; GFX1200-NEXT: v_or_b16 v6.h, 0x400, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.h, -1
+; GFX1200-NEXT: v_lshlrev_b16 v9.h, 7, v10.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 8, s0
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v1.h, 6
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s0
+; GFX1200-NEXT: v_and_b16 v1.l, v6.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v2.h, v6.h
+; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v8.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 3, v1.h
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v10.h, v14.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v5.l, 0, s1
+; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
+; GFX1200-NEXT: v_or_b16 v5.l, v9.h, v8.h
+; GFX1200-NEXT: v_and_b16 v8.h, v10.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7f, v2.h, s0
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
-; GFX1200-NEXT: v_or_b16 v1.h, v10.l, v1.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
-; GFX1200-NEXT: v_lshlrev_b16 v11.l, 3, v7.l
-; GFX1200-NEXT: v_and_b16 v3.l, v10.h, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v5.h, v10.h
-; GFX1200-NEXT: v_or_b16 v1.h, v1.h, v6.l
-; GFX1200-NEXT: v_and_b16 v9.h, v8.l, 1
-; GFX1200-NEXT: v_or_b16 v6.l, v10.l, v11.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v3.l, v6.l, v4.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v7.l
-; GFX1200-NEXT: v_and_b16 v4.h, v9.l, 1
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v7.l, v12.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_3) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v11.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v3.l, v1.h, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
-; GFX1200-NEXT: v_or_b16 v3.l, v6.l, v4.h
-; GFX1200-NEXT: v_sub_nc_u16 v4.h, 2, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v8.h, v10.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.h, v10.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
-; GFX1200-NEXT: v_min_u16 v1.h, v4.h, 15
-; GFX1200-NEXT: v_and_b16 v3.l, v6.l, v3.l
-; GFX1200-NEXT: v_and_b16 v4.h, v7.h, 63
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 6, v7.h
-; GFX1200-NEXT: v_and_b16 v10.l, v5.h, 63
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, v1.h, 1 clamp
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v4.h
-; GFX1200-NEXT: v_and_b16 v4.h, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 6, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, v6.l, 1
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v1.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: v_or_b16 v1.l, v5.l, v1.l
+; GFX1200-NEXT: v_sub_nc_u16 v5.l, 2, v10.h
+; GFX1200-NEXT: v_or_b16 v1.h, v11.l, v8.h
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v2.h, v14.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v10.l
-; GFX1200-NEXT: v_add_nc_u16 v8.h, v8.h, -1
-; GFX1200-NEXT: v_lshrrev_b16 v4.h, 7, v4.h
-; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v9.h
-; GFX1200-NEXT: v_lshrrev_b16 v11.h, v1.h, v10.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.l, s0
+; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: v_and_b16 v6.l, v7.l, 63
+; GFX1200-NEXT: v_and_b16 v1.h, v6.h, v1.h
+; GFX1200-NEXT: v_and_b16 v8.h, v2.h, 63
+; GFX1200-NEXT: v_and_b16 v8.l, v5.h, 1
+; GFX1200-NEXT: v_sub_nc_u16 v6.h, v5.l, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.l
+; GFX1200-NEXT: v_and_b16 v6.l, 0x3ff, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, 6, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, 6, v2.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
-; GFX1200-NEXT: v_and_b16 v8.h, v10.h, v8.h
-; GFX1200-NEXT: v_and_b16 v10.l, v4.h, 1
-; GFX1200-NEXT: v_and_b16 v7.h, v7.h, v9.h
-; GFX1200-NEXT: v_and_b16 v9.h, v11.h, 1
-; GFX1200-NEXT: v_mov_b16_e32 v11.l, v14.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v10.h
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v8.l, v7.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v1.h
-; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v10.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
+; GFX1200-NEXT: v_or_b16 v11.h, 0x400, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v8.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
+; GFX1200-NEXT: v_or_b16 v8.l, v11.l, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v1.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 7, v3.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v7.h
-; GFX1200-NEXT: v_cmp_o_f16_e64 s2, v13.l, v13.l
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v8.h
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v12, 0, 1, s0
+; GFX1200-NEXT: v_and_b16 v8.h, v6.l, 1
+; GFX1200-NEXT: v_and_b16 v7.h, v11.h, v7.h
+; GFX1200-NEXT: v_and_b16 v7.l, v7.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v11.h
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v12.l
+; GFX1200-NEXT: v_lshrrev_b16 v12.l, v5.l, v11.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v7.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.l
+; GFX1200-NEXT: v_or_b16 v7.h, v11.l, v8.h
+; GFX1200-NEXT: v_and_b16 v8.l, v12.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s4
+; GFX1200-NEXT: v_cndmask_b32_e64 v15, 0, 1, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 7, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v10.l, v1.h
+; GFX1200-NEXT: v_and_b16 v2.h, v2.h, v7.h
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v13.l
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v15.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v7.h, v7.h, 0, vcc_lo
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s2
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v5.h
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v9.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 7, v4.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_and_b16 v5.h, v6.l, v8.l
-; GFX1200-NEXT: v_mov_b16_e32 v6.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v9, 31, v0
-; GFX1200-NEXT: v_or_b16 v2.h, v2.h, v1.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s5
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v5.h, s3
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, v6.l
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 8, s4
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v1.h, v11.h, v1.h
-; GFX1200-NEXT: v_and_b16 v5.h, 0x80, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 6
-; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v9.l
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s5
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v1.h
-; GFX1200-NEXT: v_or_b16 v0.h, v5.h, v6.h
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v7.l, 6
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 3, v6.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 7, v1.h
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v6.l, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s3
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s3
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v6.h
-; GFX1200-NEXT: v_or_b16 v7.l, v5.h, v7.l
-; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v3.l
-; GFX1200-NEXT: v_or_b16 v8.l, v8.h, v8.l
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v9.h, s0
+; GFX1200-NEXT: v_or_b16 v7.l, v11.l, v8.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s2
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 7, v2.h
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v13.l, v13.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.h, v7.l
+; GFX1200-NEXT: v_mov_b16_e32 v5.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.h, 8, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s3
+; GFX1200-NEXT: v_cndmask_b16 v7.h, 0, 8, s2
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s1
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v9.l, v5.l
+; GFX1200-NEXT: v_and_b16 v6.h, 0x80, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v10.h, v7.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v10, 31, v0
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v12.l, v6.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, 6
+; GFX1200-NEXT: v_or_b16 v0.h, v6.h, v7.h
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, 6
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, 7, v10.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 7, v6.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 3, v5.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s3
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 3, v7.l
+; GFX1200-NEXT: v_or_b16 v0.h, v0.h, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 8, s1
+; GFX1200-NEXT: v_or_b16 v7.h, v6.h, v7.h
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
; GFX1200-NEXT: v_or_b16 v9.l, v8.h, v9.l
-; GFX1200-NEXT: v_or_b16 v3.l, v7.l, v7.h
-; GFX1200-NEXT: v_and_b16 v1.l, 0xff, v5.l
-; GFX1200-NEXT: v_or_b16 v1.h, v8.l, v1.h
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v2.h
-; GFX1200-NEXT: v_or_b16 v4.h, v9.l, v4.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v5.l
+; GFX1200-NEXT: v_or_b16 v8.l, v8.h, v8.l
+; GFX1200-NEXT: v_or_b16 v1.h, v7.h, v5.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v7.l
+; GFX1200-NEXT: v_or_b16 v2.h, v9.l, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7f, v1.l, s0
+; GFX1200-NEXT: v_or_b16 v5.l, v8.l, v6.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v3.l, v0.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v1.h, v0.h, vcc_lo
; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
-; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v3.h
+; GFX1200-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v4.h, v1.h, s3
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v2.h, v5.l, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v14.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v5.h, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v6.h, vcc_lo
; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v8.h, s0
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7f, v2.l, s1
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v14.l, v14.l
+; GFX1200-NEXT: v_lshlrev_b16 v2.h, 8, v3.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v1.h, v8.h, s1
+; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v4.h
+; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7f, v0.h, vcc_lo
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_or_b16 v6.h, v4.l, v3.h
; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7f, v0.l, s0
+; GFX1200-NEXT: v_or_b16 v6.l, v1.h, v2.h
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_or_b16 v6.l, v1.l, v1.h
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v0.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX1200-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX1200-NEXT: v_lshrrev_b32_e32 v5, 8, v6
-; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX1200-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX1200-NEXT: v_mov_b16_e32 v6.l, v6.h
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
@@ -2797,21 +2757,20 @@ define <7 x i8> @to_fp8_v7f16(<7 x half> %x) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v4.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v4.l, v1
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.h, v3
; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v7.l, v2
-; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v4.l, v0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v4.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v4.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_dual_lshrrev_b32 v5, 8, v7 :: v_dual_lshlrev_b32 v6, 16, v1
-; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v4
+; GFX1250-TRUE16-NEXT: v_cvt_pk_fp8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v4
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, v4.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v7
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v4.l
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v7.l
; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[8:9], 24, v[6:7]
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v6.l, v7.h
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v8.l
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
@@ -3251,447 +3210,440 @@ define <5 x i8> @to_bf8_v5f16(<5 x half> %x) {
; GFX1200-NEXT: s_wait_samplecnt 0x0
; GFX1200-NEXT: s_wait_bvhcnt 0x0
; GFX1200-NEXT: s_wait_kmcnt 0x0
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v2.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.h, v2.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.h, v2.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v3.l, v2.l
; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v2
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 31, v2
; GFX1200-NEXT: v_lshrrev_b16 v4.l, 8, v2.l
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
-; GFX1200-NEXT: v_sub_nc_u16 v4.h, -5, v3.l
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v3.h
-; GFX1200-NEXT: v_and_b16 v5.h, 0x7f, v3.h
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v12.l
-; GFX1200-NEXT: v_lshrrev_b16 v3.h, 7, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, -5, v3.h
+; GFX1200-NEXT: v_and_b16 v2.h, 0x3ff, v3.l
+; GFX1200-NEXT: v_and_b16 v5.l, 0x7f, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, 7, v3.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v12.l
; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
-; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v5.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v5.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.h
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, -5, v6.h
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v4.h, 1 clamp
-; GFX1200-NEXT: v_lshrrev_b16 v10.l, v4.h, v7.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.l, v12.l
+; GFX1200-NEXT: v_or_b16 v7.h, 0x400, v2.h
+; GFX1200-NEXT: v_lshrrev_b16 v2.h, 8, v2.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v5.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.h, v12.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, v4.h, 1 clamp
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v5.h
+; GFX1200-NEXT: v_and_b16 v9.l, v2.h, 1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_and_b16 v4.h, v5.l, 1
-; GFX1200-NEXT: v_min_u16 v9.l, v9.l, 15
-; GFX1200-NEXT: v_and_b16 v9.h, 0x7f, v6.l
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v6.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
+; GFX1200-NEXT: v_sub_nc_u16 v9.h, -5, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v6.l, 1
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, v6.l, v7.h
+; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v10.l, v4.h, v7.h
; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
-; GFX1200-NEXT: v_or_b16 v4.h, v11.l, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, 7, v6.l
+; GFX1200-NEXT: v_or_b16 v4.h, 0x400, v8.h
+; GFX1200-NEXT: v_and_b16 v10.h, 0x7f, v5.h
+; GFX1200-NEXT: v_and_b16 v3.l, v3.l, v9.l
+; GFX1200-NEXT: v_and_b16 v9.l, v10.l, 1
+; GFX1200-NEXT: v_and_b16 v8.l, v7.h, v8.l
; GFX1200-NEXT: v_and_b16 v4.l, 0x80, v4.l
-; GFX1200-NEXT: v_or_b16 v10.h, 0x400, v8.h
-; GFX1200-NEXT: v_and_b16 v8.l, v7.l, v8.l
-; GFX1200-NEXT: v_and_b16 v3.h, v3.h, v4.h
-; GFX1200-NEXT: v_and_b16 v4.h, v10.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.h, v9.l, 1 clamp
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v3.h, v5.l, v3.h
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v8.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v9.l, v10.h
-; GFX1200-NEXT: v_or_b16 v5.h, 0x7c, v4.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v10.h
+; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, v3.l
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, 8, v8.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v8.l
+; GFX1200-NEXT: v_min_u16 v8.l, v9.h, 15
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v3.h
-; GFX1200-NEXT: v_and_b16 v9.h, v5.l, 1
+; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s3
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v2.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, v8.l, 1 clamp
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v2.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s3, 0, v8.l
; GFX1200-NEXT: v_cmp_class_f16_e64 s6, v2.l, 0x204
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v11.l
+; GFX1200-NEXT: v_or_b16 v8.h, v11.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v9.l, v8.l, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v13, 0, 1, s1
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s2
-; GFX1200-NEXT: v_and_b16 v9.l, v8.h, 1
-; GFX1200-NEXT: v_or_b16 v4.h, v8.l, v4.h
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, v7.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v7.h, v10.h
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v11.l
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s2
-; GFX1200-NEXT: v_and_b16 v4.h, v7.l, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v7.l, v8.l, -1
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v13.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, 14
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v3.h
-; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
-; GFX1200-NEXT: v_and_b16 v7.l, v10.h, v7.l
-; GFX1200-NEXT: v_or_b16 v8.l, v8.l, v9.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v3.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 30, v3.l
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v10.l, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.l
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v8.l, 2, v3.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v8.h, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v4.l, v8.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v10.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s2
+; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v2.l, v2.l
+; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v8.h
+; GFX1200-NEXT: v_lshlrev_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, v11.l
+; GFX1200-NEXT: v_mov_b16_e32 v11.l, v14.l
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s1
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.h, -1
+; GFX1200-NEXT: v_and_b16 v8.h, v3.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v3.h, 14
+; GFX1200-NEXT: v_and_b16 v9.h, v9.l, 1
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v10.l, v6.l
+; GFX1200-NEXT: v_and_b16 v8.l, v4.h, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v7.h, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 2, v3.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s2, 1, v3.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v6.l
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s4, 0, v8.l
+; GFX1200-NEXT: v_or_b16 v8.l, v11.l, v8.h
+; GFX1200-NEXT: v_or_b16 v7.h, v4.l, v7.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s5, 30, v3.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 4, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 3, v6.l
-; GFX1200-NEXT: v_or_b16 v3.h, v8.l, v3.h
-; GFX1200-NEXT: v_or_b16 v7.l, v7.l, v9.h
+; GFX1200-NEXT: v_cndmask_b16 v8.h, 0, 4, s1
+; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s1
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s4
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v2.h
+; GFX1200-NEXT: v_or_b16 v2.h, v7.h, v2.h
; GFX1200-NEXT: v_or_b16 v8.h, v4.l, v8.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s0, 1, v3.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.l, v6.l, 0, s4
-; GFX1200-NEXT: v_and_b16 v7.l, v7.h, v7.l
-; GFX1200-NEXT: v_or_b16 v4.h, v8.h, v4.h
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s4
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v7.l, s1
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.h, s0
+; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v8.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s4, 30, v3.h
+; GFX1200-NEXT: v_sub_nc_u16 v7.l, -5, v2.l
+; GFX1200-NEXT: v_or_b16 v5.l, 0x7c, v4.l
+; GFX1200-NEXT: v_or_b16 v6.l, v8.h, v6.l
+; GFX1200-NEXT: v_or_b16 v9.h, v10.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v5.h
+; GFX1200-NEXT: s_and_b32 s1, s4, s1
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v2
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v4.h, v1.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v5.l, v3.l
-; GFX1200-NEXT: s_and_b32 s0, s3, s2
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v6.h, v7.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v6.l, s2
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, s5, s0
-; GFX1200-NEXT: v_sub_nc_u16 v5.l, -5, v4.h
+; GFX1200-NEXT: s_or_b32 s1, s5, s1
+; GFX1200-NEXT: v_and_b16 v3.h, v4.h, v9.h
+; GFX1200-NEXT: v_min_u16 v4.h, v7.l, 15
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, s0
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0, v3.h, s3
+; GFX1200-NEXT: v_sub_nc_u16 v5.h, v4.h, 1 clamp
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v4.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.l, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v7, 0, 1, s1
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v4.l, v1.l
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v9.l, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.h, 7, v13.l
+; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, s6
+; GFX1200-NEXT: v_mov_b16_e32 v6.l, v7.l
+; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v4.l
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, v5.h, 1
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v3.h
+; GFX1200-NEXT: v_and_b16 v8.h, 0x7f, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.h, v6.l
+; GFX1200-NEXT: v_or_b16 v8.l, 0x400, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v7.l, v7.l, -1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 4, vcc_lo
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v5.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v8.h
+; GFX1200-NEXT: v_and_b16 v7.l, v8.l, v7.l
+; GFX1200-NEXT: v_or_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, 14
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, 7, v4.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_and_b16 v7.l, v5.l, 1
+; GFX1200-NEXT: v_or_b16 v3.h, v6.h, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, 2, v6.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, v4.h, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s1
+; GFX1200-NEXT: v_or_b16 v6.h, v10.l, v7.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v9.l, v7.h, v9.l
+; GFX1200-NEXT: v_and_b16 v9.h, v8.h, 1
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7e, v2.h, s0
+; GFX1200-NEXT: v_and_b16 v4.l, v4.l, v6.h
; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.l
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, 14
-; GFX1200-NEXT: v_min_u16 v5.l, v5.l, 15
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v6.l
+; GFX1200-NEXT: v_or_b16 v7.l, v9.l, v3.l
+; GFX1200-NEXT: v_or_b16 v9.l, v11.l, v9.h
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.l, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, v5.h, v8.l
+; GFX1200-NEXT: s_and_b32 s1, s1, s0
+; GFX1200-NEXT: v_lshrrev_b32_e32 v13, 16, v1
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.l
+; GFX1200-NEXT: v_and_b16 v3.l, v5.h, v9.l
+; GFX1200-NEXT: v_or_b16 v4.h, 0x7c, v7.h
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.l, vcc_lo
-; GFX1200-NEXT: v_lshlrev_b16 v4.l, 7, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v7.l, v3.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 4, s0
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v2.l, v2.l
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 2, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v5.h, s6
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
-; GFX1200-NEXT: v_or_b16 v5.h, v4.l, v6.h
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v6.h, v1.l
-; GFX1200-NEXT: v_or_b16 v2.l, v4.l, v2.l
-; GFX1200-NEXT: v_sub_nc_u16 v7.l, v5.l, 1 clamp
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7e, v3.h, vcc_lo
-; GFX1200-NEXT: v_or_b16 v3.l, v5.h, v3.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.h
-; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v6.l
-; GFX1200-NEXT: v_and_b16 v5.h, 0x3ff, v6.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v7.l, 1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v6.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v2.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v2.h
-; GFX1200-NEXT: v_or_b16 v2.h, 0x400, v5.h
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.h, -1
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v3.l, 0x7f, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 8, v5.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v5.l, v2.h
-; GFX1200-NEXT: v_and_b16 v6.l, v2.h, v6.l
-; GFX1200-NEXT: s_and_b32 s0, s1, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
-; GFX1200-NEXT: v_or_b16 v3.l, 0x7c, v4.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, s0
+; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v3.l, s2
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v13.l
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 30, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s0
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v3.l, v8.h, v3.l
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, -5, v5.h
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, s2, s0
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, 7, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
-; GFX1200-NEXT: v_and_b16 v6.l, v5.h, 1
-; GFX1200-NEXT: v_and_b16 v8.h, v7.h, 1
+; GFX1200-NEXT: s_or_b32 s1, vcc_lo, s1
+; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v1.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v12.l, 0x204
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v12.l
-; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v1.l
-; GFX1200-NEXT: v_and_b16 v3.h, 0xff, v3.h
-; GFX1200-NEXT: v_or_b16 v8.l, v9.l, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.h, s1
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v3.l
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v12.l
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, 14
+; GFX1200-NEXT: v_min_u16 v6.l, v6.l, 15
+; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v5.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v4.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v4.l, v6.h, v6.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v6.l, v13.l
-; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v5.l
-; GFX1200-NEXT: v_and_b16 v2.h, v2.h, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v6.h, 0, 4, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v7.h, s1
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v2.l
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v13.l
+; GFX1200-NEXT: v_sub_nc_u16 v8.l, v6.l, 1 clamp
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, vcc_lo
+; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
+; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v7.l
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v12.l, 0x204
+; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v7.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.l, 1
+; GFX1200-NEXT: v_or_b16 v3.l, v6.h, v3.l
+; GFX1200-NEXT: v_or_b16 v6.h, v7.l, v4.l
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.l
+; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v8.h
+; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, v3.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.h, v4.l
-; GFX1200-NEXT: v_sub_nc_u16 v3.l, -5, v6.l
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, v4.h, s0
+; GFX1200-NEXT: v_and_b16 v4.h, 0x7f, v7.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v6.h, v3.l, vcc_lo
+; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v8.h
+; GFX1200-NEXT: v_and_b16 v6.h, v7.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v6.l, v7.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v2.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v2.l
; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, 0, v2.h, vcc_lo
-; GFX1200-NEXT: v_and_b16 v7.l, 0x80, v7.l
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.l
-; GFX1200-NEXT: v_min_u16 v3.l, v3.l, 15
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.l, 0x7e, v2.l, s0
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v7.h, v2.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.h
+; GFX1200-NEXT: v_and_b16 v6.h, v8.h, 1
; GFX1200-NEXT: v_lshrrev_b32_e32 v12, 16, v0
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v13.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.h, v3.l, 1 clamp
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v2.h
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, vcc_lo
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, v5.l
-; GFX1200-NEXT: v_and_b16 v5.l, 0x3ff, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.h, v6.h, 1
-; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 4, s0
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v4.h, 14
-; GFX1200-NEXT: v_or_b16 v8.h, 0x400, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v7.h, v7.h, -1
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, 8, v5.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, 2, v4.h
-; GFX1200-NEXT: v_and_b16 v7.h, v8.h, v7.h
-; GFX1200-NEXT: v_or_b16 v8.l, v7.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s0
-; GFX1200-NEXT: v_or_b16 v9.h, v7.l, v9.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v7.h
-; GFX1200-NEXT: v_and_b16 v7.h, v5.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v9.l, v3.l, v8.h
-; GFX1200-NEXT: v_or_b16 v2.h, v8.l, v2.h
-; GFX1200-NEXT: v_or_b16 v8.l, v9.h, v4.l
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v4.h
-; GFX1200-NEXT: v_or_b16 v7.h, v10.l, v7.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s0
-; GFX1200-NEXT: v_and_b16 v10.h, v9.l, 1
-; GFX1200-NEXT: v_lshrrev_b16 v6.h, v6.h, v8.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, 0x7e, v3.h, s0
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v1.l, 0x204
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v8.l, v2.h, vcc_lo
-; GFX1200-NEXT: v_and_b16 v5.h, v5.h, v7.h
+; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc_lo
; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.l
-; GFX1200-NEXT: v_or_b16 v9.h, v11.l, v10.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v3.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v4.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.l, v5.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v4.h
-; GFX1200-NEXT: v_and_b16 v5.l, v6.h, v9.h
-; GFX1200-NEXT: v_or_b16 v4.h, 0x7c, v7.l
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.h, v0.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s3, 3, v4.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v7.h, v0.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, v5.l, s0
-; GFX1200-NEXT: s_and_b32 s0, s1, vcc_lo
-; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v1.l
-; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s3
+; GFX1200-NEXT: v_and_b16 v4.l, v4.h, 1
+; GFX1200-NEXT: v_or_b16 v6.h, v9.l, v6.h
+; GFX1200-NEXT: v_lshlrev_b16 v3.h, 8, v3.h
+; GFX1200-NEXT: v_cmp_class_f16_e64 s5, v13.l, 0x204
+; GFX1200-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.l, v10.l, v4.l
+; GFX1200-NEXT: v_lshrrev_b16 v4.l, v8.l, v7.l
+; GFX1200-NEXT: v_and_b16 v6.h, v7.h, v6.h
+; GFX1200-NEXT: v_or_b16 v7.l, 0x7c, v5.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, s2, s0
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v9.l, v3.l
+; GFX1200-NEXT: s_or_b32 s1, s2, s1
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v6.l
+; GFX1200-NEXT: v_and_b16 v2.l, v4.l, v2.l
+; GFX1200-NEXT: v_add_nc_u16 v4.l, v8.h, v6.h
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v4.h, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v4.l, 0, s3
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v8.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, s1
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v1.l
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v2.h, v7.l, vcc_lo
-; GFX1200-NEXT: v_and_b16 v8.h, 0x3ff, v7.h
-; GFX1200-NEXT: v_add_nc_u16 v5.l, v6.l, v5.l
-; GFX1200-NEXT: v_sub_nc_u16 v6.l, -5, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v8.l
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0, v2.l, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, 0, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s2, v1.l, 0x204
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v5.l, 14
-; GFX1200-NEXT: v_min_u16 v6.l, v6.l, 15
-; GFX1200-NEXT: v_cndmask_b16 v5.l, 0, 4, s0
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v5.l, s1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v5.l, v0.l
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v4.h, v2.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v1.l, v1.l
+; GFX1200-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, s0
+; GFX1200-NEXT: v_sub_nc_u16 v4.h, -5, v5.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v1
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v5.h, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v2.l
+; GFX1200-NEXT: v_cndmask_b16 v8.h, v4.l, 0, vcc_lo
+; GFX1200-NEXT: v_min_u16 v4.h, v4.h, 15
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 7, v7.l
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v5.h, 14
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v5.h, v0.l
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v4.h, s2
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v2.h
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, v6.l, 1 clamp
-; GFX1200-NEXT: v_or_b16 v5.l, v6.h, v5.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v2.h
-; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v2.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0, 4, s0
+; GFX1200-NEXT: v_sub_nc_u16 v6.l, v4.h, 1 clamp
+; GFX1200-NEXT: v_or_b16 v4.l, v2.h, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v1.h
+; GFX1200-NEXT: v_and_b16 v7.h, 0x3ff, v5.h
+; GFX1200-NEXT: v_cndmask_b16 v2.h, 0x7e, v3.l, s1
+; GFX1200-NEXT: v_lshlrev_b16 v8.l, v6.l, 1
+; GFX1200-NEXT: v_cndmask_b16 v2.l, v2.l, 0, s0
+; GFX1200-NEXT: v_or_b16 v1.l, v6.h, v1.l
+; GFX1200-NEXT: v_or_b16 v9.l, 0x400, v7.h
; GFX1200-NEXT: v_or_b16 v7.l, v6.h, v7.l
-; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.l, 1
-; GFX1200-NEXT: v_or_b16 v3.l, v5.l, v3.l
-; GFX1200-NEXT: s_and_b32 s1, s1, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s3, v13.l, 0x204
-; GFX1200-NEXT: v_or_b16 v5.l, v7.l, v4.l
-; GFX1200-NEXT: v_or_b16 v7.l, 0x400, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v9.l, v9.l, -1
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
-; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v3.l, v5.l, v3.l, vcc_lo
-; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 30, v2.h
-; GFX1200-NEXT: v_and_b16 v4.l, v7.l, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v2.h, v6.l, v7.l
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v4.l
-; GFX1200-NEXT: v_or_b16 v4.l, 0x7c, v6.h
-; GFX1200-NEXT: v_and_b16 v4.h, v2.h, 1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_add_nc_u16 v8.l, v8.l, -1
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v8.h
+; GFX1200-NEXT: v_or_b16 v1.l, v1.l, v2.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s0, 30, v1.h
+; GFX1200-NEXT: v_or_b16 v2.l, v7.l, v8.h
+; GFX1200-NEXT: v_and_b16 v3.l, v9.l, v8.l
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v1.h
+; GFX1200-NEXT: v_lshrrev_b16 v3.h, v4.h, v9.l
+; GFX1200-NEXT: s_and_b32 s0, s0, vcc_lo
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 30, v1.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v3.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v2.l, v1.l, s1
+; GFX1200-NEXT: v_and_b16 v1.h, v3.h, 1
+; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v2.l, v12.l
+; GFX1200-NEXT: v_and_b16 v7.l, 0x7f, v5.h
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, s2
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s0, vcc_lo, s1
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v1.l, v1.l
+; GFX1200-NEXT: s_or_b32 s0, vcc_lo, s0
+; GFX1200-NEXT: v_lshrrev_b16 v5.h, 7, v5.h
+; GFX1200-NEXT: v_and_b16 v2.h, 0xff, v2.h
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v7.l
+; GFX1200-NEXT: v_mov_b16_e32 v3.l, v8.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1200-NEXT: v_or_b16 v1.h, v3.l, v1.h
+; GFX1200-NEXT: v_lshrrev_b16 v3.l, v6.l, v9.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 8, v7.h
+; GFX1200-NEXT: v_sub_nc_u16 v7.h, -5, v2.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v4.h
+; GFX1200-NEXT: v_mov_b16_e32 v7.l, v8.l
+; GFX1200-NEXT: v_and_b16 v1.h, v3.l, v1.h
+; GFX1200-NEXT: v_and_b16 v4.h, v6.l, 1
+; GFX1200-NEXT: v_min_u16 v3.l, v7.h, 15
+; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.l, v12.l
+; GFX1200-NEXT: v_or_b16 v7.h, 0x7c, v6.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, 0, v1.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v4.h, v7.l, v4.h
+; GFX1200-NEXT: v_sub_nc_u16 v8.h, v3.l, 1 clamp
+; GFX1200-NEXT: v_and_b16 v7.l, 0x3ff, v8.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v3.l, v4.l, s0
-; GFX1200-NEXT: v_frexp_exp_i16_f16_e32 v3.l, v12.l
-; GFX1200-NEXT: v_mov_b16_e32 v5.l, v9.l
-; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v7.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, 7, v7.h
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v13.l
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v7.h, s0
+; GFX1200-NEXT: v_add_nc_u16 v1.h, v3.h, v1.h
+; GFX1200-NEXT: v_and_b16 v3.h, v5.h, v4.h
+; GFX1200-NEXT: v_lshlrev_b16 v9.l, v8.h, 1
+; GFX1200-NEXT: v_or_b16 v4.h, 0x400, v7.l
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v13.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v1.h
+; GFX1200-NEXT: v_add_nc_u16 v3.h, v6.l, v3.h
+; GFX1200-NEXT: v_add_nc_u16 v5.h, v9.l, -1
+; GFX1200-NEXT: v_and_b16 v9.l, 0x7f, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v6.l, 8, v7.l
+; GFX1200-NEXT: v_lshrrev_b16 v8.l, 7, v8.l
+; GFX1200-NEXT: v_lshrrev_b16 v7.l, v3.l, v4.h
+; GFX1200-NEXT: v_and_b16 v5.h, v4.h, v5.h
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v9.l
+; GFX1200-NEXT: v_and_b16 v9.l, v6.l, 1
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.h, 0x7e, v1.h, vcc_lo
-; GFX1200-NEXT: v_or_b16 v4.h, v5.l, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v9.l
-; GFX1200-NEXT: v_lshrrev_b16 v5.l, v8.l, v7.l
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v8.h
-; GFX1200-NEXT: v_sub_nc_u16 v8.l, -5, v3.l
-; GFX1200-NEXT: v_frexp_mant_f16_e32 v8.h, v12.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
-; GFX1200-NEXT: v_and_b16 v4.h, v5.l, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v6.l
-; GFX1200-NEXT: v_min_u16 v5.l, v8.l, 15
-; GFX1200-NEXT: v_and_b16 v6.l, v7.l, 1
-; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.h, s1
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, s0
-; GFX1200-NEXT: v_sub_nc_u16 v9.l, v5.l, 1 clamp
-; GFX1200-NEXT: v_and_b16 v1.h, 0xff, v1.h
-; GFX1200-NEXT: v_or_b16 v6.l, v8.l, v6.l
-; GFX1200-NEXT: v_and_b16 v8.l, 0x3ff, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v2.h, v2.h, v4.h
-; GFX1200-NEXT: v_lshlrev_b16 v9.h, v9.l, 1
-; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
-; GFX1200-NEXT: v_and_b16 v4.h, v7.h, v6.l
-; GFX1200-NEXT: v_and_b16 v7.h, 0x7f, v8.h
-; GFX1200-NEXT: v_or_b16 v6.l, 0x400, v8.l
-; GFX1200-NEXT: v_add_nc_u16 v6.h, v9.h, -1
-; GFX1200-NEXT: v_lshrrev_b16 v8.h, 7, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v4.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.l, 8, v8.l
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s1, 0, v7.h
-; GFX1200-NEXT: v_and_b16 v6.h, v6.l, v6.h
-; GFX1200-NEXT: v_lshrrev_b16 v7.h, v5.l, v6.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v2.h
-; GFX1200-NEXT: v_and_b16 v8.l, v7.l, 1
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v6.h, vcc_lo
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, 0, s0
+; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v5.h
; GFX1200-NEXT: v_cndmask_b32_e64 v10, 0, 1, s1
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v4.h
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s2, 0, v6.h
-; GFX1200-NEXT: v_and_b16 v6.h, v7.h, 1
-; GFX1200-NEXT: v_lshrrev_b16 v6.l, v9.l, v6.l
-; GFX1200-NEXT: v_or_b16 v8.l, v10.l, v8.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v3.h
+; GFX1200-NEXT: v_and_b16 v5.h, v7.l, 1
+; GFX1200-NEXT: v_lshrrev_b16 v4.h, v8.h, v4.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
; GFX1200-NEXT: v_cndmask_b32_e64 v14, 0, 1, s2
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, 0, s0
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, s1
-; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v5.h, v11.l
-; GFX1200-NEXT: v_and_b16 v5.h, v8.h, v8.l
-; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_or_b16 v9.l, v10.l, v9.l
+; GFX1200-NEXT: v_cndmask_b32_e64 v11, 0, 1, s1
; GFX1200-NEXT: v_lshrrev_b16 v8.h, 8, v0.l
+; GFX1200-NEXT: v_cmp_ne_u16_e32 vcc_lo, 0, v3.l
+; GFX1200-NEXT: v_mov_b16_e32 v10.l, v14.l
+; GFX1200-NEXT: v_and_b16 v6.h, v8.l, v9.l
; GFX1200-NEXT: v_cndmask_b16 v8.l, 0, 4, s0
-; GFX1200-NEXT: v_cmp_ne_u16_e64 s0, 0, v5.l
-; GFX1200-NEXT: v_add_nc_u16 v5.h, v7.l, v5.h
-; GFX1200-NEXT: v_or_b16 v6.h, v10.l, v6.h
-; GFX1200-NEXT: v_and_b16 v5.l, 0x80, v8.h
-; GFX1200-NEXT: v_add_nc_u16 v4.l, v4.l, 14
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 3, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v5.h
-; GFX1200-NEXT: v_and_b16 v6.l, v6.l, v6.h
-; GFX1200-NEXT: v_or_b16 v7.l, v5.l, v8.l
-; GFX1200-NEXT: v_lshlrev_b16 v6.h, 2, v4.l
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s5, 30, v4.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s2
-; GFX1200-NEXT: v_cndmask_b16 v6.l, 0, v6.l, s0
-; GFX1200-NEXT: v_or_b16 v2.h, v7.l, v2.h
-; GFX1200-NEXT: v_or_b16 v6.h, v5.l, v6.h
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s3, 1, v4.l
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, v11.l
+; GFX1200-NEXT: v_and_b16 v3.l, 0x80, v8.h
+; GFX1200-NEXT: v_or_b16 v5.h, v10.l, v5.h
+; GFX1200-NEXT: v_add_nc_u16 v6.l, v6.l, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v3.h, v3.h, 0, s1
+; GFX1200-NEXT: v_add_nc_u16 v5.l, v5.l, 14
+; GFX1200-NEXT: v_or_b16 v6.h, v3.l, v8.l
+; GFX1200-NEXT: v_and_b16 v4.h, v4.h, v5.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v6.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v3.h
+; GFX1200-NEXT: v_lshlrev_b16 v5.h, 2, v5.l
+; GFX1200-NEXT: v_or_b16 v1.h, v6.h, v1.h
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, 0, v4.h, vcc_lo
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v5.l
+; GFX1200-NEXT: v_or_b16 v5.h, v3.l, v5.h
+; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v5.l
+; GFX1200-NEXT: v_add_nc_u16 v4.h, v7.l, v4.h
; GFX1200-NEXT: v_mov_b16_e32 v8.l, v9.l
-; GFX1200-NEXT: v_add_nc_u16 v6.l, v7.h, v6.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v7, 31, v0
-; GFX1200-NEXT: v_or_b16 v6.h, v6.h, v4.h
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s6, 30, v4.l
-; GFX1200-NEXT: v_add_nc_u16 v3.l, v3.l, v8.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s1, 3, v6.l
-; GFX1200-NEXT: v_lshlrev_b16 v4.h, 7, v7.l
-; GFX1200-NEXT: v_cndmask_b16 v5.h, v5.h, 0, s2
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v6.h, v2.h, s3
-; GFX1200-NEXT: v_add_nc_u16 v0.h, v3.l, 14
-; GFX1200-NEXT: v_cndmask_b16 v3.l, 0, 4, s1
-; GFX1200-NEXT: v_cndmask_b16 v4.l, v6.l, 0, s1
-; GFX1200-NEXT: s_and_b32 s1, s5, s4
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 3, v5.h
-; GFX1200-NEXT: v_lshlrev_b16 v7.l, 2, v0.h
-; GFX1200-NEXT: v_or_b16 v3.l, v4.h, v3.l
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 30, v5.l
+; GFX1200-NEXT: v_or_b16 v5.h, v5.h, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v5.l, v6.l, 0, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e32 vcc_lo, 3, v4.h
+; GFX1200-NEXT: v_add_nc_u16 v2.l, v2.l, v8.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v8, 31, v0
+; GFX1200-NEXT: s_and_b32 s0, s3, s2
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v5.h, v1.h, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v4.h, v4.h, 0, vcc_lo
+; GFX1200-NEXT: v_add_nc_u16 v0.h, v2.l, 14
+; GFX1200-NEXT: v_cndmask_b16 v2.l, 0, 4, vcc_lo
+; GFX1200-NEXT: v_lshlrev_b16 v3.h, 7, v8.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: s_or_b32 s5, s6, s1
-; GFX1200-NEXT: v_cmp_gt_i16_e64 s1, 1, v0.h
-; GFX1200-NEXT: v_cmp_eq_u16_e64 s3, 30, v0.h
-; GFX1200-NEXT: v_or_b16 v6.l, v4.h, v7.l
-; GFX1200-NEXT: v_or_b16 v3.l, v3.l, v4.l
-; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v13.l, v13.l
-; GFX1200-NEXT: v_cmp_lt_i16_e64 s4, 30, v0.h
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v4.l, v6.l, v5.h
-; GFX1200-NEXT: v_or_b16 v5.h, 0x7c, v5.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7e, v1.l, s0
-; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v0.l, 0x204
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v4.l, v3.l, s1
-; GFX1200-NEXT: s_and_b32 s1, s3, s2
-; GFX1200-NEXT: v_or_b16 v3.l, 0x7c, v4.h
+; GFX1200-NEXT: s_or_b32 s3, s4, s0
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s0, 3, v5.l
+; GFX1200-NEXT: v_lshlrev_b16 v6.h, 2, v0.h
+; GFX1200-NEXT: v_cmp_gt_i16_e32 vcc_lo, 1, v0.h
+; GFX1200-NEXT: v_or_b16 v2.l, v3.h, v2.l
+; GFX1200-NEXT: v_cmp_eq_u16_e64 s1, 30, v0.h
+; GFX1200-NEXT: v_cmp_lt_i16_e64 s2, 30, v0.h
+; GFX1200-NEXT: v_or_b16 v6.l, v3.h, v6.h
+; GFX1200-NEXT: v_cndmask_b16 v1.l, v1.l, v7.h, s5
+; GFX1200-NEXT: v_or_b16 v2.l, v2.l, v4.h
+; GFX1200-NEXT: s_and_b32 s0, s1, s0
+; GFX1200-NEXT: v_cmp_o_f16_e64 s1, v13.l, v13.l
+; GFX1200-NEXT: v_or_b16 v4.h, v6.l, v5.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.h, s5
-; GFX1200-NEXT: s_or_b32 s2, s4, s1
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s1, 0, v0.l
-; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX1200-NEXT: s_or_b32 s0, s2, s0
+; GFX1200-NEXT: v_or_b16 v5.l, 0x7c, v3.l
+; GFX1200-NEXT: v_cmp_class_f16_e64 s2, v0.l, 0x204
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7e, v1.l, s1
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v4.h, v2.l, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.l, 0x7c, v3.h
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, s3
+; GFX1200-NEXT: v_cmp_eq_f16_e32 vcc_lo, 0, v0.l
; GFX1200-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v3.l, s2
-; GFX1200-NEXT: v_cmp_eq_f16_e64 s2, 0, v12.l
-; GFX1200-NEXT: v_or_b16 v4.l, v3.h, v2.l
-; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v2.h, v2.h, v5.l, s1
-; GFX1200-NEXT: v_cmp_class_f16_e64 s1, v12.l, 0x204
-; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v4.h, s2
; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX1200-NEXT: v_cndmask_b16 v4.h, v2.h, v5.h, s0
-; GFX1200-NEXT: v_or_b16 v2.h, v1.h, v1.l
-; GFX1200-NEXT: v_cvt_u32_u16_e32 v1, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v2.l, s0
+; GFX1200-NEXT: v_cmp_eq_f16_e64 s0, 0, v12.l
+; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v3.l, vcc_lo
+; GFX1200-NEXT: v_cmp_o_f16_e32 vcc_lo, v0.l, v0.l
+; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX1200-NEXT: v_cndmask_b16 v0.h, v0.h, v3.h, s0
+; GFX1200-NEXT: v_cmp_class_f16_e64 s0, v12.l, 0x204
+; GFX1200-NEXT: v_cvt_u32_u16_e32 v3, v4.l
+; GFX1200-NEXT: v_cndmask_b16 v1.h, v1.h, v5.l, s2
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v3.l, s1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX1200-NEXT: v_cndmask_b16 v0.l, v0.h, v2.l, s0
+; GFX1200-NEXT: v_lshlrev_b16 v0.h, 8, v1.l
; GFX1200-NEXT: v_cmp_o_f16_e64 s0, v12.l, v12.l
+; GFX1200-NEXT: v_or_b32_e32 v6, 0x7e7e0000, v3
; GFX1200-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-NEXT: v_cndmask_b16 v0.h, 0x7e, v4.h, vcc_lo
-; GFX1200-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX1200-NEXT: v_or_b32_e32 v6, 0x7e7e0000, v1
+; GFX1200-NEXT: v_cndmask_b16 v1.l, 0x7e, v1.h, vcc_lo
+; GFX1200-NEXT: v_or_b16 v2.l, v2.h, v0.h
; GFX1200-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX1200-NEXT: v_cndmask_b16 v0.l, 0x7e, v0.l, s0
-; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v0.h
-; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_and_b16 v0.h, 0xff, v1.l
+; GFX1200-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_lshlrev_b16 v1.l, 8, v0.l
+; GFX1200-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX1200-NEXT: v_lshrrev_b64 v[5:6], 24, v[5:6]
-; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v2.l
-; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX1200-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-NEXT: v_or_b16 v0.l, v0.h, v1.l
+; GFX1200-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX1200-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX1200-NEXT: v_mov_b16_e32 v3.l, v5.l
; GFX1200-NEXT: s_setpc_b64 s[30:31]
;
@@ -3699,19 +3651,18 @@ define <5 x i8> @to_bf8_v5f16(<5 x half> %x) {
; GFX1250-TRUE16: ; %bb.0:
; GFX1250-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v3.h, v1
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v3.l, v1
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v5.h, s0
; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v5.l, v2
-; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v3.l, v0
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.h
-; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, v3.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250-TRUE16-NEXT: v_dual_lshlrev_b32 v4, 16, v1 :: v_dual_lshrrev_b32 v1, 8, v3
+; GFX1250-TRUE16-NEXT: v_cvt_pk_bf8_f16_e64 v0.l, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
+; GFX1250-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v2.l, v3.l
+; GFX1250-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_lshrrev_b64 v[6:7], 24, v[4:5]
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v4.l, v5.l
-; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX1250-TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.l
; GFX1250-TRUE16-NEXT: s_set_pc_i64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
index b92acb67b0bce..41372c3e422dc 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.gfx11plus.ll
@@ -89,7 +89,10 @@ define amdgpu_kernel void @fma_v2f16_uniform(
; GFX11-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY [[S_LOAD_DWORDX8_IMM]].sub6
; GFX11-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[COPY8]], %subreg.sub0, killed [[COPY7]], %subreg.sub1
; GFX11-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 killed [[REG_SEQUENCE1]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: ("amdgpu-noclobber" load (s16) from %ir.3, addrspace 1)
- ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]]
+ ; GFX11-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; GFX11-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sgpr_32 = COPY killed [[REG_SEQUENCE4]]
; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 killed [[COPY9]]
; GFX11-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed [[REG_SEQUENCE2]], 0, 0 :: ("amdgpu-noclobber" load (s32) from %ir.4, addrspace 1)
; GFX11-NEXT: [[S_LOAD_DWORD_IMM1:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM killed [[REG_SEQUENCE3]], 0, 0 :: ("amdgpu-noclobber" load (s32) from %ir.5, addrspace 1)
diff --git a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
index cb64b3de060ff..98a6c22301193 100644
--- a/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmax3-maximumnum.ll
@@ -1918,48 +1918,38 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v4
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_max3_bf16_maximumnum_maximumnum__v_v_v_0:
@@ -2021,55 +2011,45 @@ define bfloat @v_max3_bf16_maximumnum_maximumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v4
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: v_max3_bf16_maximumnum_maximumnum__v_v_v_0:
@@ -2483,17 +2463,11 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v8
@@ -2503,11 +2477,8 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
@@ -2520,11 +2491,8 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
@@ -2534,17 +2502,11 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7
@@ -2553,11 +2515,8 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -2669,17 +2628,11 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v6, v8
@@ -2690,12 +2643,9 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
@@ -2709,11 +2659,8 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
@@ -2725,17 +2672,11 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7
@@ -2745,12 +2686,9 @@ define <2 x bfloat> @v_max3_v2bf16_maximumnum_maximumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
diff --git a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
index a183ea4ad2a73..9851a14074d18 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaxnum.ll
@@ -1920,12 +1920,12 @@ define amdgpu_kernel void @test_fmax_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s3, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -2039,12 +2039,12 @@ define amdgpu_kernel void @test_fmax_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s3, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-SDAG-NEXT: v_max_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll b/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
index 7638f32cc61ac..0b1b5a6359547 100644
--- a/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmed3.bf16.ll
@@ -73,14 +73,11 @@ define bfloat @v_test_fmed3_r_i_i_bf16_minimumnum_maximumnum(bfloat %a) #1 {
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_o_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v1
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v1
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4080, v0.l, vcc_lo
@@ -205,23 +202,17 @@ define <2 x bfloat> @v_test_fmed3_r_i_i_v2bf16_minimumnum_maximumnum(<2 x bfloat
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4000, v3.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, s0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, 2.0, v2
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, 2.0, v3
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, 0x4000, v1.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x4000, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 4.0, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 4.0, v3
diff --git a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
index da7f46a2a0613..08b7279c6221b 100644
--- a/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmin3-minimumnum.ll
@@ -1920,48 +1920,38 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v4
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX11-SDAG-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX11-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-SDAG-FAKE16-LABEL: v_min3_bf16_minimumnum_minimumnum__v_v_v_0:
@@ -2023,55 +2013,45 @@ define bfloat @v_min3_bf16_minimumnum_minimumnum__v_v_v_0(bfloat %a, bfloat %b,
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_4)
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v4
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v3
; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, v2.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v2, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v3, v3
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
+; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, vcc_lo
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-SDAG-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-SDAG-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
+; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v1.l, s0
; GFX12-SDAG-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-SDAG-FAKE16-LABEL: v_min3_bf16_minimumnum_minimumnum__v_v_v_0:
@@ -2488,17 +2468,11 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v8
@@ -2508,11 +2482,8 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
@@ -2525,11 +2496,8 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX11-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
@@ -2539,17 +2507,11 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7
@@ -2558,11 +2520,8 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX11-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -2674,17 +2633,11 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v3.l, s1
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v8.l, v1.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v6, v8
@@ -2695,12 +2648,9 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v3.l
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v4.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
@@ -2714,11 +2664,8 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v3
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v0
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
; GFX12-SDAG-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v4, v4
@@ -2730,17 +2677,11 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, s1
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s2
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v7.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7
@@ -2750,12 +2691,9 @@ define <2 x bfloat> @v_min3_v2bf16_minimumnum_minimumnum__v_v_v_0(<2 x bfloat> %
; GFX12-SDAG-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-SDAG-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
diff --git a/llvm/test/CodeGen/AMDGPU/fminnum.ll b/llvm/test/CodeGen/AMDGPU/fminnum.ll
index 86329738d2520..d321b33ade280 100644
--- a/llvm/test/CodeGen/AMDGPU/fminnum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminnum.ll
@@ -1833,12 +1833,12 @@ define amdgpu_kernel void @test_fmin_f16_v_ieee_on(ptr addrspace(1) %out, half %
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s3, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
@@ -1952,12 +1952,12 @@ define amdgpu_kernel void @test_fmin_f16_s_ieee_on(ptr addrspace(1) %out, half i
; GFX12-SDAG-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
; GFX12-SDAG-NEXT: s_lshr_b32 s3, s2, 16
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s2, s2
-; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s3, s3
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.l, s2, s2
+; GFX12-SDAG-NEXT: v_max_num_f16_e64 v0.h, s3, s3
; GFX12-SDAG-NEXT: s_mov_b32 s3, 0x31016000
; GFX12-SDAG-NEXT: s_mov_b32 s2, -1
; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.h, v0.l
+; GFX12-SDAG-NEXT: v_min_num_f16_e32 v0.l, v0.l, v0.h
; GFX12-SDAG-NEXT: buffer_store_b16 v0, off, s[0:3], null
; GFX12-SDAG-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
index 9b6fd0bcf703b..76c8085d644a7 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.bf16.ll
@@ -235,30 +235,17 @@ define amdgpu_kernel void @fneg_fabs_free_bf16(ptr addrspace(1) %out, i16 %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fneg_fabs_free_bf16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fneg_fabs_free_bf16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fneg_fabs_free_bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bitset1_b32 s2, 15
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%bc = bitcast i16 %in to bfloat
%fabs = call bfloat @llvm.fabs.bf16(bfloat %bc)
%fsub = fsub bfloat -0.0, %fabs
@@ -308,30 +295,17 @@ define amdgpu_kernel void @fneg_fabs_bf16(ptr addrspace(1) %out, bfloat %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fneg_fabs_bf16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fneg_fabs_bf16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fneg_fabs_bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bitset1_b32 s2, 15
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%fabs = call bfloat @llvm.fabs.bf16(bfloat %in)
%fsub = fsub bfloat -0.0, %fabs
store bfloat %fsub, ptr addrspace(1) %out, align 2
@@ -370,12 +344,12 @@ define amdgpu_kernel void @v_fneg_fabs_bf16(ptr addrspace(1) %out, ptr addrspace
; GFX11-TRUE16-LABEL: v_fneg_fabs_bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x8000, v0
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x8000, v1
+; GFX11-TRUE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_fneg_fabs_bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
index 42fbba1658260..2ce448ad49319 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg-fabs.f16.ll
@@ -210,30 +210,17 @@ define amdgpu_kernel void @fneg_fabs_free_f16(ptr addrspace(1) %out, i16 %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fneg_fabs_free_f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fneg_fabs_free_f16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fneg_fabs_free_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bitset1_b32 s2, 15
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%bc = bitcast i16 %in to half
%fabs = call half @llvm.fabs.f16(half %bc)
%fsub = fsub half -0.0, %fabs
@@ -283,30 +270,17 @@ define amdgpu_kernel void @fneg_fabs_f16(ptr addrspace(1) %out, half %in) {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: fneg_fabs_f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: fneg_fabs_f16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_bitset1_b32 s2, 15
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: fneg_fabs_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_bitset1_b32 s2, 15
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%fabs = call half @llvm.fabs.f16(half %in)
%fsub = fsub half -0.0, %fabs
store half %fsub, ptr addrspace(1) %out, align 2
@@ -345,12 +319,12 @@ define amdgpu_kernel void @v_fneg_fabs_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX11-TRUE16-LABEL: v_fneg_fabs_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x8000, v0
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x8000, v1
+; GFX11-TRUE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: v_fneg_fabs_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
index 07d243c393d31..a9d25cc011da7 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.bf16.ll
@@ -47,30 +47,17 @@ define amdgpu_kernel void @s_fneg_bf16(ptr addrspace(1) %out, bfloat %in) #0 {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fneg_bf16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fneg_bf16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fneg_bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%fneg = fsub bfloat -0.0, %in
store bfloat %fneg, ptr addrspace(1) %out
ret void
@@ -200,30 +187,17 @@ define amdgpu_kernel void @s_fneg_free_bf16(ptr addrspace(1) %out, i16 %in) #0 {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fneg_free_bf16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fneg_free_bf16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fneg_free_bf16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%bc = bitcast i16 %in to bfloat
%fsub = fsub bfloat -0.0, %bc
store bfloat %fsub, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/fneg.f16.ll b/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
index ada89538e39c4..91686181fef64 100644
--- a/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fneg.f16.ll
@@ -48,30 +48,17 @@ define amdgpu_kernel void @s_fneg_f16(ptr addrspace(1) %out, half %in) #0 {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fneg_f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fneg_f16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fneg_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%fneg = fsub half -0.0, %in
store half %fneg, ptr addrspace(1) %out
ret void
@@ -201,30 +188,17 @@ define amdgpu_kernel void @s_fneg_free_f16(ptr addrspace(1) %out, i16 %in) #0 {
; GFX9-NEXT: global_store_short v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
-; GFX11-TRUE16-LABEL: s_fneg_free_f16:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
-; GFX11-TRUE16-NEXT: s_endpgm
-;
-; GFX11-FAKE16-LABEL: s_fneg_free_f16:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_clause 0x1
-; GFX11-FAKE16-NEXT: s_load_b32 s2, s[4:5], 0x8
-; GFX11-FAKE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
-; GFX11-FAKE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-FAKE16-NEXT: s_xor_b32 s2, s2, 0x8000
-; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
-; GFX11-FAKE16-NEXT: global_store_b16 v0, v1, s[0:1]
-; GFX11-FAKE16-NEXT: s_endpgm
+; GFX11-LABEL: s_fneg_free_f16:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8
+; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000
+; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX11-NEXT: global_store_b16 v0, v1, s[0:1]
+; GFX11-NEXT: s_endpgm
%bc = bitcast i16 %in to half
%fsub = fsub half -0.0, %bc
store half %fsub, ptr addrspace(1) %out
diff --git a/llvm/test/CodeGen/AMDGPU/fpext.f16.ll b/llvm/test/CodeGen/AMDGPU/fpext.f16.ll
index d29a425e2a1c6..9e3ecb66d4ac8 100644
--- a/llvm/test/CodeGen/AMDGPU/fpext.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fpext.f16.ll
@@ -725,11 +725,9 @@ define amdgpu_kernel void @fneg_multi_use_fpext_f16_to_f32(
; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_xor_b32_e32 v1, 0x8000, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
-; GFX11-TRUE16-NEXT: buffer_store_b32 v2, off, s[4:7], 0 dlc
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -v0.l
+; GFX11-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
+; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[4:7], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -928,11 +926,9 @@ define amdgpu_kernel void @fabs_multi_use_fpext_f16_to_f32(
; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0x7fff, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
-; GFX11-TRUE16-NEXT: buffer_store_b32 v2, off, s[4:7], 0 dlc
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l|
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v0, 0x7fff, v0
+; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[4:7], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
@@ -1131,11 +1127,9 @@ define amdgpu_kernel void @fabs_fneg_multi_use_fpext_f16_to_f32(
; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[8:11], 0
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s1
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_or_b32_e32 v1, 0x8000, v0
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, -|v0.l|
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l
-; GFX11-TRUE16-NEXT: buffer_store_b32 v2, off, s[4:7], 0 dlc
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, -|v0.l|
+; GFX11-TRUE16-NEXT: v_or_b32_e32 v0, 0x8000, v0
+; GFX11-TRUE16-NEXT: buffer_store_b32 v1, off, s[4:7], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[4:7], 0 dlc
; GFX11-TRUE16-NEXT: s_waitcnt_vscnt null, 0x0
diff --git a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
index 78ee5f7356e37..de0684d853a23 100644
--- a/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptosi-sat-vector.ll
@@ -2748,21 +2748,20 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v1.h, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v1.l, v1.h, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v1.h, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v1.h, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v2.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v2.l, v1.h, 0x7f
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v2.l, v1.h, 0x7f
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.h, v2.l, v1.h, 0x7f
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2811,21 +2810,20 @@ define <4 x i8> @test_signed_v4f16_v4i8(<4 x half> %f) {
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v2.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v1.h, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v1.l, v1.h, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v1.h, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v1.h, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v1.l
-; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v2.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v2.l, v1.h, 0x7f
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v3.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v2.l, v1.h, 0x7f
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v0.h
+; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.h, v2.l, v1.h, 0x7f
+; GFX12-TRUE16-NEXT: v_or_b16 v2.l, v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.h
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3379,19 +3377,19 @@ define <4 x i1> @test_s_signed_v4f16_v4i1(<4 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_signed_v4f16_v4i1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s0
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s0
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s3
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s2
+; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v4, v0, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v4, v2, 0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX11-TRUE16-NEXT: v_med3_i32 v0, v1, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i32 v2, v4, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i32 v1, v5, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v2, v1, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v1, v4, -1, 0
; GFX11-TRUE16-NEXT: v_med3_i32 v3, v3, -1, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3426,20 +3424,20 @@ define <4 x i1> @test_s_signed_v4f16_v4i1(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s1
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s1, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s1
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s3
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s2
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v4, v0, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v5, v2, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v4, v2, 0, 16
; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX12-TRUE16-NEXT: v_med3_i32 v0, v1, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i32 v2, v4, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i32 v1, v5, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v2, v1, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v1, v4, -1, 0
; GFX12-TRUE16-NEXT: v_med3_i32 v3, v3, -1, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3860,12 +3858,12 @@ define <4 x i16> @test_s_signed_v4f16_v4i16(<4 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_signed_v4f16_v4i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s1, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, s2
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s3
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, s2
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_signed_v4f16_v4i16:
@@ -3895,13 +3893,13 @@ define <4 x i16> @test_s_signed_v4f16_v4i16(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s1, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, s2
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s3
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v4f16_v4i16:
@@ -4496,47 +4494,46 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0xff80
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v6.l
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v2.l
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v0.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v3.l, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.h, v1.h, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v5.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.h, v3.h, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v3.l, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v6.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v5.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v2.h, v2.h, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v4.l, 0x7f
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v1.l, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v2.h, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v7.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.h, v3.h, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v2.h
+; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v3.l, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_med3_i16 v3.l, v3.h, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v1.l, v1.h
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.h, v2.h, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v5.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v0.l, v0.h
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v2.l, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
-; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v4.l, 0x7f
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.h
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v3.l
+; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v1.l, v2.h
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v2.l, v0.h
+; GFX11-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i16 v1.l, v3.h, v4.l, 0x7f
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v0.h, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -4603,47 +4600,46 @@ define <8 x i8> @test_signed_v8f16_v8i8(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, 0xff80
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v6.l
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v2.l
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v0.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v3.l, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.h, v1.h, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v3.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v5.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v1
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, v1.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.h, v3.h, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v3.l, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, v6.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v5.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v2.h, v2.h, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i16 v2.l, v2.l, v4.l, 0x7f
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v1.l, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v2.h, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, v7.l
-; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
+; GFX12-TRUE16-NEXT: v_and_b16 v1.l, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.h, v3.h, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.h, 8, v2.h
+; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v3.l, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_and_b16 v2.l, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_and_b16 v1.h, 0xff, v1.h
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX12-TRUE16-NEXT: v_med3_i16 v3.l, v3.h, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_or_b16 v6.h, v1.l, v1.h
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.h, v2.h, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, v5.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v0.l, v0.h
-; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v3.l
-; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v2.l, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.h, 8, v1.h
-; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v1.l, v4.l, 0x7f
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.h
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, v0.l
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v3.l, 8, v3.l
+; GFX12-TRUE16-NEXT: v_or_b16 v6.h, v1.l, v2.h
+; GFX12-TRUE16-NEXT: v_or_b16 v2.l, v2.l, v0.h
+; GFX12-TRUE16-NEXT: v_med3_i16 v0.l, v0.l, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i16 v1.l, v3.h, v4.l, 0x7f
+; GFX12-TRUE16-NEXT: v_or_b16 v6.l, v1.h, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v6.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX12-TRUE16-NEXT: v_or_b16 v6.l, v0.h, v1.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -5563,34 +5559,34 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_signed_v8f16_v8i1:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s3
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s3, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s1, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s4
+; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s5
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
+; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s1
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, s3
; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX11-TRUE16-NEXT: v_med3_i32 v6, v0, -1, 0
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s2
+; GFX11-TRUE16-NEXT: v_med3_i32 v7, v0, -1, 0
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11-TRUE16-NEXT: v_med3_i32 v4, v1, -1, 0
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
-; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s2, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s3
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v7.l, s0
+; GFX11-TRUE16-NEXT: v_med3_i32 v3, v2, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v5, v1, -1, 0
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX11-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 16
-; GFX11-TRUE16-NEXT: v_bfe_i32 v9, v7, 0, 16
-; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, -1, 0
+; GFX11-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v8, v6, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX11-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i32 v1, v3, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i32 v7, v8, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i32 v3, v5, -1, 0
-; GFX11-TRUE16-NEXT: v_med3_i32 v5, v9, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v6, v4, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v4, v8, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, -1, 0
+; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, -1, 0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_signed_v8f16_v8i1:
@@ -5640,37 +5636,37 @@ define <8 x i1> @test_s_signed_v8f16_v8i1(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s3
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s2
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
-; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s3, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s5, s1, 16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v5.l, s1
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s4
+; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s2, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s5
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
+; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v4.l, s3
; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
-; GFX12-TRUE16-NEXT: v_med3_i32 v6, v0, -1, 0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v6.l, s2
+; GFX12-TRUE16-NEXT: v_med3_i32 v7, v0, -1, 0
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX12-TRUE16-NEXT: v_med3_i32 v4, v1, -1, 0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s0, s2, 16
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s3
+; GFX12-TRUE16-NEXT: v_med3_i32 v3, v2, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v5, v1, -1, 0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v7.l, s0
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s4
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s1
; GFX12-TRUE16-NEXT: v_bfe_i32 v0, v0, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v3, v3, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v5, v5, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v8, v1, 0, 16
-; GFX12-TRUE16-NEXT: v_bfe_i32 v9, v7, 0, 16
-; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, -1, 0
+; GFX12-TRUE16-NEXT: v_bfe_i32 v4, v4, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v8, v6, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
+; GFX12-TRUE16-NEXT: v_bfe_i32 v2, v2, 0, 16
; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i32 v1, v3, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i32 v7, v8, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i32 v3, v5, -1, 0
-; GFX12-TRUE16-NEXT: v_med3_i32 v5, v9, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v6, v4, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v4, v8, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, -1, 0
+; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, -1, 0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v8f16_v8i1:
@@ -6411,18 +6407,18 @@ define <8 x i16> @test_s_signed_v8f16_v8i16(<8 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_signed_v8f16_v8i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s3, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s2, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, s4
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, s5
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s0, 16
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s4
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, s5
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
-; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s2
; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s3
+; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s2
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, s4
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s1
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, s2
+; GFX11-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, s3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_signed_v8f16_v8i16:
@@ -6464,20 +6460,19 @@ define <8 x i16> @test_s_signed_v8f16_v8i16(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s3, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s5, s2, 16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, s4
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, s5
-; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s5, s0, 16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s4
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, s5
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
-; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s2
; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.l, s3
+; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.l, s2
+; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.l, s1
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v0.h, s4
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v1.h, s1
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v2.h, s2
+; GFX12-TRUE16-NEXT: v_cvt_i16_f16_e32 v3.h, s3
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_signed_v8f16_v8i16:
@@ -7019,21 +7014,20 @@ define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX11-TRUE16-NEXT: s_movk_i32 s0, 0xff80
; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX11-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v0
; GFX11-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i32 v4, v2, s0, 0x7f
+; GFX11-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7f
; GFX11-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7f
-; GFX11-TRUE16-NEXT: v_med3_i32 v0, v0, s0, 0x7f
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v3.l
-; GFX11-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v2.h, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v3.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_med3_i32 v3, v4, s0, 0x7f
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v0.h, v0.l
+; GFX11-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -7078,22 +7072,21 @@ define <4 x i8> @test_signed_v4f32_v4i8(<4 x float> %f) {
; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v2, v2
; GFX12-TRUE16-NEXT: s_movk_i32 s0, 0xff80
; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v1, v1
-; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v0, v0
+; GFX12-TRUE16-NEXT: v_cvt_i32_f32_e32 v4, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_med3_i32 v3, v3, s0, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i32 v4, v2, s0, 0x7f
+; GFX12-TRUE16-NEXT: v_med3_i32 v2, v2, s0, 0x7f
; GFX12-TRUE16-NEXT: v_med3_i32 v1, v1, s0, 0x7f
-; GFX12-TRUE16-NEXT: v_med3_i32 v0, v0, s0, 0x7f
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v3.l
-; GFX12-TRUE16-NEXT: v_and_b16 v2.h, 0xff, v4.l
-; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v0.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v2.h, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v3.l
+; GFX12-TRUE16-NEXT: v_and_b16 v0.h, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_med3_i32 v3, v4, s0, 0x7f
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-TRUE16-NEXT: v_or_b16 v2.l, v0.h, v0.l
+; GFX12-TRUE16-NEXT: v_and_b16 v0.l, 0xff, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
index 830e14ec13ad1..2b6f2aa2ab6d4 100644
--- a/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
+++ b/llvm/test/CodeGen/AMDGPU/fptoui-sat-vector.ll
@@ -2531,23 +2531,22 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v1.l
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX11-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v0.h
; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX11-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v0.h, v1.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.h
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2587,23 +2586,22 @@ define <4 x i8> @test_unsigned_v4f16_v4i8(<4 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v1
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 16, v0
-; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, v1.l
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, v0.l
-; GFX12-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX12-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v0.h
; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.l
+; GFX12-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX12-TRUE16-NEXT: v_or_b16 v2.l, v0.h, v1.l
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v1.h
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v2.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v0.h, v1.l
-; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.h
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.l, v2.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -3564,12 +3562,12 @@ define <4 x i16> @test_s_unsigned_v4f16_v4i16(<4 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_unsigned_v4f16_v4i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s1, 16
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, s2
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s3
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, s2
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s1
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_unsigned_v4f16_v4i16:
@@ -3599,13 +3597,13 @@ define <4 x i16> @test_s_unsigned_v4f16_v4i16(<4 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s0, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s1, 16
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, s2
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s3
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s1
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v4f16_v4i16:
@@ -4173,45 +4171,44 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX11-TRUE16-LABEL: test_unsigned_v8f16_v8i8:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v3.l
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v4.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v0.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v2.l
-; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v5.l
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v6.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v0.l
+; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v7.l
+; GFX11-TRUE16-NEXT: v_min_u16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v4.l
; GFX11-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
-; GFX11-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v4.l
-; GFX11-TRUE16-NEXT: v_min_u16 v2.l, 0xff, v2.l
+; GFX11-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v5.l
; GFX11-TRUE16-NEXT: v_min_u16 v3.l, 0xff, v3.l
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.h, v1.h, v0.h
-; GFX11-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v2.l
-; GFX11-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v3.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX11-TRUE16-NEXT: v_or_b16 v8.l, v3.l, v0.h
+; GFX11-TRUE16-NEXT: v_or_b16 v6.h, v0.l, v0.h
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT: v_min_u16 v3.h, 0xff, v3.h
+; GFX11-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v2.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.h
+; GFX11-TRUE16-NEXT: v_or_b16 v6.l, v3.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.h
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[7:8]
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v8.h
+; GFX11-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_unsigned_v8f16_v8i8:
@@ -4269,45 +4266,44 @@ define <8 x i8> @test_unsigned_v8f16_v8i8(<8 x half> %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v3.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v3.l
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v4.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v5.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v0.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
-; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v2.l
-; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v2.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v2
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v5.l
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, v6.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, v1.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, v0.l
+; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v1.h
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, v7.l
+; GFX12-TRUE16-NEXT: v_min_u16 v2.l, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v4.l
; GFX12-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v1.l
-; GFX12-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l
; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v0.h
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v4.l, v4.l
-; GFX12-TRUE16-NEXT: v_min_u16 v2.l, 0xff, v2.l
+; GFX12-TRUE16-NEXT: v_min_u16 v1.h, 0xff, v1.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v2.l
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, v5.l
; GFX12-TRUE16-NEXT: v_min_u16 v3.l, 0xff, v3.l
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v1.l, v0.l
-; GFX12-TRUE16-NEXT: v_or_b16 v8.h, v1.h, v0.h
-; GFX12-TRUE16-NEXT: v_min_u16 v0.l, 0xff, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v2.l
-; GFX12-TRUE16-NEXT: v_min_u16 v1.l, 0xff, v3.h
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.h
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v8.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v0.l
-; GFX12-TRUE16-NEXT: v_or_b16 v8.l, v3.l, v0.h
+; GFX12-TRUE16-NEXT: v_or_b16 v6.h, v0.l, v0.h
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h
+; GFX12-TRUE16-NEXT: v_or_b16 v2.l, v1.l, v2.l
+; GFX12-TRUE16-NEXT: v_min_u16 v3.h, 0xff, v3.h
+; GFX12-TRUE16-NEXT: v_min_u16 v0.h, 0xff, v2.h
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.h
+; GFX12-TRUE16-NEXT: v_or_b16 v6.l, v3.l, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.h
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v5
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v8
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[7:8]
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v8.h
+; GFX12-TRUE16-NEXT: v_lshrrev_b64 v[3:4], 24, v[5:6]
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.h, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 8, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v7
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v6.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v6.h
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_unsigned_v8f16_v8i8:
@@ -5937,18 +5933,18 @@ define <8 x i16> @test_s_unsigned_v8f16_v8i16(<8 x half> inreg %f) {
; GFX11-TRUE16-LABEL: test_s_unsigned_v8f16_v8i16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s3, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s2, 16
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, s4
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, s5
-; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
-; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s0, 16
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s4
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, s5
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
-; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s2
; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s3
+; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s2
+; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, s4
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s1
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, s2
+; GFX11-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, s3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: test_s_unsigned_v8f16_v8i16:
@@ -5990,20 +5986,19 @@ define <8 x i16> @test_s_unsigned_v8f16_v8i16(<8 x half> inreg %f) {
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s3, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s5, s2, 16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, s4
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, s5
-; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s1, 16
-; GFX12-TRUE16-NEXT: s_lshr_b32 s5, s0, 16
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s4
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, s5
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
-; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s2
; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.l, s3
+; GFX12-TRUE16-NEXT: s_lshr_b32 s3, s3, 16
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.l, s2
+; GFX12-TRUE16-NEXT: s_lshr_b32 s2, s2, 16
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.l, s1
+; GFX12-TRUE16-NEXT: s_lshr_b32 s1, s1, 16
+; GFX12-TRUE16-NEXT: s_lshr_b32 s4, s0, 16
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.l, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v0.h, s4
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v1.h, s1
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v2.h, s2
+; GFX12-TRUE16-NEXT: v_cvt_u16_f16_e32 v3.h, s3
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GI-LABEL: test_s_unsigned_v8f16_v8i16:
@@ -6502,21 +6497,20 @@ define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
; GFX11-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
-; GFX11-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX11-TRUE16-NEXT: v_min_u32_e32 v2, 0xff, v2
; GFX11-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
; GFX11-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v4
-; GFX11-TRUE16-NEXT: v_or_b16 v2.h, v3.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: v_or_b16 v2.l, v2.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -6554,21 +6548,20 @@ define <4 x i8> @test_unsigned_v4f32_v4i8(<4 x float> %f) {
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v3, v3
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v2
-; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v1, v1
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v2, v2
+; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v4, v1
; GFX12-TRUE16-NEXT: v_cvt_u32_f32_e32 v0, v0
; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v3
-; GFX12-TRUE16-NEXT: v_min_u32_e32 v1, 0xff, v1
+; GFX12-TRUE16-NEXT: v_min_u32_e32 v2, 0xff, v2
; GFX12-TRUE16-NEXT: v_min_u32_e32 v0, 0xff, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
; GFX12-TRUE16-NEXT: v_min_u32_e32 v3, 0xff, v4
-; GFX12-TRUE16-NEXT: v_or_b16 v2.h, v3.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b16 v2.l, 8, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.h
-; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v2.h
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: v_or_b16 v2.l, v2.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b16 v1.l, 8, v3.l
+; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
+; GFX12-TRUE16-NEXT: v_or_b16 v0.l, v0.l, v1.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 8, v1
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 24, v3
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 112cfabd6d434..973bc2035c5a3 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -744,106 +744,108 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-LABEL: frem_f16:
; GFX1150-TRUE16: ; %bb.0:
; GFX1150-TRUE16-NEXT: s_clause 0x1
-; GFX1150-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1150-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1150-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1150-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX1150-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX1150-TRUE16-NEXT: s_clause 0x1
-; GFX1150-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[10:11]
-; GFX1150-TRUE16-NEXT: global_load_d16_b16 v1, v1, s[0:1] offset:8
+; GFX1150-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
+; GFX1150-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[4:5] offset:8
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v1
; GFX1150-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1150-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s2, s1, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s1, s0
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s0, s2
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1150-TRUE16-NEXT: s_and_b32 s2, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s4, s3, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s4, s4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s1, s0
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s5, s4
; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB0_2
; GFX1150-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s1, s0
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s5, s4
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s6
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
-; GFX1150-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, s6, v0.l, s7
+; GFX1150-TRUE16-NEXT: s_mov_b32 s6, 0
; GFX1150-TRUE16-NEXT: s_branch .LBB0_3
; GFX1150-TRUE16-NEXT: .LBB0_2:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX1150-TRUE16-NEXT: .LBB0_3: ; %Flow18
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1150-TRUE16-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s6, 1
; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s4
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s4
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s4, v3
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
+; GFX1150-TRUE16-NEXT: s_sub_i32 s4, s5, s4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, 11
+; GFX1150-TRUE16-NEXT: s_add_i32 s4, s4, 11
; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1150-TRUE16-NEXT: s_add_i32 s4, s4, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s4, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
; GFX1150-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX1150-TRUE16-NEXT: .LBB0_8: ; %Flow19
-; GFX1150-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
-; GFX1150-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0.l
-; GFX1150-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
-; GFX1150-TRUE16-NEXT: global_store_b16 v3, v0, s[8:9]
+; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_nge_f16 s2, 0x7c00
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, s3
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
+; GFX1150-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1150-TRUE16-NEXT: s_endpgm
;
; GFX1150-FAKE16-LABEL: frem_f16:
@@ -977,111 +979,113 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-LABEL: frem_f16:
; GFX1200-TRUE16: ; %bb.0:
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: s_load_b128 s[8:11], s[4:5], 0x24
-; GFX1200-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x34
-; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1200-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
+; GFX1200-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX1200-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-TRUE16-NEXT: s_clause 0x1
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[10:11]
-; GFX1200-TRUE16-NEXT: global_load_d16_b16 v1, v1, s[0:1] offset:8
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
+; GFX1200-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[4:5] offset:8
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v1
; GFX1200-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
-; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, 0x7fff
-; GFX1200-TRUE16-NEXT: s_and_b32 s2, s1, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s1, s0
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s0, s2
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s3, v0
+; GFX1200-TRUE16-NEXT: s_and_b32 s2, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s4, s3, 0x7fff
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s5, s2
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s4, s4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s1, s0
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s5, s4
; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB0_2
; GFX1200-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s1, s0
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v0.l
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, v0.l, v0.h, s2
-; GFX1200-TRUE16-NEXT: s_mov_b32 s2, 0
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s5, s4
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.l, 0x8000, s6
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, -1, 0
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, s6, v0.l, s7
+; GFX1200-TRUE16-NEXT: s_mov_b32 s6, 0
; GFX1200-TRUE16-NEXT: s_branch .LBB0_3
; GFX1200-TRUE16-NEXT: .LBB0_2:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT: s_mov_b32 s6, -1
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX1200-TRUE16-NEXT: .LBB0_3: ; %Flow18
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s6, s6, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s6, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s6, 1
; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s4
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s4
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s5
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s4, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v2
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s4, s5, s4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, 11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s4, s4, 11
; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s4, s4, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
-; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s4, 11
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
; GFX1200-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
+; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
-; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
-; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_cmp_nle_f16_e64 s0, 0x7c00, v0.l
-; GFX1200-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v2.l, s0
-; GFX1200-TRUE16-NEXT: global_store_b16 v3, v0, s[8:9]
+; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
+; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s2, 0x7c00
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, -1, 0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: s_and_b32 s2, s2, s3
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v0.l, s2
+; GFX1200-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: frem_f16:
@@ -1591,8 +1595,8 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
-; GFX1150-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
+; GFX1150-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v3.l, v2.l
+; GFX1150-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1150-TRUE16-NEXT: s_endpgm
;
; GFX1150-FAKE16-LABEL: fast_frem_f16:
@@ -1661,8 +1665,8 @@ define amdgpu_kernel void @fast_frem_f16(ptr addrspace(1) %out, ptr addrspace(1)
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
-; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
+; GFX1200-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v3.l, v2.l
+; GFX1200-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: fast_frem_f16:
@@ -2074,8 +2078,8 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1150-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
-; GFX1150-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
+; GFX1150-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v3.l, v2.l
+; GFX1150-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1150-TRUE16-NEXT: s_endpgm
;
; GFX1150-FAKE16-LABEL: unsafe_frem_f16:
@@ -2144,8 +2148,8 @@ define amdgpu_kernel void @unsafe_frem_f16(ptr addrspace(1) %out, ptr addrspace(
; GFX1200-TRUE16-NEXT: v_trunc_f16_e32 v0.l, v0.l
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v0, 0x8000, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v3.l
-; GFX1200-TRUE16-NEXT: global_store_b16 v1, v2, s[0:1]
+; GFX1200-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v3.l, v2.l
+; GFX1200-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX1200-TRUE16-NEXT: s_endpgm
;
; GFX1200-FAKE16-LABEL: unsafe_frem_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
index 3fb6d9d1bf244..8a311979dfc1e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
@@ -325,7 +325,6 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-TRUE16-NEXT: v_nop
; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250-GISEL-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
index 97c83fd2f9545..49f02bd11b7e7 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.f16.fp8.ll
@@ -286,7 +286,6 @@ define amdgpu_ps float @test_cvt_f16_bf8_byte3_hi(i32 %a) {
; GFX1250-GISEL-REAL16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-REAL16-NEXT: v_nop
; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_bf8_e64 v0.l, v0 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
@@ -535,7 +534,6 @@ define amdgpu_ps float @test_cvt_f16_fp8_byte3_hi(i32 %a) {
; GFX1250-GISEL-REAL16-NEXT: s_mov_b64 s[64:65], 0
; GFX1250-GISEL-REAL16-NEXT: v_nop
; GFX1250-GISEL-REAL16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-GISEL-REAL16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
; GFX1250-GISEL-REAL16-NEXT: v_cvt_f16_fp8_e64 v0.l, v0 byte_sel:3
; GFX1250-GISEL-REAL16-NEXT: v_mov_b32_e32 v1, 0
; GFX1250-GISEL-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
index 1f950e2ea8294..e1fed42905848 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fadd.ll
@@ -369,21 +369,21 @@ define amdgpu_kernel void @uniform_value_half(ptr addrspace(1) %out, half %in) {
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12DAGISEL-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12DAGISEL-NEXT: v_cvt_f32_i32_e32 v0, s3
; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX12DAGISEL-NEXT: s_cvt_f32_f16 s2, s2
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_2)
; GFX12DAGISEL-NEXT: v_mul_f32_e32 v0, s2, v0
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_2)
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(SALU_CYCLE_2)
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v0
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v0, 0
; GFX12DAGISEL-NEXT: s_cvt_f16_f32 s2, s2
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12DAGISEL-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12DAGISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX12DAGISEL-NEXT: v_mov_b32_e32 v1, s2
+; GFX12DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
%result = call half @llvm.amdgcn.wave.reduce.fadd(half %in, i32 1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
index 78e0dd4908f3f..b8bd9d9ffe783 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmax.ll
@@ -314,13 +314,12 @@ define amdgpu_kernel void @uniform_value_half(ptr addrspace(1) %out, half %in) {
; GFX12DAGISEL-LABEL: uniform_value_half:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX12DAGISEL-NEXT: s_cvt_f32_f16 s2, s2
; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX12DAGISEL-NEXT: s_cvt_f16_f32 s2, s2
-; GFX12DAGISEL-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12DAGISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
%result = call half @llvm.amdgcn.wave.reduce.fmax(half %in, i32 1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
index e45588dac7ff8..d72eb6dde1019 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fmin.ll
@@ -314,13 +314,12 @@ define amdgpu_kernel void @uniform_value_half(ptr addrspace(1) %out, half %in) {
; GFX12DAGISEL-LABEL: uniform_value_half:
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v1, 0
; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX12DAGISEL-NEXT: s_cvt_f32_f16 s2, s2
; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
; GFX12DAGISEL-NEXT: s_cvt_f16_f32 s2, s2
-; GFX12DAGISEL-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12DAGISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
%result = call half @llvm.amdgcn.wave.reduce.fmin(half %in, i32 1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
index ede0a21ed57fd..b5675133ea71e 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.reduce.fsub.ll
@@ -371,9 +371,8 @@ define amdgpu_kernel void @uniform_value_half(ptr addrspace(1) %out, half %in) {
; GFX12DAGISEL: ; %bb.0: ; %entry
; GFX12DAGISEL-NEXT: s_load_b96 s[0:2], s[4:5], 0x24
; GFX12DAGISEL-NEXT: s_mov_b32 s3, exec_lo
-; GFX12DAGISEL-NEXT: v_mov_b32_e32 v1, 0
+; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12DAGISEL-NEXT: s_bcnt1_i32_b32 s3, s3
-; GFX12DAGISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX12DAGISEL-NEXT: v_cvt_f32_i32_e32 v0, s3
; GFX12DAGISEL-NEXT: s_wait_kmcnt 0x0
; GFX12DAGISEL-NEXT: s_cvt_f32_f16 s2, s2
@@ -384,8 +383,8 @@ define amdgpu_kernel void @uniform_value_half(ptr addrspace(1) %out, half %in) {
; GFX12DAGISEL-NEXT: v_readfirstlane_b32 s2, v0
; GFX12DAGISEL-NEXT: s_cvt_f16_f32 s2, s2
; GFX12DAGISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12DAGISEL-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX12DAGISEL-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX12DAGISEL-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
+; GFX12DAGISEL-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12DAGISEL-NEXT: s_endpgm
entry:
%result = call half @llvm.amdgcn.wave.reduce.fsub(half %in, i32 1)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
index 42854dffbc196..8bde7ed3c07e5 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.bf16.ll
@@ -151,10 +151,10 @@ define bfloat @v_exp2_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
@@ -290,10 +290,10 @@ define bfloat @v_exp2_fneg_fabs_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
@@ -430,10 +430,10 @@ define bfloat @v_exp2_fneg_bf16(bfloat %in) {
; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v1, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v2
; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v1
@@ -925,37 +925,37 @@ define <2 x bfloat> @v_exp2_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v0.l, 0x7fff, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_and_b16 v1.l, 0x7fff, v1.l
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v0, v0, v3 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -1179,37 +1179,37 @@ define <2 x bfloat> @v_exp2_fneg_fabs_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v0.l, 0x8000, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_or_b16 v1.l, 0x8000, v1.l
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v0, v0, v3 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
@@ -1433,37 +1433,37 @@ define <2 x bfloat> @v_exp2_fneg_v2bf16(<2 x bfloat> %in) {
; GFX1200-SDAG-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX1200-SDAG-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v0.l, 0x8000, v0.l
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX1200-SDAG-TRUE16-NEXT: v_xor_b16 v1.l, 0x8000, v1.l
-; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, 0xc2fc0000, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, s0
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0x42800000, s0
; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v1, v1, v2 :: v_dual_lshlrev_b32 v0, 16, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v0
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, s0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_dual_add_f32 v0, v0, v3 :: v_dual_lshlrev_b32 v1, 16, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0xc2fc0000, v1
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, s0
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_1)
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v4, 0, 0x42800000, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v3, 0, 0xffffffc0, vcc_lo
-; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v0, v0, v4
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0x42800000, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: v_add_f32_e32 v1, v1, v2
+; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e64 v2, 0, 0xffffffc0, vcc_lo
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
+; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
+; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
+; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v1, v1, v2
-; GFX1200-SDAG-TRUE16-NEXT: v_exp_f32_e32 v0, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v2, v1, 16, 1
; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v4, 0x400000, v1
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v1, v1
+; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v2, v2, v1, 0x7fff
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-SDAG-TRUE16-NEXT: v_ldexp_f32 v0, v0, v3
-; GFX1200-SDAG-TRUE16-NEXT: v_bfe_u32 v3, v0, 16, 1
-; GFX1200-SDAG-TRUE16-NEXT: v_or_b32_e32 v5, 0x400000, v0
-; GFX1200-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-SDAG-TRUE16-NEXT: v_add3_u32 v3, v3, v0, 0x7fff
; GFX1200-SDAG-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX1200-SDAG-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v4, vcc_lo
; GFX1200-SDAG-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
index c29a124706d13..2fffc987b04f6 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
@@ -693,35 +693,20 @@ define amdgpu_gs void @s_fptrunc_round_f32_to_f16_upward_multiple_calls(float in
; GISEL-NEXT: global_store_short v[0:1], v2, off
; GISEL-NEXT: s_endpgm
;
-; GFX12-SDAG-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls:
-; GFX12-SDAG: ; %bb.0:
-; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
-; GFX12-SDAG-NEXT: s_cvt_f16_f32 s0, s0
-; GFX12-SDAG-NEXT: s_cvt_f16_f32 s2, s1
-; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 2
-; GFX12-SDAG-NEXT: s_cvt_f16_f32 s1, s1
-; GFX12-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
-; GFX12-SDAG-NEXT: s_add_f16 s0, s0, s2
-; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
-; GFX12-SDAG-NEXT: s_add_f16 s0, s1, s0
-; GFX12-SDAG-NEXT: v_mov_b16_e32 v2.l, s0
-; GFX12-SDAG-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-SDAG-NEXT: s_endpgm
-;
-; GFX12-GISEL-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls:
-; GFX12-GISEL: ; %bb.0:
-; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
-; GFX12-GISEL-NEXT: s_cvt_f16_f32 s0, s0
-; GFX12-GISEL-NEXT: s_cvt_f16_f32 s2, s1
-; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 2
-; GFX12-GISEL-NEXT: s_cvt_f16_f32 s1, s1
-; GFX12-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
-; GFX12-GISEL-NEXT: s_add_f16 s0, s0, s2
-; GFX12-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
-; GFX12-GISEL-NEXT: s_add_f16 s0, s1, s0
-; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s0
-; GFX12-GISEL-NEXT: global_store_b16 v[0:1], v2, off
-; GFX12-GISEL-NEXT: s_endpgm
+; GFX12-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls:
+; GFX12: ; %bb.0:
+; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 1), 1
+; GFX12-NEXT: s_cvt_f16_f32 s0, s0
+; GFX12-NEXT: s_cvt_f16_f32 s2, s1
+; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 2, 2), 2
+; GFX12-NEXT: s_cvt_f16_f32 s1, s1
+; GFX12-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 3, 1), 0
+; GFX12-NEXT: s_add_f16 s0, s0, s2
+; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)
+; GFX12-NEXT: s_add_f16 s0, s1, s0
+; GFX12-NEXT: v_mov_b32_e32 v2, s0
+; GFX12-NEXT: global_store_b16 v[0:1], v2, off
+; GFX12-NEXT: s_endpgm
%res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward")
%res2 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.upward")
%res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.downward")
diff --git a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
index 70d0d38eb656a..06d04a7e8c3ff 100644
--- a/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
+++ b/llvm/test/CodeGen/AMDGPU/load-constant-i1.ll
@@ -1810,23 +1810,24 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i32(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: global_load_d16_u8 v0, v8, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-TRUE16-NEXT: s_bfe_u32 s5, s2, 0x10005
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s2, 1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_and_b32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10001
-; GFX12-TRUE16-NEXT: s_and_b32 s6, s2, 1
-; GFX12-TRUE16-NEXT: s_bfe_u32 s7, s2, 0x10002
-; GFX12-TRUE16-NEXT: s_bfe_u32 s2, s2, 0x10004
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 7, v0
-; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v0, 6, 1
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, s7 :: v_dual_and_b32 v1, 0xffff, v0
+; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10005
+; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10003
+; GFX12-TRUE16-NEXT: s_bfe_u32 s5, s2, 0x10001
+; GFX12-TRUE16-NEXT: s_bfe_u32 s6, s2, 0x10004
+; GFX12-TRUE16-NEXT: s_bfe_u32 s2, s2, 0x10002
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v5, s4
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v7, s3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, s7
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v7, s4 :: v_dual_mov_b32 v0, s6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 7, v1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v1, 6, 1
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, s3
; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16
; GFX12-TRUE16-NEXT: global_store_b128 v8, v[4:7], s[0:1]
+; GFX12-TRUE16-NEXT: global_store_b128 v8, v[0:3], s[0:1] offset:16
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_zextload_v8i1_to_v8i32:
@@ -5854,21 +5855,23 @@ define amdgpu_kernel void @constant_zextload_v3i1_to_v3i64(ptr addrspace(1) %out
; GFX12-TRUE16-LABEL: constant_zextload_v3i1_to_v3i64:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, 0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v1
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_u8 v0, v5, s[2:3]
+; GFX12-TRUE16-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v1, 0xffff, v0
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v0, 1, 1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v0
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 1, 1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 1, v0
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 2, v1
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v5
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v5 :: v_dual_and_b32 v4, 0xffff, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v6
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 2, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v4
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v4, 0xffff, v5
; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: global_store_b64 v5, v[4:5], s[0:1] offset:16
-; GFX12-TRUE16-NEXT: global_store_b128 v5, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT: global_store_b64 v1, v[4:5], s[0:1] offset:16
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_zextload_v3i1_to_v3i64:
@@ -6224,22 +6227,22 @@ define amdgpu_kernel void @constant_zextload_v4i1_to_v4i64(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10002
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 3, v0
-; GFX12-TRUE16-NEXT: s_and_b32 s3, 0xffff, s3
+; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10001
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 3, v0
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s2, 1
+; GFX12-TRUE16-NEXT: s_and_b32 s4, 0xffff, s4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10001
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v2, 0xffff, v2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, 1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: s_and_b32 s3, 0xffff, s3
-; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff, v4
+; GFX12-TRUE16-NEXT: s_bfe_u32 s2, s2, 0x10002
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-TRUE16-NEXT: s_and_b32 s2, 0xffff, s2
; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v4
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_zextload_v4i1_to_v4i64:
@@ -6678,23 +6681,23 @@ define amdgpu_kernel void @constant_zextload_v8i1_to_v8i64(ptr addrspace(1) %out
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v13, v1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v15, v1
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_u8 v12, v1, s[2:3]
+; GFX12-TRUE16-NEXT: global_load_d16_u8 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v1
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v0, 0xffff, v12
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v12, 5, 1
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v12, 4, 1
-; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v12, 3, 1
-; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v12, 2, 1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 7, v0
-; GFX12-TRUE16-NEXT: v_bfe_u32 v0, v0, 6, 1
-; GFX12-TRUE16-NEXT: v_bfe_u32 v14, v12, 1, 1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 1, v12
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v1 :: v_dual_and_b32 v8, 1, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff, v0
+; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v0, 3, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v0, 2, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v10, v0, 1, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v2, v0, 5, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v0, v0, 4, 1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 7, v12
+; GFX12-TRUE16-NEXT: v_bfe_u32 v12, v12, 6, 1
; GFX12-TRUE16-NEXT: s_clause 0x3
-; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
-; GFX12-TRUE16-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:32
-; GFX12-TRUE16-NEXT: global_store_b128 v1, v[8:11], s[0:1] offset:16
-; GFX12-TRUE16-NEXT: global_store_b128 v1, v[12:15], s[0:1]
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:16
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[8:11], s[0:1]
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[12:15], s[0:1] offset:48
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_zextload_v8i1_to_v8i64:
@@ -7307,61 +7310,60 @@ define amdgpu_kernel void @constant_zextload_v16i1_to_v16i64(ptr addrspace(1) %o
; GFX12-TRUE16-LABEL: constant_zextload_v16i1_to_v16i64:
; GFX12-TRUE16: ; %bb.0:
; GFX12-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v9, v3
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v1
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v5, v1
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, v1
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v3, s[2:3]
+; GFX12-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff, v0
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x1000a
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff, v0
+; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10009
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v6, 11, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v0, v8, 8, 1
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10009
-; GFX12-TRUE16-NEXT: v_bfe_u32 v0, v6, 8, 1
+; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x1000d
; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x1000c
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 15, v6
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:80
+; GFX12-TRUE16-NEXT: v_bfe_u32 v9, v8, 11, 1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 15, v8
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:64
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x1000d
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10007
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[0:3], s[0:1] offset:64
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s4
; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10006
-; GFX12-TRUE16-NEXT: v_bfe_u32 v0, v6, 5, 1
-; GFX12-TRUE16-NEXT: v_bfe_u32 v6, v6, 14, 1
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:96
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
-; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10004
-; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10002
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:48
+; GFX12-TRUE16-NEXT: v_bfe_u32 v4, v8, 14, 1
+; GFX12-TRUE16-NEXT: v_bfe_u32 v8, v8, 5, 1
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:96
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s4
; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v0
; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10003
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:32
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s4
+; GFX12-TRUE16-NEXT: s_bfe_u32 s4, s2, 0x10002
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:48
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x10001
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, 1
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1] offset:16
+; GFX12-TRUE16-NEXT: s_and_b32 s4, s2, 1
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s2
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, s3
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s4
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, s3
+; GFX12-TRUE16-NEXT: s_bfe_u32 s3, s2, 0x1000a
+; GFX12-TRUE16-NEXT: s_bfe_u32 s2, s2, 0x10004
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1]
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s3
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v9
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:80
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v8
; GFX12-TRUE16-NEXT: s_clause 0x1
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[6:9], s[0:1] offset:112
-; GFX12-TRUE16-NEXT: global_store_b128 v3, v[2:5], s[0:1]
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[4:7], s[0:1] offset:112
+; GFX12-TRUE16-NEXT: global_store_b128 v1, v[0:3], s[0:1] offset:32
; GFX12-TRUE16-NEXT: s_endpgm
;
; GFX12-FAKE16-LABEL: constant_zextload_v16i1_to_v16i64:
diff --git a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
index bd2fa2a024fa6..f860c5731ee6d 100644
--- a/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/maximumnum.bf16.ll
@@ -116,21 +116,17 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) #1 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -176,19 +172,15 @@ define bfloat @v_maximumnum_bf16(bfloat %x, bfloat %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -304,12 +296,10 @@ define bfloat @v_maximumnum_bf16_nnan(bfloat %x, bfloat %y) #1 {
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v2
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -343,9 +333,8 @@ define bfloat @v_maximumnum_bf16_nnan(bfloat %x, bfloat %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v2
; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -570,17 +559,11 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7
@@ -589,11 +572,8 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -671,17 +651,11 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7
@@ -692,11 +666,8 @@ define <2 x bfloat> @v_maximumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -897,12 +868,9 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
@@ -963,12 +931,9 @@ define <2 x bfloat> @v_maximumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
@@ -1271,58 +1236,48 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
@@ -1400,64 +1355,54 @@ define <3 x bfloat> @v_maximumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1711,35 +1656,31 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1794,29 +1735,24 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v7, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v9, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1824,7 +1760,7 @@ define <3 x bfloat> @v_maximumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s1
; GFX12-TRUE16-NEXT: s_and_b32 s0, s4, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2208,74 +2144,61 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
@@ -2375,85 +2298,75 @@ define <4 x bfloat> @v_maximumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2781,43 +2694,39 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v10, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v12, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v6.l, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v4bf16_nnan:
@@ -2887,48 +2796,44 @@ define <4 x bfloat> @v_maximumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v10, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v4
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v12, v11
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v4.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v6.l, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v4bf16_nnan:
@@ -3478,111 +3383,93 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v8
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v14.l, v13.l, s1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v18, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v9.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v12, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v14, v16
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v8.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v18, v19
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v12.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v14, v13
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v16, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s3
; GFX11-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v9.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v12.l, s6
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s2
@@ -3719,124 +3606,106 @@ define <6 x bfloat> @v_maximumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v8
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v14.l, v13.l, s1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v18, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v18, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v9.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v14, v16
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v12, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v8.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v18, v19
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v14, v13
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v16, v15
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s3
; GFX12-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v9.l, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v12.l, s6
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, s3
; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4623,163 +4492,138 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v10.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v19, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v15.l, v12.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v14.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v14.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v12.l, s3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v12.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v7
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v3.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v10.l, v13.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v17.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v14.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v3.l, v17.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v15, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s0, s3
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v17.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v0.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v8.l, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v17.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v8
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v8bf16:
@@ -4939,184 +4783,160 @@ define <8 x bfloat> @v_maximumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v10.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v10.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v19, v19
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v15.l, v12.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v15, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v14.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v14, v15
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v15, v17
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v14.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v12.l, s3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v14.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v12.l, v8.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s0, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v3.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v10.l, v13.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v17.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v15, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v14.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v3.l, v17.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v12
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v16, v15
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v15, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v8.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s0, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v17.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v1.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v2.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v0.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v8.l, s7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v17.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v3
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v8bf16:
@@ -6532,327 +6352,276 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-TRUE16-LABEL: v_maximumnum_v16bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v23.l, v20.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v21.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v19.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v17.l, s3
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v25
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v21.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v22.l, v23.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.h, v18.l, v19.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v24.l, v20.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v23.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v19.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v20.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v26, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v18.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v24.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v22.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v27, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v7.l, v21.l, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s0, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v22.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v24.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v28.l, s3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v17.l, v23.l, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v20.l, v18.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v28.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v24.l, v21.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v19.l, v22.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v21.l, v17.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v28.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v17.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v15.l, v17.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v13
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v21
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v14.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v9.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v21, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v13
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v9.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v4, v19
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v18
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v19 :: v_dual_mov_b32 v5, v18
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v17
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v16bf16:
@@ -7178,372 +6947,320 @@ define <16 x bfloat> @v_maximumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v16, v7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v18.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v17.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v20, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v21, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v23.l, v20.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v21.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s1, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v19.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v17.l, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v24, v25
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v24, v25
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v21.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v22.l, v23.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v18.l, v19.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v24, v25
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v21.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v19, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v24.l, v20.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v23.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v19.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v20.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v26, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v18.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v24.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v22.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v27, v29
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v26, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v26, v27
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v23.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v7.l, v21.l, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v26, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s0, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v22.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v19.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v28.l, s3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v17.l, v23.l, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v20.l, v18.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v28.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v24.l, v21.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v19.l, v22.l, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v24.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v21.l, v17.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v6
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v28.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v17.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v22, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v20.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v17.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v16.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v15.l, v17.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v3
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v21
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v14.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v21, v16
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v13, v12
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v12, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v14, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v21, v16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v9.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v20 :: v_dual_mov_b32 v3, v16
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v19 :: v_dual_mov_b32 v5, v18
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v17
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v16bf16:
@@ -10369,633 +10086,534 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v51, v51
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v53, v53
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v52, v52
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v54, v54
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v66, v66
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v33.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v34.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v39.l, v36.l, s4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v55, v55
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v27
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s16, v97, v128
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v98, v129
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v54, v54
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s47, v66, v66
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v100.l, v99.l, s16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v132.l, v131.l, s24
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v49, v49
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v51, v51
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v53, v53
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v55, v55
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s56, v69, v69
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v80.l, v71.l, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v96.l, v87.l, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v112.l, v103.l, s18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v48.l, v147.l, s28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v35
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v39
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v98.l, v99.l, v54.l, s17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v114.l, v131.l, v66.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v33
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v36
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v117, v97
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v36.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s17, s2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v30
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v53.l, s15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v54
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v100.l, v103.l, v55.l, s19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v118.l, v147.l, v48.l, s29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v98
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v69, v130
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v80, v131
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v81, v132
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v52, v52
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v64.l, v38.l, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v84.l, v83.l, s12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v116.l, v115.l, s20
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s15, v96, v119
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v87, v135
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v115, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v100, v130
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v102, v132
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v101, v131
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v112, v133
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v34.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v99, v144
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v103, v145
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s16, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v38.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v113, v134
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s20, s5
; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v48.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v114, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v53
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v118
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v97, v146
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v65, v65
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v50, v50
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v68.l, v67.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v144.l, v135.l, s26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v51.l, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v52.l, s13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v102.l, v115.l, v64.l, s21
; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v50.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v51.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v52.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v54.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v55.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v37.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v116, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v49.l
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX11-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s13, s28, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v96, v145
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v117, v81
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v98.l, v54.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v33
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v36
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v65, v65
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v128.l, v119.l, s22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v51
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v52
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v64
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v116.l, v135.l, v68.l, s27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v71
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v83
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v102
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v35.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v96
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v97
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v98
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v112.l, v119.l, v65.l, s23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v66
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v114
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v85, v135
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v86, v144
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v101, v69
+; GFX11-TRUE16-NEXT: s_and_b32 s17, s17, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v37.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v39.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v113, v80
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v51.l, s22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v83.l, v52.l, s23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v102.l, v64.l, s27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s43
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s45
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v35.l, s17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v49
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v114.l, v66.l, s29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v83
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s18, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s19, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v34.l, v37.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v36.l, v39.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s9
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v64.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v82, v133
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v114
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v50
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v55
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v67
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v147, 16, v100
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s20
+; GFX11-TRUE16-NEXT: s_and_b32 s10, s27, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v84, v134
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v99, v147
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v71
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s21
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v99
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s46
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v52.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v65
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v112
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v87.l, v53.l, s24
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v102
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s47
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v128, v82
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v100.l, v55.l, s26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v67
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s20, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v38.l, v49.l, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v103, v130
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v80
+; GFX11-TRUE16-NEXT: s_and_b32 s6, s23, s6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v50.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s56
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v100
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.h, v71.l, v52.l, s6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v53.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v103
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v30
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s21, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v67.l, v50.l, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s24, s7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v119, v132
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.h, v80.l, v53.l, s7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v29
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v13.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s43
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v68
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s44, 0, v128
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v116
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v112.l, v65.l, s28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v69
+; GFX11-TRUE16-NEXT: s_and_b32 s16, s44, s16
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s41, v115, v131
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s16
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v119
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v81
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v118.l, v48.l, s42
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v116.l, v68.l, s41
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v51.l
+; GFX11-TRUE16-NEXT: s_and_b32 s15, s43, s15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v54.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s15
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v101
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v112
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v82
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v85
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v86
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v87
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s22, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s25, s8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v55.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v65.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v66.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v68.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v48.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v113
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v116
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v117
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v118
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v69.l, v51.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v81.l, v54.l, s8
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s26, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s11, s28, s11
+; GFX11-TRUE16-NEXT: s_and_b32 s12, s29, s12
+; GFX11-TRUE16-NEXT: s_and_b32 s13, s41, s13
+; GFX11-TRUE16-NEXT: s_and_b32 s14, s42, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v82.l, v55.l, s9
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v31
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v96, v97
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v39
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v96.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v98, v98
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v32
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v96.l, v32.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v84.l, v65.l, s11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v33
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v83.l, v64.l, s10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v35, v37
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v34, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v32.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v85.l, v66.l, s12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v35
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v86.l, v68.l, s13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v87.l, v48.l, s14
; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s29, s14
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v52, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v129, v133
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v37, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v26
; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v53, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v54, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v39, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v11.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v39, v38
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s3
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v7
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v39, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v25.l, v9.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v38, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v23, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v24
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v26, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v26, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v24.l, v8.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v9.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v21
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v22.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v21.l, v5.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v12
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v19.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v21, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v16
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v18
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v5.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v6.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v7.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v8.l, v4.l, s2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v49 :: v_dual_mov_b32 v2, v48
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v39 :: v_dual_mov_b32 v4, v38
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v36 :: v_dual_mov_b32 v6, v35
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v34 :: v_dual_mov_b32 v8, v33
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v32 :: v_dual_mov_b32 v10, v31
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v30 :: v_dual_mov_b32 v12, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v35 :: v_dual_mov_b32 v1, v34
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v33 :: v_dual_mov_b32 v3, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v31 :: v_dual_mov_b32 v5, v30
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v29 :: v_dual_mov_b32 v7, v28
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v27 :: v_dual_mov_b32 v9, v36
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_maximumnum_v32bf16:
@@ -11574,697 +11192,589 @@ define <32 x bfloat> @v_maximumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v12
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v30
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v29
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v29
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v28
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v28
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
; GFX12-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v51, v51
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v53, v53
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v15
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v52, v52
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v54, v54
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v66, v66
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v33.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v34.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v39.l, v36.l, s4
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v13
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v55, v55
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v27
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s16, v97, v128
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v98, v129
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v54, v54
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s47, v66, v66
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v100.l, v99.l, s16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v132.l, v131.l, s24
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v49, v49
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v51, v51
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v53, v53
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v55, v55
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s56, v69, v69
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v80.l, v71.l, s10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v96.l, v87.l, s14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v112.l, v103.l, s18
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v48.l, v147.l, s28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v35
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v39
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v98.l, v99.l, v54.l, s17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v114.l, v131.l, v66.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v33
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v36
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v27
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX12-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v117, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v30
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v36.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s17, s2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v53.l, s15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v54
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v100.l, v103.l, v55.l, s19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v118.l, v147.l, v48.l, s29
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v98
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s17, v69, v130
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v80, v131
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v81, v132
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s15, v96, v119
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v52, v52
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v64.l, v38.l, s6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v87, v135
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v115, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s18, v100, v130
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v84.l, v83.l, s12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v116.l, v115.l, s20
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v53
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v48
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v87
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v118
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v97, v146
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s18
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s19
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v65, v65
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v50, v50
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v68.l, v67.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v144.l, v135.l, s26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v51.l, s11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v52.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v102.l, v115.l, v64.l, s21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v96, v145
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s42, v117, v81
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v98.l, v54.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v33
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v34
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v36
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v65, v65
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v128.l, v119.l, s22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v51
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v52
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v64
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v116.l, v135.l, v68.l, s27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v71
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v83
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v102
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v35.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v96
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v97
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v98
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v102, v132
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s19, v101, v131
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v112.l, v119.l, v65.l, s23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v66
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v114
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v85, v135
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s23, v86, v144
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s27, v101, v69
+; GFX12-TRUE16-NEXT: s_and_b32 s17, s17, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v37.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v39.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s7
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s29, v113, v80
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v51.l, s22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v83.l, v52.l, s23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v102.l, v64.l, s27
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s43
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s45
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v35.l, s17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v49
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v112, v133
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v34.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s24, v99, v144
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v114.l, v66.l, s29
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v83
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s18, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s19, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v12
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v34.l, v37.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v36.l, v39.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s9
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v64.l
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s20, v82, v133
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v114
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v50
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v55
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v67
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v147, 16, v100
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s20
+; GFX12-TRUE16-NEXT: s_and_b32 s10, s27, s10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s21, v84, v134
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v99, v147
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v38
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v71
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v49.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s25, v103, v145
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s16, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s21
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v99
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s46
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v52.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v65
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v112
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v87.l, v53.l, s24
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v102
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s47
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s44, v128, v82
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v100.l, v55.l, s26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v67
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s20, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v28
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v38.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s22, v113, v134
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s20, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v38.l, v49.l, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v103, v130
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v80
+; GFX12-TRUE16-NEXT: s_and_b32 s6, s23, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v50.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s56
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v100
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0, v48.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s26, v114, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX12-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v50.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v51.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0, v52.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v71.l, v52.l, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v53.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v103
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v30
+; GFX12-TRUE16-NEXT: s_and_b32 s4, s21, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX12-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX12-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v64.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v53.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v54.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v55.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v37.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s28, v116, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v49.l
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v67.l, v50.l, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s24, s7
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s43, v119, v132
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX12-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s13, s28, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v80.l, v53.l, s7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v29
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0, v13.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0, v14.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s43
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v68
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s44, 0, v128
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v116
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v112.l, v65.l, s28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v30
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v69
+; GFX12-TRUE16-NEXT: s_and_b32 s16, s44, s16
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s41, v115, v131
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s16
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v119
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v81
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v118.l, v48.l, s42
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v116.l, v68.l, s41
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0, v51.l
+; GFX12-TRUE16-NEXT: s_and_b32 s15, s43, s15
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v54.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s15
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v101
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v112
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v82
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v84
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v85
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v86
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v87
+; GFX12-TRUE16-NEXT: s_and_b32 s5, s22, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s25, s8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0, v55.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0, v65.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0, v66.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0, v68.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0, v48.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v113
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v116
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v117
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v118
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v69.l, v51.l, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v81.l, v54.l, s8
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s26, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s11, s28, s11
+; GFX12-TRUE16-NEXT: s_and_b32 s12, s29, s12
+; GFX12-TRUE16-NEXT: s_and_b32 s13, s41, s13
+; GFX12-TRUE16-NEXT: s_and_b32 s14, s42, s14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v82.l, v55.l, s9
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v31
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v96.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v98, v98
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v32
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v96, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v96.l, v32.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v84.l, v65.l, s11
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v36, v39
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v32.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s29, s14
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v33
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v31
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v83.l, v64.l, s10
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v35, v37
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v34, v39
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v32.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v32.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v33
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v31
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v85.l, v66.l, s12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v34
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v35
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v86.l, v68.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v87.l, v48.l, s14
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v14.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v52, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v129, v133
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v13.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v37, v39
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v53, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v54, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v12.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v39, v38
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v11.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
+; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s3, v39, v38
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s3
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s0, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v7
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v39, v39
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v25.l, v9.l, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v25, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v38, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v23, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v23, v26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v24
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v26, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v26, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v23, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v24.l, v8.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v9.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v21
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v19
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v5.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v22.l, v6.l, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v9, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v10, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v21.l, v5.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v4.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v11, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v7, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v16, v12
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v18, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v18, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v21, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v16
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v18
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0, v0.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v5.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.l, v1.l, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v6.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v7.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v8.l, v4.l, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v29 :: v_dual_mov_b32 v1, v49
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v39
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v35 :: v_dual_mov_b32 v1, v34
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v33 :: v_dual_mov_b32 v3, v32
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v38 :: v_dual_mov_b32 v5, v36
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v35 :: v_dual_mov_b32 v7, v34
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v33 :: v_dual_mov_b32 v9, v32
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v31 :: v_dual_mov_b32 v11, v30
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v12, v37
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v31 :: v_dual_mov_b32 v5, v30
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v29 :: v_dual_mov_b32 v7, v28
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v27 :: v_dual_mov_b32 v9, v36
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_maximumnum_v32bf16:
@@ -13032,21 +12542,17 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13092,19 +12598,15 @@ define bfloat @v_maximumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13333,17 +12835,11 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7
@@ -13352,11 +12848,8 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -13434,17 +12927,11 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v6
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v5, v7
@@ -13455,11 +12942,8 @@ define <2 x bfloat> @v_maximumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v2.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -13773,58 +13257,48 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
@@ -13902,64 +13376,54 @@ define <3 x bfloat> @v_maximumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v6, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v5, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14363,74 +13827,61 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
@@ -14530,85 +13981,75 @@ define <4 x bfloat> @v_maximumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s2, v11, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s0, v11, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0, v0.l
; GFX12-TRUE16-NEXT: v_cmp_gt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v6.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
index 32091c78120a1..f222aa5c6c54b 100644
--- a/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimummaximum.ll
@@ -246,28 +246,16 @@ define amdgpu_ps void @s_test_minmax_f16(half inreg %a, half inreg %b, half inre
; GFX1170-GISEL-FAKE16-NEXT: global_store_b16 v1, v0, s[6:7]
; GFX1170-GISEL-FAKE16-NEXT: s_endpgm
;
-; GFX12-SDAG-TRUE16-LABEL: s_test_minmax_f16:
-; GFX12-SDAG-TRUE16: ; %bb.0:
-; GFX12-SDAG-TRUE16-NEXT: s_maximum_f16 s0, s0, s1
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0
-; GFX12-SDAG-TRUE16-NEXT: s_mov_b32 s5, s4
-; GFX12-SDAG-TRUE16-NEXT: s_mov_b32 s4, s3
-; GFX12-SDAG-TRUE16-NEXT: s_minimum_f16 s0, s0, s2
-; GFX12-SDAG-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX12-SDAG-TRUE16-NEXT: global_store_b16 v1, v0, s[4:5]
-; GFX12-SDAG-TRUE16-NEXT: s_endpgm
-;
-; GFX12-SDAG-FAKE16-LABEL: s_test_minmax_f16:
-; GFX12-SDAG-FAKE16: ; %bb.0:
-; GFX12-SDAG-FAKE16-NEXT: s_maximum_f16 s0, s0, s1
-; GFX12-SDAG-FAKE16-NEXT: s_mov_b32 s5, s4
-; GFX12-SDAG-FAKE16-NEXT: s_mov_b32 s4, s3
-; GFX12-SDAG-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
-; GFX12-SDAG-FAKE16-NEXT: s_minimum_f16 s0, s0, s2
-; GFX12-SDAG-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
-; GFX12-SDAG-FAKE16-NEXT: global_store_b16 v0, v1, s[4:5]
-; GFX12-SDAG-FAKE16-NEXT: s_endpgm
+; GFX12-SDAG-LABEL: s_test_minmax_f16:
+; GFX12-SDAG: ; %bb.0:
+; GFX12-SDAG-NEXT: s_maximum_f16 s0, s0, s1
+; GFX12-SDAG-NEXT: s_mov_b32 s5, s4
+; GFX12-SDAG-NEXT: s_mov_b32 s4, s3
+; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_3)
+; GFX12-SDAG-NEXT: s_minimum_f16 s0, s0, s2
+; GFX12-SDAG-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
+; GFX12-SDAG-NEXT: global_store_b16 v0, v1, s[4:5]
+; GFX12-SDAG-NEXT: s_endpgm
;
; GFX12-GISEL-LABEL: s_test_minmax_f16:
; GFX12-GISEL: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
index d5d49a74815fc..f1ffce9066d7e 100644
--- a/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/minimumnum.bf16.ll
@@ -118,21 +118,17 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) #1 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -178,19 +174,15 @@ define bfloat @v_minimumnum_bf16(bfloat %x, bfloat %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -309,12 +301,10 @@ define bfloat @v_minimumnum_bf16_nnan(bfloat %x, bfloat %y) #1 {
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v3, v2
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -348,9 +338,8 @@ define bfloat @v_minimumnum_bf16_nnan(bfloat %x, bfloat %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v2
; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -579,17 +568,11 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7
@@ -598,11 +581,8 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -680,17 +660,11 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7
@@ -701,11 +675,8 @@ define <2 x bfloat> @v_minimumnum_v2bf16(<2 x bfloat> %x, <2 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -909,12 +880,9 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
@@ -975,12 +943,9 @@ define <2 x bfloat> @v_minimumnum_v2bf16_nnan(<2 x bfloat> %x, <2 x bfloat> %y)
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v1.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v4
@@ -1286,58 +1251,48 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
@@ -1415,64 +1370,54 @@ define <3 x bfloat> @v_minimumnum_v3bf16(<3 x bfloat> %x, <3 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1728,35 +1673,31 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s1
; GFX11-TRUE16-NEXT: s_and_b32 s0, s4, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1811,29 +1752,24 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v7, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v2
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v9, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1841,7 +1777,7 @@ define <3 x bfloat> @v_minimumnum_v3bf16_nnan(<3 x bfloat> %x, <3 x bfloat> %y)
; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s1
; GFX12-TRUE16-NEXT: s_and_b32 s0, s4, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v5.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2228,74 +2164,61 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
@@ -2395,85 +2318,75 @@ define <4 x bfloat> @v_minimumnum_v4bf16(<4 x bfloat> %x, <4 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -2804,43 +2717,39 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v10, v5
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v12, v11
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v6.l, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v4bf16_nnan:
@@ -2910,48 +2819,44 @@ define <4 x bfloat> @v_minimumnum_v4bf16_nnan(<4 x bfloat> %x, <4 x bfloat> %y)
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v4
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v4, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v5, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v7.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v10, v5
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v4
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v12, v11
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v4.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
+; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v8
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v4.l, v6.l, s5
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v7.l, v6.l, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v4bf16_nnan:
@@ -3504,111 +3409,93 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v8
; GFX11-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v14.l, v13.l, s1
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v18, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v9.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v12, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v14, v16
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v8.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v18, v19
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v12.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v14, v13
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v16, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s3
; GFX11-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v9.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v12.l, s6
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v3.l, v0.l, s2
@@ -3745,124 +3632,106 @@ define <6 x bfloat> @v_minimumnum_v6bf16(<6 x bfloat> %x, <6 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v5
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v4
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v9, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v3
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v14, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v15, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v8
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v15, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v12.l, v11.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v14.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v14.l, v13.l, s1
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v11.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v13.l, v9.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v18, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v11.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v22, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v17, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v10.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v18, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v9.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v21, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, s5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v8.l, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v6, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v12
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v14, v16
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v13
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v4.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v12, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v1.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v6, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v7.l, v8.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v17, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v11.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v8.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v18, v19
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v13.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v14, v13
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v16, v15
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v1.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v0.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s2, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v3
+; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s3
; GFX12-TRUE16-NEXT: s_and_b32 s6, s0, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v7
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v10.l, v8.l, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v6.l, v9.l, s6
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v6.l, v9.l, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v12.l, s6
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, s3
; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -4651,163 +4520,138 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
; GFX11-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v10.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v19, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v15.l, v12.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v14.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v14.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v12.l, s3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v17
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v12.l, v8.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v7
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v3.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.h, v10.l, v13.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v17.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v14.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v3.l, v17.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v15, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v8.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s2
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s0, s3
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v17.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s3, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v8.l, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v17.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX11-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v8
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v8bf16:
@@ -4967,184 +4811,160 @@ define <8 x bfloat> @v_minimumnum_v8bf16(<8 x bfloat> %x, <8 x bfloat> %y) #1 {
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v7
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v5
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v8, v8
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v11, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v11, 16, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v2
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v8.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v14, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v12, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v10.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v6
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v19, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v10.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v16.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v12.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v5
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v10.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v19, v19
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v16.l, v12.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v15.l, v12.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v15, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v18, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v12.l, v14.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v13
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v8.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v14, v15
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v16, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v17, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v12, 16, v4
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v15, v17
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v15, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v16.l, v15.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v14.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v14.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v13.l, s0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v16, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v14.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.h, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v12.l, s3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v15.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v14.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v19
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v12.l, v8.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v15, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v17
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s0, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v11.l, v10.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v17
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v3.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v13.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.h, v10.l, v13.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v15.l, v14.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v7.l, v17.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v12, v12
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v15, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v2.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v6.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v15, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v4
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.h, v11.l, v14.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v8.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v4
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v13, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v13, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v2.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v17
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v8.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v15.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v15, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v7.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v3.l, v17.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v12
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v16, v15
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v2.l, v9.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v10
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v15, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v8.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v5.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v7.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s2, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v5.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v0.l, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s0, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v4
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v17.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v1.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v2.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v11
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_and_b32 s3, s3, s6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v1.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v8.l, s7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v9.l, v17.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
; GFX12-TRUE16-NEXT: s_and_b32 s2, s4, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v8.l, v14.l, s7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v6.l, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v4.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v6.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, v2 :: v_dual_mov_b32 v2, v7
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v3
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, v8
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v8bf16:
@@ -6562,327 +6382,276 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX11-TRUE16-LABEL: v_minimumnum_v16bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v16, v7
; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v16
; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v4
; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v7
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v22
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v23.l, v20.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v21.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v19.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v17.l, s3
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v25
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v21.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v22.l, v23.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.h, v18.l, v19.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v21.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v24.l, v20.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v23.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v19.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX11-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v20.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v26, v27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v18.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v24.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v27
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v22.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v27, v29
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.h, v7.l, v21.l, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
; GFX11-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v27
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s0, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v22.l
; GFX11-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v19.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v24.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v28.l, s3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.h, v17.l, v23.l, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.h, v20.l, v18.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v28.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v24.l, v21.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v15
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v19.l, v22.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v21.l, v17.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v28.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v17.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v17.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.h, v15.l, v17.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v3
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v13
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v21
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v17.l, v14.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v16
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v9.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v21, v16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v5.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v13
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v20.l, v9.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v16 :: v_dual_mov_b32 v4, v19
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v18
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v19 :: v_dual_mov_b32 v5, v18
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v17
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v16bf16:
@@ -7208,372 +6977,320 @@ define <16 x bfloat> @v_minimumnum_v16bf16(<16 x bfloat> %x, <16 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v16, v7 :: v_dual_mov_b32 v17, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v16, v7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v14
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v6, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v14
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v17, 16, v16
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v6, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v16
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v26, 16, v4
; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 16, v15
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v1
; GFX12-TRUE16-NEXT: v_and_b32_e32 v29, 0xffff0000, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v6.l
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v18, 0xffff0000, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, vcc_lo
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v18, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v18.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v18, 16, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v17.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v20, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v18.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v13
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v19
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v23.l, v22.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v17.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v18
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v21, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v22.l, v20.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v23.l, v20.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-TRUE16-NEXT: v_and_b32_e32 v22, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v20.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v18.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v21.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v19.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v21.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v19.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s1, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v19.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v17.l, s3
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v26.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v24, v25
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v24, v25
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v22.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v20.l, v21.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v26.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v27
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v20.l, s1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v27, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v23.l
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v21.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v22.l, v23.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v20, 0xffff0000, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.h, v7.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v19.l, v18.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v27, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.h, v18.l, v19.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v19, 16, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v7
; GFX12-TRUE16-NEXT: v_and_b32_e32 v26, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v24, v25
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v28, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v20, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v18
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v21.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v19, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v23.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v19.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v24.l, v20.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v26, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v23, 16, v10
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v7.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v19, 16, v10
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v19.l, v7.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v24.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v17.l, v23.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v19.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
; GFX12-TRUE16-NEXT: v_and_b32_e32 v24, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v18.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v30.l, v19.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v17
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v31.l, v23.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v20.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v26, v27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v19
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v18.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v24.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v29, v29
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v27
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v30
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v29, 16, v31
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v22.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v28.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v27, v29
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v26.l, v24.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v27.l, v25.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v18.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v20.l, v18.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v26, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v28
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v28.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v23.l, v23.l, v19.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v27
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v29.l, v23.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v28
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v26, v27
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v22.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v23.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v21.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v6.l, v22.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v29
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.h, v7.l, v21.l, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v27, 16, v24
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v19
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
; GFX12-TRUE16-NEXT: v_and_b32_e32 v21, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v25.l, v24.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v20
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v21, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v20.l, v6.l
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v22, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v26, v27
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s0, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v22.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v25, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v19.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v22.l, v21.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v24.l, v28.l, s3
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v24, 16, v0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.h, v18.l, v7.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.h, v17.l, v23.l, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v21, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v20.l, v18.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v28.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v21.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v24.l, v21.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v23
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v26, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v15
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.h, v23.l, v19.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v20.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v19.l, v22.l, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v24.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v21.l, v17.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v6
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v16.l, v15.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v18
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.h, v7.l, v28.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v6.l, v24.l, s0
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v16.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v17.l, v14.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v14.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v20.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v18.l, v17.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v13
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v22, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v6.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v13.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v16.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v15.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v20.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v13.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v17.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v5
; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v17
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v16.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v14.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v7.l, v20.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.h, v15.l, v17.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v14
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v15.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v16.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v12
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v13.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v21, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v3
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v17, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v17, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v4.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v22, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v11
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v21
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v11.l, s3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v14.l, v6.l, s3
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v17.l, v14.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v21, v16
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v22, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v3.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v18.l, v13.l, v5.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v9
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v22, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v17, v17
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v9.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v14, v14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v8.l, s1
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v21, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v11
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v10.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v9.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v12.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v13, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v13, v12
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v12, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v17, v14
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v22, v21
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v11.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v14, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v10
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v21, v16
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v5.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v13
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v14.l, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v13
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v14, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v8
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v13
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v14
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v13
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v9.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v12.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v16.l, v11.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v1.l, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v11.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v20.l, v9.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v10.l, v4.l, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v15
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v20 :: v_dual_mov_b32 v3, v16
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v15 :: v_dual_mov_b32 v3, v20
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v19 :: v_dual_mov_b32 v5, v18
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v6, v17
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v16bf16:
@@ -10402,633 +10119,534 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v14
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v12
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v30
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v13
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v29
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v28
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v28
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
; GFX11-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v51, v51
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v53, v53
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v15
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v11
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX11-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
; GFX11-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
; GFX11-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v52, v52
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v54, v54
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v66, v66
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v33.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v34.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v39.l, v36.l, s4
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v14
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v55, v55
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v12
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v27
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s16, v97, v128
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s17, v98, v129
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v54, v54
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s47, v66, v66
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v100.l, v99.l, s16
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v132.l, v131.l, s24
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s5
; GFX11-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v49, v49
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v51, v51
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v53, v53
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v55, v55
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s56, v69, v69
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v80.l, v71.l, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v53.l, v96.l, v87.l, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v112.l, v103.l, s18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v48.l, v147.l, s28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v35
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v39
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v98.l, v99.l, v54.l, s17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v114.l, v131.l, v66.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v33
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v36
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX11-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v117, v97
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v36.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s17, s2
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v30
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v53.l, s15
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v54
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v100.l, v103.l, v55.l, s19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v118.l, v147.l, v48.l, s29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v98
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s17, v69, v130
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v80, v131
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v81, v132
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v52, v52
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v64.l, v38.l, s6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v84.l, v83.l, s12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v64.l, v116.l, v115.l, s20
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s15, v96, v119
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v87, v135
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v115, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v100, v130
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v102, v132
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v101, v131
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v112, v133
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v34.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v99, v144
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v35.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v103, v145
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v39.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s16, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v38.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v113, v134
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX11-TRUE16-NEXT: s_and_b32 s5, s20, s5
; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v48.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX11-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v114, v146
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v53
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v48
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v87
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v118
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v97, v146
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s17
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v65, v65
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v50, v50
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v50.l, v68.l, v67.l, s8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v68.l, v144.l, v135.l, s26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v51.l, s11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v52.l, s13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v102.l, v115.l, v64.l, s21
; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX11-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v50.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v51.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v52.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX11-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX11-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX11-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v64.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v53.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v54.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX11-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v55.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v37.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v116, v119
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v49.l
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX11-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX11-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX11-TRUE16-NEXT: s_and_b32 s13, s28, s13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v96, v145
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v117, v81
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v81.l, v98.l, v54.l, s25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v33
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v34
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v36
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v65, v65
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v65.l, v128.l, v119.l, s22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v51
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v52
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v64
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v116.l, v135.l, v68.l, s27
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v71
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v83
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v102
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v35.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v96
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v97
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v98
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v112.l, v119.l, v65.l, s23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v66
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v114
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v85, v135
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v86, v144
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v101, v69
+; GFX11-TRUE16-NEXT: s_and_b32 s17, s17, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v37.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v39.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s7
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v113, v80
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v51.l, s22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v71.l, v83.l, v52.l, s23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v83.l, v102.l, v64.l, s27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s43
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s45
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v35.l, s17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v49
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v85.l, v114.l, v66.l, s29
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v83
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s18, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s19, s2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v13
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.h, v34.l, v37.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.h, v36.l, v39.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s9
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v64.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v82, v133
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v114
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v50
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v55
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v67
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v147, 16, v100
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s20
+; GFX11-TRUE16-NEXT: s_and_b32 s10, s27, s10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v84, v134
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v99, v147
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v71
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v49.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s21
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v99
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s46
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v52.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v65
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v112
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v80.l, v87.l, v53.l, s24
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v102
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s47
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v128, v82
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v82.l, v100.l, v55.l, s26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v67
+; GFX11-TRUE16-NEXT: s_and_b32 s3, s20, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v28
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.h, v38.l, v49.l, s3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v103, v130
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v80
+; GFX11-TRUE16-NEXT: s_and_b32 s6, s23, s6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v50.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s56
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v100
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.h, v71.l, v52.l, s6
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v53.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v103
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v30
+; GFX11-TRUE16-NEXT: s_and_b32 s4, s21, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.h, v67.l, v50.l, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s7, s24, s7
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v119, v132
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.h, v80.l, v53.l, s7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v29
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v13.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v14.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s43
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v68
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s44, 0, v128
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v116
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v84.l, v112.l, v65.l, s28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v30
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v69
+; GFX11-TRUE16-NEXT: s_and_b32 s16, s44, s16
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s41, v115, v131
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s16
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v119
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v81
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v118.l, v48.l, s42
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v86.l, v116.l, v68.l, s41
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v51.l
+; GFX11-TRUE16-NEXT: s_and_b32 s15, s43, s15
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v54.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s15
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v101
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v112
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v82
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v84
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v85
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v86
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v87
+; GFX11-TRUE16-NEXT: s_and_b32 s5, s22, s5
+; GFX11-TRUE16-NEXT: s_and_b32 s8, s25, s8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v55.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v65.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v66.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v68.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v48.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v113
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v116
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v117
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v118
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v69.l, v51.l, s5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v81.l, v54.l, s8
+; GFX11-TRUE16-NEXT: s_and_b32 s9, s26, s9
+; GFX11-TRUE16-NEXT: s_and_b32 s11, s28, s11
+; GFX11-TRUE16-NEXT: s_and_b32 s12, s29, s12
+; GFX11-TRUE16-NEXT: s_and_b32 s13, s41, s13
+; GFX11-TRUE16-NEXT: s_and_b32 s14, s42, s14
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.h, v82.l, v55.l, s9
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v31
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v31
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_4) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v96, v97
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v39
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v96.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v98, v98
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v32
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v96.l, v32.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.h, v84.l, v65.l, s11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v33
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.h, v83.l, v64.l, s10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v35, v37
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v34, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v32.l, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v32.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v33
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v31
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.h, v85.l, v66.l, s12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v34
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v35
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.h, v86.l, v68.l, s13
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.h, v87.l, v48.l, s14
; GFX11-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s29, s14
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v128
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v52, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v129, v133
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v37, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v26
; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v53, v50
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v54, v52
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v39, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v11.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v11.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v10.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v39, v38
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s3
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s0, s2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v7
+; GFX11-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v39, v39
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; GFX11-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v25.l, v9.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v24
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v38, v37
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v9
; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v23, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v26
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v7.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v24
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v26, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX11-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v26, v25
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v27.l, v24.l, v8.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v28.l, v9.l, v7.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v21
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v6
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v19
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, s0
+; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5.l
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v22.l, v6.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v30.l, v21.l, v5.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v12
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v19.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v21, v20
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v5
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v16
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v18
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX11-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX11-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX11-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX11-TRUE16-NEXT: s_and_b32 s4, s5, s8
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v29
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v35.l, v5.l, v0.l, s3
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.l, v1.l, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v33.l, v6.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v32.l, v7.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v31.l, v8.l, v4.l, s2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, v49 :: v_dual_mov_b32 v2, v48
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v3, v39 :: v_dual_mov_b32 v4, v38
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v5, v36 :: v_dual_mov_b32 v6, v35
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v7, v34 :: v_dual_mov_b32 v8, v33
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v9, v32 :: v_dual_mov_b32 v10, v31
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v11, v30 :: v_dual_mov_b32 v12, v37
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v35 :: v_dual_mov_b32 v1, v34
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v33 :: v_dual_mov_b32 v3, v32
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v4, v31 :: v_dual_mov_b32 v5, v30
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v29 :: v_dual_mov_b32 v7, v28
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v8, v27 :: v_dual_mov_b32 v9, v36
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_minimumnum_v32bf16:
@@ -11607,697 +11225,589 @@ define <32 x bfloat> @v_minimumnum_v32bf16(<32 x bfloat> %x, <32 x bfloat> %y) #
; GFX12-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-TRUE16-NEXT: s_wait_kmcnt 0x0
; GFX12-TRUE16-NEXT: scratch_load_b32 v31, off, s32
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v15
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v35, 0xffff0000, v14
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v38, 0xffff0000, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v14
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v53, 0xffff0000, v12
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v33, 16, v30
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v14
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v65, 16, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v13
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v29
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v66, 16, v28
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v50, 16, v12
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v51, 0xffff0000, v28
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v35, v35
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v34, 0xffff0000, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v15
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v38, v38
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v49, v49
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v37, 0xffff0000, v30
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v11
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v48, v48
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v51, v51
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v34, v34
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v35, v35
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v36.l, v33.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v39.l, v65.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v50.l, v66.l, s4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v53, 16, v11
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v26
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v10
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v35, 16, v14
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v50, 0xffff0000, v30
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v34, 16, v29
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v37, 16, v13
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v52, 0xffff0000, v29
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v36, 16, v28
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v39, 16, v12
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v28
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v66, 0xffff0000, v10
; GFX12-TRUE16-NEXT: v_and_b32_e32 v98, 0xffff0000, v6
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v148, 16, v0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v37, v37
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v14
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v30
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v52, v52
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v55, v55
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v49, v49
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v51, v51
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v53, v53
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v48, 0xffff0000, v15
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v55, 0xffff0000, v11
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
; GFX12-TRUE16-NEXT: v_and_b32_e32 v70, 0xffff0000, v9
; GFX12-TRUE16-NEXT: v_and_b32_e32 v86, 0xffff0000, v7
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v99, 16, v22
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v100, 16, v6
; GFX12-TRUE16-NEXT: v_and_b32_e32 v101, 0xffff0000, v22
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v146, 0xffff0000, v0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v50, v50
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v52, v52
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s5, v54, v54
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v29
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s8, v66, v66
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v66, 16, v11
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s16, v98, v98
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v37, v37
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v38, v38
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v53.l, v67.l, s6
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v64.l, v68.l, s8
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v128.l, v119.l, s22
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v148.l, v147.l, s28
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v36.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v65.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v129.l, v66.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v35.l, v33.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v37.l, v34.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v39.l, v36.l, s4
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v71, 16, v25
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v80, 16, v9
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v23
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v147, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v48, v48
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v48, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v49, 0xffff0000, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v14
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v13
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s6, v55, v55
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v55, 16, v12
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v27
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s10, v70, v70
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s14, v86, v86
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s17, v101, v101
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v100.l, v99.l, s16
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v147.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v129
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v80.l, v71.l, s10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v99.l, v50.l, s17
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v64.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s16, v97, v128
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s17, v98, v129
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s28, v146, v146
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s44, v54, v54
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s47, v66, v66
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v100.l, v99.l, s16
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v132.l, v131.l, s24
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s5
; GFX12-TRUE16-NEXT: v_and_b32_e32 v82, 0xffff0000, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v118, 0xffff0000, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s15, v97, v97
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s29, v49, v49
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s41, v51, v51
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s43, v53, v53
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s45, v55, v55
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s56, v69, v69
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v66.l, v66.l, v36.l, s17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v80.l, v71.l, s10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v53.l, v96.l, v87.l, s14
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v112.l, v103.l, s18
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v48.l, v147.l, s28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v35
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v39
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v98.l, v99.l, v54.l, s17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v114.l, v131.l, v66.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v33
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v34
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v36
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v38, 16, v27
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v64, 16, v11
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v83, 16, v24
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v84, 16, v8
; GFX12-TRUE16-NEXT: v_and_b32_e32 v85, 0xffff0000, v24
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v130, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v117, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v66.l
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v117, 0xffff0000, v20
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v30
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s12, v82, v82
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v36.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v54, 0xffff0000, v27
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v7
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v114, 0xffff0000, v4
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v131, 16, v18
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v132, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v97
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v133, 0xffff0000, v18
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v134, 0xffff0000, v1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s24, v130, v130
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v84.l, v83.l, s12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s17, s2
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v115, 16, v20
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v116, 16, v4
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s22, v118, v118
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v53.l, s15
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v54
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v100.l, v103.l, v55.l, s19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v118.l, v147.l, v48.l, s29
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v98
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s17, v69, v130
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v80, v131
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v81, v132
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v65, 0xffff0000, v27
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v67, 16, v26
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v68, 16, v10
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v135, 16, v17
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v144, 16, v1
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v145, 0xffff0000, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v54, v54
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s20, v114, v114
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s25, v133, v133
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v15
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s13, v85, v85
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s21, v117, v117
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s26, v134, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v96.l, v87.l, s14
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v54.l, v132.l, v131.l, s24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v34.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v83.l, v48.l, s13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v119.l, v53.l, s23
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.h, v66.l, v36.l, s2
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v81, 0xffff0000, v25
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v69, 0xffff0000, v26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v116.l, v115.l, s20
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v55.l, v144.l, v135.l, s26
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s11, v81, v81
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v131.l, v54.l, s25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s7
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s9, v69, v69
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v39.l, s11
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v87.l, v49.l, s15
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v50.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v115.l, v52.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v54.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v135.l, v55.l, s27
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v135.l, v80.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s15, v96, v119
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v84.l
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v102, 0xffff0000, v5
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v37.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v130.l, v67.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v135
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s42, v52, v52
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v64.l, v38.l, s6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v34.l, s15
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v65.l, v35.l, s16
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v103, 16, v21
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v112, 16, v5
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s18, v102, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v130
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v87, v135
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v115, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v87.l, v33.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v65.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v51.l, v112.l, v103.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s18, v100, v130
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v113, 0xffff0000, v21
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v132.l, v69.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v87, 16, v87
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v52.l, v84.l, v83.l, s12
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v64.l, v116.l, v115.l, s20
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s27, v145, v145
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v53
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v48
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v87
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v81, 16, v118
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v97, v146
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v35.l, s17
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v34.l, v37.l, s18
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v36.l, v39.l, s19
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v119, 16, v19
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v128, 16, v3
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v129, 0xffff0000, v19
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s7, v65, v65
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v65, 16, v28
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s40, v50, v50
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v50.l, v68.l, v67.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v144.l, v135.l, s26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v51.l, s11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v52.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v102.l, v115.l, v64.l, s21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v96, v145
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s42, v117, v81
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v37.l, s18
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s19, v113, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v38.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v131.l, v68.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v98.l, v54.l, s25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v33
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v34
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v36
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s23, v129, v129
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s46, v65, v65
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v65.l, v128.l, v119.l, s22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v85, 16, v51
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v86, 16, v52
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v64
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v116.l, v135.l, v68.l, s27
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v135, 16, v71
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v83
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v69, 16, v102
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v32, 16, v15
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v132
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s15, 0, v87
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s16, 0, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v98.l, v67.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v48.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v35.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s17, 0, v96
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v97
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v98
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v103.l, v51.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v133.l, v70.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v131
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v102, v132
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v98
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v51.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v144.l, v81.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v133
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s19, v101, v131
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v52.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v145.l, v82.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v112.l, v119.l, v65.l, s23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v66
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v80, 16, v114
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v85, v135
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s23, v86, v144
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s27, v101, v69
+; GFX12-TRUE16-NEXT: s_and_b32 s17, s17, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v37.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v39.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s7
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s29, v113, v80
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v71.l, v51.l, s22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v83.l, v52.l, s23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v102.l, v64.l, s27
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, s43
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s45
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v35.l, s17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v49
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v38
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v69.l, v69.l, v39.l, s20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s18, 0, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v144, 16, v144
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v112, v133
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v68.l, v68.l, v38.l, s19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v145, 16, v145
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v100.l, v69.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v34.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s24, v99, v144
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v114.l, v66.l, s29
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v83
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s18, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s19, s2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v13
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v129, 16, v12
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v34.l, v37.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.h, v36.l, v39.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s9
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v64.l
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s20, v82, v133
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v114
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v84, 16, v50
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v55
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v67
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v147, 16, v100
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v38.l, v49.l, s20
+; GFX12-TRUE16-NEXT: s_and_b32 s10, s27, s10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s21, v84, v134
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v99, v147
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v38
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v71
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v49.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v82, 16, v29
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v70.l, v70.l, v48.l, s21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v99.l, v68.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v35.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v49.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v134.l, v71.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s25, v103, v145
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v100
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v101.l, v70.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v99, 16, v99
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s15, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v39.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v53.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v146.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v134, 16, v134
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v80.l, v50.l, s23
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v81.l, v81.l, v51.l, s24
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v82.l, v52.l, s25
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v100
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s16, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v67.l, v67.l, v50.l, s21
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s20, 0, v99
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v70, 16, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s46
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v52.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v65
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v130, 16, v112
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v80.l, v87.l, v53.l, s24
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v102
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, s47
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s44, v128, v82
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v82.l, v100.l, v55.l, s26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v100, 16, v67
+; GFX12-TRUE16-NEXT: s_and_b32 s3, s20, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v133, 16, v28
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.h, v33.l, v34.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v149, 16, v13
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.h, v65.l, v35.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v38.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v101
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s19, 0, v99
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v146, 16, v146
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s22, v113, v134
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v103.l, v80.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v112.l, v81.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v113.l, v82.l
-; GFX12-TRUE16-NEXT: s_and_b32 s5, s20, s5
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v14.l, v30.l, s41
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.h, v38.l, v49.l, s3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v103, v130
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v80
+; GFX12-TRUE16-NEXT: s_and_b32 s6, s23, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v50.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s56
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v100
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v69.l, v39.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s6, 0x8000, v48.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s21, 0, v101
-; GFX12-TRUE16-NEXT: s_and_b32 s4, s19, s4
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s26, v114, v146
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v86.l, v64.l, s29
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v103, 16, v103
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v112
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v113
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s42
-; GFX12-TRUE16-NEXT: s_and_b32 s6, s21, s6
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v50.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v51.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s10, 0x8000, v52.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v83.l, v83.l, v53.l, s26
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v117.l, v86.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s23, 0, v103
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v112
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v113
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.h, v71.l, v52.l, s6
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v53.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s24, 0, v103
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v132, 16, v30
+; GFX12-TRUE16-NEXT: s_and_b32 s4, s21, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s44
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v70.l, v48.l, s6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v118.l, v14.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e64 v128.l, v30.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v114.l, v83.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v117
-; GFX12-TRUE16-NEXT: s_and_b32 s8, s23, s8
-; GFX12-TRUE16-NEXT: s_and_b32 s9, s24, s9
-; GFX12-TRUE16-NEXT: s_and_b32 s10, s25, s10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v128
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v64.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v114, 16, v114
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v117
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v53.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v55.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v119.l, v85.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v114
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v84.l, v54.l, s27
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v54.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v119
-; GFX12-TRUE16-NEXT: s_and_b32 s11, s26, s11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v115.l, v84.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v55.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v37.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s28, v116, v119
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v71.l, v71.l, v49.l, s22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v115
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v49.l
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s18, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v85.l, v85.l, v55.l, s28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.h, v67.l, v50.l, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s7, s24, s7
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s43, v119, v132
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v67.l, v37.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s27, 0, v115
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v102.l, v71.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v116.l, v85.l
-; GFX12-TRUE16-NEXT: s_and_b32 s12, s27, s12
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v102, 16, v102
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v116
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v102
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v116
-; GFX12-TRUE16-NEXT: s_and_b32 s7, s22, s7
-; GFX12-TRUE16-NEXT: s_and_b32 s13, s28, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.h, v80.l, v53.l, s7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v128, 16, v29
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s16, 0x8000, v13.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s15, 0x8000, v14.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s43
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v68
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s44, 0, v128
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v131, 16, v116
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v84.l, v112.l, v65.l, s28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v119, 16, v30
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v101, 16, v69
+; GFX12-TRUE16-NEXT: s_and_b32 s16, s44, s16
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s41, v115, v131
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s16
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s43, 0, v119
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v112, 16, v81
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v118.l, v48.l, s42
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v86.l, v116.l, v68.l, s41
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s5, 0x8000, v51.l
+; GFX12-TRUE16-NEXT: s_and_b32 s15, s43, s15
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v54.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.h, v85.l, v55.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s15
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s22, 0, v101
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s25, 0, v112
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v113, 16, v82
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v115, 16, v84
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v116, 16, v85
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v117, 16, v86
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v118, 16, v87
+; GFX12-TRUE16-NEXT: s_and_b32 s5, s22, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s8, s25, s8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s9, 0x8000, v55.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s11, 0x8000, v65.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s12, 0x8000, v66.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s13, 0x8000, v68.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s14, 0x8000, v48.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s26, 0, v113
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s28, 0, v115
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s29, 0, v116
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s41, 0, v117
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s42, 0, v118
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v69.l, v51.l, s5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v81.l, v54.l, s8
+; GFX12-TRUE16-NEXT: s_and_b32 s9, s26, s9
+; GFX12-TRUE16-NEXT: s_and_b32 s11, s28, s11
+; GFX12-TRUE16-NEXT: s_and_b32 s12, s29, s12
+; GFX12-TRUE16-NEXT: s_and_b32 s13, s41, s13
+; GFX12-TRUE16-NEXT: s_and_b32 s14, s42, s14
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.h, v82.l, v55.l, s9
; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v87, 16, v31
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v96, 0xffff0000, v31
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v96, 16, v31
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v97, 0xffff0000, v31
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v98, 16, v31
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v15.l, v31.l, s40
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v68.l, v38.l, s4
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v87.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v96, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v34.l, v15.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v96.l, v32.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v87.l, v87.l, v32.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v98, v98
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v36, 16, v34
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v71.l, v49.l, s7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v96, 16, v96
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v97.l, v87.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v32.l, v96.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v97, v97
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v98, v98
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v15
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v32
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v97, 16, v97
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v35.l, v31.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v96, v97
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v35
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v80.l, v50.l, s8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v96.l, v32.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.h, v84.l, v65.l, s11
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v87.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v36, v39
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v32.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.h, v81.l, v51.l, s9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v118
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v38.l, v33.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v149, v149
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.h, v83.l, v53.l, s11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v48, 16, v38
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.h, v82.l, v52.l, s10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v31.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v29
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v13.l, v29.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v48
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.h, v84.l, v54.l, s12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v13.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s29, s14
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v128
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v12
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.h, v86.l, v64.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v50
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v33
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v31
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.h, v83.l, v64.l, s10
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v35, v37
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v34, v39
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v27
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v33.l, v32.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v51, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v28
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v31.l, v15.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v15.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v29.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v30.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v12.l, v28.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v51
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v32.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v34, 16, v33
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v35, 16, v31
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.h, v85.l, v66.l, s12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v34
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v35
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.h, v86.l, v68.l, s13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.h, v87.l, v48.l, s14
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s1, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v70, v70
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.h, v33.l, v32.l, s0
; GFX12-TRUE16-NEXT: v_cndmask_b16 v15.l, v31.l, v15.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v14.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v52, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v12.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v11
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v29.l, v13.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v14.l, v30.l, v14.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v27
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v29.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v10
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v129, v133
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v27.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v53
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v11.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v26.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v50, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v28.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v27.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v55.l, v10.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v25
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v13.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v54.l, v26.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v25.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v52, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v53, 16, v53
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v54
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v54, 16, v55
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v37, v39
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v28
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v53, v50
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v51
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v54, v52
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v50.l, v25.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v51.l, v9.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, s2
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v27.l, v11.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v12.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v39, v38
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v27
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v11.l
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v26.l, v26.l, v10.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v51, 16, v51
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v52.l, v27.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v53.l, v26.l
+; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s3, v39, v38
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v26
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v37.l, v28.l, v12.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v51, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v52, 16, v52
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v50, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v53
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v13.l, v29.l, v13.l, s3
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v25.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v52
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v11.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v10.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v50, v50
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v28.l, v12.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s3
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v25, v25
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v28
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v28, 16, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v28.l, v12.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v25.l, v25.l, v9.l, s3
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s0, s2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v27.l, v11.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v26.l, v10.l, s1
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v24.l, v8.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v23
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v28, v28
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v25
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v27.l, v11.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v25
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v38, v38
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v39, 16, v7
+; GFX12-TRUE16-NEXT: s_and_b32 s3, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v37
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v24.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v38, v38
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v9.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v24.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v25.l, v8.l
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v39, v39
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v23
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v26.l, v10.l, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v23.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v37, v37
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
-; GFX12-TRUE16-NEXT: s_and_b32 s1, vcc_lo, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v25
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v23.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v37, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v38, 16, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v12.l, v9.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v25.l, v9.l, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v23.l, v7.l, vcc_lo
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v26, v26
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v22
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v25, v24
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v11.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v7.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v22
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v38, v37
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v9
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v22.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v23, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v10.l, v8.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v24.l, v24.l, v8.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v22.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v9.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v23, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v10.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v6.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v23, v26
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v25, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v24
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v22
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v21.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v24, v24
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v7.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v11.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v24, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v12.l, v21.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v11.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v24
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v22
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v22.l, v12.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v23.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v21
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v10.l, v10.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v26, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v25, 16, v21
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v26, 16, v5
; GFX12-TRUE16-NEXT: s_and_b32 s2, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v23
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v21
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v21.l, v10.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v23
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v7.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v22.l, v22.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v26, v25
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v23, 16, v4
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v9.l, v8.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v23, v22
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v21
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v27.l, v24.l, v8.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v21.l, v21.l, v5.l, s1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v11.l, v7.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v12.l, v5.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v20
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v28.l, v9.l, v7.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v23, v23
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v20
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v21
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v7.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v20.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v19
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: s_and_b32 s3, s0, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v9, v9
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v4.l
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v19
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v20.l, v4.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v19.l, s3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v7, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v5.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v10.l, v6.l, s3
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v22.l, v6.l, s0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v19.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v9, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v20, v20
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v0
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s2, s4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v18
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v36.l, v7.l, v5.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v10, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v12, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v18
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v30.l, v21.l, v5.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v18.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v17
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v5, v5
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v16
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v19
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v20, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v18.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v17.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v6, v6
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v5.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v16.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v18.l, v2.l, s2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v8.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v4.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v17.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v11, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v16.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v12
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v17.l, v8.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v18.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v16
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v18
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v19.l, v6.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v17.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v7, v5
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v16.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v6
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v20, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v21, 16, v0
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v3.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v16, v12
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v18, v17
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v19
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v19.l, v3.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v18, v17
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v22, 16, v8
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v21, v20
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v2.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v9.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v2.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v7
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v1.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v8.l, v8.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v10
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v5.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v7.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v16.l, v8.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v16
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s2, 0x8000, v3.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v10
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v9.l, v9.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v22
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v17, 16, v6
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s0, 0, v16
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v16, 16, v9
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v18, 16, v5
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v3.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v17
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v2.l
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v11
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v12
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s5, 0, v16
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s6, 0, v18
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s7, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s8, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s2
-; GFX12-TRUE16-NEXT: s_and_b32 s2, s3, s4
+; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s0, s1
+; GFX12-TRUE16-NEXT: s_and_b32 s1, s3, s4
; GFX12-TRUE16-NEXT: s_and_b32 s3, s6, s7
; GFX12-TRUE16-NEXT: s_and_b32 s4, s5, s8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v29.l, v8.l, v0.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v49.l, v7.l, v1.l, s4
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v48.l, v5.l, v2.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v39.l, v9.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v38.l, v6.l, v4.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v35.l, v5.l, v0.l, s3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v34.l, v9.l, v1.l, s4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v33.l, v6.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v32.l, v7.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v31.l, v8.l, v4.l, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v29 :: v_dual_mov_b32 v1, v49
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v48 :: v_dual_mov_b32 v3, v39
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v35 :: v_dual_mov_b32 v1, v34
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v33 :: v_dual_mov_b32 v3, v32
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v38 :: v_dual_mov_b32 v5, v36
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v35 :: v_dual_mov_b32 v7, v34
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v33 :: v_dual_mov_b32 v9, v32
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v31 :: v_dual_mov_b32 v11, v30
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v12, v37
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v4, v31 :: v_dual_mov_b32 v5, v30
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v6, v29 :: v_dual_mov_b32 v7, v28
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v27 :: v_dual_mov_b32 v9, v36
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-FAKE16-LABEL: v_minimumnum_v32bf16:
@@ -13067,21 +12577,17 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v1.l, v0.l, s0
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -13127,19 +12633,15 @@ define bfloat @v_minimumnum_bf16_no_ieee(bfloat %x, bfloat %y) #0 {
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v0.h, v0.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v3, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v2, v3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 16, v1
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -13371,17 +12873,11 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7
@@ -13390,11 +12886,8 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -13472,17 +12965,11 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v2.l, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s2
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v4, v6
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v5, v7
@@ -13493,11 +12980,8 @@ define <2 x bfloat> @v_minimumnum_v2bf16_no_ieee(<2 x bfloat> %x, <2 x bfloat> %
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v0.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v2.l
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.l, v1.l
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v5
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v1
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
@@ -13814,58 +13298,48 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_and_b32 s0, s3, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX11-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s1
@@ -13943,64 +13417,54 @@ define <3 x bfloat> @v_minimumnum_v3bf16_no_ieee(<3 x bfloat> %x, <3 x bfloat> %
; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v0
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v9, v9
; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v2
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v9, v9
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v10, v10
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v7, v7
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s2
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v5.l, v6.l, s1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v1
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v5.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v6, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v4
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v3
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v5, v7
+; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v9, v8
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v11, v10
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v10, v11
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v6.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e32 vcc_lo, 0x8000, v6.l
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v1.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v5, 16, v4
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s1, 0x8000, v0.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v7.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v6
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v5
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v6
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s3, 0, v7
-; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3)
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s4, 0, v8
; GFX12-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX12-TRUE16-NEXT: s_and_b32 s0, s3, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v5.l, v4.l, s2
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v4.l, v6.l, s2
; GFX12-TRUE16-NEXT: s_and_b32 s1, s4, s1
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -14407,74 +13871,61 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX11-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX11-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX11-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX11-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v12
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
; GFX11-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX11-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
-; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX11-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
; GFX11-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, s4
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
; GFX11-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX11-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
@@ -14574,85 +14025,75 @@ define <4 x bfloat> @v_minimumnum_v4bf16_no_ieee(<4 x bfloat> %x, <4 x bfloat> %
; GFX12-TRUE16-NEXT: v_and_b32_e32 v7, 0xffff0000, v3
; GFX12-TRUE16-NEXT: v_and_b32_e32 v8, 0xffff0000, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v4, v4
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v1
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v0
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v6.l, v5.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v0
-; GFX12-TRUE16-NEXT: v_and_b32_e32 v11, 0xffff0000, v2
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v6, 16, v3
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v6.l, v5.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v0
+; GFX12-TRUE16-NEXT: v_and_b32_e32 v10, 0xffff0000, v2
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v8, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v7, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v2
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s3, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s0
; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v11, v11
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s2, v6, v6
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v12, v12
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v6.l, v10.l, v9.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v4.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v5.l
-; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s4, v13, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v4.l, v4.l, v9.l, vcc_lo
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v10, v10
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v6
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s1
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s3
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v6.l, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v6.l
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s2
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s4
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
-; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v11
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v3.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v11.l, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v12.l, v2.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v13.l, v0.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v1.l, v3.l, s0
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s0, v7, v7
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v0.l, v2.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_u_f32_e64 s1, v8, v8
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v4.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v11
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v12
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v13
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v9.l, v4.l, vcc_lo
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v4
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
+; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s2, v11, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v3
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v11, 16, v1
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v12, 16, v2
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v13, 16, v0
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v5.l, v5.l, v6.l, s2
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e32 vcc_lo, v8, v9
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s0, v11, v10
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s3, 0x8000, v0.l
; GFX12-TRUE16-NEXT: v_cmp_lt_f32_e64 s1, v13, v12
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v5
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v6.l, vcc_lo
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v7.l, v7.l, v4.l, vcc_lo
; GFX12-TRUE16-NEXT: s_wait_alu depctr_va_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v3.l, v3.l, v1.l, s0
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
; GFX12-TRUE16-NEXT: v_cndmask_b16 v2.l, v2.l, v0.l, s1
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v9.l, v7.l
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v8.l, v3.l
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v7
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v3
; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s4, 0x8000, v1.l
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v10.l, v2.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v9, 16, v9
+; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v2
; GFX12-TRUE16-NEXT: s_and_b32 s5, vcc_lo, s0
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v8, 16, v8
-; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v6.l
-; GFX12-TRUE16-NEXT: v_lshlrev_b32_e32 v10, 16, v10
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v9
-; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v4.l, s5
-; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v8
+; GFX12-TRUE16-NEXT: v_cmp_eq_u16_e64 s0, 0x8000, v4.l
+; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s1, 0, v9
; GFX12-TRUE16-NEXT: v_cmp_eq_f32_e64 s2, 0, v10
-; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v6.l, s0
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.h, v5.l, v6.l, s5
+; GFX12-TRUE16-NEXT: s_and_b32 s0, vcc_lo, s0
; GFX12-TRUE16-NEXT: s_and_b32 s1, s1, s4
-; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
+; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.h, v7.l, v4.l, s0
+; GFX12-TRUE16-NEXT: s_and_b32 s0, s2, s3
; GFX12-TRUE16-NEXT: v_cndmask_b16 v1.l, v3.l, v1.l, s1
+; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: v_cndmask_b16 v0.l, v2.l, v0.l, s0
; GFX12-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index e24f50f91bf1b..04a4efb0b1a67 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -113,9 +113,10 @@ define amdgpu_ps void @s_test_minmax_i32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; SDAG-GFX1250-LABEL: s_test_minmax_i32:
; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-NEXT: v_nop
; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-NEXT: v_nop
+; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-NEXT: s_max_i32 s0, s0, s1
; SDAG-GFX1250-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-NEXT: s_min_i32 s0, s0, s2
@@ -126,9 +127,10 @@ define amdgpu_ps void @s_test_minmax_i32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; GISEL-GFX1250-LABEL: s_test_minmax_i32:
; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-NEXT: v_nop
; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-NEXT: v_nop
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-NEXT: s_max_i32 s0, s0, s1
; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
; GISEL-GFX1250-NEXT: s_min_i32 s0, s0, s2
@@ -382,9 +384,10 @@ define amdgpu_ps void @s_test_minmax_u32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; SDAG-GFX1250-LABEL: s_test_minmax_u32:
; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-NEXT: v_nop
; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-NEXT: v_nop
+; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-NEXT: s_max_u32 s0, s0, s1
; SDAG-GFX1250-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-NEXT: s_min_u32 s0, s0, s2
@@ -395,9 +398,10 @@ define amdgpu_ps void @s_test_minmax_u32(i32 inreg %a, i32 inreg %b, i32 inreg %
;
; GISEL-GFX1250-LABEL: s_test_minmax_u32:
; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-NEXT: v_nop
; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-NEXT: v_nop
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-NEXT: s_max_u32 s0, s0, s1
; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
; GISEL-GFX1250-NEXT: s_min_u32 s0, s0, s2
@@ -694,9 +698,10 @@ define amdgpu_ps void @s_test_minmax_f32_ieee_false(float inreg %a, float inreg
;
; SDAG-GFX1250-LABEL: s_test_minmax_f32_ieee_false:
; SDAG-GFX1250: ; %bb.0:
-; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-NEXT: v_nop
; SDAG-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-NEXT: v_nop
+; SDAG-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1250-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-NEXT: s_mov_b32 s4, s3
@@ -706,9 +711,10 @@ define amdgpu_ps void @s_test_minmax_f32_ieee_false(float inreg %a, float inreg
;
; GISEL-GFX1250-LABEL: s_test_minmax_f32_ieee_false:
; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-NEXT: v_nop
; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-NEXT: v_nop
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-NEXT: s_max_num_f32 s0, s0, s1
; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
; GISEL-GFX1250-NEXT: s_mov_b32 s7, s4
@@ -741,9 +747,10 @@ define amdgpu_ps float @test_minmax_commuted_f32_ieee_false(float %a, float %b,
;
; GFX1250-LABEL: test_minmax_commuted_f32_ieee_false:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_maxmin_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%max = call float @llvm.maxnum.f32(float %a, float %b)
@@ -848,9 +855,10 @@ define amdgpu_ps float @test_maxmin_commuted_f32_ieee_false(float %a, float %b,
;
; GFX1250-LABEL: test_maxmin_commuted_f32_ieee_false:
; GFX1250: ; %bb.0:
-; GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GFX1250-NEXT: v_nop
; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-NEXT: v_nop
+; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250-NEXT: v_minmax_num_f32 v0, v0, v1, v2
; GFX1250-NEXT: ; return to shader part epilog
%min = call float @llvm.minnum.f32(float %a, float %b)
@@ -1003,33 +1011,37 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
;
; SDAG-GFX1250-TRUE16-LABEL: test_minmax_f16_ieee_false:
; SDAG-GFX1250-TRUE16: ; %bb.0:
-; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-TRUE16-NEXT: v_nop
; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-TRUE16-NEXT: v_nop
+; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; SDAG-GFX1250-FAKE16-LABEL: test_minmax_f16_ieee_false:
; SDAG-GFX1250-FAKE16: ; %bb.0:
-; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-FAKE16-NEXT: v_nop
; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-FAKE16-NEXT: v_nop
+; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-TRUE16-LABEL: test_minmax_f16_ieee_false:
; GISEL-GFX1250-TRUE16: ; %bb.0:
-; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-TRUE16-NEXT: v_nop
; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-TRUE16-NEXT: v_nop
+; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-FAKE16-LABEL: test_minmax_f16_ieee_false:
; GISEL-GFX1250-FAKE16: ; %bb.0:
-; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-FAKE16-NEXT: v_nop
; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-FAKE16-NEXT: v_nop
+; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-FAKE16-NEXT: v_maxmin_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: ; return to shader part epilog
%max = call half @llvm.maxnum.f16(half %a, half %b)
@@ -1137,9 +1149,10 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; SDAG-GFX1250-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX1250-TRUE16: ; %bb.0:
-; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-TRUE16-NEXT: v_nop
; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-TRUE16-NEXT: v_nop
+; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
; SDAG-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s5, s4
@@ -1150,9 +1163,10 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; SDAG-GFX1250-FAKE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX1250-FAKE16: ; %bb.0:
-; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-FAKE16-NEXT: v_nop
; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-FAKE16-NEXT: v_nop
+; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-FAKE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1250-FAKE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-FAKE16-NEXT: s_mov_b32 s4, s3
@@ -1162,9 +1176,10 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; GISEL-GFX1250-LABEL: s_test_minmax_f16_ieee_false:
; GISEL-GFX1250: ; %bb.0:
-; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-NEXT: v_nop
; GISEL-GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-NEXT: v_nop
+; GISEL-GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-NEXT: s_max_num_f16 s0, s0, s1
; GISEL-GFX1250-NEXT: s_mov_b32 s6, s3
; GISEL-GFX1250-NEXT: s_mov_b32 s7, s4
@@ -1411,33 +1426,37 @@ define amdgpu_ps half @test_maxmin_f16_ieee_false(half %a, half %b, half %c) {
;
; SDAG-GFX1250-TRUE16-LABEL: test_maxmin_f16_ieee_false:
; SDAG-GFX1250-TRUE16: ; %bb.0:
-; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-TRUE16-NEXT: v_nop
; SDAG-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-TRUE16-NEXT: v_nop
+; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; SDAG-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; SDAG-GFX1250-FAKE16-LABEL: test_maxmin_f16_ieee_false:
; SDAG-GFX1250-FAKE16: ; %bb.0:
-; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; SDAG-GFX1250-FAKE16-NEXT: v_nop
; SDAG-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; SDAG-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; SDAG-GFX1250-FAKE16-NEXT: v_nop
+; SDAG-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; SDAG-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; SDAG-GFX1250-FAKE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-TRUE16-LABEL: test_maxmin_f16_ieee_false:
; GISEL-GFX1250-TRUE16: ; %bb.0:
-; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-TRUE16-NEXT: v_nop
; GISEL-GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-TRUE16-NEXT: v_nop
+; GISEL-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-TRUE16-NEXT: v_minmax_num_f16 v0.l, v0.l, v1.l, v2.l
; GISEL-GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GISEL-GFX1250-FAKE16-LABEL: test_maxmin_f16_ieee_false:
; GISEL-GFX1250-FAKE16: ; %bb.0:
-; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, null scope:SCOPE_SE
-; GISEL-GFX1250-FAKE16-NEXT: v_nop
; GISEL-GFX1250-FAKE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GISEL-GFX1250-FAKE16-NEXT: s_mov_b64 s[64:65], 0
+; GISEL-GFX1250-FAKE16-NEXT: v_nop
+; GISEL-GFX1250-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GISEL-GFX1250-FAKE16-NEXT: v_minmax_num_f16 v0, v0, v1, v2
; GISEL-GFX1250-FAKE16-NEXT: ; return to shader part epilog
%min = call half @llvm.minnum.f16(half %a, half %b)
diff --git a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
index 99b77b1517bd2..11eaaa82353f3 100644
--- a/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
+++ b/llvm/test/CodeGen/AMDGPU/move-to-valu-pseudo-scalar-trans-f16-true16.ll
@@ -10,13 +10,15 @@ define amdgpu_kernel void @exp_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_EXP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_EXP_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_EXP_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
- ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_EXP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_EXP_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_EXP_F16_t16_e64_]], %subreg.lo16, [[DEF2]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+ ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY2]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
%res = call half @llvm.amdgcn.exp2.f16(half %val)
@@ -33,13 +35,15 @@ define amdgpu_kernel void @log_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_LOG_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_LOG_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_LOG_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
- ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_LOG_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_LOG_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_LOG_F16_t16_e64_]], %subreg.lo16, [[DEF2]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+ ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY2]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
%res = call half @llvm.amdgcn.log.f16(half %val)
@@ -56,13 +60,15 @@ define amdgpu_kernel void @rcp_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_RCP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RCP_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RCP_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
- ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_RCP_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RCP_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RCP_F16_t16_e64_]], %subreg.lo16, [[DEF2]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+ ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY2]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
%res = call half @llvm.amdgcn.rcp.f16(half %val)
@@ -79,13 +85,15 @@ define amdgpu_kernel void @rsq_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_RSQ_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RSQ_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RSQ_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
- ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_RSQ_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_RSQ_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_RSQ_F16_t16_e64_]], %subreg.lo16, [[DEF2]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+ ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY2]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
%res = call half @llvm.amdgcn.rsq.f16(half %val)
@@ -102,13 +110,15 @@ define amdgpu_kernel void @sqrt_f16(ptr addrspace(1) %ptr) {
; CHECK-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec_xnull = S_LOAD_DWORDX2_IMM [[COPY]](p4), 36, 0 :: (dereferenceable invariant load (s64) from %ir.ptr.kernarg.offset, align 4, addrspace 4)
; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK-NEXT: [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_:%[0-9]+]]:vgpr_16 = GLOBAL_LOAD_SHORT_D16_SADDR_t16 [[S_LOAD_DWORDX2_IMM]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (volatile "amdgpu-noclobber" load (s16) from %ir.ptr.load, addrspace 1)
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, [[DEF]], %subreg.hi16
- ; CHECK-NEXT: [[V_SQRT_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_SQRT_F16_t16_e64 0, killed [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_SQRT_F16_t16_e64_]], %subreg.lo16, [[DEF1]], %subreg.hi16
- ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[REG_SEQUENCE1]]
- ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY1]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE killed [[GLOBAL_LOAD_SHORT_D16_SADDR_t16_]], %subreg.lo16, killed [[DEF]], %subreg.hi16
+ ; CHECK-NEXT: [[V_SQRT_F16_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_SQRT_F16_t16_e64 0, [[REG_SEQUENCE]].lo16, 0, 0, 0, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[DEF2:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_SQRT_F16_t16_e64_]], %subreg.lo16, [[DEF2]], %subreg.hi16
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY killed [[REG_SEQUENCE1]]
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
+ ; CHECK-NEXT: GLOBAL_STORE_SHORT_SADDR_t16 [[V_MOV_B32_e32_]], killed [[COPY2]], [[S_LOAD_DWORDX2_IMM]], 0, 0, implicit $exec :: (store (s16) into %ir.ptr.load, addrspace 1)
; CHECK-NEXT: S_ENDPGM 0
%val = load volatile half, ptr addrspace(1) %ptr
%res = call half @llvm.amdgcn.sqrt.f16(half %val)
diff --git a/llvm/test/CodeGen/AMDGPU/sad.ll b/llvm/test/CodeGen/AMDGPU/sad.ll
index 3b45835ca10d1..8f29305194543 100644
--- a/llvm/test/CodeGen/AMDGPU/sad.ll
+++ b/llvm/test/CodeGen/AMDGPU/sad.ll
@@ -1246,7 +1246,7 @@ define amdgpu_kernel void @v_sad_u32_i16_pat1(ptr addrspace(1) %out, i16 %a, i16
; GFX12-5-GISEL-NEXT: s_sub_co_i32 s2, s5, s2
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s2, s3
-; GFX12-5-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-5-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
%icmp0 = icmp ugt i16 %a, %b
@@ -1364,7 +1364,7 @@ define amdgpu_kernel void @v_sad_u32_i16_pat2(ptr addrspace(1) %out) {
; GFX12-5-GISEL-NEXT: v_readfirstlane_b32 s5, v2
; GFX12-5-GISEL-NEXT: s_add_co_i32 s2, s2, s5
; GFX12-5-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX12-5-GISEL-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-5-GISEL-NEXT: v_mov_b32_e32 v0, s2
; GFX12-5-GISEL-NEXT: s_wait_kmcnt 0x0
; GFX12-5-GISEL-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX12-5-GISEL-NEXT: s_endpgm
>From 854a747f73692bde507a9b7a3f0526ec2b1ffe87 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Mon, 31 Aug 2026 00:19:14 -0400
Subject: [PATCH 3/4] add more cases
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 88 +++++++++++--------
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h | 4 +-
.../AMDGPU/AMDGPUInstructionSelector.cpp | 20 ++++-
.../GlobalISel/combine-fma-add-fma-mul.ll | 12 +--
llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll | 8 +-
llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll | 5 +-
.../AMDGPU/GlobalISel/inst-select-anyext.mir | 10 ++-
.../AMDGPU/GlobalISel/inst-select-fabs.mir | 10 ++-
.../GlobalISel/inst-select-fceil.s16.mir | 30 ++++---
.../GlobalISel/inst-select-ffloor.s16.mir | 30 ++++---
.../GlobalISel/inst-select-fmul.v2s16.mir | 5 +-
.../AMDGPU/GlobalISel/inst-select-fneg.mir | 20 +++--
.../AMDGPU/GlobalISel/inst-select-freeze.mir | 15 ++--
.../AMDGPU/GlobalISel/inst-select-sitofp.mir | 10 ++-
.../AMDGPU/GlobalISel/inst-select-uitofp.mir | 10 ++-
.../GlobalISel/llvm.amdgcn.interp.inreg.ll | 12 +--
...llvm.amdgcn.raw.buffer.store.format.f16.ll | 10 ++-
.../llvm.amdgcn.raw.buffer.store.ll | 5 +-
.../llvm.amdgcn.raw.tbuffer.store.f16.ll | 84 ++++++++++--------
...vm.amdgcn.struct.buffer.load.format.f16.ll | 5 +-
...m.amdgcn.struct.buffer.store.format.f16.ll | 7 +-
llvm/test/CodeGen/AMDGPU/flat_atomics.ll | 79 +++++++++--------
llvm/test/CodeGen/AMDGPU/fma.f16.ll | 16 +++-
llvm/test/CodeGen/AMDGPU/fmaximum.ll | 20 ++---
llvm/test/CodeGen/AMDGPU/fminimum.ll | 20 ++---
llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll | 6 +-
llvm/test/CodeGen/AMDGPU/global_atomics.ll | 24 ++---
.../CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll | 10 ++-
.../AMDGPU/llvm.amdgcn.interp.inreg.ll | 12 +--
.../test/CodeGen/AMDGPU/llvm.fptrunc.round.ll | 24 +++--
llvm/test/CodeGen/AMDGPU/llvm.frexp.ll | 28 +++---
31 files changed, 352 insertions(+), 287 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index ba539628a14b4..6e5acdf608dbc 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -4781,80 +4781,97 @@ bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode *N) const {
->isMemOpHasNoClobberedMemOperand(N)));
}
-const TargetRegisterClass *AMDGPUDAGToDAGISel::getDefRegClass(SDNode *N) const {
- if (!N->isMachineOpcode())
- return nullptr;
-
- LLVM_DEBUG(dbgs() << "GetDefRegClass:\n"; N->dump(CurDAG); dbgs() << "\n");
+const TargetRegisterClass *
+AMDGPUDAGToDAGISel::inferDefRegClass(SDNode *N) const {
+ // LLVM_DEBUG(dbgs() << "GetDefRegClass:\n"; N->dump(CurDAG); dbgs() << "\n");
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
- const TargetRegisterClass *DstRC = nullptr;
+ if (!N->isMachineOpcode()) {
+ switch (N->getOpcode()) {
+ case ISD::CopyFromReg: {
+ Register Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
+ if (!Reg.isPhysical())
+ return nullptr;
+ return TRI->getPhysRegBaseClass(Reg);
+ }
+ }
+ return nullptr;
+ }
+
switch (N->getMachineOpcode()) {
case TargetOpcode::COPY:
- DstRC = getOperandRegClass(N, 0);
- break;
+ return inferDefRegClass(N->getOperand(0).getNode());
case TargetOpcode::EXTRACT_SUBREG: {
- SDNode *Src = N->getOperand(0).getNode();
- if (!Src->isMachineOpcode())
- return nullptr;
- const TargetRegisterClass *SrcRC = getDefRegClass(Src);
+ const TargetRegisterClass *SrcRC =
+ inferDefRegClass(N->getOperand(0).getNode());
if (!SrcRC)
return nullptr;
unsigned SubIdx = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
- DstRC = TRI->getSubClassWithSubReg(SrcRC, SubIdx);
- } break;
+ return TRI->getSubClassWithSubReg(SrcRC, SubIdx);
+ }
case TargetOpcode::REG_SEQUENCE: {
unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
- DstRC = TRI->getRegClass(RCID);
- } break;
+ return TRI->getRegClass(RCID);
+ }
case TargetOpcode::COPY_TO_REGCLASS: {
unsigned RCID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
- DstRC = TRI->getRegClass(RCID);
- } break;
+ return TRI->getRegClass(RCID);
+ }
default:
const MCInstrDesc &Desc = TII->get(N->getMachineOpcode());
- DstRC = TII->getRegClass(Desc, 0);
+ return TII->getRegClass(Desc, 0);
}
- return DstRC;
}
-bool AMDGPUDAGToDAGISel::PromoteSGPR16(MachineSDNode *N) {
+bool AMDGPUDAGToDAGISel::Legalize16BitRegClass(SDNode *N) {
if (!CurDAG->getTarget().getTargetTriple().isAMDGCN() ||
- !Subtarget->useRealTrue16Insts() || !N->isMachineOpcode())
+ !Subtarget->useRealTrue16Insts())
return false;
- const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
-
LLVM_DEBUG(dbgs() << "XXXXXXXXXXXXX:\n"; N->dump(CurDAG); dbgs() << "\n");
+ const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
+
+ // Check 16bit types only
EVT VT = N->getValueType(0);
if (VT != MVT::i16 && VT != MVT::f16 && VT != MVT::bf16)
return false;
- // Get Def RC
- const TargetRegisterClass *DstRC = getDefRegClass(N);
+ SmallVector<std::pair<SDNode *, unsigned>, 4> ToFix;
+
+ // Try to check def register class
+ const TargetRegisterClass *DstRC = inferDefRegClass(N);
if (!DstRC) {
- LLVM_DEBUG(dbgs() << "FALED:\n");
+ LLVM_DEBUG(dbgs() << "FAILED TO INFER:\n");
return false;
}
-
bool IsSGPR32 = TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_32RegClass);
bool IsVGPR16 = TRI->getCommonSubClass(DstRC, &AMDGPU::VGPR_16RegClass);
- LLVM_DEBUG(dbgs() << "IsSGPR32:" << IsSGPR32 << "\n");
- LLVM_DEBUG(dbgs() << "IsVGPR16:" << IsVGPR16 << "\n");
-
- SmallVector<std::pair<SDNode *, unsigned>, 4> ToFix;
+ LLVM_DEBUG(dbgs() << "IsSGPR32:" << IsSGPR32 << ", IsVGPR16:" << IsVGPR16
+ << "\n");
+ // Scan users
for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); UI != UE;
++UI) {
SDNode *User = UI->getUser();
unsigned OperandNo = UI->getOperandNo();
- LLVM_DEBUG(dbgs() << "User:" << OperandNo << "\n"; User->dump(CurDAG);
+ LLVM_DEBUG(dbgs() << "User:" << OperandNo << "---"; User->dump(CurDAG);
dbgs() << "\n");
const TargetRegisterClass *UserRC = getOperandRegClass(User, OperandNo);
+ // SGPR32 used by reg_sequence with 16bit subreg
+ if (IsSGPR32 && User->getOpcode() == TargetOpcode::REG_SEQUENCE) {
+ unsigned RCID =
+ cast<ConstantSDNode>(User->getOperand(OperandNo + 1))->getZExtValue();
+ if (TRI->getCommonSubClass(TRI->getRegClass(RCID),
+ &AMDGPU::VGPR_16RegClass)) {
+ LLVM_DEBUG(dbgs() << "Found To Fix OperandNo:" << "\n");
+ ToFix.emplace_back(User, OperandNo);
+ }
+ }
+
// Cross bank 16bit Def-Use that requires a fix
if ((IsSGPR32 && TRI->getCommonSubClass(UserRC, &AMDGPU::VGPR_16RegClass) &&
!TRI->getCommonSubClass(UserRC, &AMDGPU::SGPR_32RegClass)) ||
@@ -4935,12 +4952,13 @@ void AMDGPUDAGToDAGISel::PostprocessISelDAG() {
SelectionDAG::allnodes_iterator Position = CurDAG->allnodes_begin();
while (Position != CurDAG->allnodes_end()) {
SDNode *Node = &*Position++;
+
+ IsModified = Legalize16BitRegClass(Node);
+
MachineSDNode *MachineNode = dyn_cast<MachineSDNode>(Node);
if (!MachineNode)
continue;
- IsModified = PromoteSGPR16(MachineNode);
-
SDNode *ResNode = Lowering.PostISelFolding(MachineNode, *CurDAG);
if (ResNode != Node) {
if (ResNode)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
index 99dfe399dd406..ecc6d7f3ec5d8 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.h
@@ -312,8 +312,8 @@ class AMDGPUDAGToDAGISel : public SelectionDAGISel {
void SelectINTRINSIC_VOID(SDNode *N);
void SelectWAVE_ADDRESS(SDNode *N);
void SelectSTACKRESTORE(SDNode *N);
- bool PromoteSGPR16(MachineSDNode *N);
- const TargetRegisterClass *getDefRegClass(SDNode *N) const;
+ bool Legalize16BitRegClass(SDNode *N);
+ const TargetRegisterClass *inferDefRegClass(SDNode *N) const;
protected:
// Include the pieces autogenerated from the target description.
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
index bb8d9a825d8ba..689f27d47719e 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUInstructionSelector.cpp
@@ -2749,15 +2749,29 @@ bool AMDGPUInstructionSelector::selectG_SZA_EXT(MachineInstr &I) const {
// FIXME: This should probably be illegal and split earlier.
if (I.getOpcode() == AMDGPU::G_ANYEXT) {
- if (DstSize <= 32)
- return selectCOPY(I);
-
const TargetRegisterClass *SrcRC =
TRI.getRegClassForTypeOnBank(SrcTy, *SrcBank);
const RegisterBank *DstBank = RBI.getRegBank(DstReg, *MRI, TRI);
const TargetRegisterClass *DstRC =
TRI.getRegClassForSizeOnBank(DstSize, *DstBank);
+ if (DstSize <= 32) {
+ if (STI.useRealTrue16Insts() && DstSize == 32 &&
+ SrcBank->getID() == AMDGPU::VGPRRegBankID) {
+ Register UndefReg = MRI->createVirtualRegister(SrcRC);
+ BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
+ BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
+ .addReg(SrcReg)
+ .addImm(AMDGPU::lo16)
+ .addReg(UndefReg)
+ .addImm(AMDGPU::hi16);
+ I.eraseFromParent();
+ return RBI.constrainGenericRegister(DstReg, *DstRC, *MRI) &&
+ RBI.constrainGenericRegister(SrcReg, *SrcRC, *MRI);
+ } else
+ return selectCOPY(I);
+ }
+
Register UndefReg = MRI->createVirtualRegister(SrcRC);
BuildMI(MBB, I, DL, TII.get(AMDGPU::IMPLICIT_DEF), UndefReg);
BuildMI(MBB, I, DL, TII.get(AMDGPU::REG_SEQUENCE), DstReg)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
index ce4de6e628573..8d318b2ad59c5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-add-fma-mul.ll
@@ -159,10 +159,10 @@ define half @test_half_add_mul(half %a, half %b, half %c, half %d, half %e) {
; GFX11-CONTRACT-TRUE16-LABEL: test_half_add_mul:
; GFX11-CONTRACT-TRUE16: ; %bb.0: ; %.entry
; GFX11-CONTRACT-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-CONTRACT-TRUE16-NEXT: v_fma_f16 v2.l, v2.l, v3.l, v4.l
+; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v2.l, v3.l
; GFX11-CONTRACT-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
-; GFX11-CONTRACT-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v0.l, v1.l
+; GFX11-CONTRACT-TRUE16-NEXT: v_mov_b32_e32 v0, v4
; GFX11-CONTRACT-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-CONTRACT-FAKE16-LABEL: test_half_add_mul:
@@ -236,10 +236,10 @@ define half @test_half_add_mul_rhs(half %a, half %b, half %c, half %d, half %e)
; GFX11-CONTRACT-TRUE16-LABEL: test_half_add_mul_rhs:
; GFX11-CONTRACT-TRUE16: ; %bb.0: ; %.entry
; GFX11-CONTRACT-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-CONTRACT-TRUE16-NEXT: v_fma_f16 v2.l, v2.l, v3.l, v4.l
+; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v2.l, v3.l
; GFX11-CONTRACT-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
-; GFX11-CONTRACT-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-CONTRACT-TRUE16-NEXT: v_fmac_f16_e32 v4.l, v0.l, v1.l
+; GFX11-CONTRACT-TRUE16-NEXT: v_mov_b32_e32 v0, v4
; GFX11-CONTRACT-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-CONTRACT-FAKE16-LABEL: test_half_add_mul_rhs:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
index e6a93c653cedf..aa9df2bf0c7f2 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fma.ll
@@ -152,7 +152,8 @@ define half @v_fma_f16(half %x, half %y, half %z) {
; GFX11-TRUE16-LABEL: v_fma_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, v2.l
+; GFX11-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: v_fma_f16:
@@ -168,7 +169,8 @@ define half @v_fma_f16(half %x, half %y, half %z) {
; GFX12-NEXT: s_wait_samplecnt 0x0
; GFX12-NEXT: s_wait_bvhcnt 0x0
; GFX12-NEXT: s_wait_kmcnt 0x0
-; GFX12-NEXT: v_fma_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX12-NEXT: v_mov_b32_e32 v0, v2
; GFX12-NEXT: s_setpc_b64 s[30:31]
%fma = call half @llvm.fma.f16(half %x, half %y, half %z)
ret half %fma
@@ -1527,7 +1529,7 @@ define amdgpu_ps half @fma_s16_uniform(half inreg %a, half inreg %b, half inreg
; GFX11-TRUE16-LABEL: fma_s16_uniform:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX11-TRUE16-NEXT: v_fma_f16 v0.l, s1, s0, v0.l
+; GFX11-TRUE16-NEXT: v_fmac_f16_e64 v0.l, s0, s1
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
; GFX11-FAKE16-LABEL: fma_s16_uniform:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
index 72e17d30b2734..0b8ac09bd7721 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fshr.ll
@@ -3864,10 +3864,9 @@ define amdgpu_ps half @v_fshr_i16_vss(i16 %lhs, i16 inreg %rhs, i16 inreg %amt)
; GFX11-TRUE16-NEXT: s_and_not1_b32 s2, 15, s1
; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 15
; GFX11-TRUE16-NEXT: s_and_b32 s0, 0xffff, s0
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, s2, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: s_lshr_b32 s0, s0, s1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, s2, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, s0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
index 6dca3753d5a0b..95ab4c72f11d0 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-anyext.mir
@@ -291,8 +291,9 @@ body: |
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: anyext_vgpr_s1_to_vgpr_s32
; GFX11-FAKE16: liveins: $vgpr0
@@ -351,8 +352,9 @@ body: |
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: anyext_vgpr_s16_to_vgpr_s32
; GFX11-FAKE16: liveins: $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
index 52d7b77708a2b..36f65f500846f 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fabs.mir
@@ -309,8 +309,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FABS:%[0-9]+]]:vgpr_16(s16) = G_FABS [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FABS]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fabs_s16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -379,8 +380,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FABS:%[0-9]+]]:vgpr_16(s16) = G_FABS [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FABS]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FABS]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fabs_s16_vs
; GFX11-FAKE16: liveins: $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
index 3f6363ebda21d..5e44404637ff5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fceil.s16.mir
@@ -73,8 +73,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FCEIL:%[0-9]+]]:vgpr_16(s16) = G_FCEIL [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FCEIL]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FCEIL]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fceil_s16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -91,8 +92,9 @@ body: |
; GFX12-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX12-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX12-TRUE16-NEXT: [[FCEIL:%[0-9]+]]:vgpr_16(s16) = G_FCEIL [[TRUNC]]
- ; GFX12-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FCEIL]](s16)
- ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX12-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FCEIL]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX12-FAKE16-LABEL: name: fceil_s16_vv
; GFX12-FAKE16: liveins: $vgpr0
@@ -134,8 +136,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FCEIL:%[0-9]+]]:vgpr_16(s16) = G_FCEIL [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FCEIL]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FCEIL]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fceil_s16_vs
; GFX11-FAKE16: liveins: $sgpr0
@@ -152,8 +155,9 @@ body: |
; GFX12-TRUE16-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX12-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX12-TRUE16-NEXT: [[FCEIL:%[0-9]+]]:vgpr_16(s16) = G_FCEIL [[TRUNC]]
- ; GFX12-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FCEIL]](s16)
- ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX12-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FCEIL]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX12-FAKE16-LABEL: name: fceil_s16_vs
; GFX12-FAKE16: liveins: $sgpr0
@@ -197,8 +201,9 @@ body: |
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
; GFX11-TRUE16-NEXT: [[FCEIL:%[0-9]+]]:vgpr_16(s16) = G_FCEIL [[FNEG]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FCEIL]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FCEIL]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fceil_fneg_s16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -217,8 +222,9 @@ body: |
; GFX12-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX12-TRUE16-NEXT: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
; GFX12-TRUE16-NEXT: [[FCEIL:%[0-9]+]]:vgpr_16(s16) = G_FCEIL [[FNEG]]
- ; GFX12-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FCEIL]](s16)
- ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX12-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FCEIL]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX12-FAKE16-LABEL: name: fceil_fneg_s16_vv
; GFX12-FAKE16: liveins: $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
index 5f02793d6f434..c989a24409ceb 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-ffloor.s16.mir
@@ -73,8 +73,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FFLOOR:%[0-9]+]]:vgpr_16(s16) = G_FFLOOR [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FFLOOR]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FFLOOR]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: ffloor_s16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -91,8 +92,9 @@ body: |
; GFX12-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX12-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX12-TRUE16-NEXT: [[FFLOOR:%[0-9]+]]:vgpr_16(s16) = G_FFLOOR [[TRUNC]]
- ; GFX12-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FFLOOR]](s16)
- ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX12-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FFLOOR]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX12-FAKE16-LABEL: name: ffloor_s16_vv
; GFX12-FAKE16: liveins: $vgpr0
@@ -134,8 +136,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FFLOOR:%[0-9]+]]:vgpr_16(s16) = G_FFLOOR [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FFLOOR]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FFLOOR]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: ffloor_s16_vs
; GFX11-FAKE16: liveins: $sgpr0
@@ -152,8 +155,9 @@ body: |
; GFX12-TRUE16-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX12-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX12-TRUE16-NEXT: [[FFLOOR:%[0-9]+]]:vgpr_16(s16) = G_FFLOOR [[TRUNC]]
- ; GFX12-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FFLOOR]](s16)
- ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX12-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FFLOOR]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX12-FAKE16-LABEL: name: ffloor_s16_vs
; GFX12-FAKE16: liveins: $sgpr0
@@ -197,8 +201,9 @@ body: |
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
; GFX11-TRUE16-NEXT: [[FFLOOR:%[0-9]+]]:vgpr_16(s16) = G_FFLOOR [[FNEG]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FFLOOR]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FFLOOR]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: ffloor_fneg_s16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -217,8 +222,9 @@ body: |
; GFX12-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX12-TRUE16-NEXT: [[FNEG:%[0-9]+]]:vgpr(s16) = G_FNEG [[TRUNC]]
; GFX12-TRUE16-NEXT: [[FFLOOR:%[0-9]+]]:vgpr_16(s16) = G_FFLOOR [[FNEG]]
- ; GFX12-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FFLOOR]](s16)
- ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX12-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FFLOOR]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX12-FAKE16-LABEL: name: ffloor_fneg_s16_vv
; GFX12-FAKE16: liveins: $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
index 2f87867414cb1..c47cd68239dd5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fmul.v2s16.mir
@@ -80,8 +80,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX11-TRUE16-NEXT: [[COPY3:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
; GFX11-TRUE16-NEXT: [[V_XOR_B16_t16_e64_:%[0-9]+]]:vgpr_16 = V_XOR_B16_t16_e64 0, 32768, 0, [[COPY3]], 0, implicit $exec
- ; GFX11-TRUE16-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[V_XOR_B16_t16_e64_]]
- ; GFX11-TRUE16-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[COPY4]], implicit $exec
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_XOR_B16_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: [[V_AND_B32_e32_:%[0-9]+]]:vgpr_32 = V_AND_B32_e32 65535, [[REG_SEQUENCE]], implicit $exec
; GFX11-TRUE16-NEXT: [[V_LSHL_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHL_OR_B32_e64 [[COPY2]], 16, [[V_AND_B32_e32_]], implicit $exec
; GFX11-TRUE16-NEXT: [[V_PK_MUL_F16_:%[0-9]+]]:vgpr_32 = nofpexcept V_PK_MUL_F16 8, [[V_LSHL_OR_B32_e64_]], 8, [[COPY]], 0, 0, 0, 0, 0, implicit $mode, implicit $exec
; GFX11-TRUE16-NEXT: S_ENDPGM 0, implicit [[V_PK_MUL_F16_]]
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
index 07c8bf6348879..69ab52febb139 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fneg.mir
@@ -261,8 +261,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FNEG:%[0-9]+]]:vgpr_16(s16) = G_FNEG [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FNEG]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fneg_s16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -331,8 +332,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FNEG:%[0-9]+]]:vgpr_16(s16) = G_FNEG [[TRUNC]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32(s32) = COPY [[FNEG]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32(s32) = REG_SEQUENCE [[FNEG]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fneg_s16_vs
; GFX11-FAKE16: liveins: $sgpr0
@@ -942,8 +944,9 @@ body: |
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FABS:%[0-9]+]]:vgpr(s16) = G_FABS [[TRUNC]]
; GFX11-TRUE16-NEXT: [[FNEG:%[0-9]+]]:vgpr_16(s16) = G_FNEG [[FABS]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_32(s32) = REG_SEQUENCE [[FNEG]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fneg_fabs_s16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -1019,8 +1022,9 @@ body: |
; GFX11-TRUE16-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)
; GFX11-TRUE16-NEXT: [[FNEG:%[0-9]+]]:sgpr(s16) = G_FNEG [[TRUNC]]
; GFX11-TRUE16-NEXT: [[FNEG1:%[0-9]+]]:vgpr_16(s16) = G_FNEG [[FNEG]]
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[FNEG1]](s16)
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]](s32)
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_32(s32) = REG_SEQUENCE [[FNEG1]](s16), %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]](s32)
;
; GFX11-FAKE16-LABEL: name: fneg_fabs_s16_vs
; GFX11-FAKE16: liveins: $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
index 87ebb9fe98cd6..f1a60d6a37e96 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-freeze.mir
@@ -31,8 +31,9 @@ body: |
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: test_freeze_s1_vgpr_to_vgpr
; GFX11-FAKE16: liveins: $vgpr0
@@ -73,8 +74,9 @@ body: |
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $agpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $agpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: test_freeze_s1_vgpr_to_agpr
; GFX11-FAKE16: liveins: $vgpr0
@@ -149,8 +151,9 @@ body: |
; GFX11-TRUE16-NEXT: {{ $}}
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_16 = COPY [[COPY]].lo16
- ; GFX11-TRUE16-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY2]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: test_freeze_s16_vgpr_to_vgpr
; GFX11-FAKE16: liveins: $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
index db14200f7908c..108bb6d892bf5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-sitofp.mir
@@ -92,8 +92,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[V_CVT_F32_I32_e64_]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_CVT_F16_F32_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: sitofp_i32_to_f16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -141,8 +142,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX11-TRUE16-NEXT: [[V_CVT_F32_I32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_I32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[V_CVT_F32_I32_e64_]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_CVT_F16_F32_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: sitofp_i32_to_f16_vs
; GFX11-FAKE16: liveins: $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
index d957ab39d83e4..96a9b5b7b8e94 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-uitofp.mir
@@ -106,8 +106,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX11-TRUE16-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[V_CVT_F32_U32_e64_]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_CVT_F16_F32_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: uitofp_i32_to_f16_vv
; GFX11-FAKE16: liveins: $vgpr0
@@ -155,8 +156,9 @@ body: |
; GFX11-TRUE16-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GFX11-TRUE16-NEXT: [[V_CVT_F32_U32_e64_:%[0-9]+]]:vgpr_32 = V_CVT_F32_U32_e64 [[COPY]], 0, 0, implicit $mode, implicit $exec
; GFX11-TRUE16-NEXT: [[V_CVT_F16_F32_t16_e64_:%[0-9]+]]:vgpr_16 = nofpexcept V_CVT_F16_F32_t16_e64 0, [[V_CVT_F32_U32_e64_]], 0, 0, 0, implicit $mode, implicit $exec
- ; GFX11-TRUE16-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_CVT_F16_F32_t16_e64_]]
- ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[COPY1]]
+ ; GFX11-TRUE16-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX11-TRUE16-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[V_CVT_F16_F32_t16_e64_]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX11-TRUE16-NEXT: $vgpr0 = COPY [[REG_SEQUENCE]]
;
; GFX11-FAKE16-LABEL: name: uitofp_i32_to_f16_vs
; GFX11-FAKE16: liveins: $sgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
index 225ae801fc12b..90e64ffca7703 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.interp.inreg.ll
@@ -383,15 +383,15 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
;
; GFX12-TRUE16-LABEL: v_interp_f16_imm_params:
; GFX12-TRUE16: ; %bb.0: ; %main_body
+; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0
-; GFX12-TRUE16-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, 0
-; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, s0
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v3, 0
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v1.l, v0.l, v1, v2 wait_exp:7
-; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v0, v0.l, v3, v0.l wait_exp:7
+; GFX12-TRUE16-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
+; GFX12-TRUE16-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v2, v3 wait_exp:7
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX12-TRUE16-NEXT: v_readfirstlane_b32 s1, v0
; GFX12-TRUE16-NEXT: s_cvt_f16_f32 s0, s0
; GFX12-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
index e355992416d1f..f667905e441e5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll
@@ -47,8 +47,9 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_16 = COPY [[COPY4]].lo16
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY5]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void
@@ -95,8 +96,9 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409
; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_16 = COPY [[COPY4]].lo16
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY5]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
index a9ada36d4b2ff..89e22eeed547c 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll
@@ -971,8 +971,9 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr
; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_16 = COPY [[COPY4]].lo16
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]]
- ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY5]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
index 4225ab16bac30..8e818e7085633 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll
@@ -47,8 +47,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0)
ret void
@@ -335,7 +336,8 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.2:
@@ -345,20 +347,20 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
- ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
- ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
- ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec
+ ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub0_sub1
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub2_sub3
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
; GFX12-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 killed [[S_AND_B32_]], implicit-def $exec, implicit-def $scc, implicit $exec
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE2]], [[COPY7]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -489,7 +491,8 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.2:
@@ -499,13 +502,13 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
- ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
- ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
- ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec
+ ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub0_sub1
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub2_sub3
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY7]], implicit $exec
@@ -515,7 +518,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__vgpr_soff
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE2]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -648,8 +651,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr5
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY6]]
; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo
; GFX12-NEXT: {{ $}}
; GFX12-NEXT: bb.2:
@@ -659,13 +663,13 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
; GFX12-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec
; GFX12-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec
; GFX12-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec
- ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
- ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
- ; GFX12-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
- ; GFX12-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1
- ; GFX12-NEXT: [[COPY13:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3
- ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec
- ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY13]], [[COPY11]], implicit $exec
+ ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3
+ ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1
+ ; GFX12-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3
+ ; GFX12-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub0_sub1
+ ; GFX12-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE2]].sub2_sub3
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec
+ ; GFX12-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec
; GFX12-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc
; GFX12-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY7]], implicit $exec
; GFX12-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY7]], implicit $exec
@@ -675,7 +679,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff
; GFX12-NEXT: bb.3:
; GFX12-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)
; GFX12-NEXT: {{ $}}
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY9]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE2]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def $scc
; GFX12-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec
; GFX12-NEXT: {{ $}}
@@ -734,8 +738,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1)
ret void
@@ -785,8 +790,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2)
ret void
@@ -836,8 +842,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3)
ret void
@@ -887,8 +894,9 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff
; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY8]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
index 1588f254b801d..7286fceff992a 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll
@@ -512,8 +512,9 @@ define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vg
; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1
; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8)
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_16 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]].lo16
- ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY7]]
- ; GFX12-NEXT: $vgpr0 = COPY [[COPY8]]
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY7]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: $vgpr0 = COPY [[REG_SEQUENCE2]]
; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0
%val = call i16 @llvm.amdgcn.struct.buffer.load.format.i16(<4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
%fval = bitcast i16 %val to half
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
index 8473cbb2ddceb..09f078157600e 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll
@@ -52,9 +52,10 @@ define amdgpu_ps void @struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr
; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr1
; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr2
; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6
- ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]]
- ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
- ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact [[COPY9]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
+ ; GFX12-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY1]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1
+ ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8)
; GFX12-NEXT: S_ENDPGM 0
call void @llvm.amdgcn.struct.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 0)
ret void
diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics.ll
index 232a170b7b2b3..6932e65c0f823 100644
--- a/llvm/test/CodeGen/AMDGPU/flat_atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/flat_atomics.ll
@@ -8193,12 +8193,12 @@ define amdgpu_kernel void @atomic_store_i8_offset(i8 %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_i8_offset:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b8 v[1:2], v0 offset:16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b8 v[0:1], v2 offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_i8_offset:
@@ -8254,12 +8254,12 @@ define amdgpu_kernel void @atomic_store_i8(i8 %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_i8:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b8 v[1:2], v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b8 v[0:1], v2
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_i8:
@@ -8329,9 +8329,10 @@ define amdgpu_kernel void @atomic_store_i8_addr64_offset(i8 %in, ptr %out, i64 %
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_add_u32 s0, s0, s2
; GFX11-TRUE16-NEXT: s_addc_u32 s1, s1, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s4
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: flat_store_b8 v[1:2], v0 offset:16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b8 v[0:1], v2 offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_i8_addr64_offset:
@@ -8655,12 +8656,12 @@ define amdgpu_kernel void @atomic_store_i16_offset(i16 %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_i16_offset:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0 offset:16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b16 v[0:1], v2 offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_i16_offset:
@@ -8716,12 +8717,12 @@ define amdgpu_kernel void @atomic_store_i16(i16 %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_i16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b16 v[0:1], v2
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_i16:
@@ -8793,12 +8794,12 @@ define amdgpu_kernel void @atomic_store_i16_addr64_offset(i16 %in, ptr %out, i64
; GFX11-TRUE16-NEXT: s_load_b32 s4, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_lshl_b64 s[2:3], s[2:3], 1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_u32 s0, s0, s2
; GFX11-TRUE16-NEXT: s_addc_u32 s1, s1, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
-; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0 offset:16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b16 v[0:1], v2 offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_i16_addr64_offset:
@@ -8863,12 +8864,12 @@ define amdgpu_kernel void @atomic_store_f16_offset(half %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_f16_offset:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0 offset:16
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b16 v[0:1], v2 offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_f16_offset:
@@ -8924,12 +8925,12 @@ define amdgpu_kernel void @atomic_store_f16(half %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_f16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b16 v[0:1], v2
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_f16:
@@ -8984,12 +8985,12 @@ define amdgpu_kernel void @atomic_store_bf16_offset(bfloat %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_bf16_offset:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b16 v[0:1], v2
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_bf16_offset:
@@ -9044,12 +9045,12 @@ define amdgpu_kernel void @atomic_store_bf16(bfloat %in, ptr %out) {
; GFX11-TRUE16-LABEL: atomic_store_bf16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
+; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: flat_store_b16 v[1:2], v0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v1, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-TRUE16-NEXT: flat_store_b16 v[0:1], v2
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: atomic_store_bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/fma.f16.ll b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
index aa6f54af57d16..9f9c70235a9a0 100644
--- a/llvm/test/CodeGen/AMDGPU/fma.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fma.f16.ll
@@ -43,7 +43,9 @@ define half @test_fma(half %x, half %y, half %z) {
; GFX11-GISEL-TRUE16-LABEL: test_fma:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_fma:
@@ -79,7 +81,9 @@ define half @test_fma(half %x, half %y, half %z) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_fma_f16 v0.l, v0.l, v1.l, v2.l
+; GFX12-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, v0.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_fma:
@@ -302,7 +306,9 @@ define half @test_fmamk(half %x, half %y, half %z) {
; GFX11-GISEL-TRUE16-LABEL: test_fmamk:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0x4200, v2.l
+; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, 0x4200, v0.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_fmamk:
@@ -338,7 +344,9 @@ define half @test_fmamk(half %x, half %y, half %z) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0x4200, v2.l
+; GFX12-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v2.l, 0x4200, v0.l
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_fmamk:
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum.ll b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
index 6e2c47ac62c24..090d58c9666db 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum.ll
@@ -724,12 +724,10 @@ define amdgpu_ps <3 x half> @test_fmaximum_v3f16_ss(<3 x half> inreg %a, <3 x ha
;
; GFX1170-GISEL-TRUE16-LABEL: test_fmaximum_v3f16_ss:
; GFX1170-GISEL-TRUE16: ; %bb.0:
-; GFX1170-GISEL-TRUE16-NEXT: v_maximum_f16 v0.l, s1, s3
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_maximum_f16 v1.l, s1, s3
; GFX1170-GISEL-TRUE16-NEXT: v_pk_maximum_f16 v0, s0, s2
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v1
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, s0
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
@@ -1520,18 +1518,18 @@ define amdgpu_kernel void @fmaximum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_clause 0x1
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v1, v2, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-TRUE16-NEXT: s_maximum_f16 s2, s2, s3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
; GFX12-GISEL-FAKE16-LABEL: fmaximum_f16_move_to_valu:
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum.ll b/llvm/test/CodeGen/AMDGPU/fminimum.ll
index 2156fc6f2397c..7933859ff08f6 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum.ll
@@ -724,12 +724,10 @@ define amdgpu_ps <3 x half> @test_fminimum_v3f16_ss(<3 x half> inreg %a, <3 x ha
;
; GFX1170-GISEL-TRUE16-LABEL: test_fminimum_v3f16_ss:
; GFX1170-GISEL-TRUE16: ; %bb.0:
-; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v0.l, s1, s3
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1170-GISEL-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l
+; GFX1170-GISEL-TRUE16-NEXT: v_minimum_f16 v1.l, s1, s3
; GFX1170-GISEL-TRUE16-NEXT: v_pk_minimum_f16 v0, s0, s2
+; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s0, v1
-; GFX1170-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1170-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, s0
; GFX1170-GISEL-TRUE16-NEXT: ; return to shader part epilog
;
@@ -1520,18 +1518,18 @@ define amdgpu_kernel void @fminimum_f16_move_to_valu(ptr addrspace(1) %out, ptr
; GFX12-GISEL-TRUE16-NEXT: s_clause 0x1
; GFX12-GISEL-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX12-GISEL-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v2, s[2:3] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v1, v2, s[4:5] scope:SCOPE_SYS
+; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v2, v0, s[4:5] scope:SCOPE_SYS
; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v0
-; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s2, v1
+; GFX12-GISEL-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
; GFX12-GISEL-TRUE16-NEXT: s_minimum_f16 s2, s2, s3
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, s2
-; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v1, s2
+; GFX12-GISEL-TRUE16-NEXT: global_store_b16 v0, v1, s[0:1]
; GFX12-GISEL-TRUE16-NEXT: s_endpgm
;
; GFX12-GISEL-FAKE16-LABEL: fminimum_f16_move_to_valu:
diff --git a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
index 79e76039d6777..693e0aa0f52a4 100644
--- a/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmul-to-ldexp.ll
@@ -3827,7 +3827,8 @@ define half @v_fma_mul_add_32_f16(half %x, half %y) {
; GFX11-GISEL-TRUE16-LABEL: v_fma_mul_add_32_f16:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0x5000, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v1.l, 0x5000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_fma_mul_add_32_f16:
@@ -3925,7 +3926,8 @@ define half @v_fma_mul_add_neg32_f16(half %x, half %y) {
; GFX11-GISEL-TRUE16-LABEL: v_fma_mul_add_neg32_f16:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_fmamk_f16 v0.l, v0.l, 0xd000, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_fmac_f16_e32 v1.l, 0xd000, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v1
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: v_fma_mul_add_neg32_f16:
diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics.ll b/llvm/test/CodeGen/AMDGPU/global_atomics.ll
index fdc8eff962d24..9aa3800ff64a5 100644
--- a/llvm/test/CodeGen/AMDGPU/global_atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/global_atomics.ll
@@ -7594,9 +7594,8 @@ define amdgpu_kernel void @atomic_store_i8_offset(i8 %in, ptr addrspace(1) %out)
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1] offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -7653,9 +7652,8 @@ define amdgpu_kernel void @atomic_store_i8(i8 %in, ptr addrspace(1) %out) {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b8 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -7865,9 +7863,8 @@ define amdgpu_kernel void @atomic_store_i16_offset(i16 %in, ptr addrspace(1) %ou
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -7924,9 +7921,8 @@ define amdgpu_kernel void @atomic_store_i16(i16 %in, ptr addrspace(1) %out) {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -7984,9 +7980,8 @@ define amdgpu_kernel void @atomic_store_f16_offset(half %in, ptr addrspace(1) %o
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -8043,9 +8038,8 @@ define amdgpu_kernel void @atomic_store_f16(half %in, ptr addrspace(1) %out) {
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -8103,9 +8097,8 @@ define amdgpu_kernel void @atomic_store_bf16_offset(bfloat %in, ptr addrspace(1)
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1] offset:16
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -8161,9 +8154,8 @@ define amdgpu_kernel void @atomic_store_bf16(bfloat %in, ptr addrspace(1) %out)
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b32 s2, s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x2c
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
diff --git a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
index e99181f425be9..dcc1861a24479 100644
--- a/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
+++ b/llvm/test/CodeGen/AMDGPU/isel-amdgpu-cs-chain-cc.ll
@@ -530,8 +530,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_cc_half(half inreg %a, half %b) {
; GISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY]]
- ; GISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
- ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY3]]
+ ; GISEL-GFX11-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[REG_SEQUENCE]]
; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc
; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4)
; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1
@@ -600,8 +601,9 @@ define amdgpu_cs_chain void @amdgpu_cs_chain_cc_bfloat(bfloat inreg %a, bfloat %
; GISEL-GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[COPY1]].lo16
; GISEL-GFX11-NEXT: ADJCALLSTACKUP 0, 0, implicit-def $scc, implicit-def $sgpr32, implicit $sgpr32
; GISEL-GFX11-NEXT: $vgpr0 = COPY [[COPY]]
- ; GISEL-GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY2]]
- ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[COPY3]]
+ ; GISEL-GFX11-NEXT: [[DEF:%[0-9]+]]:vgpr_16 = IMPLICIT_DEF
+ ; GISEL-GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[COPY2]], %subreg.lo16, [[DEF]], %subreg.hi16
+ ; GISEL-GFX11-NEXT: $vgpr1 = COPY [[REG_SEQUENCE]]
; GISEL-GFX11-NEXT: [[SI_PC_ADD_REL_OFFSET:%[0-9]+]]:sreg_64 = SI_PC_ADD_REL_OFFSET target-flags(amdgpu-gotprel32-lo) @use, target-flags(amdgpu-gotprel32-hi) @use, implicit-def $scc
; GISEL-GFX11-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[SI_PC_ADD_REL_OFFSET]], 0, 0 :: (dereferenceable invariant load (p0) from got, addrspace 4)
; GISEL-GFX11-NEXT: $sgpr30_sgpr31 = noconvergent SI_CALL [[S_LOAD_DWORDX2_IMM]], @use, csr_amdgpu_si_gfx, implicit $vgpr0, implicit $vgpr1
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
index 8efa1133bc8c1..6b930f8cbb537 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.interp.inreg.ll
@@ -413,15 +413,15 @@ define amdgpu_ps half @v_interp_f16_imm_params(float inreg %i, float inreg %j) #
;
; GFX12-TRUE16-GISEL-LABEL: v_interp_f16_imm_params:
; GFX12-TRUE16-GISEL: ; %bb.0: ; %main_body
+; GFX12-TRUE16-GISEL-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1
; GFX12-TRUE16-GISEL-NEXT: v_mov_b16_e32 v0.l, 0
-; GFX12-TRUE16-GISEL-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, 0
-; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v3, s0
+; GFX12-TRUE16-GISEL-NEXT: v_mov_b32_e32 v3, 0
; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-GISEL-NEXT: v_interp_p2_f16_f32 v1.l, v0.l, v1, v2 wait_exp:7
-; GFX12-TRUE16-GISEL-NEXT: v_interp_p10_f16_f32 v0, v0.l, v3, v0.l wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p10_f16_f32 v1, v0.l, v1, v0.l wait_exp:7
+; GFX12-TRUE16-GISEL-NEXT: v_interp_p2_f16_f32 v0.l, v0.l, v2, v3 wait_exp:7
; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s1, v1
-; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s0, v1
+; GFX12-TRUE16-GISEL-NEXT: v_readfirstlane_b32 s1, v0
; GFX12-TRUE16-GISEL-NEXT: s_cvt_f16_f32 s0, s0
; GFX12-TRUE16-GISEL-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-TRUE16-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_2)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
index 2fffc987b04f6..9445fe072fce0 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll
@@ -1179,22 +1179,20 @@ define amdgpu_gs void @s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v2.l, s0
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v3.l, s1
-; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v4.l, s3
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
-; GFX11-GISEL-NEXT: v_mov_b16_e32 v5.l, v2.l
-; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v2.l, s2
-; GFX11-GISEL-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v4.l, s2
+; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v5.l, s3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v2
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v3
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s4, v4
+; GFX11-GISEL-NEXT: v_readfirstlane_b32 s5, v5
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2
-; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v3.l, s3
-; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v4
-; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v5
-; GFX11-GISEL-NEXT: v_mov_b16_e32 v5.l, v2.l
; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v2.l, s2
-; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v6
-; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3)
-; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-GISEL-NEXT: v_cvt_f16_f32_e64 v3.l, s3
; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s0, s0, s1
-; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s1, s2, s3
+; GFX11-GISEL-NEXT: s_pack_ll_b32_b16 s1, s4, s5
+; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s2, v2
; GFX11-GISEL-NEXT: v_readfirstlane_b32 s3, v3
; GFX11-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
index 6ab411182a651..f073b3913cb60 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.frexp.ll
@@ -107,13 +107,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i32:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX11-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-GISEL-FAKE16-LABEL: test_frexp_f16_i32:
@@ -132,13 +129,10 @@ define { half, i32 } @test_frexp_f16_i32(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v0.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
-; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v0, 0, 16
+; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v0.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
+; GFX12-GISEL-TRUE16-NEXT: v_bfe_i32 v1, v1, 0, 16
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX12-GISEL-FAKE16-LABEL: test_frexp_f16_i32:
@@ -1049,10 +1043,9 @@ define { half, i16 } @test_frexp_f16_i16(half %a) {
; GFX11-GISEL-TRUE16-LABEL: test_frexp_f16_i16:
; GFX11-GISEL-TRUE16: ; %bb.0:
; GFX11-GISEL-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.l
-; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
+; GFX11-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v2.l, v0.l
; GFX11-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX11-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX11-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
@@ -1072,10 +1065,9 @@ define { half, i16 } @test_frexp_f16_i16(half %a) {
; GFX12-GISEL-TRUE16-NEXT: s_wait_samplecnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_bvhcnt 0x0
; GFX12-GISEL-TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v1.l, v0.l
-; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX12-GISEL-TRUE16-NEXT: v_mov_b16_e32 v2.l, v1.l
+; GFX12-GISEL-TRUE16-NEXT: v_frexp_mant_f16_e32 v2.l, v0.l
; GFX12-GISEL-TRUE16-NEXT: v_frexp_exp_i16_f16_e32 v1.l, v0.l
+; GFX12-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX12-GISEL-TRUE16-NEXT: v_mov_b32_e32 v0, v2
; GFX12-GISEL-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
>From 521400f5468e47be1193db1194908969dba30e98 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 1 Sep 2026 10:48:55 -0400
Subject: [PATCH 4/4] update patch
---
llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp | 92 ++++++++-------
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 +
llvm/test/CodeGen/AMDGPU/bf16-math.ll | 4 +-
llvm/test/CodeGen/AMDGPU/bf16.ll | 109 ++++++++----------
llvm/test/CodeGen/AMDGPU/br_cc.f16.ll | 44 +++----
llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll | 48 ++++----
llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll | 35 +++---
llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll | 1 +
llvm/test/CodeGen/AMDGPU/fmaximum3.ll | 4 +-
llvm/test/CodeGen/AMDGPU/fminimum3.ll | 4 +-
.../CodeGen/AMDGPU/function-args-inreg.ll | 79 +++++--------
.../AMDGPU/insert_vector_elt.v2bf16.ll | 13 +--
.../CodeGen/AMDGPU/insert_vector_elt.v2i16.ll | 38 +++---
.../CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll | 3 +-
.../test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll | 20 ++--
.../AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll | 2 +-
llvm/test/CodeGen/AMDGPU/llvm.round.ll | 6 +-
llvm/test/CodeGen/AMDGPU/minmax.ll | 12 +-
18 files changed, 243 insertions(+), 276 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
index 6e5acdf608dbc..74faf62be1379 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUISelDAGToDAG.cpp
@@ -426,8 +426,8 @@ const TargetRegisterClass *AMDGPUDAGToDAGISel::getOperandRegClass(SDNode *N,
SDValue SubRegOp = N->getOperand(OpNo + 1);
unsigned SubRegIdx = SubRegOp->getAsZExtVal();
- return Subtarget->getRegisterInfo()->getSubClassWithSubReg(SuperRC,
- SubRegIdx);
+ return Subtarget->getRegisterInfo()->getSubRegisterClass(SuperRC,
+ SubRegIdx);
}
}
}
@@ -4783,24 +4783,23 @@ bool AMDGPUDAGToDAGISel::isUniformLoad(const SDNode *N) const {
const TargetRegisterClass *
AMDGPUDAGToDAGISel::inferDefRegClass(SDNode *N) const {
- // LLVM_DEBUG(dbgs() << "GetDefRegClass:\n"; N->dump(CurDAG); dbgs() << "\n");
-
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
if (!N->isMachineOpcode()) {
switch (N->getOpcode()) {
case ISD::CopyFromReg: {
Register Reg = cast<RegisterSDNode>(N->getOperand(1))->getReg();
- if (!Reg.isPhysical())
- return nullptr;
- return TRI->getPhysRegBaseClass(Reg);
+ if (Reg.isPhysical())
+ return TRI->getPhysRegBaseClass(Reg);
+ return CurDAG->getMachineFunction().getRegInfo().getRegClass(Reg);
}
}
return nullptr;
}
switch (N->getMachineOpcode()) {
- case TargetOpcode::COPY:
+ case TargetOpcode::COPY: {
return inferDefRegClass(N->getOperand(0).getNode());
+ }
case TargetOpcode::EXTRACT_SUBREG: {
const TargetRegisterClass *SrcRC =
inferDefRegClass(N->getOperand(0).getNode());
@@ -4810,8 +4809,8 @@ AMDGPUDAGToDAGISel::inferDefRegClass(SDNode *N) const {
return TRI->getSubClassWithSubReg(SrcRC, SubIdx);
}
case TargetOpcode::REG_SEQUENCE: {
- unsigned RCID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue();
- return TRI->getRegClass(RCID);
+ unsigned RCID = N->getConstantOperandVal(0);
+ return Subtarget->getRegisterInfo()->getRegClass(RCID);
}
case TargetOpcode::COPY_TO_REGCLASS: {
unsigned RCID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
@@ -4828,13 +4827,21 @@ bool AMDGPUDAGToDAGISel::Legalize16BitRegClass(SDNode *N) {
!Subtarget->useRealTrue16Insts())
return false;
- LLVM_DEBUG(dbgs() << "XXXXXXXXXXXXX:\n"; N->dump(CurDAG); dbgs() << "\n");
-
const SIRegisterInfo *TRI = Subtarget->getRegisterInfo();
- // Check 16bit types only
EVT VT = N->getValueType(0);
- if (VT != MVT::i16 && VT != MVT::f16 && VT != MVT::bf16)
+ if (!VT.isSimple())
+ return false;
+ MVT SVT = VT.getSimpleVT();
+ if (SVT == MVT::Other || SVT == MVT::Glue || SVT == MVT::Untyped)
+ return false;
+ if (VT.isScalableVector())
+ return false;
+
+ // Check 16/32bit types only
+ bool Is16Bit = VT.getSizeInBits() == 16;
+ bool Is32Bit = VT.getSizeInBits() == 32;
+ if (!Is16Bit && !Is32Bit)
return false;
SmallVector<std::pair<SDNode *, unsigned>, 4> ToFix;
@@ -4842,44 +4849,35 @@ bool AMDGPUDAGToDAGISel::Legalize16BitRegClass(SDNode *N) {
// Try to check def register class
const TargetRegisterClass *DstRC = inferDefRegClass(N);
if (!DstRC) {
- LLVM_DEBUG(dbgs() << "FAILED TO INFER:\n");
return false;
}
bool IsSGPR32 = TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_32RegClass);
bool IsVGPR16 = TRI->getCommonSubClass(DstRC, &AMDGPU::VGPR_16RegClass);
- LLVM_DEBUG(dbgs() << "IsSGPR32:" << IsSGPR32 << ", IsVGPR16:" << IsVGPR16
- << "\n");
-
// Scan users
for (SDNode::use_iterator UI = N->use_begin(), UE = N->use_end(); UI != UE;
++UI) {
SDNode *User = UI->getUser();
unsigned OperandNo = UI->getOperandNo();
- LLVM_DEBUG(dbgs() << "User:" << OperandNo << "---"; User->dump(CurDAG);
- dbgs() << "\n");
const TargetRegisterClass *UserRC = getOperandRegClass(User, OperandNo);
+ if (!UserRC)
+ continue;
- // SGPR32 used by reg_sequence with 16bit subreg
- if (IsSGPR32 && User->getOpcode() == TargetOpcode::REG_SEQUENCE) {
- unsigned RCID =
- cast<ConstantSDNode>(User->getOperand(OperandNo + 1))->getZExtValue();
- if (TRI->getCommonSubClass(TRI->getRegClass(RCID),
- &AMDGPU::VGPR_16RegClass)) {
- LLVM_DEBUG(dbgs() << "Found To Fix OperandNo:" << "\n");
+ if (Is16Bit) {
+ // SGPR32 used by reg_sequence with 16bit type requires a fix
+ if ((IsSGPR32 &&
+ !TRI->getCommonSubClass(UserRC, &AMDGPU::SGPR_32RegClass)) ||
+ (IsVGPR16 &&
+ !TRI->getCommonSubClass(UserRC, &AMDGPU::VGPR_16RegClass))) {
+ ToFix.emplace_back(User, OperandNo);
+ }
+ } else if (Is32Bit && IsSGPR32) {
+ // SGPR32 used by extract_subreg
+ if (User->isMachineOpcode() &&
+ User->getMachineOpcode() == TargetOpcode::EXTRACT_SUBREG) {
ToFix.emplace_back(User, OperandNo);
}
- }
-
- // Cross bank 16bit Def-Use that requires a fix
- if ((IsSGPR32 && TRI->getCommonSubClass(UserRC, &AMDGPU::VGPR_16RegClass) &&
- !TRI->getCommonSubClass(UserRC, &AMDGPU::SGPR_32RegClass)) ||
- (IsVGPR16 && TRI->getCommonSubClass(UserRC, &AMDGPU::SGPR_32RegClass) &&
- !TRI->getCommonSubClass(UserRC, &AMDGPU::VGPR_16RegClass))) {
-
- LLVM_DEBUG(dbgs() << "Found To Fix OperandNo:" << "\n");
- ToFix.emplace_back(User, OperandNo);
}
}
@@ -4891,21 +4889,29 @@ bool AMDGPUDAGToDAGISel::Legalize16BitRegClass(SDNode *N) {
if (IsSGPR32) {
// t0: sgpr_32 = ...
// ... = t0: vgpr_16
- // to
+ // to (is32bit)
+ // t0: sgpr_32 = ...
+ // t1: vgpr_32 = COPY_REGCLASS t0
+ //
+ // to (is16bit)
// t0: sgpr_32 = ...
// t1: vgpr_32 = COPY_REGCLASS t0
// t2: vgpr_16 = EXTRACT_SUBREG t1, lo16
// ... = t2: vgpr_16
SDValue RCImm =
CurDAG->getTargetConstant(AMDGPU::VGPR_32RegClassID, DL, MVT::i32);
- SDValue SubRegIdx = CurDAG->getTargetConstant(AMDGPU::lo16, DL, MVT::i32);
SDValue CopyToReg =
SDValue(CurDAG->getMachineNode(AMDGPU::COPY_TO_REGCLASS, DL, VT,
SDValue(N, 0), RCImm),
0);
- NewValue = SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG, DL,
- VT, CopyToReg, SubRegIdx),
- 0);
+ if (Is16Bit) {
+ SDValue SubRegIdx = CurDAG->getTargetConstant(AMDGPU::lo16, DL, MVT::i32);
+ NewValue = SDValue(CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
+ DL, VT, CopyToReg, SubRegIdx),
+ 0);
+ } else
+ NewValue = CopyToReg;
+
} else if (IsVGPR16) {
// t0: vgpr_16 = ...
// ... = t0: sgpr_32
@@ -4936,8 +4942,6 @@ bool AMDGPUDAGToDAGISel::Legalize16BitRegClass(SDNode *N) {
NewOps[OperandNo] = NewValue;
CurDAG->UpdateNodeOperands(User, NewOps);
}
- CurDAG->RemoveDeadNodes();
-
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index 3094c1390e9cf..693107c679ca3 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -6471,6 +6471,11 @@ void SIInstrInfo::legalizeOpWithMove(MachineInstr &MI, unsigned OpIdx) const {
.addImm(AMDGPU::sub0_sub1)
.addReg(Low64, RegState::Kill)
.addImm(AMDGPU::sub2_sub3);
+ } else if (Size == 16 && RI.getCommonSubClass(&AMDGPU::SGPR_32RegClass, RC)) {
+ // Special legalization for sreg32 to vgpr16 copy
+ Register VReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
+ BuildMI(*MBB, I, DL, get(Opcode), VReg).add(MO);
+ BuildMI(*MBB, I, DL, get(Opcode), Reg).addReg(VReg, {}, AMDGPU::lo16);
} else {
BuildMI(*MBB, I, DL, get(Opcode), Reg).add(MO);
}
diff --git a/llvm/test/CodeGen/AMDGPU/bf16-math.ll b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
index f0b3e305e7620..4d551620447ce 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16-math.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16-math.ll
@@ -490,7 +490,7 @@ define amdgpu_ps bfloat @test_clamp_bf16_s(bfloat inreg %src) {
; TRUE16-NEXT: s_mov_b64 s[64:65], 0
; TRUE16-NEXT: v_nop
; TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; TRUE16-NEXT: v_mov_b32_e32 v0, s0
; TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
; TRUE16-NEXT: ; return to shader part epilog
@@ -548,7 +548,7 @@ define amdgpu_ps float @test_clamp_bf16_hi16_s(<2 x bfloat> inreg %src) {
; TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; TRUE16-NEXT: s_lshr_b32 s0, s0, 16
; TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; TRUE16-NEXT: v_mov_b32_e32 v0, s0
; TRUE16-NEXT: v_pk_max_num_bf16 v0, v0, v0 op_sel_hi:[0,0] clamp
; TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0
diff --git a/llvm/test/CodeGen/AMDGPU/bf16.ll b/llvm/test/CodeGen/AMDGPU/bf16.ll
index d3e89cd1e469b..6857ee1d7cef4 100644
--- a/llvm/test/CodeGen/AMDGPU/bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/bf16.ll
@@ -2721,35 +2721,20 @@ define amdgpu_gfx void @test_inreg_arg_store(bfloat inreg %in, ptr addrspace(1)
; GFX10-NEXT: global_store_short v[0:1], v2, off
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11TRUE16-LABEL: test_inreg_arg_store:
-; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v2.l, s4
-; GFX11TRUE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11FAKE16-LABEL: test_inreg_arg_store:
-; GFX11FAKE16: ; %bb.0:
-; GFX11FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11FAKE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX11FAKE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX11FAKE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1250TRUE16-LABEL: test_inreg_arg_store:
-; GFX1250TRUE16: ; %bb.0:
-; GFX1250TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250TRUE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v2.l, s4
-; GFX1250TRUE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1250TRUE16-NEXT: s_set_pc_i64 s[30:31]
+; GFX11-LABEL: test_inreg_arg_store:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v2, s4
+; GFX11-NEXT: global_store_b16 v[0:1], v2, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
;
-; GFX1250FAKE16-LABEL: test_inreg_arg_store:
-; GFX1250FAKE16: ; %bb.0:
-; GFX1250FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0
-; GFX1250FAKE16-NEXT: s_wait_kmcnt 0x0
-; GFX1250FAKE16-NEXT: v_mov_b32_e32 v2, s4
-; GFX1250FAKE16-NEXT: global_store_b16 v[0:1], v2, off
-; GFX1250FAKE16-NEXT: s_set_pc_i64 s[30:31]
+; GFX1250-LABEL: test_inreg_arg_store:
+; GFX1250: ; %bb.0:
+; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
+; GFX1250-NEXT: s_wait_kmcnt 0x0
+; GFX1250-NEXT: v_mov_b32_e32 v2, s4
+; GFX1250-NEXT: global_store_b16 v[0:1], v2, off
+; GFX1250-NEXT: s_set_pc_i64 s[30:31]
store bfloat %in, ptr addrspace(1) %out
ret void
}
@@ -40894,7 +40879,7 @@ define amdgpu_ps i32 @s_select_bf16(bfloat inreg %a, bfloat inreg %b, i32 %c) #0
; GFX11TRUE16-LABEL: s_select_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v0.l, vcc_lo
; GFX11TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
@@ -40920,7 +40905,7 @@ define amdgpu_ps i32 @s_select_bf16(bfloat inreg %a, bfloat inreg %b, i32 %c) #0
; GFX1250TRUE16-NEXT: v_nop
; GFX1250TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX1250TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v0.l, vcc_lo
; GFX1250TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l
@@ -41133,14 +41118,13 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX11TRUE16-NEXT: s_lshr_b32 s3, s0, 16
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s1, 16
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v0.l, s2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.l, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, s1, v0.h, vcc_lo
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v1.l, vcc_lo
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_vselect_v2bf16:
@@ -41168,14 +41152,13 @@ define amdgpu_ps i32 @s_vselect_v2bf16(<2 x bfloat> inreg %a, <2 x bfloat> inreg
; GFX1250TRUE16-NEXT: s_lshr_b32 s3, s0, 16
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s2, 0, v1
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s3
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, s0
+; GFX1250TRUE16-NEXT: v_dual_mov_b32 v0, s3 :: v_dual_mov_b32 v1, s0
; GFX1250TRUE16-NEXT: s_lshr_b32 s0, s1, 16
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instid1(SALU_CYCLE_1)
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v0.l, s2
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.l, s2
; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, s1, v0.h, vcc_lo
-; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s1, v1.l, vcc_lo
+; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX1250TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250FAKE16-LABEL: s_vselect_v2bf16:
@@ -42280,19 +42263,18 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v1
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v2
; GFX11TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v3
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s9
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s1
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s7 :: v_dual_mov_b32 v1, s9
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX11TRUE16-NEXT: s_lshr_b32 s8, s3, 16
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s2, 16
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.h, s8, v0.l, s6
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.h, s4
-; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s2, v1.l, vcc_lo
-; GFX11TRUE16-NEXT: v_cndmask_b16 v2.l, s3, v1.h, s5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v2
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.h, s8, v0.l, s6
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v1.l, s4
+; GFX11TRUE16-NEXT: v_cndmask_b16 v1.l, s2, v2.l, vcc_lo
+; GFX11TRUE16-NEXT: v_cndmask_b16 v0.l, s3, v3.l, s5
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
; GFX11FAKE16-LABEL: s_vselect_v4bf16:
@@ -42335,19 +42317,18 @@ define amdgpu_ps <2 x i32> @s_vselect_v4bf16(<4 x bfloat> inreg %a, <4 x bfloat>
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s4, 0, v1
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s5, 0, v2
; GFX1250TRUE16-NEXT: v_cmp_eq_u32_e64 s6, 0, v3
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.l, s7
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v0.h, s9
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
-; GFX1250TRUE16-NEXT: v_mov_b16_e32 v1.h, s1
+; GFX1250TRUE16-NEXT: v_dual_mov_b32 v0, s7 :: v_dual_mov_b32 v1, s9
+; GFX1250TRUE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1
; GFX1250TRUE16-NEXT: s_lshr_b32 s8, s3, 16
; GFX1250TRUE16-NEXT: s_lshr_b32 s0, s2, 16
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.h, s8, v0.l, s6
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s0, v0.h, s4
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s2, v1.l, vcc_lo
-; GFX1250TRUE16-NEXT: v_cndmask_b16 v2.l, s3, v1.h, s5
-; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v0
-; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s1, v2
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_2)
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.h, s8, v0.l, s6
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.h, s0, v1.l, s4
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v1.l, s2, v2.l, vcc_lo
+; GFX1250TRUE16-NEXT: v_cndmask_b16 v0.l, s3, v3.l, s5
+; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s0, v1
+; GFX1250TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250TRUE16-NEXT: v_readfirstlane_b32 s1, v0
; GFX1250TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250FAKE16-LABEL: s_vselect_v4bf16:
diff --git a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
index 9e23cdc0fbddb..09701340e4fb0 100644
--- a/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/br_cc.f16.ll
@@ -73,19 +73,17 @@ define amdgpu_kernel void @br_cc_f16(
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3
; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], 0 glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[8:11], 0 glc dlc
+; GFX11-TRUE16-NEXT: buffer_load_d16_hi_b16 v0, off, s[8:11], 0 glc dlc
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v1.l
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_2
-; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
+; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, v0.l, v0.h
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_2
+; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
; GFX11-TRUE16-NEXT: .LBB0_2: ; %two
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
-; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: br_cc_f16:
@@ -179,23 +177,21 @@ define amdgpu_kernel void @br_cc_f16_imm_a(
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3800
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3
-; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
+; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_nlt_f16_e32 vcc_lo, 0.5, v0.l
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB1_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
-; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
; GFX11-TRUE16-NEXT: .LBB1_2: ; %two
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
-; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: br_cc_f16_imm_a:
@@ -284,23 +280,21 @@ define amdgpu_kernel void @br_cc_f16_imm_b(
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_mov_b32 s7, 0x31016000
; GFX11-TRUE16-NEXT: s_mov_b32 s6, -1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0x3800
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, 0x3800
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_mov_b32 s4, s2
; GFX11-TRUE16-NEXT: s_mov_b32 s5, s3
-; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v1, off, s[4:7], 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
+; GFX11-TRUE16-NEXT: buffer_load_d16_b16 v0, off, s[4:7], 0
+; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f16_e32 vcc_lo, 0.5, v0.l
; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB2_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %one
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
-; GFX11-TRUE16-NEXT: buffer_store_b16 v1, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
; GFX11-TRUE16-NEXT: .LBB2_2: ; %two
-; GFX11-TRUE16-NEXT: s_mov_b32 s2, s6
-; GFX11-TRUE16-NEXT: s_mov_b32 s3, s7
-; GFX11-TRUE16-NEXT: buffer_store_b16 v0, off, s[0:3], 0
+; GFX11-TRUE16-NEXT: buffer_store_d16_hi_b16 v0, off, s[0:3], 0
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: br_cc_f16_imm_b:
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
index 04632801c6ed1..45421d3e39cbf 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.bf16.ll
@@ -95,7 +95,7 @@ define bfloat @v_copysign_bf16_s_bf16(bfloat %mag, bfloat inreg %sign) {
; GFX11TRUE16-LABEL: v_copysign_bf16_s_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v1, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -151,7 +151,7 @@ define bfloat @v_copysign_s_bf16_bf16(bfloat inreg %mag, bfloat %sign) {
; GFX11TRUE16-LABEL: v_copysign_s_bf16_bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v1, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11TRUE16-NEXT: s_setpc_b64 s[30:31]
@@ -363,10 +363,9 @@ define amdgpu_ps i32 @s_copysign_bf16_bf16(bfloat inreg %mag, bfloat inreg %sign
;
; GFX11TRUE16-LABEL: s_copysign_bf16_bf16:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -435,7 +434,7 @@ define amdgpu_ps i32 @s_copysign_bf16_f32(bfloat inreg %mag, float inreg %sign.f
;
; GFX11TRUE16-LABEL: s_copysign_bf16_f32:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
@@ -508,7 +507,7 @@ define amdgpu_ps i32 @s_copysign_bf16_f64(bfloat inreg %mag, double inreg %sign.
;
; GFX11TRUE16-LABEL: s_copysign_bf16_f64:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
@@ -579,10 +578,9 @@ define amdgpu_ps i32 @s_copysign_bf16_f16(bfloat inreg %mag, half inreg %sign.f1
;
; GFX11TRUE16-LABEL: s_copysign_bf16_f16:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -715,6 +713,7 @@ define amdgpu_ps i32 @s_copysign_f32_bf16(float inreg %mag, bfloat inreg %sign.b
;
; GFX11TRUE16-LABEL: s_copysign_f32_bf16:
; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
@@ -827,10 +826,9 @@ define amdgpu_ps i32 @s_copysign_f16_bf16(half inreg %mag, bfloat inreg %sign.bf
;
; GFX11TRUE16-LABEL: s_copysign_f16_bf16:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
@@ -963,6 +961,7 @@ define amdgpu_ps <2 x i32> @s_copysign_f64_bf16(double inreg %mag, bfloat inreg
;
; GFX11TRUE16-LABEL: s_copysign_f64_bf16:
; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
@@ -2851,6 +2850,7 @@ define amdgpu_ps i32 @s_copysign_out_f32_mag_f32_sign_bf16(float inreg %mag, bfl
;
; GFX11TRUE16-LABEL: s_copysign_out_f32_mag_f32_sign_bf16:
; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s1
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
@@ -2918,6 +2918,7 @@ define amdgpu_ps <2 x i32> @s_copysign_out_f64_mag_f64_sign_bf16(double inreg %m
;
; GFX11TRUE16-LABEL: s_copysign_out_f64_mag_f64_sign_bf16:
; GFX11TRUE16: ; %bb.0:
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
@@ -2981,7 +2982,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_bf16_sign_f32(bfloat inreg %mag, f
;
; GFX11TRUE16-LABEL: s_copysign_out_bf16_mag_bf16_sign_f32:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
@@ -3045,7 +3046,7 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_bf16_sign_f64(bfloat inreg %mag, d
;
; GFX11TRUE16-LABEL: s_copysign_out_bf16_mag_bf16_sign_f64:
; GFX11TRUE16: ; %bb.0:
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
@@ -3140,14 +3141,13 @@ define amdgpu_ps i16 @s_copysign_out_bf16_mag_f32_sign_bf16(float inreg %mag, bf
; GFX11TRUE16-NEXT: s_add_i32 s2, s2, s0
; GFX11TRUE16-NEXT: s_bitset1_b32 s0, 22
; GFX11TRUE16-NEXT: s_addk_i32 s2, 0x7fff
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
; GFX11TRUE16-NEXT: s_and_b32 s3, s3, exec_lo
; GFX11TRUE16-NEXT: s_cselect_b32 s0, s0, s2
; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11TRUE16-NEXT: s_lshr_b32 s0, s0, 16
-; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
@@ -4158,13 +4158,15 @@ define amdgpu_ps <2 x i32> @s_copysign_out_v2f32_mag_v2f32_sign_v2bf16(<2 x floa
; GFX11TRUE16-LABEL: s_copysign_out_v2f32_mag_v2f32_sign_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_lshr_b32 s3, s2, 16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s3
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v1
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
@@ -4257,13 +4259,15 @@ define amdgpu_ps <4 x i32> @s_copysign_out_v2f64_mag_v2f64_sign_v2bf16(<2 x doub
; GFX11TRUE16-LABEL: s_copysign_out_v2f64_mag_v2f64_sign_v2bf16:
; GFX11TRUE16: ; %bb.0:
; GFX11TRUE16-NEXT: s_lshr_b32 s5, s4, 16
+; GFX11TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX11TRUE16-NEXT: v_mov_b16_e32 v0.h, s4
; GFX11TRUE16-NEXT: v_mov_b16_e32 v1.h, s5
-; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
-; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v1
; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v1
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11TRUE16-NEXT: v_readfirstlane_b32 s3, v1
; GFX11TRUE16-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
index 9db4987fc8210..971e1bcead501 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f16.ll
@@ -41,10 +41,9 @@ define amdgpu_ps i16 @s_copysign_f16(half inreg %mag, half inreg %sign) {
;
; GFX11-TRUE16-LABEL: s_copysign_f16:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s0
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -1220,7 +1219,7 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f64_sign_f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_and_b32 s3, s1, 0x1ff
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_or_b32 s0, s3, s0
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, 1, 0
; GFX11-TRUE16-NEXT: s_bfe_u32 s3, s1, 0xb0014
@@ -1262,8 +1261,8 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f64_sign_f16(double inreg %mag, hal
; GFX11-TRUE16-NEXT: s_cmpk_eq_i32 s3, 0x40f
; GFX11-TRUE16-NEXT: s_cselect_b32 s0, s0, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s0
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
@@ -2475,6 +2474,7 @@ define amdgpu_ps i32 @s_copysign_out_f32_mag_f32_sign_f16(float inreg %mag, half
;
; GFX11-TRUE16-LABEL: s_copysign_out_f32_mag_f32_sign_f16:
; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s1
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
@@ -2524,6 +2524,7 @@ define amdgpu_ps <2 x i32> @s_copysign_out_f64_mag_f64_sign_f16(double inreg %ma
;
; GFX11-TRUE16-LABEL: s_copysign_out_f64_mag_f64_sign_f16:
; GFX11-TRUE16: ; %bb.0:
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
@@ -2572,7 +2573,7 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f16_sign_f32(half inreg %mag, float
;
; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f16_sign_f32:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
@@ -2621,7 +2622,7 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f16_sign_f64(half inreg %mag, doubl
;
; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f16_sign_f64:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e64 v1, 16, s2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
@@ -2671,10 +2672,10 @@ define amdgpu_ps i16 @s_copysign_out_f16_mag_f32_sign_f16(float inreg %mag, half
;
; GFX11-TRUE16-LABEL: s_copysign_out_f16_mag_f32_sign_f16:
; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s1
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s1
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, s0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v1, v0
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -3596,13 +3597,15 @@ define amdgpu_ps <2 x i32> @s_copysign_out_v2f32_mag_v2f32_sign_v2f16(<2 x float
; GFX11-TRUE16-LABEL: s_copysign_out_v2f32_mag_v2f32_sign_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s2, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s2
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, s3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s0, v0
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v1
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
@@ -3670,13 +3673,15 @@ define amdgpu_ps <4 x i32> @s_copysign_out_v2f64_mag_v2f64_sign_v2f16(<2 x doubl
; GFX11-TRUE16-LABEL: s_copysign_out_v2f64_mag_v2f64_sign_v2f16:
; GFX11-TRUE16: ; %bb.0:
; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s4, 16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, s4
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, s5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_bfi_b32 v0, 0x7fffffff, s1, v0
-; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_bfi_b32 v1, 0x7fffffff, s3, v1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s1, v0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v1
; GFX11-TRUE16-NEXT: ; return to shader part epilog
;
diff --git a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
index 819d4e289b4a9..ae9f7fb24bc61 100644
--- a/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fcopysign.f64.ll
@@ -374,6 +374,7 @@ define amdgpu_kernel void @s_test_copysign_f64_f16(ptr addrspace(1) %out, [8 x i
; GFX11-NEXT: s_load_b64 s[2:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, s6
; GFX11-NEXT: v_mov_b16_e32 v0.h, s6
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-NEXT: v_bfi_b32 v1, 0x7fffffff, s1, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
index c534f89fd3d7e..52fd1cf14bb63 100644
--- a/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fmaximum3.ll
@@ -1557,7 +1557,7 @@ define half @v_fmaximum3_f16_commute(half %a, half %b, half %c) {
define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %c) {
; GFX12-TRUE16-LABEL: s_fmaximum3_f16:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_maximum3_f16 v0.l, s0, s1, v0.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1579,7 +1579,7 @@ define amdgpu_ps i32 @s_fmaximum3_f16(half inreg %a, half inreg %b, half inreg %
;
; GFX1170-TRUE16-LABEL: s_fmaximum3_f16:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_maximum3_f16 v0.l, s0, s1, v0.l
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
diff --git a/llvm/test/CodeGen/AMDGPU/fminimum3.ll b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
index 2aac73fae170d..66e2d69764b8e 100644
--- a/llvm/test/CodeGen/AMDGPU/fminimum3.ll
+++ b/llvm/test/CodeGen/AMDGPU/fminimum3.ll
@@ -1557,7 +1557,7 @@ define half @v_fminimum3_f16_commute(half %a, half %b, half %c) {
define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %c) {
; GFX12-TRUE16-LABEL: s_fminimum3_f16:
; GFX12-TRUE16: ; %bb.0:
-; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX12-TRUE16-NEXT: v_minimum3_f16 v0.l, s0, s1, v0.l
; GFX12-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
@@ -1579,7 +1579,7 @@ define amdgpu_ps i32 @s_fminimum3_f16(half inreg %a, half inreg %b, half inreg %
;
; GFX1170-TRUE16-LABEL: s_fminimum3_f16:
; GFX1170-TRUE16: ; %bb.0:
-; GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX1170-TRUE16-NEXT: v_mov_b32_e32 v0, s2
; GFX1170-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1170-TRUE16-NEXT: v_minimum3_f16 v0.l, s0, s1, v0.l
; GFX1170-TRUE16-NEXT: v_and_b32_e32 v0, 0xffff, v0
diff --git a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
index 38eee088d0902..65c79a6a4bab1 100644
--- a/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/function-args-inreg.ll
@@ -34,19 +34,12 @@ define void @void_func_i8_inreg(i8 inreg %arg0) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: void_func_i8_inreg:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: global_store_b8 v[0:1], v0, off
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: void_func_i8_inreg:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-FAKE16-NEXT: global_store_b8 v[0:1], v0, off
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: void_func_i8_inreg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: global_store_b8 v[0:1], v0, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
store i8 %arg0, ptr addrspace(1) poison
ret void
}
@@ -60,19 +53,12 @@ define void @void_func_i16_inreg(i16 inreg %arg0) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: void_func_i16_inreg:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: void_func_i16_inreg:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: void_func_i16_inreg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v0, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
store i16 %arg0, ptr addrspace(1) poison
ret void
}
@@ -125,19 +111,12 @@ define void @void_func_f16_inreg(half inreg %arg0) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: void_func_f16_inreg:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: void_func_f16_inreg:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: void_func_f16_inreg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v0, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
store half %arg0, ptr addrspace(1) poison
ret void
}
@@ -2144,19 +2123,12 @@ define void @void_func_bf16_inreg(bfloat inreg %arg0) #0 {
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
-; GFX11-TRUE16-LABEL: void_func_bf16_inreg:
-; GFX11-TRUE16: ; %bb.0:
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s0
-; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off
-; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX11-FAKE16-LABEL: void_func_bf16_inreg:
-; GFX11-FAKE16: ; %bb.0:
-; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0
-; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off
-; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
+; GFX11-LABEL: void_func_bf16_inreg:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_mov_b32_e32 v0, s0
+; GFX11-NEXT: global_store_b16 v[0:1], v0, off
+; GFX11-NEXT: s_setpc_b64 s[30:31]
store bfloat %arg0, ptr addrspace(1) poison
ret void
}
@@ -2617,3 +2589,6 @@ define void @void_func_a16i32_inreg__noimplicit([16 x i32] inreg %arg0, ptr addr
attributes #0 = { nounwind }
attributes #1 = { nounwind noinline }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX11-FAKE16: {{.*}}
+; GFX11-TRUE16: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
index 1526d59749a1f..2e0ca416a02a6 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2bf16.ll
@@ -816,9 +816,8 @@ define amdgpu_kernel void @v_insertelement_v4bf16_0(ptr addrspace(1) %out, ptr a
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_b64 v[0:1], v2, s[2:3] scale_offset
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.l, s4
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_lshrrev_b32 v3, 16, v0
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1250-REAL16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX1250-REAL16-NEXT: global_store_b64 v2, v[0:1], s[0:1] scale_offset
; GFX1250-REAL16-NEXT: s_endpgm
@@ -1051,10 +1050,10 @@ define amdgpu_kernel void @v_insertelement_v4bf16_2(ptr addrspace(1) %out, ptr a
; GFX1250-REAL16-NEXT: s_wait_kmcnt 0x0
; GFX1250-REAL16-NEXT: global_load_b64 v[0:1], v2, s[2:3] scale_offset
; GFX1250-REAL16-NEXT: s_wait_loadcnt 0x0
-; GFX1250-REAL16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1250-REAL16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX1250-REAL16-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_lshrrev_b32 v1, 16, v1
+; GFX1250-REAL16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1250-REAL16-NEXT: v_mov_b16_e32 v3.h, v1.l
+; GFX1250-REAL16-NEXT: v_mov_b32_e32 v1, v3
; GFX1250-REAL16-NEXT: global_store_b64 v2, v[0:1], s[0:1] scale_offset
; GFX1250-REAL16-NEXT: s_endpgm
%tid = call i32 @llvm.amdgcn.workitem.id.x() #1
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
index 63f7ab59ecff1..824b34629be79 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll
@@ -1893,7 +1893,7 @@ define amdgpu_kernel void @v_insertelement_v4f16_0(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s4
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v3.l
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
@@ -2091,11 +2091,12 @@ define amdgpu_kernel void @v_insertelement_v4f16_2(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -2291,11 +2292,12 @@ define amdgpu_kernel void @v_insertelement_v4i16_2(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 3, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b64 v[0:1], v2, s[2:3]
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, s4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v1
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v1, 16, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v1.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v3
; GFX11-TRUE16-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -2713,11 +2715,12 @@ define amdgpu_kernel void @v_insertelement_v8i16_6(ptr addrspace(1) %out, ptr ad
; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v4, 4, v0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v4, s[2:3]
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, s4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v5
; GFX11-TRUE16-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -3219,11 +3222,12 @@ define amdgpu_kernel void @v_insertelement_v16i16_6(ptr addrspace(1) %out, ptr a
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_load_b128 v[0:3], v8, s[2:3]
; GFX11-TRUE16-NEXT: global_load_b128 v[4:7], v8, s[2:3] offset:16
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, s4
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, s4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v9.l
+; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.h, v3.l
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v3, v9
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
index db8687edb2642..feb957eecc78c 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.alignbyte.ll
@@ -92,9 +92,8 @@ define amdgpu_kernel void @v_alignbyte_b32(ptr addrspace(1) %out, i32 %src1, i32
; GFX11-TRUE16-SDAG-NEXT: s_clause 0x1
; GFX11-TRUE16-SDAG-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-TRUE16-SDAG-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-SDAG-NEXT: s_waitcnt lgkmcnt(0)
-; GFX11-TRUE16-SDAG-NEXT: v_mov_b16_e32 v0.l, s2
+; GFX11-TRUE16-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v0, s2
; GFX11-TRUE16-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-SDAG-NEXT: v_alignbyte_b32 v0, s0, s1, v0.l
; GFX11-TRUE16-SDAG-NEXT: global_store_b32 v1, v0, s[4:5]
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
index 8a311979dfc1e..acd80345f621a 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.bitop3.ll
@@ -297,16 +297,16 @@ define amdgpu_ps half @bitop3_b16_sss(i16 inreg %a, i16 inreg %b, i16 inreg %c)
; GFX950-NEXT: v_bitop3_b16 v0, s0, v0, v1 bitop3:0x12
; GFX950-NEXT: ; return to shader part epilog
;
-; GFX1250-SDG-TRUE16-LABEL: bitop3_b16_sss:
-; GFX1250-SDG-TRUE16: ; %bb.0:
-; GFX1250-SDG-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
-; GFX1250-SDG-TRUE16-NEXT: s_mov_b64 s[64:65], 0
-; GFX1250-SDG-TRUE16-NEXT: v_nop
-; GFX1250-SDG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; GFX1250-SDG-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; GFX1250-SDG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1250-SDG-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
-; GFX1250-SDG-TRUE16-NEXT: ; return to shader part epilog
+; GFX1250-TRUE16-LABEL: bitop3_b16_sss:
+; GFX1250-TRUE16: ; %bb.0:
+; GFX1250-TRUE16-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1 ; msbs: dst=0 src0=0 src1=0 src2=0
+; GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
+; GFX1250-TRUE16-NEXT: v_nop
+; GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
+; GFX1250-TRUE16-NEXT: v_mov_b32_e32 v0, s2
+; GFX1250-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1250-TRUE16-NEXT: v_bitop3_b16 v0.l, s0, s1, v0.l bitop3:0x12
+; GFX1250-TRUE16-NEXT: ; return to shader part epilog
;
; GFX1250-FAKE16-LABEL: bitop3_b16_sss:
; GFX1250-FAKE16: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
index 452b83a7fbd36..50659fe405e24 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fdot2.bf16.bf16.ll
@@ -150,7 +150,7 @@ entry:
define amdgpu_ps void @test_llvm_amdgcn_fdot2_bf16_bf16_sis(
; SDAG-GFX11-TRUE16-LABEL: test_llvm_amdgcn_fdot2_bf16_bf16_sis:
; SDAG-GFX11-TRUE16: ; %bb.0: ; %entry
-; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, s1
+; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, s1
; SDAG-GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; SDAG-GFX11-TRUE16-NEXT: v_dot2_bf16_bf16 v2.l, s0, 0x3f803f80, v2.l
; SDAG-GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v2, off
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
index c2776a0439996..0fed9df4c29ba 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.round.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.round.ll
@@ -832,7 +832,7 @@ define amdgpu_kernel void @round_f16(ptr addrspace(1) %out, i32 %x.arg) #0 {
; GFX11-TRUE16-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, s2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_sub_f16_e32 v0.h, s2, v0.l
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
@@ -996,7 +996,7 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s2, 16
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.l, s2
; GFX11-TRUE16-NEXT: v_trunc_f16_e32 v0.h, s3
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, s3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_sub_f16_e32 v1.l, s2, v0.l
; GFX11-TRUE16-NEXT: v_sub_f16_e32 v1.h, s3, v0.h
@@ -1004,7 +1004,7 @@ define amdgpu_kernel void @round_v2f16(ptr addrspace(1) %out, i32 %in.arg) #0 {
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s6, |v1.l|, 0.5
; GFX11-TRUE16-NEXT: v_cmp_ge_f16_e64 s7, |v1.h|, 0.5
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s2
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: v_cndmask_b16 v2.l, 0, 0x3c00, s6
; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, 0, 0x3c00, s7
diff --git a/llvm/test/CodeGen/AMDGPU/minmax.ll b/llvm/test/CodeGen/AMDGPU/minmax.ll
index 04a4efb0b1a67..f6f90ee7fd835 100644
--- a/llvm/test/CodeGen/AMDGPU/minmax.ll
+++ b/llvm/test/CodeGen/AMDGPU/minmax.ll
@@ -1052,8 +1052,7 @@ define amdgpu_ps half @test_minmax_f16_ieee_false(half %a, half %b, half %c) {
define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b, half inreg %c, ptr addrspace(1) inreg %out) {
; SDAG-GFX11-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX11-TRUE16: ; %bb.0:
-; SDAG-GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX11-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX11-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX11-TRUE16-NEXT: v_maxmin_f16 v0.l, s0, s1, v0.l
@@ -1089,8 +1088,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; SDAG-GFX1170-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX1170-TRUE16: ; %bb.0:
-; SDAG-GFX1170-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX1170-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX1170-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1170-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1170-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX1170-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
@@ -1119,8 +1117,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
;
; SDAG-GFX12-TRUE16-LABEL: s_test_minmax_f16_ieee_false:
; SDAG-GFX12-TRUE16: ; %bb.0:
-; SDAG-GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX12-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX12-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
@@ -1153,8 +1150,7 @@ define amdgpu_ps void @s_test_minmax_f16_ieee_false(half inreg %a, half inreg %b
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b64 s[64:65], 0
; SDAG-GFX1250-TRUE16-NEXT: v_nop
; SDAG-GFX1250-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE
-; SDAG-GFX1250-TRUE16-NEXT: v_mov_b16_e32 v0.l, s2
-; SDAG-GFX1250-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; SDAG-GFX1250-TRUE16-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, 0
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s5, s4
; SDAG-GFX1250-TRUE16-NEXT: s_mov_b32 s4, s3
; SDAG-GFX1250-TRUE16-NEXT: v_maxmin_num_f16 v0.l, s0, s1, v0.l
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