[llvm-branch-commits] [llvm] [AArch64] Support direct RCPC3 FP atomic loads and stores (PR #231492)

[Vimal Patel via llvm-branch-commits]

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@@ -890,33 +890,90 @@ let Predicates = [HasLSFE] in {
 
 // v8.9a/v9.4a FEAT_LRCPC patterns
 let Predicates = [HasRCPC3, HasNEON] in {
+  def : Pat<(bf16 (acquiring_load<atomic_load_nonext_bf16> GPR64sp:$Rn)),
+            (LDAPURhi GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(bf16 (acquiring_load<atomic_load_nonext_bf16>
+                  (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
+            (LDAPURhi GPR64sp:$Rn, simm9:$offset)>;
+
+  def : Pat<(f16 (acquiring_load<atomic_load_nonext_f16> GPR64sp:$Rn)),
+            (LDAPURhi GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(f16 (acquiring_load<atomic_load_nonext_f16>
+                 (am_unscaled16 GPR64sp:$Rn, simm9:$offset))),
+            (LDAPURhi GPR64sp:$Rn, simm9:$offset)>;
+
+  def : Pat<(f32 (acquiring_load<atomic_load_nonext_f32> GPR64sp:$Rn)),
+            (LDAPURsi GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(f32 (acquiring_load<atomic_load_nonext_f32>
+                 (am_unscaled32 GPR64sp:$Rn, simm9:$offset))),
+            (LDAPURsi GPR64sp:$Rn, simm9:$offset)>;
+
+  def : Pat<(f64 (acquiring_load<atomic_load_nonext_f64> GPR64sp:$Rn)),
+            (LDAPURdi GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(f64 (acquiring_load<atomic_load_nonext_f64>
+                 (am_unscaled64 GPR64sp:$Rn, simm9:$offset))),
+            (LDAPURdi GPR64sp:$Rn, simm9:$offset)>;
+
+  def : Pat<(releasing_store<atomic_store_bf16> GPR64sp:$Rn,
+                  (bf16 FPR16:$val)),
+            (STLURhi FPR16:$val, GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(releasing_store<atomic_store_bf16>
+                 (am_unscaled16 GPR64sp:$Rn, simm9:$offset),
+                 (bf16 FPR16:$val)),
+            (STLURhi FPR16:$val, GPR64sp:$Rn, simm9:$offset)>;
+  def : Pat<(releasing_store<atomic_store_f16> GPR64sp:$Rn,
+                  (f16 FPR16:$val)),
+            (STLURhi FPR16:$val, GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(releasing_store<atomic_store_f16>
+                 (am_unscaled16 GPR64sp:$Rn, simm9:$offset),
+                 (f16 FPR16:$val)),
+            (STLURhi FPR16:$val, GPR64sp:$Rn, simm9:$offset)>;
+  def : Pat<(releasing_store<atomic_store_f32> GPR64sp:$Rn,
+                  (f32 FPR32:$val)),
+            (STLURsi FPR32:$val, GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(releasing_store<atomic_store_f32>
+                 (am_unscaled32 GPR64sp:$Rn, simm9:$offset),
+                 (f32 FPR32:$val)),
+            (STLURsi FPR32:$val, GPR64sp:$Rn, simm9:$offset)>;
+  def : Pat<(releasing_store<atomic_store_f64> GPR64sp:$Rn,
+                  (f64 FPR64:$val)),
+            (STLURdi FPR64:$val, GPR64sp:$Rn, (i64 0))>;
+  def : Pat<(releasing_store<atomic_store_f64>
+                 (am_unscaled64 GPR64sp:$Rn, simm9:$offset),
+                 (f64 FPR64:$val)),
+            (STLURdi FPR64:$val, GPR64sp:$Rn, simm9:$offset)>;
+
   // LDAP1 loads
   def : Pat<(vector_insert (v2i64 VecListOne128:$Rd),
                 (i64 (acquiring_load<atomic_load_nonext_64> GPR64sp:$Rn)), (i64 VectorIndexD:$idx)),
             (LDAP1 VecListOne128:$Rd, VectorIndexD:$idx, GPR64sp:$Rn)>;
   def : Pat<(vector_insert (v2f64 VecListOne128:$Rd),
-                (f64 (bitconvert (i64 (acquiring_load<atomic_load_nonext_64> GPR64sp:$Rn)))), (i64 VectorIndexD:$idx)),
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pvimal816a wrote:

Yeah, this is the same issue as seen in the first PR. I'll fix it. Thanks for catching it.

https://github.com/llvm/llvm-project/pull/231492