[llvm-branch-commits] [llvm] 1ae42c9 - Revert "[MISched] Add anti-dependency breaking to PostMachineScheduler"
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sun Oct 25 22:23:48 PDT 2026
Author: Aiden Grossman
Date: 2026-10-25T22:23:44-07:00
New Revision: 1ae42c97e06cb8d28160a6e9e202d589ee8e9722
URL: https://github.com/llvm/llvm-project/commit/1ae42c97e06cb8d28160a6e9e202d589ee8e9722
DIFF: https://github.com/llvm/llvm-project/commit/1ae42c97e06cb8d28160a6e9e202d589ee8e9722.diff
LOG: Revert "[MISched] Add anti-dependency breaking to PostMachineScheduler"
This reverts commit 7c7c0baf96f2607eb0bb2be4b576dea9d1f8e3ac.
Added:
Modified:
llvm/include/llvm/CodeGen/MachineScheduler.h
llvm/lib/CodeGen/MachineScheduler.cpp
llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
Removed:
llvm/test/CodeGen/RISCV/postmisched-antidep-region.mir
llvm/test/CodeGen/RISCV/postmisched-antidep.ll
################################################################################
diff --git a/llvm/include/llvm/CodeGen/MachineScheduler.h b/llvm/include/llvm/CodeGen/MachineScheduler.h
index e5e675bc9792f..7ecc34fed40f8 100644
--- a/llvm/include/llvm/CodeGen/MachineScheduler.h
+++ b/llvm/include/llvm/CodeGen/MachineScheduler.h
@@ -81,7 +81,6 @@
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/Twine.h"
-#include "llvm/CodeGen/AntiDepBreaker.h"
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineBlockFrequencyInfo.h"
#include "llvm/CodeGen/MachinePassRegistry.h"
@@ -96,8 +95,8 @@
#include "llvm/Support/ErrorHandling.h"
#include <algorithm>
#include <cassert>
-#include <list>
#include <llvm/Support/raw_ostream.h>
+#include <list>
#include <memory>
#include <string>
#include <vector>
@@ -122,8 +121,6 @@ enum Direction {
/// Returns -misched-prera-direction.
LLVM_ABI MISched::Direction getPreRADirection();
-/// Returns -misched-postra-break-antideps.
-LLVM_ABI TargetSubtargetInfo::AntiDepBreakMode getPostRABreakAntiDeps();
/// Returns whether -verify-misched is set.
LLVM_ABI bool shouldVerifyScheduling();
@@ -312,47 +309,6 @@ class LLVM_ABI MachineSchedStrategy {
virtual void releaseBottomNode(SUnit *SU) = 0;
};
-/// State for breaking physical-register anti-dependencies while scheduling a
-/// machine basic block after register allocation.
-class LLVM_ABI AntiDepState {
- /// The selected breaker, or null when anti-dependency breaking is disabled.
- std::unique_ptr<AntiDepBreaker> Breaker;
-
- /// Instruction index of the current region's end in its basic block.
- unsigned RegionEndIndex = 0;
-
- /// Position from which boundary instructions are scanned for liveness.
- MachineBasicBlock::iterator BoundaryScanPos;
-
- /// Instruction index corresponding to `BoundaryScanPos`.
- unsigned BoundaryScanIndex = 0;
-
- /// Whether ScheduleDAGMI::schedule() processed the current region.
- bool RegionProcessed = false;
-
-public:
- AntiDepState(MachineSchedContext *C,
- TargetSubtargetInfo::AntiDepBreakMode AntiDepMode);
-
- void startBlock(MachineBasicBlock *MBB);
-
- void finishBlock();
-
- void enterRegion(MachineBasicBlock::iterator End);
-
- void exitRegion(MachineBasicBlock::iterator Begin,
- MachineBasicBlock::iterator End);
-
- bool breakAntiDependencies(const std::vector<SUnit> &SUnits,
- MachineBasicBlock::iterator Begin,
- MachineBasicBlock::iterator End,
- AntiDepBreaker::DbgValueVector &DbgValues);
-
-private:
- void scanRangeBackwards(MachineBasicBlock::iterator From,
- MachineBasicBlock::iterator To);
-};
-
/// ScheduleDAGMI is an implementation of ScheduleDAGInstrs that simply
/// schedules machine instructions according to the given MachineSchedStrategy
/// without much extra book-keeping. This is the common functionality between
@@ -364,9 +320,6 @@ class LLVM_ABI ScheduleDAGMI : public ScheduleDAGInstrs {
MachineBlockFrequencyInfo *MBFI;
std::unique_ptr<MachineSchedStrategy> SchedImpl;
- /// State for optional post-RA anti-dependency breaking.
- AntiDepState AntiDep;
-
/// Ordered list of DAG postprocessing steps.
std::vector<std::unique_ptr<ScheduleDAGMutation>> Mutations;
@@ -385,18 +338,8 @@ class LLVM_ABI ScheduleDAGMI : public ScheduleDAGInstrs {
public:
ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
bool RemoveKillFlags)
- : ScheduleDAGMI(C, std::move(S), RemoveKillFlags,
- TargetSubtargetInfo::ANTIDEP_NONE) {}
-
- /// Construct a post-RA scheduler with the requested anti-dependency mode.
- ScheduleDAGMI(MachineSchedContext *C, std::unique_ptr<MachineSchedStrategy> S,
- bool RemoveKillFlags,
- TargetSubtargetInfo::AntiDepBreakMode AntiDepMode)
: ScheduleDAGInstrs(*C->MF, C->MLI, RemoveKillFlags), AA(C->AA),
- LIS(C->LIS), MBFI(C->MBFI), SchedImpl(std::move(S)),
- AntiDep(C, SchedImpl->doMBBSchedRegionsTopDown()
- ? TargetSubtargetInfo::ANTIDEP_NONE
- : AntiDepMode) {}
+ LIS(C->LIS), MBFI(C->MBFI), SchedImpl(std::move(S)) {}
// Provide a vtable anchor
~ScheduleDAGMI() override;
@@ -430,12 +373,11 @@ class LLVM_ABI ScheduleDAGMI : public ScheduleDAGInstrs {
/// Implement the ScheduleDAGInstrs interface for handling the next scheduling
/// region. This covers all instructions in a block, while schedule() may only
/// cover a subset.
- void enterRegion(MachineBasicBlock *bb, MachineBasicBlock::iterator begin,
+ void enterRegion(MachineBasicBlock *bb,
+ MachineBasicBlock::iterator begin,
MachineBasicBlock::iterator end,
unsigned regioninstrs) override;
- void exitRegion() override;
-
/// Implement ScheduleDAGInstrs interface for scheduling a sequence of
/// reorderable instructions.
void schedule() override;
@@ -1504,7 +1446,7 @@ ScheduleDAGMILive *createSchedLive(MachineSchedContext *C) {
template <typename Strategy = PostGenericScheduler>
ScheduleDAGMI *createSchedPostRA(MachineSchedContext *C) {
return new ScheduleDAGMI(C, std::make_unique<Strategy>(C),
- /*RemoveKillFlags=*/true, getPostRABreakAntiDeps());
+ /*RemoveKillFlags=*/true);
}
class MachineSchedulerPass
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index 4eded9484cccf..ed9bf1b2d8de0 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -204,25 +204,11 @@ static cl::opt<bool>
DumpCriticalPathLength("misched-dcpl", cl::Hidden,
cl::desc("Print critical path length to stdout"));
-static cl::opt<TargetSubtargetInfo::AntiDepBreakMode> PostRABreakAntiDeps(
- "misched-postra-break-antideps", cl::Hidden,
- cl::desc("Set the post-RA MISched anti-dependency break mode"),
- cl::init(TargetSubtargetInfo::ANTIDEP_NONE),
- cl::values(clEnumValN(TargetSubtargetInfo::ANTIDEP_NONE, "none",
- "No anti-dependency breaking"),
- clEnumValN(TargetSubtargetInfo::ANTIDEP_CRITICAL, "critical",
- "Break critical-path anti-dependencies"),
- clEnumValN(TargetSubtargetInfo::ANTIDEP_ALL, "all",
- "Break all anti-dependencies")));
-
static cl::opt<bool> VerifyScheduling(
"verify-misched", cl::Hidden,
cl::desc("Verify machine instrs before and after machine scheduling"));
MISched::Direction llvm::getPreRADirection() { return PreRADirection; }
-TargetSubtargetInfo::AntiDepBreakMode llvm::getPostRABreakAntiDeps() {
- return PostRABreakAntiDeps;
-}
bool llvm::shouldVerifyScheduling() { return VerifyScheduling; }
#ifndef NDEBUG
@@ -398,7 +384,6 @@ class PostMachineSchedulerImpl : public MachineSchedulerBase {
struct RequiredAnalyses {
MachineLoopInfo &MLI;
AAResults &AA;
- RegisterClassInfo &RCI;
};
PostMachineSchedulerImpl() = default;
// Migration only
@@ -540,7 +525,6 @@ void PostMachineSchedulerLegacy::getAnalysisUsage(AnalysisUsage &AU) const {
AU.addRequired<MachineLoopInfoWrapperPass>();
AU.addRequired<AAResultsWrapperPass>();
AU.addRequired<TargetPassConfig>();
- AU.addRequired<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
@@ -738,7 +722,6 @@ bool PostMachineSchedulerImpl::run(MachineFunction &Func,
MLI = &Analyses.MLI;
this->TM = &TM;
AA = &Analyses.AA;
- RegClassInfo = &Analyses.RCI;
if (VerifyScheduling) {
const char *PostMSchedBanner = "Before post machine scheduling.";
@@ -919,9 +902,8 @@ bool PostMachineSchedulerLegacy::runOnMachineFunction(MachineFunction &MF) {
auto &MLI = getAnalysis<MachineLoopInfoWrapperPass>().getLI();
auto &TM = getAnalysis<TargetPassConfig>().getTM<TargetMachine>();
auto &AA = getAnalysis<AAResultsWrapperPass>().getAAResults();
- auto &RCI = getAnalysis<MachineRegisterClassInfoWrapperPass>().getRCI();
Impl.setLegacyPass(this);
- return Impl.run(MF, TM, {MLI, AA, RCI});
+ return Impl.run(MF, TM, {MLI, AA});
}
PreservedAnalyses
@@ -939,10 +921,9 @@ PostMachineSchedulerPass::run(MachineFunction &MF,
auto &FAM = MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
.getManager();
auto &AA = FAM.getResult<AAManager>(MF.getFunction());
- auto &RCI = MFAM.getResult<MachineRegisterClassAnalysis>(MF);
Impl->setMFAM(&MFAM);
- bool Changed = Impl->run(MF, *TM, {MLI, AA, RCI});
+ bool Changed = Impl->run(MF, *TM, {MLI, AA});
if (!Changed)
return PreservedAnalyses::all();
@@ -1117,91 +1098,6 @@ LLVM_DUMP_METHOD void ReadyQueue::dump() const {
// virtual registers.
// ===----------------------------------------------------------------------===/
-AntiDepState::AntiDepState(MachineSchedContext *C,
- TargetSubtargetInfo::AntiDepBreakMode AntiDepMode) {
- if (AntiDepMode == TargetSubtargetInfo::ANTIDEP_NONE)
- return;
-
- assert(C->MF->getRegInfo().tracksLiveness() &&
- "Live-ins must be accurate for anti-dependency breaking");
- assert(C->RegClassInfo &&
- "Register class info is required for anti-dependency breaking");
- if (AntiDepMode == TargetSubtargetInfo::ANTIDEP_ALL) {
- SmallVector<const TargetRegisterClass *, 4> CriticalPathRCs;
- C->MF->getSubtarget().getCriticalPathRCs(CriticalPathRCs);
- Breaker.reset(createAggressiveAntiDepBreaker(*C->MF, *C->RegClassInfo,
- CriticalPathRCs));
- } else {
- assert(AntiDepMode == TargetSubtargetInfo::ANTIDEP_CRITICAL &&
- "Unexpected anti-dependency break mode");
- Breaker.reset(createCriticalAntiDepBreaker(*C->MF, *C->RegClassInfo));
- }
-}
-
-void AntiDepState::scanRangeBackwards(MachineBasicBlock::iterator From,
- MachineBasicBlock::iterator To) {
- for (auto I = From; I != To;) {
- MachineInstr &MI = *--I;
- --BoundaryScanIndex;
- if (!MI.isDebugOrPseudoInstr())
- Breaker->Observe(MI, BoundaryScanIndex, RegionEndIndex);
- if (MI.isBundle())
- BoundaryScanIndex -= MI.getBundleSize();
- }
-}
-
-void AntiDepState::startBlock(MachineBasicBlock *MBB) {
- if (!Breaker)
- return;
- Breaker->StartBlock(MBB);
- BoundaryScanPos = MBB->end();
- BoundaryScanIndex = MBB->size();
- RegionEndIndex = BoundaryScanIndex;
-}
-
-void AntiDepState::finishBlock() {
- if (!Breaker)
- return;
- Breaker->FinishBlock();
-}
-
-void AntiDepState::enterRegion(MachineBasicBlock::iterator End) {
- if (!Breaker)
- return;
-
- // Scheduling regions exclude boundary instructions and may have gaps between
- // them. Scan those gaps so the breaker's liveness remains synchronized.
- scanRangeBackwards(BoundaryScanPos, End);
- RegionEndIndex = BoundaryScanIndex;
- RegionProcessed = false;
-}
-
-void AntiDepState::exitRegion(MachineBasicBlock::iterator Begin,
- MachineBasicBlock::iterator End) {
- if (!Breaker)
- return;
-
- BoundaryScanPos = Begin;
- if (RegionProcessed) {
- BoundaryScanIndex -= std::distance(Begin, End);
- } else {
- // schedule() skips empty and single-instruction regions. Scan a skipped
- // region here so its instructions still contribute to liveness.
- scanRangeBackwards(End, Begin);
- }
-}
-
-bool AntiDepState::breakAntiDependencies(
- const std::vector<SUnit> &SUnits, MachineBasicBlock::iterator Begin,
- MachineBasicBlock::iterator End,
- AntiDepBreaker::DbgValueVector &DbgValues) {
- if (!Breaker)
- return false;
- RegionProcessed = true;
- return Breaker->BreakAntiDependencies(SUnits, Begin, End, RegionEndIndex,
- DbgValues) != 0;
-}
-
// Provide a vtable anchor.
ScheduleDAGMI::~ScheduleDAGMI() = default;
@@ -1278,11 +1174,9 @@ void ScheduleDAGMI::releasePredecessors(SUnit *SU) {
void ScheduleDAGMI::startBlock(MachineBasicBlock *bb) {
ScheduleDAGInstrs::startBlock(bb);
SchedImpl->enterMBB(bb);
- AntiDep.startBlock(bb);
}
void ScheduleDAGMI::finishBlock() {
- AntiDep.finishBlock();
SchedImpl->leaveMBB();
ScheduleDAGInstrs::finishBlock();
}
@@ -1292,11 +1186,11 @@ void ScheduleDAGMI::finishBlock() {
/// in the region, including the boundary itself and single-instruction regions
/// that don't get scheduled.
void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
- MachineBasicBlock::iterator begin,
- MachineBasicBlock::iterator end,
- unsigned regioninstrs) {
+ MachineBasicBlock::iterator begin,
+ MachineBasicBlock::iterator end,
+ unsigned regioninstrs)
+{
ScheduleDAGInstrs::enterRegion(bb, begin, end, regioninstrs);
- AntiDep.enterRegion(end);
SchedImpl->initPolicy(begin, end, regioninstrs);
@@ -1311,11 +1205,6 @@ void ScheduleDAGMI::enterRegion(MachineBasicBlock *bb,
setDumpDirection(D);
}
-void ScheduleDAGMI::exitRegion() {
- AntiDep.exitRegion(RegionBegin, RegionEnd);
- ScheduleDAGInstrs::exitRegion();
-}
-
/// This is normally called from the main scheduler loop but may also be invoked
/// by the scheduling strategy to perform additional code motion.
void ScheduleDAGMI::moveInstruction(
@@ -1358,14 +1247,6 @@ void ScheduleDAGMI::schedule() {
// Build the DAG.
buildSchedGraph(AA);
- if (AntiDep.breakAntiDependencies(SUnits, RegionBegin, RegionEnd,
- DbgValues)) {
- // Renaming invalidates register dependencies. Rebuild the base DAG before
- // applying mutations below, as SchedulePostRATDList does. Updating the DAG
- // in place would also need to account for edges removed by mutations.
- buildSchedGraph(AA);
- }
-
postProcessDAG();
SmallVector<SUnit*, 8> TopRoots, BotRoots;
diff --git a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
index 5f5f954589d28..742721a2df16d 100644
--- a/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp
@@ -110,11 +110,6 @@ class AArch64ExpandPseudoLegacy : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &MF) override;
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
StringRef getPassName() const override { return AARCH64_EXPAND_PSEUDO_NAME; }
};
diff --git a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
index 4b19c0943f0b4..1eaecfff7b177 100644
--- a/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp
@@ -219,7 +219,6 @@ struct AArch64LoadStoreOptLegacy : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<AAResultsWrapperPass>();
- AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
diff --git a/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp b/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
index ab52549f522d3..ac0dc353a9a18 100644
--- a/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
+++ b/llvm/lib/Target/AArch64/AArch64SpeculationHardening.cpp
@@ -126,11 +126,6 @@ class AArch64SpeculationHardening : public MachineFunctionPass {
bool runOnMachineFunction(MachineFunction &Fn) override;
- void getAnalysisUsage(AnalysisUsage &AU) const override {
- AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
- MachineFunctionPass::getAnalysisUsage(AU);
- }
-
StringRef getPassName() const override {
return AARCH64_SPECULATION_HARDENING_NAME;
}
diff --git a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
index a489f394dd5ff..9efe85d27c6c0 100644
--- a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
@@ -56,7 +56,6 @@ struct RISCVLoadStoreOpt : public MachineFunctionPass {
void getAnalysisUsage(AnalysisUsage &AU) const override {
AU.addRequired<AAResultsWrapperPass>();
- AU.addPreserved<MachineRegisterClassInfoWrapperPass>();
MachineFunctionPass::getAnalysisUsage(AU);
}
diff --git a/llvm/test/CodeGen/RISCV/postmisched-antidep-region.mir b/llvm/test/CodeGen/RISCV/postmisched-antidep-region.mir
deleted file mode 100644
index 28230ae8fd322..0000000000000
--- a/llvm/test/CodeGen/RISCV/postmisched-antidep-region.mir
+++ /dev/null
@@ -1,96 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=postmisched \
-# RUN: -enable-post-misched -misched-postra-break-antideps=all \
-# RUN: -o - %s | FileCheck %s --check-prefix=ANTIDEP
-# RUN: llc -mtriple=riscv64 -mcpu=sifive-x280 -run-pass=postmisched \
-# RUN: -enable-post-misched -misched-postra-break-antideps=none \
-# RUN: -o - %s | FileCheck %s --check-prefix=NO-ANTIDEP
-
-# A WAR hazard within a single scheduling region: the second definition is
-# renamed so it no longer reuses the register the earlier instruction reads.
----
-name: gpr_region_war
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10, $x11, $x12, $x13, $x15
- ; ANTIDEP-LABEL: name: gpr_region_war
- ; ANTIDEP: liveins: $x10, $x11, $x12, $x13, $x15
- ; ANTIDEP-NEXT: {{ $}}
- ; ANTIDEP-NEXT: renamable $x14 = ADD killed renamable $x15, killed renamable $x10
- ; ANTIDEP-NEXT: $x11 = LD killed renamable $x11, 0 :: (load (s64))
- ; ANTIDEP-NEXT: SD killed $x11, killed renamable $x12, 0 :: (store (s64))
- ; ANTIDEP-NEXT: SD killed renamable $x14, killed renamable $x13, 0 :: (store (s64))
- ; ANTIDEP-NEXT: PseudoRET
- ;
- ; NO-ANTIDEP-LABEL: name: gpr_region_war
- ; NO-ANTIDEP: liveins: $x10, $x11, $x12, $x13, $x15
- ; NO-ANTIDEP-NEXT: {{ $}}
- ; NO-ANTIDEP-NEXT: renamable $x14 = ADD killed renamable $x15, killed renamable $x10
- ; NO-ANTIDEP-NEXT: renamable $x15 = LD killed renamable $x11, 0 :: (load (s64))
- ; NO-ANTIDEP-NEXT: SD killed renamable $x15, killed renamable $x12, 0 :: (store (s64))
- ; NO-ANTIDEP-NEXT: SD killed renamable $x14, killed renamable $x13, 0 :: (store (s64))
- ; NO-ANTIDEP-NEXT: PseudoRET
- renamable $x14 = ADD renamable $x15, renamable $x10
- renamable $x15 = LD renamable $x11, 0 :: (load (s64))
- SD renamable $x15, renamable $x12, 0 :: (store (s64))
- SD renamable $x14, renamable $x13, 0 :: (store (s64))
- PseudoRET
-...
-
----
-name: fpr_region_war
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10, $x11, $x12, $f10_d, $f11_d
- ; ANTIDEP-LABEL: name: fpr_region_war
- ; ANTIDEP: liveins: $x10, $x11, $x12, $f10_d, $f11_d
- ; ANTIDEP-NEXT: {{ $}}
- ; ANTIDEP-NEXT: renamable $f12_d = nofpexcept FADD_D killed renamable $f10_d, killed renamable $f11_d, 7, implicit $frm
- ; ANTIDEP-NEXT: $f11_d = FLD killed renamable $x10, 0 :: (load (s64))
- ; ANTIDEP-NEXT: FSD killed $f11_d, killed renamable $x11, 0 :: (store (s64))
- ; ANTIDEP-NEXT: FSD killed renamable $f12_d, killed renamable $x12, 0 :: (store (s64))
- ; ANTIDEP-NEXT: PseudoRET
- ;
- ; NO-ANTIDEP-LABEL: name: fpr_region_war
- ; NO-ANTIDEP: liveins: $x10, $x11, $x12, $f10_d, $f11_d
- ; NO-ANTIDEP-NEXT: {{ $}}
- ; NO-ANTIDEP-NEXT: renamable $f12_d = nofpexcept FADD_D killed renamable $f10_d, killed renamable $f11_d, 7, implicit $frm
- ; NO-ANTIDEP-NEXT: renamable $f10_d = FLD killed renamable $x10, 0 :: (load (s64))
- ; NO-ANTIDEP-NEXT: FSD killed renamable $f10_d, killed renamable $x11, 0 :: (store (s64))
- ; NO-ANTIDEP-NEXT: FSD killed renamable $f12_d, killed renamable $x12, 0 :: (store (s64))
- ; NO-ANTIDEP-NEXT: PseudoRET
- renamable $f12_d = nofpexcept FADD_D renamable $f10_d, renamable $f11_d, 7, implicit $frm
- renamable $f10_d = FLD renamable $x10, 0 :: (load (s64))
- FSD renamable $f10_d, renamable $x11, 0 :: (store (s64))
- FSD renamable $f12_d, renamable $x12, 0 :: (store (s64))
- PseudoRET
-...
-
----
-name: rvv_region_war
-tracksRegLiveness: true
-body: |
- bb.0:
- liveins: $x10, $x11, $v8
- ; ANTIDEP-LABEL: name: rvv_region_war
- ; ANTIDEP: liveins: $x10, $x11, $v8
- ; ANTIDEP-NEXT: {{ $}}
- ; ANTIDEP-NEXT: $v31 = VL1RE8_V killed renamable $x10 :: (load unknown-size, align 1)
- ; ANTIDEP-NEXT: $x12 = PseudoVMV_X_S killed renamable $v8, 5 /* e32 */, implicit $vtype
- ; ANTIDEP-NEXT: VS1R_V killed $v31, killed renamable $x11 :: (store unknown-size, align 1)
- ; ANTIDEP-NEXT: PseudoRET
- ;
- ; NO-ANTIDEP-LABEL: name: rvv_region_war
- ; NO-ANTIDEP: liveins: $x10, $x11, $v8
- ; NO-ANTIDEP-NEXT: {{ $}}
- ; NO-ANTIDEP-NEXT: $x12 = PseudoVMV_X_S killed renamable $v8, 5 /* e32 */, implicit $vtype
- ; NO-ANTIDEP-NEXT: renamable $v8 = VL1RE8_V killed renamable $x10 :: (load unknown-size, align 1)
- ; NO-ANTIDEP-NEXT: VS1R_V killed renamable $v8, killed renamable $x11 :: (store unknown-size, align 1)
- ; NO-ANTIDEP-NEXT: PseudoRET
- $x12 = PseudoVMV_X_S renamable $v8, 5 /* e32 */, implicit $vtype
- renamable $v8 = VL1RE8_V renamable $x10 :: (load unknown-size, align 1)
- VS1R_V renamable $v8, renamable $x11 :: (store unknown-size, align 1)
- PseudoRET
-...
diff --git a/llvm/test/CodeGen/RISCV/postmisched-antidep.ll b/llvm/test/CodeGen/RISCV/postmisched-antidep.ll
deleted file mode 100644
index 8cb74b093a850..0000000000000
--- a/llvm/test/CodeGen/RISCV/postmisched-antidep.ll
+++ /dev/null
@@ -1,26 +0,0 @@
-; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 \
-; RUN: -misched-postra-break-antideps=all -o - %s \
-; RUN: | FileCheck %s --check-prefix=ALL
-; RUN: llc -mtriple=riscv64 -mcpu=sifive-u74 \
-; RUN: -misched-postra-break-antideps=none -o - %s \
-; RUN: | FileCheck %s --check-prefix=NONE
-
-define i64 @sdiv4096(i64 %x) {
-; ALL-LABEL: sdiv4096:
-; ALL: # %bb.0:
-; ALL-NEXT: srai a1, a0, 63
-; ALL-NEXT: srli a2, a1, 52
-; ALL-NEXT: add a5, a0, a2
-; ALL-NEXT: srai a0, a5, 12
-; ALL-NEXT: ret
-;
-; NONE-LABEL: sdiv4096:
-; NONE: # %bb.0:
-; NONE-NEXT: srai a1, a0, 63
-; NONE-NEXT: srli a1, a1, 52
-; NONE-NEXT: add a0, a0, a1
-; NONE-NEXT: srai a0, a0, 12
-; NONE-NEXT: ret
- %result = sdiv i64 %x, 4096
- ret i64 %result
-}
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