[llvm-branch-commits] [RISCV] Port PreAllocZilsdOpt to NewPM (PR #235513)
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Sun Oct 25 12:26:18 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Aiden Grossman (boomanaiden154)
<details>
<summary>Changes</summary>
Standard NewPM pass porting. Also rename the pass name to match the
class name.
---
Full diff: https://github.com/llvm/llvm-project/pull/235513.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCV.h (+9-2)
- (modified) llvm/lib/Target/RISCV/RISCVPassRegistry.def (+2)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2-2)
- (modified) llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp (+64-23)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 36924db70283d..678729dec60ae 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -266,8 +266,15 @@ class RISCVLoadStoreOptPass
FunctionPass *createRISCVLoadStoreOptLegacyPass();
void initializeRISCVLoadStoreOptLegacyPass(PassRegistry &);
-FunctionPass *createRISCVPreAllocZilsdOptPass();
-void initializeRISCVPreAllocZilsdOptPass(PassRegistry &);
+class RISCVPreAllocZilsdOptPass
+ : public OptionalPassInfoMixin<RISCVPreAllocZilsdOptPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVPreAllocZilsdOptLegacyPass();
+void initializeRISCVPreAllocZilsdOptLegacyPass(PassRegistry &);
class RISCVZacasABIFixPass
: public RequiredPassInfoMixin<RISCVZacasABIFixPass> {
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index 905c3fe29c771..596ec6cbade1c 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -65,4 +65,6 @@ MACHINE_FUNCTION_PASS("riscv-redundant-copy-elimination",
MACHINE_FUNCTION_PASS("riscv-vector-peephole", RISCVVectorPeepholePass())
MACHINE_FUNCTION_PASS("riscv-vl-optimizer", RISCVVLOptimizerPass())
MACHINE_FUNCTION_PASS("risv-vmv0-elimination", RISCVVMV0EliminationPass())
+MACHINE_FUNCTION_PASS("riscv-pre-alloc-zilsd-opt",
+ RISCVPreAllocZilsdOptPass())
#undef MACHINE_FUNCTION_PASS
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index aa91c3de66061..ff3f80b38af7d 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -77,7 +77,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVPushPopOptLegacyPass(*PR);
initializeRISCVIndirectBranchTrackingLegacyPass(*PR);
initializeRISCVLoadStoreOptLegacyPass(*PR);
- initializeRISCVPreAllocZilsdOptPass(*PR);
+ initializeRISCVPreAllocZilsdOptLegacyPass(*PR);
initializeRISCVExpandPseudoAtomicsLegacyPass(*PR);
initializeRISCVRedundantCopyEliminationLegacyPass(*PR);
initializeRISCVAsmPrinterPass(*PR);
@@ -570,7 +570,7 @@ void RISCVPassConfig::addPreRegAlloc() {
if (TM->getOptLevel() != CodeGenOptLevel::None) {
addPass(createRISCVMergeBaseOffsetLegacyPass());
// Add Zilsd pre-allocation load/store optimization
- addPass(createRISCVPreAllocZilsdOptPass());
+ addPass(createRISCVPreAllocZilsdOptLegacyPass());
}
addPass(createRISCVInsertReadWriteCSRLegacyPass());
diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index 6d95d46f92987..11fcc0e8a43ea 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -31,17 +31,20 @@
#include "llvm/CodeGen/MachineBasicBlock.h"
#include "llvm/CodeGen/MachineDominators.h"
#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstr.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachinePassManager.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/IR/Analysis.h"
#include "llvm/InitializePasses.h"
#include "llvm/Support/Debug.h"
#include <algorithm>
using namespace llvm;
-#define DEBUG_TYPE "riscv-zilsd-opt"
+#define DEBUG_TYPE "riscv-pre-alloc-zilsd-opt"
STATISTIC(NumLDFormed, "Number of LD instructions formed");
STATISTIC(NumSDFormed, "Number of SD instructions formed");
@@ -51,11 +54,11 @@ namespace {
//===----------------------------------------------------------------------===//
// Pre-allocation Zilsd optimization pass
//===----------------------------------------------------------------------===//
-class RISCVPreAllocZilsdOpt : public MachineFunctionPass {
+class RISCVPreAllocZilsdOptLegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVPreAllocZilsdOpt() : MachineFunctionPass(ID) {}
+ RISCVPreAllocZilsdOptLegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
@@ -73,6 +76,9 @@ class RISCVPreAllocZilsdOpt : public MachineFunctionPass {
AU.setPreservesCFG();
MachineFunctionPass::getAnalysisUsage(AU);
}
+};
+
+class RISCVPreAllocZilsdOptImpl {
enum class MemoryOffsetKind {
Imm = 0,
Global = 1,
@@ -84,7 +90,6 @@ class RISCVPreAllocZilsdOpt : public MachineFunctionPass {
using MemOffset = std::pair<MemoryOffsetKind, int>;
using BaseRegInfo = std::pair<unsigned, MemoryOffsetKind>;
-private:
bool isMemoryOp(const MachineInstr &MI);
bool rescheduleLoadStoreInstrs(MachineBasicBlock *MBB);
bool canFormLdSdPair(MachineInstr *MI0, MachineInstr *MI1);
@@ -102,27 +107,33 @@ class RISCVPreAllocZilsdOpt : public MachineFunctionPass {
AliasAnalysis *AA;
MachineDominatorTree *DT;
Align RequiredAlign;
+
+public:
+ bool runOnMachineFunction(MachineFunction &MF,
+ function_ref<AliasAnalysis *()> GetAA,
+ function_ref<MachineDominatorTree *()> GetMDT);
};
} // end anonymous namespace
-char RISCVPreAllocZilsdOpt::ID = 0;
+char RISCVPreAllocZilsdOptLegacy::ID = 0;
-INITIALIZE_PASS_BEGIN(RISCVPreAllocZilsdOpt, "riscv-prera-zilsd-opt",
+INITIALIZE_PASS_BEGIN(RISCVPreAllocZilsdOptLegacy, "riscv-prera-zilsd-opt",
"RISC-V pre-allocation Zilsd optimization", false, false)
INITIALIZE_PASS_DEPENDENCY(AAResultsWrapperPass)
INITIALIZE_PASS_DEPENDENCY(MachineDominatorTreeWrapperPass)
-INITIALIZE_PASS_END(RISCVPreAllocZilsdOpt, "riscv-prera-zilsd-opt",
+INITIALIZE_PASS_END(RISCVPreAllocZilsdOptLegacy, "riscv-prera-zilsd-opt",
"RISC-V pre-allocation Zilsd optimization", false, false)
//===----------------------------------------------------------------------===//
// Pre-allocation pass implementation
//===----------------------------------------------------------------------===//
-bool RISCVPreAllocZilsdOpt::runOnMachineFunction(MachineFunction &MF) {
-
+bool RISCVPreAllocZilsdOptImpl::runOnMachineFunction(
+ MachineFunction &MF, function_ref<AliasAnalysis *()> GetAA,
+ function_ref<MachineDominatorTree *()> GetMDT) {
STI = &MF.getSubtarget<RISCVSubtarget>();
- if (!STI->getCLOpts().zilsd_opt || skipFunction(MF.getFunction()))
+ if (!STI->getCLOpts().zilsd_opt)
return false;
// Only run on RV32 with Zilsd extension
@@ -132,8 +143,8 @@ bool RISCVPreAllocZilsdOpt::runOnMachineFunction(MachineFunction &MF) {
TII = STI->getInstrInfo();
TRI = STI->getRegisterInfo();
MRI = &MF.getRegInfo();
- AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
- DT = &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ AA = GetAA();
+ DT = GetMDT();
// Check alignment: default is 8-byte, but allow 4-byte with tune feature
// If unaligned scalar memory is enabled, allow any alignment
@@ -146,8 +157,8 @@ bool RISCVPreAllocZilsdOpt::runOnMachineFunction(MachineFunction &MF) {
return Modified;
}
-RISCVPreAllocZilsdOpt::MemOffset
-RISCVPreAllocZilsdOpt::getMemoryOpOffset(const MachineInstr &MI) {
+RISCVPreAllocZilsdOptImpl::MemOffset
+RISCVPreAllocZilsdOptImpl::getMemoryOpOffset(const MachineInstr &MI) {
switch (MI.getOpcode()) {
case RISCV::LW:
case RISCV::SW: {
@@ -182,8 +193,8 @@ RISCVPreAllocZilsdOpt::getMemoryOpOffset(const MachineInstr &MI) {
return std::make_pair(MemoryOffsetKind::Unknown, 0);
}
-bool RISCVPreAllocZilsdOpt::canFormLdSdPair(MachineInstr *MI0,
- MachineInstr *MI1) {
+bool RISCVPreAllocZilsdOptImpl::canFormLdSdPair(MachineInstr *MI0,
+ MachineInstr *MI1) {
if (!MI0->hasOneMemOperand() || !MI1->hasOneMemOperand())
return false;
@@ -208,8 +219,9 @@ bool RISCVPreAllocZilsdOpt::canFormLdSdPair(MachineInstr *MI0,
return true;
}
-bool RISCVPreAllocZilsdOpt::isSafeToMove(MachineInstr *MI, MachineInstr *Target,
- bool MoveForward) {
+bool RISCVPreAllocZilsdOptImpl::isSafeToMove(MachineInstr *MI,
+ MachineInstr *Target,
+ bool MoveForward) {
MachineBasicBlock *MBB = MI->getParent();
MachineBasicBlock::iterator Start = MI->getIterator();
MachineBasicBlock::iterator End = Target->getIterator();
@@ -271,7 +283,7 @@ bool RISCVPreAllocZilsdOpt::isSafeToMove(MachineInstr *MI, MachineInstr *Target,
return true;
}
-bool RISCVPreAllocZilsdOpt::rescheduleOps(
+bool RISCVPreAllocZilsdOptImpl::rescheduleOps(
MachineBasicBlock *MBB, SmallVectorImpl<MachineInstr *> &MIs,
BaseRegInfo Base, bool IsLoad,
DenseMap<MachineInstr *, unsigned> &MI2LocMap) {
@@ -386,7 +398,7 @@ bool RISCVPreAllocZilsdOpt::rescheduleOps(
return Modified;
}
-bool RISCVPreAllocZilsdOpt::isMemoryOp(const MachineInstr &MI) {
+bool RISCVPreAllocZilsdOptImpl::isMemoryOp(const MachineInstr &MI) {
unsigned Opcode = MI.getOpcode();
if (Opcode != RISCV::LW && Opcode != RISCV::SW)
return false;
@@ -416,7 +428,8 @@ bool RISCVPreAllocZilsdOpt::isMemoryOp(const MachineInstr &MI) {
return true;
}
-bool RISCVPreAllocZilsdOpt::rescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
+bool RISCVPreAllocZilsdOptImpl::rescheduleLoadStoreInstrs(
+ MachineBasicBlock *MBB) {
bool Modified = false;
// Process the basic block in windows delimited by calls, terminators,
@@ -524,6 +537,34 @@ bool RISCVPreAllocZilsdOpt::rescheduleLoadStoreInstrs(MachineBasicBlock *MBB) {
// Pass creation functions
//===----------------------------------------------------------------------===//
-FunctionPass *llvm::createRISCVPreAllocZilsdOptPass() {
- return new RISCVPreAllocZilsdOpt();
+FunctionPass *llvm::createRISCVPreAllocZilsdOptLegacyPass() {
+ return new RISCVPreAllocZilsdOptLegacy();
+}
+
+bool RISCVPreAllocZilsdOptLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+ RISCVPreAllocZilsdOptImpl Impl;
+ return Impl.runOnMachineFunction(
+ MF, [&]() { return &getAnalysis<AAResultsWrapperPass>().getAAResults(); },
+ [&]() {
+ return &getAnalysis<MachineDominatorTreeWrapperPass>().getDomTree();
+ });
+}
+
+PreservedAnalyses
+RISCVPreAllocZilsdOptPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ RISCVPreAllocZilsdOptImpl Impl;
+ bool Changed = Impl.runOnMachineFunction(
+ MF,
+ [&]() {
+ return &MFAM.getResult<FunctionAnalysisManagerMachineFunctionProxy>(MF)
+ .getManager()
+ .getResult<AAManager>(MF.getFunction());
+ },
+ [&]() { return &MFAM.getResult<MachineDominatorTreeAnalysis>(MF); });
+ return Changed ? getMachineFunctionPassPreservedAnalyses()
+ .preserveSet<CFGAnalyses>()
+ : PreservedAnalyses::all();
}
``````````
</details>
https://github.com/llvm/llvm-project/pull/235513
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