[llvm-branch-commits] [RISCV] Port MoveMergePass to NewPM (PR #235504)
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llvm-branch-commits at lists.llvm.org
Sun Oct 25 11:34:01 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Aiden Grossman (boomanaiden154)
<details>
<summary>Changes</summary>
Standard NewPM pass porting. Also note in the LegacyPM that this pass
preserves the CFG.
---
Full diff: https://github.com/llvm/llvm-project/pull/235504.diff
4 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCV.h (+8-2)
- (modified) llvm/lib/Target/RISCV/RISCVMoveMerger.cpp (+72-37)
- (modified) llvm/lib/Target/RISCV/RISCVPassRegistry.def (+1)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2-2)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index b16112a13cd16..4ca09c071be6d 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -238,8 +238,14 @@ class RISCVRedundantCopyEliminationPass
FunctionPass *createRISCVRedundantCopyEliminationLegacyPass();
void initializeRISCVRedundantCopyEliminationLegacyPass(PassRegistry &);
-FunctionPass *createRISCVMoveMergePass();
-void initializeRISCVMoveMergePass(PassRegistry &);
+class RISCVMoveMergePass : public OptionalPassInfoMixin<RISCVMoveMergePass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVMoveMergeLegacyPass();
+void initializeRISCVMoveMergeLegacyPass(PassRegistry &);
FunctionPass *createRISCVPushPopOptimizationPass();
void initializeRISCVPushPopOptPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
index b8e728ce083bc..6419f70eefb23 100644
--- a/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMoveMerger.cpp
@@ -13,19 +13,36 @@
//
//===----------------------------------------------------------------------===//
+#include "RISCV.h"
#include "RISCVInstrInfo.h"
#include "RISCVSubtarget.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
+#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/IR/Analysis.h"
+#include "llvm/Pass.h"
using namespace llvm;
#define RISCV_MOVE_MERGE_NAME "RISC-V Zcmp move merging pass"
namespace {
-struct RISCVMoveMerge : public MachineFunctionPass {
+class RISCVMoveMergeLegacy : public MachineFunctionPass {
+public:
static char ID;
- RISCVMoveMerge() : MachineFunctionPass(ID) {}
+ RISCVMoveMergeLegacy() : MachineFunctionPass(ID) {}
+ bool runOnMachineFunction(MachineFunction &Fn) override;
+
+ StringRef getPassName() const override { return RISCV_MOVE_MERGE_NAME; }
+
+ void getAnalysisUsage(AnalysisUsage &AU) const override {
+ AU.setPreservesCFG();
+ MachineFunctionPass::getAnalysisUsage(AU);
+ }
+};
+class RISCVMoveMergeImpl {
const RISCVSubtarget *ST;
const RISCVInstrInfo *TII;
const TargetRegisterInfo *TRI;
@@ -63,16 +80,16 @@ struct RISCVMoveMerge : public MachineFunctionPass {
MachineBasicBlock::iterator findMatchingPLI(MachineBasicBlock::iterator &MBBI,
bool EvenRegPair);
bool mergeMovePairs(MachineBasicBlock &MBB);
- bool runOnMachineFunction(MachineFunction &Fn) override;
- StringRef getPassName() const override { return RISCV_MOVE_MERGE_NAME; }
+public:
+ bool runOnMachineFunction(MachineFunction &MF);
};
-char RISCVMoveMerge::ID = 0;
+char RISCVMoveMergeLegacy::ID = 0;
} // end of anonymous namespace
-INITIALIZE_PASS(RISCVMoveMerge, "riscv-move-merge", RISCV_MOVE_MERGE_NAME,
+INITIALIZE_PASS(RISCVMoveMergeLegacy, "riscv-move-merge", RISCV_MOVE_MERGE_NAME,
false, false)
static unsigned getCM_MVOpcode(const RISCVSubtarget &ST, bool MoveFromSToA) {
@@ -99,8 +116,8 @@ static unsigned getPairedPLIOpcode(unsigned Opc) {
}
}
-bool RISCVMoveMerge::isGPRPairCopyCandidate(const DestSourcePair &RegPair,
- bool EvenRegPair) {
+bool RISCVMoveMergeImpl::isGPRPairCopyCandidate(const DestSourcePair &RegPair,
+ bool EvenRegPair) {
Register Destination = RegPair.Destination->getReg();
Register Source = RegPair.Source->getReg();
@@ -121,7 +138,8 @@ bool RISCVMoveMerge::isGPRPairCopyCandidate(const DestSourcePair &RegPair,
}
// Check if registers meet CM.MVA01S constraints.
-bool RISCVMoveMerge::isCandidateToMergeMVA01S(const DestSourcePair &RegPair) {
+bool RISCVMoveMergeImpl::isCandidateToMergeMVA01S(
+ const DestSourcePair &RegPair) {
Register Destination = RegPair.Destination->getReg();
Register Source = RegPair.Source->getReg();
// If destination is not a0 or a1.
@@ -133,7 +151,8 @@ bool RISCVMoveMerge::isCandidateToMergeMVA01S(const DestSourcePair &RegPair) {
}
// Check if registers meet CM.MVSA01 constraints.
-bool RISCVMoveMerge::isCandidateToMergeMVSA01(const DestSourcePair &RegPair) {
+bool RISCVMoveMergeImpl::isCandidateToMergeMVSA01(
+ const DestSourcePair &RegPair) {
Register Destination = RegPair.Destination->getReg();
Register Source = RegPair.Source->getReg();
// If Source is s0 - s7.
@@ -146,8 +165,8 @@ bool RISCVMoveMerge::isCandidateToMergeMVSA01(const DestSourcePair &RegPair) {
// Check if MI is a single-reg pli/plui whose destination is a half of a
// GPRPair.
-bool RISCVMoveMerge::isPLIPairCandidate(const MachineInstr &MI,
- bool EvenRegPair) {
+bool RISCVMoveMergeImpl::isPLIPairCandidate(const MachineInstr &MI,
+ bool EvenRegPair) {
if (!ST->hasStdExtP() || ST->is64Bit())
return false;
if (!getPairedPLIOpcode(MI.getOpcode()))
@@ -160,9 +179,9 @@ bool RISCVMoveMerge::isPLIPairCandidate(const MachineInstr &MI,
}
MachineBasicBlock::iterator
-RISCVMoveMerge::mergeGPRPairInsns(MachineBasicBlock::iterator I,
- MachineBasicBlock::iterator Paired,
- bool RegPairIsEven) {
+RISCVMoveMergeImpl::mergeGPRPairInsns(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired,
+ bool RegPairIsEven) {
MachineBasicBlock::iterator E = I->getParent()->end();
MachineBasicBlock::iterator NextI = next_nodbg(I, E);
DestSourcePair FirstPair = *TII->isCopyInstrImpl(*I);
@@ -196,9 +215,9 @@ RISCVMoveMerge::mergeGPRPairInsns(MachineBasicBlock::iterator I,
}
MachineBasicBlock::iterator
-RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,
- MachineBasicBlock::iterator Paired,
- bool MoveFromSToA) {
+RISCVMoveMergeImpl::mergePairedInsns(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired,
+ bool MoveFromSToA) {
const MachineOperand *Sreg1, *Sreg2;
MachineBasicBlock::iterator E = I->getParent()->end();
MachineBasicBlock::iterator NextI = next_nodbg(I, E);
@@ -250,9 +269,9 @@ RISCVMoveMerge::mergePairedInsns(MachineBasicBlock::iterator I,
}
MachineBasicBlock::iterator
-RISCVMoveMerge::mergePLIPair(MachineBasicBlock::iterator I,
- MachineBasicBlock::iterator Paired,
- bool RegPairIsEven) {
+RISCVMoveMergeImpl::mergePLIPair(MachineBasicBlock::iterator I,
+ MachineBasicBlock::iterator Paired,
+ bool RegPairIsEven) {
MachineBasicBlock::iterator E = I->getParent()->end();
MachineBasicBlock::iterator NextI = next_nodbg(I, E);
@@ -275,9 +294,9 @@ RISCVMoveMerge::mergePLIPair(MachineBasicBlock::iterator I,
}
MachineBasicBlock::iterator
-RISCVMoveMerge::findMatchingGPRPairCopy(MachineBasicBlock::iterator &MBBI,
- bool EvenRegPair,
- const DestSourcePair &RegPair) {
+RISCVMoveMergeImpl::findMatchingGPRPairCopy(MachineBasicBlock::iterator &MBBI,
+ bool EvenRegPair,
+ const DestSourcePair &RegPair) {
MachineBasicBlock::iterator E = MBBI->getParent()->end();
ModifiedRegUnits.clear();
UsedRegUnits.clear();
@@ -331,9 +350,9 @@ RISCVMoveMerge::findMatchingGPRPairCopy(MachineBasicBlock::iterator &MBBI,
}
MachineBasicBlock::iterator
-RISCVMoveMerge::findMatchingSACopy(MachineBasicBlock::iterator &MBBI,
- bool MoveFromSToA,
- const DestSourcePair &RegPair) {
+RISCVMoveMergeImpl::findMatchingSACopy(MachineBasicBlock::iterator &MBBI,
+ bool MoveFromSToA,
+ const DestSourcePair &RegPair) {
MachineBasicBlock::iterator E = MBBI->getParent()->end();
// Track which register units have been modified and used between the first
@@ -381,8 +400,8 @@ RISCVMoveMerge::findMatchingSACopy(MachineBasicBlock::iterator &MBBI,
// Look for a same-opcode pli/plui writing the other lane of the same GPRPair
// with the same immediate. Return the matching instruction if one exists.
MachineBasicBlock::iterator
-RISCVMoveMerge::findMatchingPLI(MachineBasicBlock::iterator &MBBI,
- bool EvenRegPair) {
+RISCVMoveMergeImpl::findMatchingPLI(MachineBasicBlock::iterator &MBBI,
+ bool EvenRegPair) {
MachineBasicBlock::iterator E = MBBI->getParent()->end();
ModifiedRegUnits.clear();
UsedRegUnits.clear();
@@ -429,7 +448,7 @@ RISCVMoveMerge::findMatchingPLI(MachineBasicBlock::iterator &MBBI,
// Finds instructions, which could be represented as C.MV instructions and
// merged into CM.MVA01S or CM.MVSA01.
-bool RISCVMoveMerge::mergeMovePairs(MachineBasicBlock &MBB) {
+bool RISCVMoveMergeImpl::mergeMovePairs(MachineBasicBlock &MBB) {
bool Modified = false;
for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
@@ -482,11 +501,8 @@ bool RISCVMoveMerge::mergeMovePairs(MachineBasicBlock &MBB) {
return Modified;
}
-bool RISCVMoveMerge::runOnMachineFunction(MachineFunction &Fn) {
- if (skipFunction(Fn.getFunction()))
- return false;
-
- ST = &Fn.getSubtarget<RISCVSubtarget>();
+bool RISCVMoveMergeImpl::runOnMachineFunction(MachineFunction &MF) {
+ ST = &MF.getSubtarget<RISCVSubtarget>();
bool HasGPRPairCopy =
!ST->is64Bit() && (ST->hasStdExtZdinx() || ST->hasStdExtP());
if (!ST->hasStdExtZcmp() && !ST->hasVendorXqccmp() && !HasGPRPairCopy)
@@ -500,11 +516,30 @@ bool RISCVMoveMerge::runOnMachineFunction(MachineFunction &Fn) {
ModifiedRegUnits.init(*TRI);
UsedRegUnits.init(*TRI);
bool Modified = false;
- for (auto &MBB : Fn)
+ for (auto &MBB : MF)
Modified |= mergeMovePairs(MBB);
return Modified;
}
/// createRISCVMoveMergePass - returns an instance of the
/// move merge pass.
-FunctionPass *llvm::createRISCVMoveMergePass() { return new RISCVMoveMerge(); }
+FunctionPass *llvm::createRISCVMoveMergeLegacyPass() {
+ return new RISCVMoveMergeLegacy();
+}
+
+bool RISCVMoveMergeLegacy::runOnMachineFunction(MachineFunction &MF) {
+ if (skipFunction(MF.getFunction()))
+ return false;
+ RISCVMoveMergeImpl Impl;
+ return Impl.runOnMachineFunction(MF);
+}
+
+PreservedAnalyses
+RISCVMoveMergePass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ RISCVMoveMergeImpl Impl;
+ return Impl.runOnMachineFunction(MF)
+ ? getMachineFunctionPassPreservedAnalyses()
+ .preserveSet<CFGAnalyses>()
+ : PreservedAnalyses::all();
+}
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index b89d5a085bedc..975a335b3d8ef 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -55,6 +55,7 @@ MACHINE_FUNCTION_PASS("riscv-late-branch-opt", RISCVLateBranchOptPass())
MACHINE_FUNCTION_PASS("riscv-lpad-setup", RISCVLandingPadSetupPass())
MACHINE_FUNCTION_PASS("riscv-make-compressible", RISCVMakeCompressiblePass())
MACHINE_FUNCTION_PASS("riscv-merge-base-offset", RISCVMergeBaseOffsetPass())
+MACHINE_FUNCTION_PASS("riscv-move-merge", RISCVMoveMergePass())
MACHINE_FUNCTION_PASS("riscv-opt-w-instrs", RISCVOptWInstrsPass())
MACHINE_FUNCTION_PASS("riscv-qc-relax-marking", RISCVQCRelaxMarkingPass())
MACHINE_FUNCTION_PASS("riscv-redundant-copy-elimination",
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 8451a80655cf2..42c5a25c242d7 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -73,7 +73,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVInsertReadWriteCSRLegacyPass(*PR);
initializeRISCVInsertWriteVXRMLegacyPass(*PR);
initializeRISCVDAGToDAGISelLegacyPass(*PR);
- initializeRISCVMoveMergePass(*PR);
+ initializeRISCVMoveMergeLegacyPass(*PR);
initializeRISCVPushPopOptPass(*PR);
initializeRISCVIndirectBranchTrackingLegacyPass(*PR);
initializeRISCVLoadStoreOptPass(*PR);
@@ -515,7 +515,7 @@ void RISCVPassConfig::addPreEmitPass() {
void RISCVPassConfig::addPreEmitPass2() {
if (TM->getOptLevel() != CodeGenOptLevel::None) {
- addPass(createRISCVMoveMergePass());
+ addPass(createRISCVMoveMergeLegacyPass());
// Schedule PushPop Optimization before expansion of Pseudo instruction,
// ensuring return instruction is detected correctly.
addPass(createRISCVPushPopOptimizationPass());
``````````
</details>
https://github.com/llvm/llvm-project/pull/235504
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