[llvm-branch-commits] [RISCV] Port InsertWriteVXRM to NewPM (PR #235412)

[via llvm-branch-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tools-llvm-exegesis

Author: Aiden Grossman (boomanaiden154)

<details>
<summary>Changes</summary>

Standard NewPM pass porting.


---
Full diff: https://github.com/llvm/llvm-project/pull/235412.diff


5 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCV.h (+9-2) 
- (modified) llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp (+43-18) 
- (modified) llvm/lib/Target/RISCV/RISCVPassRegistry.def (+1) 
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2-2) 
- (modified) llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 8409404a23076..9e1df92cbbf99 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -214,8 +214,15 @@ class RISCVInsertReadWriteCSRPass
 FunctionPass *createRISCVInsertReadWriteCSRLegacyPass();
 void initializeRISCVInsertReadWriteCSRLegacyPass(PassRegistry &);
 
-FunctionPass *createRISCVInsertWriteVXRMPass();
-void initializeRISCVInsertWriteVXRMPass(PassRegistry &);
+class RISCVInsertWriteVXRMPass
+    : public RequiredPassInfoMixin<RISCVInsertWriteVXRMPass> {
+public:
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVInsertWriteVXRMLegacyPass();
+void initializeRISCVInsertWriteVXRMLegacyPass(PassRegistry &);
 
 FunctionPass *createRISCVRedundantCopyEliminationPass();
 void initializeRISCVRedundantCopyEliminationPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp b/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
index c58a5c07a34f7..a2012807061f7 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp
@@ -28,7 +28,10 @@
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "RISCV.h"
 #include "RISCVSubtarget.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/IR/Analysis.h"
 #include <queue>
 
 using namespace llvm;
@@ -191,16 +194,27 @@ struct BlockData {
   BlockData() = default;
 };
 
-class RISCVInsertWriteVXRM : public MachineFunctionPass {
+class RISCVInsertWriteVXRMImpl {
   const TargetInstrInfo *TII;
 
   std::vector<BlockData> BlockInfo;
   std::queue<const MachineBasicBlock *> WorkList;
 
+  bool computeVXRMChanges(const MachineBasicBlock &MBB);
+  void computeAvailable(const MachineBasicBlock &MBB);
+  void computeAnticipated(const MachineFunction &MF,
+                          const MachineBasicBlock &MBB);
+  void emitWriteVXRM(MachineBasicBlock &MBB);
+
+public:
+  bool runOnMachineFunction(MachineFunction &MF);
+};
+
+class RISCVInsertWriteVXRMLegacy : public MachineFunctionPass {
 public:
   static char ID;
 
-  RISCVInsertWriteVXRM() : MachineFunctionPass(ID) {}
+  RISCVInsertWriteVXRMLegacy() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
@@ -212,22 +226,17 @@ class RISCVInsertWriteVXRM : public MachineFunctionPass {
   StringRef getPassName() const override {
     return RISCV_INSERT_WRITE_VXRM_NAME;
   }
-
-private:
-  bool computeVXRMChanges(const MachineBasicBlock &MBB);
-  void computeAvailable(const MachineBasicBlock &MBB);
-  void computeAnticipated(const MachineFunction &MF, const MachineBasicBlock &MBB);
-  void emitWriteVXRM(MachineBasicBlock &MBB);
 };
 
 } // end anonymous namespace
 
-char RISCVInsertWriteVXRM::ID = 0;
+char RISCVInsertWriteVXRMLegacy::ID = 0;
 
-INITIALIZE_PASS(RISCVInsertWriteVXRM, DEBUG_TYPE, RISCV_INSERT_WRITE_VXRM_NAME,
-                false, false)
+INITIALIZE_PASS(RISCVInsertWriteVXRMLegacy, DEBUG_TYPE,
+                RISCV_INSERT_WRITE_VXRM_NAME, false, false)
 
-bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) {
+bool RISCVInsertWriteVXRMImpl::computeVXRMChanges(
+    const MachineBasicBlock &MBB) {
   BlockData &BBInfo = BlockInfo[MBB.getNumber()];
 
   bool NeedVXRMWrite = false;
@@ -256,7 +265,7 @@ bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) {
   return NeedVXRMWrite;
 }
 
-void RISCVInsertWriteVXRM::computeAvailable(const MachineBasicBlock &MBB) {
+void RISCVInsertWriteVXRMImpl::computeAvailable(const MachineBasicBlock &MBB) {
   BlockData &BBInfo = BlockInfo[MBB.getNumber()];
 
   BBInfo.InQueue = false;
@@ -298,7 +307,8 @@ void RISCVInsertWriteVXRM::computeAvailable(const MachineBasicBlock &MBB) {
   }
 }
 
-void RISCVInsertWriteVXRM::computeAnticipated(const MachineFunction &MF, const MachineBasicBlock &MBB) {
+void RISCVInsertWriteVXRMImpl::computeAnticipated(
+    const MachineFunction &MF, const MachineBasicBlock &MBB) {
   BlockData &BBInfo = BlockInfo[MBB.getNumber()];
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
 
@@ -347,7 +357,7 @@ void RISCVInsertWriteVXRM::computeAnticipated(const MachineFunction &MF, const M
   }
 }
 
-void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) {
+void RISCVInsertWriteVXRMImpl::emitWriteVXRM(MachineBasicBlock &MBB) {
   const BlockData &BBInfo = BlockInfo[MBB.getNumber()];
 
   VXRMInfo Info = BBInfo.AvailableIn;
@@ -437,7 +447,7 @@ void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) {
   }
 }
 
-bool RISCVInsertWriteVXRM::runOnMachineFunction(MachineFunction &MF) {
+bool RISCVInsertWriteVXRMImpl::runOnMachineFunction(MachineFunction &MF) {
   // Skip if the vector extension is not enabled.
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
   if (!ST.hasVInstructions())
@@ -489,6 +499,21 @@ bool RISCVInsertWriteVXRM::runOnMachineFunction(MachineFunction &MF) {
   return true;
 }
 
-FunctionPass *llvm::createRISCVInsertWriteVXRMPass() {
-  return new RISCVInsertWriteVXRM();
+FunctionPass *llvm::createRISCVInsertWriteVXRMLegacyPass() {
+  return new RISCVInsertWriteVXRMLegacy();
+}
+
+bool RISCVInsertWriteVXRMLegacy::runOnMachineFunction(MachineFunction &MF) {
+  RISCVInsertWriteVXRMImpl Impl;
+  return Impl.runOnMachineFunction(MF);
+}
+
+PreservedAnalyses
+RISCVInsertWriteVXRMPass::run(MachineFunction &MF,
+                              MachineFunctionAnalysisManager &MFAM) {
+  RISCVInsertWriteVXRMImpl Impl;
+  return Impl.runOnMachineFunction(MF)
+             ? getMachineFunctionPassPreservedAnalyses()
+                   .preserveSet<CFGAnalyses>()
+             : PreservedAnalyses::all();
 }
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index 1d8787ad7643d..b6003a9c29f02 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -49,6 +49,7 @@ MACHINE_FUNCTION_PASS("riscv-indirect-branch-tracking",
 MACHINE_FUNCTION_PASS("riscv-insert-read-write-csr",
                       RISCVInsertReadWriteCSRPass())
 MACHINE_FUNCTION_PASS("riscv-insert-vsetvli", RISCVInsertVSETVLIPass())
+MACHINE_FUNCTION_PASS("riscv-insert-write-vxrm", RISCVInsertWriteVXRMPass())
 MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
 MACHINE_FUNCTION_PASS("riscv-late-branch-opt", RISCVLateBranchOptPass())
 MACHINE_FUNCTION_PASS("riscv-lpad-setup", RISCVLandingPadSetupPass())
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 16c8bca119be2..394014d6c1e7c 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -71,7 +71,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   initializeRISCVVMV0EliminationLegacyPass(*PR);
   initializeRISCVInsertVSETVLILegacyPass(*PR);
   initializeRISCVInsertReadWriteCSRLegacyPass(*PR);
-  initializeRISCVInsertWriteVXRMPass(*PR);
+  initializeRISCVInsertWriteVXRMLegacyPass(*PR);
   initializeRISCVDAGToDAGISelLegacyPass(*PR);
   initializeRISCVMoveMergePass(*PR);
   initializeRISCVPushPopOptPass(*PR);
@@ -574,7 +574,7 @@ void RISCVPassConfig::addPreRegAlloc() {
   }
 
   addPass(createRISCVInsertReadWriteCSRLegacyPass());
-  addPass(createRISCVInsertWriteVXRMPass());
+  addPass(createRISCVInsertWriteVXRMLegacyPass());
   addPass(createRISCVLandingPadSetupLegacyPass());
 
   if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_pipeliner)
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 8743a12f6a79e..ca7ddd1ab0a69 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -742,7 +742,7 @@ class ExegesisRISCVTarget : public ExegesisTarget {
     PM.add(createRISCVInsertVSETVLILegacyPass());
     // Setting up the correct FRM.
     PM.add(createRISCVInsertReadWriteCSRLegacyPass());
-    PM.add(createRISCVInsertWriteVXRMPass());
+    PM.add(createRISCVInsertWriteVXRMLegacyPass());
     // This will assign physical register to the result of VSETVLI instructions
     // that produce VLMAX.
     PM.add(exegesis::createRISCVPostprocessingPass());

``````````

</details>


https://github.com/llvm/llvm-project/pull/235412