[llvm-branch-commits] [RISCV] Port RISCVInsertReadWriteCSR to NewPM (PR #235409)

[via llvm-branch-commits]

llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-tools-llvm-exegesis

Author: Aiden Grossman (boomanaiden154)

<details>
<summary>Changes</summary>

Standard NewPM pass porting. Plumb TII through static helper functions
given an Impl class seems overkill for this purpose.


---
Full diff: https://github.com/llvm/llvm-project/pull/235409.diff


5 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCV.h (+9-2) 
- (modified) llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp (+30-18) 
- (modified) llvm/lib/Target/RISCV/RISCVPassRegistry.def (+2) 
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+2-2) 
- (modified) llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp (+1-1) 


``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 42145c031ee2c..8409404a23076 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -204,8 +204,15 @@ FunctionPass *createRISCVInsertVSETVLILegacyPass();
 void initializeRISCVInsertVSETVLILegacyPass(PassRegistry &);
 extern char &RISCVInsertVSETVLILegacyID;
 
-FunctionPass *createRISCVInsertReadWriteCSRPass();
-void initializeRISCVInsertReadWriteCSRPass(PassRegistry &);
+class RISCVInsertReadWriteCSRPass
+    : public RequiredPassInfoMixin<RISCVInsertReadWriteCSRPass> {
+public:
+  PreservedAnalyses run(MachineFunction &MF,
+                        MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVInsertReadWriteCSRLegacyPass();
+void initializeRISCVInsertReadWriteCSRLegacyPass(PassRegistry &);
 
 FunctionPass *createRISCVInsertWriteVXRMPass();
 void initializeRISCVInsertWriteVXRMPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
index c565928afd509..50905bed72483 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp
@@ -17,7 +17,10 @@
 #include "MCTargetDesc/RISCVBaseInfo.h"
 #include "RISCV.h"
 #include "RISCVSubtarget.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/IR/Analysis.h"
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-insert-read-write-csr"
@@ -25,13 +28,11 @@ using namespace llvm;
 
 namespace {
 
-class RISCVInsertReadWriteCSR : public MachineFunctionPass {
-  const TargetInstrInfo *TII;
-
+class RISCVInsertReadWriteCSRLegacy : public MachineFunctionPass {
 public:
   static char ID;
 
-  RISCVInsertReadWriteCSR() : MachineFunctionPass(ID) {}
+  RISCVInsertReadWriteCSRLegacy() : MachineFunctionPass(ID) {}
 
   bool runOnMachineFunction(MachineFunction &MF) override;
 
@@ -43,21 +44,18 @@ class RISCVInsertReadWriteCSR : public MachineFunctionPass {
   StringRef getPassName() const override {
     return RISCV_INSERT_READ_WRITE_CSR_NAME;
   }
-
-private:
-  bool emitWriteRoundingMode(MachineBasicBlock &MBB);
-  bool emitWriteRoundingModeOpt(MachineBasicBlock &MBB);
 };
 
 } // end anonymous namespace
 
-char RISCVInsertReadWriteCSR::ID = 0;
+char RISCVInsertReadWriteCSRLegacy::ID = 0;
 
-INITIALIZE_PASS(RISCVInsertReadWriteCSR, DEBUG_TYPE,
+INITIALIZE_PASS(RISCVInsertReadWriteCSRLegacy, DEBUG_TYPE,
                 RISCV_INSERT_READ_WRITE_CSR_NAME, false, false)
 
 // TODO: Use more accurate rounding mode at the start of MBB.
-bool RISCVInsertReadWriteCSR::emitWriteRoundingModeOpt(MachineBasicBlock &MBB) {
+static bool emitWriteRoundingModeOpt(MachineBasicBlock &MBB,
+                                     const TargetInstrInfo *TII) {
   bool Changed = false;
   MachineInstr *LastFRMChanger = nullptr;
   unsigned CurrentRM = RISCVFPRndMode::DYN;
@@ -135,7 +133,8 @@ bool RISCVInsertReadWriteCSR::emitWriteRoundingModeOpt(MachineBasicBlock &MBB) {
 
 // This function also swaps frm and restores it when encountering an RVV
 // floating point instruction with a static rounding mode.
-bool RISCVInsertReadWriteCSR::emitWriteRoundingMode(MachineBasicBlock &MBB) {
+static bool emitWriteRoundingMode(MachineBasicBlock &MBB,
+                                  const TargetInstrInfo *TII) {
   bool Changed = false;
   for (MachineInstr &MI : MBB) {
     int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc());
@@ -167,26 +166,39 @@ bool RISCVInsertReadWriteCSR::emitWriteRoundingMode(MachineBasicBlock &MBB) {
   return Changed;
 }
 
-bool RISCVInsertReadWriteCSR::runOnMachineFunction(MachineFunction &MF) {
+static bool insertReadWriteCSROnMachineFunction(MachineFunction &MF) {
   // Skip if the vector extension is not enabled.
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
   if (!ST.hasVInstructions())
     return false;
 
-  TII = ST.getInstrInfo();
+  const TargetInstrInfo *TII = ST.getInstrInfo();
 
   bool Changed = false;
 
   for (MachineBasicBlock &MBB : MF) {
     if (!ST.getCLOpts().frm_insert_opt)
-      Changed |= emitWriteRoundingMode(MBB);
+      Changed |= emitWriteRoundingMode(MBB, TII);
     else
-      Changed |= emitWriteRoundingModeOpt(MBB);
+      Changed |= emitWriteRoundingModeOpt(MBB, TII);
   }
 
   return Changed;
 }
 
-FunctionPass *llvm::createRISCVInsertReadWriteCSRPass() {
-  return new RISCVInsertReadWriteCSR();
+FunctionPass *llvm::createRISCVInsertReadWriteCSRLegacyPass() {
+  return new RISCVInsertReadWriteCSRLegacy();
+}
+
+bool RISCVInsertReadWriteCSRLegacy::runOnMachineFunction(MachineFunction &MF) {
+  return insertReadWriteCSROnMachineFunction(MF);
+}
+
+PreservedAnalyses
+RISCVInsertReadWriteCSRPass::run(MachineFunction &MF,
+                                 MachineFunctionAnalysisManager &MFAM) {
+  return insertReadWriteCSROnMachineFunction(MF)
+             ? getMachineFunctionPassPreservedAnalyses()
+                   .preserveSet<CFGAnalyses>()
+             : PreservedAnalyses::all();
 }
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index 42a12818db6e0..1d8787ad7643d 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -46,6 +46,8 @@ MACHINE_FUNCTION_PASS("riscv-expand-pseudo-pre-ra",
 MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
 MACHINE_FUNCTION_PASS("riscv-indirect-branch-tracking",
                       RISCVIndirectBranchTrackingPass())
+MACHINE_FUNCTION_PASS("riscv-insert-read-write-csr",
+                      RISCVInsertReadWriteCSRPass())
 MACHINE_FUNCTION_PASS("riscv-insert-vsetvli", RISCVInsertVSETVLIPass())
 MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
 MACHINE_FUNCTION_PASS("riscv-late-branch-opt", RISCVLateBranchOptPass())
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index 62a2e76347bd0..16c8bca119be2 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -70,7 +70,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
   initializeRISCVVLOptimizerLegacyPass(*PR);
   initializeRISCVVMV0EliminationLegacyPass(*PR);
   initializeRISCVInsertVSETVLILegacyPass(*PR);
-  initializeRISCVInsertReadWriteCSRPass(*PR);
+  initializeRISCVInsertReadWriteCSRLegacyPass(*PR);
   initializeRISCVInsertWriteVXRMPass(*PR);
   initializeRISCVDAGToDAGISelLegacyPass(*PR);
   initializeRISCVMoveMergePass(*PR);
@@ -573,7 +573,7 @@ void RISCVPassConfig::addPreRegAlloc() {
     addPass(createRISCVPreAllocZilsdOptPass());
   }
 
-  addPass(createRISCVInsertReadWriteCSRPass());
+  addPass(createRISCVInsertReadWriteCSRLegacyPass());
   addPass(createRISCVInsertWriteVXRMPass());
   addPass(createRISCVLandingPadSetupLegacyPass());
 
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 2ade1277f2009..8743a12f6a79e 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -741,7 +741,7 @@ class ExegesisRISCVTarget : public ExegesisTarget {
     PM.add(exegesis::createRISCVPreprocessingPass());
     PM.add(createRISCVInsertVSETVLILegacyPass());
     // Setting up the correct FRM.
-    PM.add(createRISCVInsertReadWriteCSRPass());
+    PM.add(createRISCVInsertReadWriteCSRLegacyPass());
     PM.add(createRISCVInsertWriteVXRMPass());
     // This will assign physical register to the result of VSETVLI instructions
     // that produce VLMAX.

``````````

</details>


https://github.com/llvm/llvm-project/pull/235409