[llvm-branch-commits] [RISCV] Port RISCVInsertVSETVLI to NewPM (PR #235407)
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Sat Oct 24 23:52:55 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-tools-llvm-exegesis
Author: Aiden Grossman (boomanaiden154)
<details>
<summary>Changes</summary>
Standard NewPM pass porting. Use an Impl class to avoid teasing out all
the state in the original pass class.
---
Full diff: https://github.com/llvm/llvm-project/pull/235407.diff
5 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCV.h (+10-3)
- (modified) llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp (+78-46)
- (modified) llvm/lib/Target/RISCV/RISCVPassRegistry.def (+1)
- (modified) llvm/lib/Target/RISCV/RISCVTargetMachine.cpp (+3-3)
- (modified) llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp (+1-1)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h
index 88017ff92327ad..42145c031ee2c5 100644
--- a/llvm/lib/Target/RISCV/RISCV.h
+++ b/llvm/lib/Target/RISCV/RISCV.h
@@ -193,9 +193,16 @@ class RISCVExpandPseudoAtomicsPass
FunctionPass *createRISCVExpandPseudoAtomicsLegacyPass();
void initializeRISCVExpandPseudoAtomicsLegacyPass(PassRegistry &);
-FunctionPass *createRISCVInsertVSETVLIPass();
-void initializeRISCVInsertVSETVLIPass(PassRegistry &);
-extern char &RISCVInsertVSETVLIID;
+class RISCVInsertVSETVLIPass
+ : public RequiredPassInfoMixin<RISCVInsertVSETVLIPass> {
+public:
+ PreservedAnalyses run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM);
+};
+
+FunctionPass *createRISCVInsertVSETVLILegacyPass();
+void initializeRISCVInsertVSETVLILegacyPass(PassRegistry &);
+extern char &RISCVInsertVSETVLILegacyID;
FunctionPass *createRISCVInsertReadWriteCSRPass();
void initializeRISCVInsertReadWriteCSRPass(PassRegistry &);
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 19c6465c2acf40..77c0b52f1c4e8b 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -32,7 +32,11 @@
#include "llvm/CodeGen/LiveDebugVariables.h"
#include "llvm/CodeGen/LiveIntervals.h"
#include "llvm/CodeGen/LiveStacks.h"
+#include "llvm/CodeGen/MachineFunctionAnalysisManager.h"
#include "llvm/CodeGen/MachineFunctionPass.h"
+#include "llvm/CodeGen/MachinePassManager.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/IR/Analysis.h"
#include <queue>
using namespace llvm;
using namespace RISCV;
@@ -82,21 +86,11 @@ enum TKTMMode {
VSETTM = 1,
};
-class RISCVInsertVSETVLI : public MachineFunctionPass {
- const RISCVSubtarget *ST;
- const TargetInstrInfo *TII;
- MachineRegisterInfo *MRI;
- // Possibly null!
- LiveIntervals *LIS;
- RISCVVSETVLIInfoAnalysis VIA;
-
- std::vector<BlockData> BlockInfo;
- std::queue<const MachineBasicBlock *> WorkList;
-
+class RISCVInsertVSETVLILegacy : public MachineFunctionPass {
public:
static char ID;
- RISCVInsertVSETVLI() : MachineFunctionPass(ID) {}
+ RISCVInsertVSETVLILegacy() : MachineFunctionPass(ID) {}
bool runOnMachineFunction(MachineFunction &MF) override;
void getAnalysisUsage(AnalysisUsage &AU) const override {
@@ -112,8 +106,19 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
}
StringRef getPassName() const override { return RISCV_INSERT_VSETVLI_NAME; }
+};
+
+class RISCVInsertVSETVLIImpl {
+ const RISCVSubtarget *ST;
+ const TargetInstrInfo *TII;
+ MachineRegisterInfo *MRI;
+ // Possibly null!
+ LiveIntervals *LIS;
+ RISCVVSETVLIInfoAnalysis VIA;
+
+ std::vector<BlockData> BlockInfo;
+ std::queue<const MachineBasicBlock *> WorkList;
-private:
bool needVSETVLI(const DemandedFields &Used, const VSETVLIInfo &Require,
const VSETVLIInfo &CurInfo) const;
bool needVSETVLIPHI(const VSETVLIInfo &Require,
@@ -139,20 +144,23 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
const MachineInstr &MI) const;
void coalesceVSETVLIsForTWiden(MachineBasicBlock &MBB) const;
bool insertVSETMTK(MachineBasicBlock &MBB, TKTMMode Mode) const;
+
+public:
+ bool runOnMachineFunction(MachineFunction &MF, LiveIntervals *LISToUpdate);
};
} // end anonymous namespace
-char RISCVInsertVSETVLI::ID = 0;
-char &llvm::RISCVInsertVSETVLIID = RISCVInsertVSETVLI::ID;
+char RISCVInsertVSETVLILegacy::ID = 0;
+char &llvm::RISCVInsertVSETVLILegacyID = RISCVInsertVSETVLILegacy::ID;
-INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
+INITIALIZE_PASS(RISCVInsertVSETVLILegacy, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME,
false, false)
-void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator InsertPt,
- DebugLoc DL, const VSETVLIInfo &Info,
- const VSETVLIInfo &PrevInfo) {
+void RISCVInsertVSETVLIImpl::insertVSETVLI(MachineBasicBlock &MBB,
+ MachineBasicBlock::iterator InsertPt,
+ DebugLoc DL, const VSETVLIInfo &Info,
+ const VSETVLIInfo &PrevInfo) {
++NumInsertedVSETVL;
if (PrevInfo.isKnown()) {
@@ -262,9 +270,9 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
/// Return true if a VSETVLI is required to transition from CurInfo to Require
/// given a set of DemandedFields \p Used.
-bool RISCVInsertVSETVLI::needVSETVLI(const DemandedFields &Used,
- const VSETVLIInfo &Require,
- const VSETVLIInfo &CurInfo) const {
+bool RISCVInsertVSETVLIImpl::needVSETVLI(const DemandedFields &Used,
+ const VSETVLIInfo &Require,
+ const VSETVLIInfo &CurInfo) const {
if (!CurInfo.isKnown() || CurInfo.hasSEWLMULRatioOnly())
return true;
@@ -295,8 +303,8 @@ static VSETVLIInfo adjustIncoming(const VSETVLIInfo &PrevInfo,
// Given an incoming state reaching MI, minimally modifies that state so that it
// is compatible with MI. The resulting state is guaranteed to be semantically
// legal for MI, but may not be the state requested by MI.
-void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
- const MachineInstr &MI) const {
+void RISCVInsertVSETVLIImpl::transferBefore(VSETVLIInfo &Info,
+ const MachineInstr &MI) const {
if (ST->getCLOpts().insert_vsetvli_whole_vector_register_move_valid_vtype &&
RISCV::isVectorCopy(ST->getRegisterInfo(), MI) &&
(!Info.isKnown() || Info.hasSEWLMULRatioOnly())) {
@@ -366,8 +374,8 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info,
// Given a state with which we evaluated MI (see transferBefore above for why
// this might be different that the state MI requested), modify the state to
// reflect the changes MI might make.
-void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
- const MachineInstr &MI) const {
+void RISCVInsertVSETVLIImpl::transferAfter(VSETVLIInfo &Info,
+ const MachineInstr &MI) const {
if (RISCVInstrInfo::isVectorConfigInstr(MI)) {
Info = VIA.getInfoForVSETVLI(MI);
return;
@@ -401,8 +409,8 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info,
Info = VSETVLIInfo::getUnknown();
}
-bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB,
- VSETVLIInfo &Info) const {
+bool RISCVInsertVSETVLIImpl::computeVLVTYPEChanges(const MachineBasicBlock &MBB,
+ VSETVLIInfo &Info) const {
bool HadVectorOp = false;
Info = BlockInfo[MBB.getNumber()].Pred;
@@ -421,7 +429,8 @@ bool RISCVInsertVSETVLI::computeVLVTYPEChanges(const MachineBasicBlock &MBB,
return HadVectorOp;
}
-void RISCVInsertVSETVLI::computeIncomingVLVTYPE(const MachineBasicBlock &MBB) {
+void RISCVInsertVSETVLIImpl::computeIncomingVLVTYPE(
+ const MachineBasicBlock &MBB) {
BlockData &BBInfo = BlockInfo[MBB.getNumber()];
@@ -478,8 +487,8 @@ void RISCVInsertVSETVLI::computeIncomingVLVTYPE(const MachineBasicBlock &MBB) {
// If we weren't able to prove a vsetvli was directly unneeded, it might still
// be unneeded if the AVL was a phi node where all incoming values are VL
// outputs from the last VSETVLI in their respective basic blocks.
-bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
- const MachineBasicBlock &MBB) const {
+bool RISCVInsertVSETVLIImpl::needVSETVLIPHI(
+ const VSETVLIInfo &Require, const MachineBasicBlock &MBB) const {
if (!Require.hasAVLReg())
return true;
@@ -522,7 +531,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require,
return false;
}
-void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
+void RISCVInsertVSETVLIImpl::emitVSETVLIs(MachineBasicBlock &MBB) {
VSETVLIInfo CurInfo = BlockInfo[MBB.getNumber()].Pred;
// Track whether the prefix of the block we've scanned is transparent
// (meaning has not yet changed the abstract state).
@@ -644,7 +653,7 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) {
/// beginning of one block to the end of one of its predecessors. Specifically,
/// this is geared to catch the common case of a fixed length vsetvl in a single
/// block loop when it could execute once in the preheader instead.
-void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
+void RISCVInsertVSETVLIImpl::doPRE(MachineBasicBlock &MBB) {
if (!BlockInfo[MBB.getNumber()].Pred.isUnknown())
return;
@@ -746,7 +755,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) {
// fields which would be observed.
// If AVLDefToMove is non-null after the call, it points to an ADDI
// instruction that needs to be moved before PrevMI.
-bool RISCVInsertVSETVLI::canMutatePriorConfig(
+bool RISCVInsertVSETVLIImpl::canMutatePriorConfig(
const MachineInstr &PrevMI, const MachineInstr &MI,
const DemandedFields &Used, MachineInstr *&AVLDefToMove) const {
AVLDefToMove = nullptr;
@@ -807,7 +816,7 @@ bool RISCVInsertVSETVLI::canMutatePriorConfig(
return areCompatibleVTYPEs(PriorVType, VType, Used);
}
-void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
+void RISCVInsertVSETVLIImpl::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
MachineInstr *NextMI = nullptr;
// We can have arbitrary code in successors, so VL and VTYPE
// must be considered demanded.
@@ -960,7 +969,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
// ...
// VSETVLTNT %avl, type2
//
-bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
+bool RISCVInsertVSETVLIImpl::canMutatePriorConfigWithTWiden(
const MachineInstr &PrevMI, const MachineInstr &MI) const {
if (PrevMI.getOpcode() != RISCV::PseudoVSETVLI)
@@ -1016,7 +1025,7 @@ bool RISCVInsertVSETVLI::canMutatePriorConfigWithTWiden(
return true;
}
-void RISCVInsertVSETVLI::coalesceVSETVLIsForTWiden(
+void RISCVInsertVSETVLIImpl::coalesceVSETVLIsForTWiden(
MachineBasicBlock &MBB) const {
MachineInstr *NextMI = nullptr;
@@ -1041,7 +1050,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIsForTWiden(
}
}
-void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
+void RISCVInsertVSETVLIImpl::insertReadVL(MachineBasicBlock &MBB) {
for (auto I = MBB.begin(), E = MBB.end(); I != E;) {
MachineInstr &MI = *I++;
if (RISCVInstrInfo::isFaultOnlyFirstLoad(MI)) {
@@ -1068,8 +1077,8 @@ void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) {
}
}
-bool RISCVInsertVSETVLI::insertVSETMTK(MachineBasicBlock &MBB,
- TKTMMode Mode) const {
+bool RISCVInsertVSETVLIImpl::insertVSETMTK(MachineBasicBlock &MBB,
+ TKTMMode Mode) const {
bool Changed = false;
for (auto &MI : MBB) {
@@ -1124,7 +1133,8 @@ bool RISCVInsertVSETVLI::insertVSETMTK(MachineBasicBlock &MBB,
return Changed;
}
-bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
+bool RISCVInsertVSETVLIImpl::runOnMachineFunction(MachineFunction &MF,
+ LiveIntervals *LISToUpdate) {
// Skip if the vector extension is not enabled.
ST = &MF.getSubtarget<RISCVSubtarget>();
if (!ST->hasVInstructions())
@@ -1134,8 +1144,7 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
TII = ST->getInstrInfo();
MRI = &MF.getRegInfo();
- auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
- LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
+ LIS = LISToUpdate;
VIA = RISCVVSETVLIInfoAnalysis(ST, LIS);
assert(BlockInfo.empty() && "Expect empty block infos");
@@ -1219,6 +1228,29 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) {
}
/// Returns an instance of the Insert VSETVLI pass.
-FunctionPass *llvm::createRISCVInsertVSETVLIPass() {
- return new RISCVInsertVSETVLI();
+FunctionPass *llvm::createRISCVInsertVSETVLILegacyPass() {
+ return new RISCVInsertVSETVLILegacy();
+}
+
+bool RISCVInsertVSETVLILegacy::runOnMachineFunction(MachineFunction &MF) {
+ RISCVInsertVSETVLIImpl Impl;
+ auto *LISWrapper = getAnalysisIfAvailable<LiveIntervalsWrapperPass>();
+ LiveIntervals *LIS = LISWrapper ? &LISWrapper->getLIS() : nullptr;
+ return Impl.runOnMachineFunction(MF, LIS);
+}
+
+PreservedAnalyses
+RISCVInsertVSETVLIPass::run(MachineFunction &MF,
+ MachineFunctionAnalysisManager &MFAM) {
+ RISCVInsertVSETVLIImpl Impl;
+ LiveIntervals *LIS = MFAM.getCachedResult<LiveIntervalsAnalysis>(MF);
+ bool Changed = Impl.runOnMachineFunction(MF, LIS);
+ if (!Changed)
+ return PreservedAnalyses::all();
+ return getMachineFunctionPassPreservedAnalyses()
+ .preserveSet<CFGAnalyses>()
+ .preserve<LiveIntervalsAnalysis>()
+ .preserve<SlotIndexesAnalysis>()
+ .preserve<LiveDebugVariablesAnalysis>()
+ .preserve<LiveStacksAnalysis>();
}
diff --git a/llvm/lib/Target/RISCV/RISCVPassRegistry.def b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
index 85427b64dd8c59..42a12818db6e0c 100644
--- a/llvm/lib/Target/RISCV/RISCVPassRegistry.def
+++ b/llvm/lib/Target/RISCV/RISCVPassRegistry.def
@@ -46,6 +46,7 @@ MACHINE_FUNCTION_PASS("riscv-expand-pseudo-pre-ra",
MACHINE_FUNCTION_PASS("riscv-fold-mem-offset", RISCVFoldMemOffsetPass())
MACHINE_FUNCTION_PASS("riscv-indirect-branch-tracking",
RISCVIndirectBranchTrackingPass())
+MACHINE_FUNCTION_PASS("riscv-insert-vsetvli", RISCVInsertVSETVLIPass())
MACHINE_FUNCTION_PASS("riscv-isel", RISCVISelDAGToDAGPass(*this, getOptLevel()))
MACHINE_FUNCTION_PASS("riscv-late-branch-opt", RISCVLateBranchOptPass())
MACHINE_FUNCTION_PASS("riscv-lpad-setup", RISCVLandingPadSetupPass())
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index c3905b82f229b5..62a2e76347bd04 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -69,7 +69,7 @@ extern "C" LLVM_ABI LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() {
initializeRISCVVectorPeepholeLegacyPass(*PR);
initializeRISCVVLOptimizerLegacyPass(*PR);
initializeRISCVVMV0EliminationLegacyPass(*PR);
- initializeRISCVInsertVSETVLIPass(*PR);
+ initializeRISCVInsertVSETVLILegacyPass(*PR);
initializeRISCVInsertReadWriteCSRPass(*PR);
initializeRISCVInsertWriteVXRMPass(*PR);
initializeRISCVDAGToDAGISelLegacyPass(*PR);
@@ -382,7 +382,7 @@ FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) {
bool RISCVPassConfig::addRegAssignAndRewriteFast() {
addPass(createRVVRegAllocPass(false));
- addPass(createRISCVInsertVSETVLIPass());
+ addPass(createRISCVInsertVSETVLILegacyPass());
if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_dead_defs)
addPass(createRISCVDeadRegisterDefinitionsLegacyPass());
return TargetPassConfig::addRegAssignAndRewriteFast();
@@ -391,7 +391,7 @@ bool RISCVPassConfig::addRegAssignAndRewriteFast() {
bool RISCVPassConfig::addRegAssignAndRewriteOptimized() {
addPass(createRVVRegAllocPass(true));
addPass(createVirtRegRewriter(false));
- addPass(createRISCVInsertVSETVLIPass());
+ addPass(createRISCVInsertVSETVLILegacyPass());
if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_dead_defs)
addPass(createRISCVDeadRegisterDefinitionsLegacyPass());
return TargetPassConfig::addRegAssignAndRewriteOptimized();
diff --git a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
index 8dbfc4268513a0..2ade1277f20090 100644
--- a/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
+++ b/llvm/tools/llvm-exegesis/lib/RISCV/Target.cpp
@@ -739,7 +739,7 @@ class ExegesisRISCVTarget : public ExegesisTarget {
void addTargetSpecificPasses(PassManagerBase &PM) const override {
// Turn AVL operand of physical registers into virtual registers.
PM.add(exegesis::createRISCVPreprocessingPass());
- PM.add(createRISCVInsertVSETVLIPass());
+ PM.add(createRISCVInsertVSETVLILegacyPass());
// Setting up the correct FRM.
PM.add(createRISCVInsertReadWriteCSRPass());
PM.add(createRISCVInsertWriteVXRMPass());
``````````
</details>
https://github.com/llvm/llvm-project/pull/235407
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