[llvm-branch-commits] [llvm] [AMDGPU] Use addressable arch VGPR count for CFI. NFC (PR #235335)

[Chinmay Deshpande via llvm-branch-commits]

https://github.com/chinmaydd created https://github.com/llvm/llvm-project/pull/235335

`emitPrologueEntryCFI` assumed 1024 arch VGPRs on targets with VGPR MSBs, regardless of wave size.

In wave64 only 512 are addressable, and VGPRs above that have no DWARF number. Use
`getAddressableNumArchVGPRs`, as whole wave function handling already does.

>From c2f08a09ca745c97deed82ce685c30989355d8a5 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Sat, 24 Oct 2026 13:51:19 -0400
Subject: [PATCH] [AMDGPU] Use addressable arch VGPR count for CFI

emitPrologueEntryCFI assumed 1024 arch VGPRs on targets with VGPR
MSBs, regardless of wave size. In wave64 only 512 are addressable, and
VGPRs above that have no DWARF number. Use
getAddressableNumArchVGPRs, as whole wave function handling already
does.

No upstream target with VGPR MSBs supports wave64. NFC.

Change-Id: Ic65c4bb284e8583395bbe98ceeccd0f46b877538
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/lib/Target/AMDGPU/SIFrameLowering.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
index 0356f6351600f..4aea4c4ec41d9 100644
--- a/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFrameLowering.cpp
@@ -1131,7 +1131,7 @@ void SIFrameLowering::emitPrologueEntryCFI(MachineBasicBlock &MBB,
   };
 
   // Emit CFI rules for caller saved Arch VGPRs which are clobbered
-  unsigned NumArchVGPRs = ST.hasVGPRMSBs() ? 1024 : 256;
+  unsigned NumArchVGPRs = ST.getAddressableNumArchVGPRs();
   for_each(AMDGPU::VGPR_32RegClass.getRegisters().take_front(NumArchVGPRs),
            ProcessReg);