[llvm-branch-commits] [llvm] [AMDGPU] Derive addressable VGPRs from encoding width (PR #235332)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Chinmay Deshpande (chinmaydd)

<details>
<summary>Changes</summary>

The addressable VGPR count is bounded by both the operand encoding width and the register file size. 

Compute it as the smaller of the two instead of listing per-target values. Wave64 on targets with VGPR MSBs was already `min(1024, 512)`. NFC.

---
Full diff: https://github.com/llvm/llvm-project/pull/235332.diff


1 Files Affected:

- (modified) llvm/lib/TargetParser/AMDGPUTargetParser.cpp (+7-2) 


``````````diff
diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
index 0428fc524a628..72ef675af1ccb 100644
--- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
@@ -458,9 +458,14 @@ unsigned AMDGPU::getAddressableNumVGPRs(GPUKind AK, bool IsWave32) {
   // The unified register file makes the AGPRs addressable as VGPRs.
   if (Features.test(FEAT_GFX90A_INSTS))
     return 512;
+
+  // VGPR operand fields are 8 bits; VGPR MSBs add 2 more per operand.
+  constexpr unsigned OperandBits = 8;
+  constexpr unsigned MSBBits = 2;
+  unsigned Bits = OperandBits;
   if (Features.test(FEAT_VGPR_MSBS))
-    return IsWave32 ? 1024 : 512;
-  return 256;
+    Bits += MSBBits;
+  return std::min(1u << Bits, getTotalNumVGPRs(AK, IsWave32));
 }
 
 unsigned AMDGPU::getAddressableNumVGPRs(Triple::SubArchType SubArch,

``````````

</details>


https://github.com/llvm/llvm-project/pull/235332