[llvm-branch-commits] [llvm] [AMDGPU] Derive addressable VGPRs from encoding width (PR #235332)

[Chinmay Deshpande via llvm-branch-commits]

https://github.com/chinmaydd created https://github.com/llvm/llvm-project/pull/235332

The addressable VGPR count is bounded by both the operand encoding width and the register file size. 

Compute it as the smaller of the two instead of listing per-target values. Wave64 on targets with VGPR MSBs was already `min(1024, 512)`. NFC.

>From 0a4d73046db157f5cc4b06a906a1d1f6768b3993 Mon Sep 17 00:00:00 2001
From: Chinmay Deshpande <chdeshpa at amd.com>
Date: Sat, 24 Oct 2026 13:38:39 -0400
Subject: [PATCH] [AMDGPU] Derive addressable VGPRs from encoding width

The addressable VGPR count is bounded by both the operand encoding
width and the register file size. Compute it as the smaller of the two
instead of listing per-target values. Wave64 on targets with VGPR MSBs
was already min(1024, 512). NFC.

Change-Id: Ia0e030a9005fb2e915ef09e4ac7fd5ded22ab9b2
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/lib/TargetParser/AMDGPUTargetParser.cpp | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
index 0428fc524a628..72ef675af1ccb 100644
--- a/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
+++ b/llvm/lib/TargetParser/AMDGPUTargetParser.cpp
@@ -458,9 +458,14 @@ unsigned AMDGPU::getAddressableNumVGPRs(GPUKind AK, bool IsWave32) {
   // The unified register file makes the AGPRs addressable as VGPRs.
   if (Features.test(FEAT_GFX90A_INSTS))
     return 512;
+
+  // VGPR operand fields are 8 bits; VGPR MSBs add 2 more per operand.
+  constexpr unsigned OperandBits = 8;
+  constexpr unsigned MSBBits = 2;
+  unsigned Bits = OperandBits;
   if (Features.test(FEAT_VGPR_MSBS))
-    return IsWave32 ? 1024 : 512;
-  return 256;
+    Bits += MSBBits;
+  return std::min(1u << Bits, getTotalNumVGPRs(AK, IsWave32));
 }
 
 unsigned AMDGPU::getAddressableNumVGPRs(Triple::SubArchType SubArch,