[llvm-branch-commits] [SLP][NFC]Add a test with incorrect vectorization, NFC (PR #235285)
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llvm-branch-commits at lists.llvm.org
Sat Oct 24 05:11:31 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
Author: Alexey Bataev (alexey-bataev)
<details>
<summary>Changes</summary>
---
Full diff: https://github.com/llvm/llvm-project/pull/235285.diff
1 Files Affected:
- (added) llvm/test/Transforms/SLPVectorizer/X86/bit-test-narrowed-samesign.ll (+178)
``````````diff
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bit-test-narrowed-samesign.ll b/llvm/test/Transforms/SLPVectorizer/X86/bit-test-narrowed-samesign.ll
new file mode 100644
index 0000000000000..55beaeb6ee0c2
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/X86/bit-test-narrowed-samesign.ll
@@ -0,0 +1,178 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
+
+define void @samesign_ne_sext_mask_sign_bit(ptr noalias %pa, ptr noalias %dst) {
+; CHECK-LABEL: define void @samesign_ne_sext_mask_sign_bit(
+; CHECK-SAME: ptr noalias [[PA:%.*]], ptr noalias [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[PA]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i8> [[TMP0]], <i8 -128, i8 -128, i8 -128, i8 1>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp samesign ne <4 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> splat (i32 3), <4 x i32> splat (i32 5)
+; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[DST]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %pa1 = getelementptr i8, ptr %pa, i64 1
+ %pa2 = getelementptr i8, ptr %pa, i64 2
+ %pa3 = getelementptr i8, ptr %pa, i64 3
+ %a0 = load i8, ptr %pa, align 1
+ %a1 = load i8, ptr %pa1, align 1
+ %a2 = load i8, ptr %pa2, align 1
+ %a3 = load i8, ptr %pa3, align 1
+ %A0 = sext i8 %a0 to i32
+ %A1 = sext i8 %a1 to i32
+ %A2 = sext i8 %a2 to i32
+ %A3 = sext i8 %a3 to i32
+ %m0 = and i32 %A0, 128
+ %m1 = and i32 %A1, 128
+ %m2 = and i32 %A2, 128
+ %c0 = icmp samesign ne i32 %m0, 0
+ %c1 = icmp samesign ne i32 %m1, 0
+ %c2 = icmp samesign ne i32 %m2, 0
+ %c3 = trunc i32 %A3 to i1
+ %s0 = select i1 %c0, i32 3, i32 5
+ %s1 = select i1 %c1, i32 3, i32 5
+ %s2 = select i1 %c2, i32 3, i32 5
+ %s3 = select i1 %c3, i32 3, i32 5
+ %pd1 = getelementptr i32, ptr %dst, i64 1
+ %pd2 = getelementptr i32, ptr %dst, i64 2
+ %pd3 = getelementptr i32, ptr %dst, i64 3
+ store i32 %s0, ptr %dst, align 4
+ store i32 %s1, ptr %pd1, align 4
+ store i32 %s2, ptr %pd2, align 4
+ store i32 %s3, ptr %pd3, align 4
+ ret void
+}
+
+define void @samesign_eq_sext_mask_sign_bit(ptr noalias %pa, ptr noalias %dst) {
+; CHECK-LABEL: define void @samesign_eq_sext_mask_sign_bit(
+; CHECK-SAME: ptr noalias [[PA:%.*]], ptr noalias [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[PA]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i8> [[TMP0]], <i8 -128, i8 -128, i8 -128, i8 1>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp samesign eq <4 x i8> [[TMP1]], <i8 0, i8 0, i8 0, i8 1>
+; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> splat (i32 3), <4 x i32> splat (i32 5)
+; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[DST]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %pa1 = getelementptr i8, ptr %pa, i64 1
+ %pa2 = getelementptr i8, ptr %pa, i64 2
+ %pa3 = getelementptr i8, ptr %pa, i64 3
+ %a0 = load i8, ptr %pa, align 1
+ %a1 = load i8, ptr %pa1, align 1
+ %a2 = load i8, ptr %pa2, align 1
+ %a3 = load i8, ptr %pa3, align 1
+ %A0 = sext i8 %a0 to i32
+ %A1 = sext i8 %a1 to i32
+ %A2 = sext i8 %a2 to i32
+ %A3 = sext i8 %a3 to i32
+ %m0 = and i32 %A0, 128
+ %m1 = and i32 %A1, 128
+ %m2 = and i32 %A2, 128
+ %c0 = icmp samesign eq i32 %m0, 0
+ %c1 = icmp samesign eq i32 %m1, 0
+ %c2 = icmp samesign eq i32 %m2, 0
+ %c3 = trunc i32 %A3 to i1
+ %s0 = select i1 %c0, i32 3, i32 5
+ %s1 = select i1 %c1, i32 3, i32 5
+ %s2 = select i1 %c2, i32 3, i32 5
+ %s3 = select i1 %c3, i32 3, i32 5
+ %pd1 = getelementptr i32, ptr %dst, i64 1
+ %pd2 = getelementptr i32, ptr %dst, i64 2
+ %pd3 = getelementptr i32, ptr %dst, i64 3
+ store i32 %s0, ptr %dst, align 4
+ store i32 %s1, ptr %pd1, align 4
+ store i32 %s2, ptr %pd2, align 4
+ store i32 %s3, ptr %pd3, align 4
+ ret void
+}
+
+define void @samesign_ne_sext_mask_non_sign_bit(ptr noalias %pa, ptr noalias %dst) {
+; CHECK-LABEL: define void @samesign_ne_sext_mask_non_sign_bit(
+; CHECK-SAME: ptr noalias [[PA:%.*]], ptr noalias [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[PA]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i8> [[TMP0]], <i8 64, i8 64, i8 64, i8 1>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp samesign ne <4 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> splat (i32 3), <4 x i32> splat (i32 5)
+; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[DST]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %pa1 = getelementptr i8, ptr %pa, i64 1
+ %pa2 = getelementptr i8, ptr %pa, i64 2
+ %pa3 = getelementptr i8, ptr %pa, i64 3
+ %a0 = load i8, ptr %pa, align 1
+ %a1 = load i8, ptr %pa1, align 1
+ %a2 = load i8, ptr %pa2, align 1
+ %a3 = load i8, ptr %pa3, align 1
+ %A0 = sext i8 %a0 to i32
+ %A1 = sext i8 %a1 to i32
+ %A2 = sext i8 %a2 to i32
+ %A3 = sext i8 %a3 to i32
+ %m0 = and i32 %A0, 64
+ %m1 = and i32 %A1, 64
+ %m2 = and i32 %A2, 64
+ %c0 = icmp samesign ne i32 %m0, 0
+ %c1 = icmp samesign ne i32 %m1, 0
+ %c2 = icmp samesign ne i32 %m2, 0
+ %c3 = trunc i32 %A3 to i1
+ %s0 = select i1 %c0, i32 3, i32 5
+ %s1 = select i1 %c1, i32 3, i32 5
+ %s2 = select i1 %c2, i32 3, i32 5
+ %s3 = select i1 %c3, i32 3, i32 5
+ %pd1 = getelementptr i32, ptr %dst, i64 1
+ %pd2 = getelementptr i32, ptr %dst, i64 2
+ %pd3 = getelementptr i32, ptr %dst, i64 3
+ store i32 %s0, ptr %dst, align 4
+ store i32 %s1, ptr %pd1, align 4
+ store i32 %s2, ptr %pd2, align 4
+ store i32 %s3, ptr %pd3, align 4
+ ret void
+}
+
+define void @samesign_ne_zext_mask_sign_bit(ptr noalias %pa, ptr noalias %dst) {
+; CHECK-LABEL: define void @samesign_ne_zext_mask_sign_bit(
+; CHECK-SAME: ptr noalias [[PA:%.*]], ptr noalias [[DST:%.*]]) {
+; CHECK-NEXT: [[ENTRY:.*:]]
+; CHECK-NEXT: [[TMP0:%.*]] = load <4 x i8>, ptr [[PA]], align 1
+; CHECK-NEXT: [[TMP1:%.*]] = and <4 x i8> [[TMP0]], <i8 -128, i8 -128, i8 -128, i8 1>
+; CHECK-NEXT: [[TMP2:%.*]] = icmp ne <4 x i8> [[TMP1]], zeroinitializer
+; CHECK-NEXT: [[TMP3:%.*]] = select <4 x i1> [[TMP2]], <4 x i32> splat (i32 3), <4 x i32> splat (i32 5)
+; CHECK-NEXT: store <4 x i32> [[TMP3]], ptr [[DST]], align 4
+; CHECK-NEXT: ret void
+;
+entry:
+ %pa1 = getelementptr i8, ptr %pa, i64 1
+ %pa2 = getelementptr i8, ptr %pa, i64 2
+ %pa3 = getelementptr i8, ptr %pa, i64 3
+ %a0 = load i8, ptr %pa, align 1
+ %a1 = load i8, ptr %pa1, align 1
+ %a2 = load i8, ptr %pa2, align 1
+ %a3 = load i8, ptr %pa3, align 1
+ %A0 = zext i8 %a0 to i32
+ %A1 = zext i8 %a1 to i32
+ %A2 = zext i8 %a2 to i32
+ %A3 = zext i8 %a3 to i32
+ %m0 = and i32 %A0, 128
+ %m1 = and i32 %A1, 128
+ %m2 = and i32 %A2, 128
+ %c0 = icmp samesign ne i32 %m0, 0
+ %c1 = icmp samesign ne i32 %m1, 0
+ %c2 = icmp samesign ne i32 %m2, 0
+ %c3 = trunc i32 %A3 to i1
+ %s0 = select i1 %c0, i32 3, i32 5
+ %s1 = select i1 %c1, i32 3, i32 5
+ %s2 = select i1 %c2, i32 3, i32 5
+ %s3 = select i1 %c3, i32 3, i32 5
+ %pd1 = getelementptr i32, ptr %dst, i64 1
+ %pd2 = getelementptr i32, ptr %dst, i64 2
+ %pd3 = getelementptr i32, ptr %dst, i64 3
+ store i32 %s0, ptr %dst, align 4
+ store i32 %s1, ptr %pd1, align 4
+ store i32 %s2, ptr %pd2, align 4
+ store i32 %s3, ptr %pd3, align 4
+ ret void
+}
``````````
</details>
https://github.com/llvm/llvm-project/pull/235285
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