[llvm-branch-commits] [llvm] SystemZ: Replace AEXT128/ZEXT128/PAIR128 pseudos with patterns (PR #234297)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Oct 22 22:12:31 PDT 2026
https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/234297
>From d511349ce8e70309191fe8e6726d702062f38fca Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 11 Oct 2026 20:29:22 +0200
Subject: [PATCH 1/2] SystemZ: Replace AEXT128/ZEXT128/PAIR128 pseudos with
patterns
These pseudos only existed because GR128 values were untyped, so the
REG_SEQUENCE they expand to could not be written as a pattern. Now that
GR128 holds v2i64, select the extensions with REG_SEQUENCE output
patterns, and build GR128 pairs with a PAIR128 target node instead of a
custom inserter.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
.../Target/SystemZ/SystemZISelLowering.cpp | 59 +------------------
llvm/lib/Target/SystemZ/SystemZISelLowering.h | 4 --
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 44 +++++++-------
llvm/lib/Target/SystemZ/SystemZOperators.td | 3 +
llvm/test/CodeGen/SystemZ/int-div-01.ll | 3 +-
llvm/test/CodeGen/SystemZ/int-div-03.ll | 6 +-
llvm/test/CodeGen/SystemZ/int-div-04.ll | 6 +-
llvm/test/CodeGen/SystemZ/int-mul-08.ll | 3 +-
llvm/test/CodeGen/SystemZ/multiselect-02.mir | 13 ++--
.../SystemZ/regcoal_remat_empty_subrange.ll | 14 ++---
10 files changed, 48 insertions(+), 107 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index dd0368bc2569a8..c23bcc9d87deba 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -2034,8 +2034,7 @@ static SDValue lowerI128ToGR128(SelectionDAG &DAG, SDValue In) {
std::tie(Lo, Hi) = DAG.SplitScalar(In, DL, MVT::i64, MVT::i64);
}
- SDNode *Pair = DAG.getMachineNode(SystemZ::PAIR128, DL, MVT::v2i64, Hi, Lo);
- return SDValue(Pair, 0);
+ return DAG.getNode(SystemZISD::PAIR128, DL, MVT::v2i64, Hi, Lo);
}
static SDValue lowerGR128ToI128(SelectionDAG &DAG, SDValue In) {
@@ -10580,56 +10579,6 @@ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
return DoneMBB;
}
-// Emit a move from two GR64s to a GR128.
-MachineBasicBlock *
-SystemZTargetLowering::emitPair128(MachineInstr &MI,
- MachineBasicBlock *MBB) const {
- const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
- const DebugLoc &DL = MI.getDebugLoc();
-
- Register Dest = MI.getOperand(0).getReg();
- BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::REG_SEQUENCE), Dest)
- .add(MI.getOperand(1))
- .addImm(SystemZ::subreg_h64)
- .add(MI.getOperand(2))
- .addImm(SystemZ::subreg_l64);
- MI.eraseFromParent();
- return MBB;
-}
-
-// Emit an extension from a GR64 to a GR128. ClearEven is true
-// if the high register of the GR128 value must be cleared or false if
-// it's "don't care".
-MachineBasicBlock *SystemZTargetLowering::emitExt128(MachineInstr &MI,
- MachineBasicBlock *MBB,
- bool ClearEven) const {
- MachineFunction &MF = *MBB->getParent();
- const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
- MachineRegisterInfo &MRI = MF.getRegInfo();
- DebugLoc DL = MI.getDebugLoc();
-
- Register Dest = MI.getOperand(0).getReg();
- Register Src = MI.getOperand(1).getReg();
- Register In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
-
- BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
- if (ClearEven) {
- Register NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
- Register Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
-
- BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
- .addImm(0);
- BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
- .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
- In128 = NewIn128;
- }
- BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
- .addReg(In128).addReg(Src).addImm(SystemZ::subreg_l64);
-
- MI.eraseFromParent();
- return MBB;
-}
-
MachineBasicBlock *
SystemZTargetLowering::emitMemMemWrapper(MachineInstr &MI,
MachineBasicBlock *MBB,
@@ -11345,12 +11294,6 @@ MachineBasicBlock *SystemZTargetLowering::EmitInstrWithCustomInserter(
case SystemZ::UCmp128Hi:
return emitICmp128Hi(MI, MBB, true);
- case SystemZ::PAIR128:
- return emitPair128(MI, MBB);
- case SystemZ::AEXT128:
- return emitExt128(MI, MBB, false);
- case SystemZ::ZEXT128:
- return emitExt128(MI, MBB, true);
case SystemZ::ATOMIC_SWAPW:
return emitAtomicLoadBinary(MI, MBB, 0);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.h b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
index 59ab1c893d229d..d90a8b9c7ff095 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.h
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.h
@@ -431,10 +431,6 @@ class SystemZTargetLowering : public TargetLowering {
bool Invert) const;
MachineBasicBlock *emitICmp128Hi(MachineInstr &MI, MachineBasicBlock *BB,
bool Unsigned) const;
- MachineBasicBlock *emitPair128(MachineInstr &MI,
- MachineBasicBlock *MBB) const;
- MachineBasicBlock *emitExt128(MachineInstr &MI, MachineBasicBlock *MBB,
- bool ClearEven) const;
MachineBasicBlock *emitAtomicLoadBinary(MachineInstr &MI,
MachineBasicBlock *BB,
unsigned BinOpcode,
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 02d5a1f21219a1..48c0d5fd82fe99 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -441,9 +441,6 @@ let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>;
}
-let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
- def PAIR128 : Pseudo<(outs GR128:$dst), (ins GR64:$hi, GR64:$lo), []>;
-
// Immediate moves.
let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
// 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
@@ -832,9 +829,14 @@ let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;
}
-// Extend GR64s to GR128s.
-let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
- def ZEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
+def : Pat<(z_pair128 GR64:$hi, GR64:$lo),
+ (REG_SEQUENCE GR128Bit, GR64:$hi, subreg_h64, GR64:$lo, subreg_l64)>;
+
+// Extend a GR64 to a GR128.
+def zext128 : OutPatFrag<(ops node:$op),
+ (v2i64 (REG_SEQUENCE GR128Bit,
+ (i64 (LLILL 0)), subreg_h64,
+ $op, subreg_l64))>;
//===----------------------------------------------------------------------===//
// "Any" extensions
@@ -844,9 +846,11 @@ let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
def : Pat<(i64 (anyext GR32:$src)),
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_l32)>;
-// Extend GR64s to GR128s.
-let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in
- def AEXT128 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
+// Extend a GR64 to a GR128, leaving the high part undefined.
+def aext128 : OutPatFrag<(ops node:$op),
+ (v2i64 (REG_SEQUENCE GR128Bit, (
+ i64 (IMPLICIT_DEF)), subreg_h64,
+ $op, subreg_l64))>;
//===----------------------------------------------------------------------===//
// Truncations
@@ -1519,7 +1523,7 @@ def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>;
def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2),
(MGRK GR64:$src1, GR64:$src2)>;
def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2),
- (MLGR (AEXT128 GR64:$src1), GR64:$src2)>;
+ (MLGR (aext128 GR64:$src1), GR64:$src2)>;
// Multiplication of memory, producing two results.
def M : BinaryRX <"m", 0x5C, null_frag, GR128, z_load, 4>;
@@ -1530,9 +1534,9 @@ def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, z_load, 4>;
def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, z_load, 8>;
def : Pat<(z_smul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),
- (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
+ (MG (aext128 GR64:$src1), bdxaddr20only:$src2)>;
def : Pat<(z_umul_lohi GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),
- (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
+ (MLG (aext128 GR64:$src1), bdxaddr20only:$src2)>;
//===----------------------------------------------------------------------===//
// Division and remainder
@@ -1554,24 +1558,24 @@ let hasSideEffects = 1 in { // Do not speculatively execute.
def DLG : BinaryRXY<"dlg", 0xE387, null_frag, GR128, z_load, 8>;
}
def : Pat<(z_sdivrem GR64:$src1, GR32:$src2),
- (DSGFR (AEXT128 GR64:$src1), GR32:$src2)>;
+ (DSGFR (aext128 GR64:$src1), GR32:$src2)>;
def : Pat<(z_sdivrem GR64:$src1, (i32 (z_load bdxaddr20only:$src2))),
- (DSGF (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
+ (DSGF (aext128 GR64:$src1), bdxaddr20only:$src2)>;
def : Pat<(z_sdivrem GR64:$src1, GR64:$src2),
- (DSGR (AEXT128 GR64:$src1), GR64:$src2)>;
+ (DSGR (aext128 GR64:$src1), GR64:$src2)>;
def : Pat<(z_sdivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),
- (DSG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>;
+ (DSG (aext128 GR64:$src1), bdxaddr20only:$src2)>;
def : Pat<(z_udivrem GR32:$src1, GR32:$src2),
- (DLR (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
+ (DLR (zext128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
subreg_l32)), GR32:$src2)>;
def : Pat<(z_udivrem GR32:$src1, (i32 (z_load bdxaddr20only:$src2))),
- (DL (ZEXT128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
+ (DL (zext128 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src1,
subreg_l32)), bdxaddr20only:$src2)>;
def : Pat<(z_udivrem GR64:$src1, GR64:$src2),
- (DLGR (ZEXT128 GR64:$src1), GR64:$src2)>;
+ (DLGR (zext128 GR64:$src1), GR64:$src2)>;
def : Pat<(z_udivrem GR64:$src1, (i64 (z_load bdxaddr20only:$src2))),
- (DLG (ZEXT128 GR64:$src1), bdxaddr20only:$src2)>;
+ (DLG (zext128 GR64:$src1), bdxaddr20only:$src2)>;
//===----------------------------------------------------------------------===//
// Shifts
diff --git a/llvm/lib/Target/SystemZ/SystemZOperators.td b/llvm/lib/Target/SystemZ/SystemZOperators.td
index 6c02c1973c0879..7e52a019a10420 100644
--- a/llvm/lib/Target/SystemZ/SystemZOperators.td
+++ b/llvm/lib/Target/SystemZ/SystemZOperators.td
@@ -372,6 +372,9 @@ def z_umul_lohi : SDNode<"SystemZISD::UMUL_LOHI", SDT_ZGR128Binary>;
def z_sdivrem : SDNode<"SystemZISD::SDIVREM", SDT_ZGR128Binary>;
def z_udivrem : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>;
+// Create a GR128 from two i64 GPRs. The first operand is the high part.
+def z_pair128 : SDNode<"SystemZISD::PAIR128", SDT_ZJoinDwords>;
+
// Add/subtract with overflow/carry. These have the same operands as
// the corresponding standard operations, except with the carry flag
// replaced by a condition code value.
diff --git a/llvm/test/CodeGen/SystemZ/int-div-01.ll b/llvm/test/CodeGen/SystemZ/int-div-01.ll
index 6bc7fb80dbeb99..880074e7f5e60f 100644
--- a/llvm/test/CodeGen/SystemZ/int-div-01.ll
+++ b/llvm/test/CodeGen/SystemZ/int-div-01.ll
@@ -51,8 +51,7 @@ define i32 @f4(i32 %dummy, i32 signext %a, i32 %b) {
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4
; CHECK-NOT: dsgfr
-; CHECK: or %r3, %r2
-; CHECK: lr %r2, %r3
+; CHECK: or %r2, %r3
; CHECK: br %r14
%div = sdiv i32 %a, %b
%rem = srem i32 %a, %b
diff --git a/llvm/test/CodeGen/SystemZ/int-div-03.ll b/llvm/test/CodeGen/SystemZ/int-div-03.ll
index 0567c10c453cff..01085a8b20caf9 100644
--- a/llvm/test/CodeGen/SystemZ/int-div-03.ll
+++ b/llvm/test/CodeGen/SystemZ/int-div-03.ll
@@ -36,8 +36,7 @@ define i64 @f3(i64 %dummy, i64 %a, i32 %b) {
; CHECK-LABEL: f3:
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgfr %r2, %r4
-; CHECK: ogr %r3, %r2
-; CHECK: lgr %r2, %r3
+; CHECK: ogr %r2, %r3
; CHECK: br %r14
%bext = sext i32 %b to i64
%div = sdiv i64 %a, %bext
@@ -103,8 +102,7 @@ define i64 @f8(i64 %dummy, i64 %a, ptr %src) {
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgf %r2, 0(%r4)
; CHECK-NOT: {{dsgf|dsgfr}}
-; CHECK: ogr %r3, %r2
-; CHECK: lgr %r2, %r3
+; CHECK: ogr %r2, %r3
; CHECK: br %r14
%b = load i32, ptr %src
%bext = sext i32 %b to i64
diff --git a/llvm/test/CodeGen/SystemZ/int-div-04.ll b/llvm/test/CodeGen/SystemZ/int-div-04.ll
index 840423e91d3496..2f72ba52fa99ad 100644
--- a/llvm/test/CodeGen/SystemZ/int-div-04.ll
+++ b/llvm/test/CodeGen/SystemZ/int-div-04.ll
@@ -34,8 +34,7 @@ define i64 @f3(i64 %dummy1, i64 %a, i64 %b) {
; CHECK-NOT: {{%r[234]}}
; CHECK: dsgr %r2, %r4
; CHECK-NOT: dsgr
-; CHECK: ogr %r3, %r2
-; CHECK: lgr %r2, %r3
+; CHECK: ogr %r2, %r3
; CHECK: br %r14
%div = sdiv i64 %a, %b
%rem = srem i64 %a, %b
@@ -75,8 +74,7 @@ define i64 @f6(i64 %dummy, i64 %a, ptr %src) {
; CHECK-NOT: {{%r[234]}}
; CHECK: dsg %r2, 0(%r4)
; CHECK-NOT: {{dsg|dsgr}}
-; CHECK: ogr %r3, %r2
-; CHECK: lgr %r2, %r3
+; CHECK: ogr %r2, %r3
; CHECK: br %r14
%b = load i64, ptr %src
%div = sdiv i64 %a, %b
diff --git a/llvm/test/CodeGen/SystemZ/int-mul-08.ll b/llvm/test/CodeGen/SystemZ/int-mul-08.ll
index ca100f24eb73b3..11b39ec937e731 100644
--- a/llvm/test/CodeGen/SystemZ/int-mul-08.ll
+++ b/llvm/test/CodeGen/SystemZ/int-mul-08.ll
@@ -60,8 +60,7 @@ define i64 @f4(i64 %dummy, i64 %a, i64 %b) {
; CHECK-LABEL: f4:
; CHECK-NOT: {{%r[234]}}
; CHECK: mlgr %r2, %r4
-; CHECK: ogr %r3, %r2
-; CHECK: lgr %r2, %r3
+; CHECK: ogr %r2, %r3
; CHECK: br %r14
%ax = zext i64 %a to i128
%bx = zext i64 %b to i128
diff --git a/llvm/test/CodeGen/SystemZ/multiselect-02.mir b/llvm/test/CodeGen/SystemZ/multiselect-02.mir
index 92dd2776366599..b9fb586aedefa2 100644
--- a/llvm/test/CodeGen/SystemZ/multiselect-02.mir
+++ b/llvm/test/CodeGen/SystemZ/multiselect-02.mir
@@ -3,12 +3,12 @@
# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z10 -passes=finalize-isel -o - %s \
# RUN: | FileCheck %s
#
-# Test that an instruction (ZEXT128) that uses custom insertion gets treated
-# correctly also when it lies between two Select instructions that could
-# potentially be handled together.
+# Test that an instruction (ADJCALLSTACKDOWN) that uses custom insertion gets
+# treated correctly also when it lies between two Select instructions that
+# could potentially be handled together.
#
# CHECK-LABEL: bb.0.entry:
-# CHECK-NOT: ZEXT128
+# CHECK-NOT: ADJCALLSTACKDOWN
--- |
declare void @bar(i32)
@@ -27,7 +27,9 @@ body: |
%5:gr32bit = LHI 128
%7:gr64bit = IMPLICIT_DEF
%6:gr64bit = INSERT_SUBREG %7, killed %5, %subreg.subreg_l32
- %8:gr128bit = ZEXT128 killed %6
+ ADJCALLSTACKDOWN 0, 0
+ %16:gr64bit = LLILL 0
+ %8:gr128bit = REG_SEQUENCE killed %16, %subreg.subreg_h64, killed %6, %subreg.subreg_l64
%10:addr64bit = IMPLICIT_DEF
%9:gr128bit = DL %8, %10, 0, $noreg :: (load (s32) from `ptr undef` + 4)
%11:gr32bit = COPY %9.subreg_l32
@@ -36,7 +38,6 @@ body: |
%14:gr64bit = Select64 killed %13, killed %12, 14, 8, implicit $cc
CR %4, %11, implicit-def $cc
%15:gr32bit = Select32 %11, %4, 14, 4, implicit $cc
- ADJCALLSTACKDOWN 0, 0
$r2d = COPY %14
CallBRASL @bar, $r2d, csr_systemz_elf, implicit-def dead $r14d, implicit-def dead $cc, implicit $fpc
ADJCALLSTACKUP 0, 0
diff --git a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
index ff9b6a34c1d534..4aed997398b783 100644
--- a/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
+++ b/llvm/test/CodeGen/SystemZ/regcoal_remat_empty_subrange.ll
@@ -15,16 +15,16 @@ define void @main(i16 %in) {
; CHECK-LABEL: main:
; CHECK: # %bb.0:
; CHECK-NEXT: lhr %r2, %r2
-; CHECK-NEXT: larl %r1, g_151
-; CHECK-NEXT: lghi %r3, 0
+; CHECK-NEXT: larl %r3, g_151
+; CHECK-NEXT: lghi %r1, 0
; CHECK-NEXT: chi %r2, 0
; CHECK-NEXT: lhi %r0, 1
-; CHECK-NEXT: locghile %r3, 1
-; CHECK-NEXT: o %r0, 0(%r1)
-; CHECK-NEXT: larl %r1, g_222
-; CHECK-NEXT: dsgfr %r2, %r0
+; CHECK-NEXT: locghile %r1, 1
+; CHECK-NEXT: o %r0, 0(%r3)
; CHECK-NEXT: lghi %r3, 0
-; CHECK-NEXT: stgrl %r2, g_39
+; CHECK-NEXT: dsgfr %r0, %r0
+; CHECK-NEXT: larl %r1, g_222
+; CHECK-NEXT: stgrl %r0, g_39
; CHECK-NEXT: stc %r3, 19(%r1)
; CHECK-NEXT: br %r14
%tmp = load i32, ptr @g_151, align 4
>From 8d915ce0948ee15d7f36097e3fdb9ee9f5b94362 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 22 Oct 2026 15:50:59 -0700
Subject: [PATCH 2/2] SystemZ: Move z_pair128 pattern to the moves section
Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.td | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
index 48c0d5fd82fe99..5b670683475b23 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.td
@@ -441,6 +441,9 @@ let Defs = [CC], CCValues = 0xE, CompareZeroCCMask = 0xE in {
def LTGR : UnaryRRE<"ltgr", 0xB902, null_frag, GR64, GR64>;
}
+def : Pat<(z_pair128 GR64:$hi, GR64:$lo),
+ (REG_SEQUENCE GR128Bit, GR64:$hi, subreg_h64, GR64:$lo, subreg_l64)>;
+
// Immediate moves.
let isAsCheapAsAMove = 1, isMoveImm = 1, isReMaterializable = 1 in {
// 16-bit sign-extended immediates. LHIMux expands to LHI or IIHF,
@@ -829,9 +832,6 @@ let Predicates = [FeatureLoadAndTrap], hasSideEffects = 1 in {
def LLGTAT : UnaryRXY<"llgtat", 0xE39C, null_frag, GR64, 4>;
}
-def : Pat<(z_pair128 GR64:$hi, GR64:$lo),
- (REG_SEQUENCE GR128Bit, GR64:$hi, subreg_h64, GR64:$lo, subreg_l64)>;
-
// Extend a GR64 to a GR128.
def zext128 : OutPatFrag<(ops node:$op),
(v2i64 (REG_SEQUENCE GR128Bit,
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