[llvm-branch-commits] [llvm] [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms (PR #232526)

[via llvm-branch-commits]

================
@@ -25661,8 +25693,7 @@ static SDValue performIntrinsicCombine(SDNode *N,
   case Intrinsic::aarch64_sve_subr:
     return convertMergedOpToPredOp(N, ISD::SUB, DAG, true, true);
   case Intrinsic::aarch64_sve_and_u:
-    return DAG.getNode(ISD::AND, SDLoc(N), N->getValueType(0), N->getOperand(2),
-                       N->getOperand(3));
+    return performSVEAndUIntrinsicCombine(N, DAG);
----------------
CarolineConcatto wrote:

So, maybe the best solution would be to lower this to a target ISDNode, something like: 
AArch64ISD::AND_U
So we create a patterns for that cases where we can replace by BIC and we also add:
  case AArch64ISD::AND_U:
    return DAG.getNode(ISD::AND, SDLoc(N), N->getValueType(0),
                       N->getOperand(1), N->getOperand(2));
For when it is not able to use bic. 


https://github.com/llvm/llvm-project/pull/232526