[llvm-branch-commits] [clang] [llvm] [AArch64][llvm] Add support for FEAT_FPv2 (PR #231436)

[Martin Wehking via llvm-branch-commits]

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@@ -6311,6 +6311,107 @@ multiclass sve_fp_2op_p_pd<bits<3> opc, string asm,
 }
 
 
+//===----------------------------------------------------------------------===//
+// SVE Floating Point Compare - Total Order
+//===----------------------------------------------------------------------===//
+
+class sve_fp_3op_u_pd<bits<2> sz, bits<3> opc, string asm, ZPRRegOp zprty,
+                      PPRRegOp pprty>
+: I<(outs pprty:$Pd), (ins  zprty:$Zn, zprty:$Zm),
+  asm, "\t$Pd, $Zn, $Zm",
+  "", []>, Sched<[]> {
+  bits<4> Pd;
+  bits<5> Zm;
+  bits<5> Zn;
+  let Inst{31-24} = 0b01100101;
+  let Inst{23-22} = sz;
+  let Inst{21}    = 0b0;
+  let Inst{20-16} = Zm;
+  let Inst{15-13} = 0b000;
+  let Inst{12-10} = opc;
+  let Inst{9-5}   = Zn;
+  let Inst{4}     = 0;
+  let Inst{3-0}   = Pd;
+
+  let hasSideEffects = 0;
+  let mayRaiseFPException = 0;
+  let Uses = [ FPCR ];
+}
+
+
+multiclass sve_fp_3op_u_pd_totalcomp<bits<3> opc, string asm> {
+  def _H : sve_fp_3op_u_pd<0b01, opc, asm, ZPR16, PPR16>;
+  def _S : sve_fp_3op_u_pd<0b10, opc, asm, ZPR32, PPR32>;
+  def _D : sve_fp_3op_u_pd<0b11, opc, asm, ZPR64, PPR64>;
+}
+
+//===----------------------------------------------------------------------===//
+// SVE Min Max
+//===----------------------------------------------------------------------===//
+
+class sve_fp_2op_p_zds_minmax<bits<2> sz, bits<1> op, bits<2> opc, string asm,
----------------
MartinWehking wrote:

So my assumption is that `zds` stand for the multiple zd`s we have in the asm string. zdn is the same sve reg as _zdn, but it appears as input and output in the asm.

There are quite a few similar classes that follow the same naming scheme:sve_fp_2op_p_zds (fadd/fsub...)


https://github.com/llvm/llvm-project/pull/231436