[llvm-branch-commits] [llvm] PowerPC: Use minimal tablegen inputs for TargetParser (PR #233061)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/233061

>From aab17ee9bc3fd19c6ea5061e80d2ac64d94f5c88 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Wed, 14 Oct 2026 08:29:04 -0700
Subject: [PATCH] PowerPC: Use minimal tablegen inputs for TargetParser

Generate PPCGenTargetFeatures.inc from a file that only includes the
feature and processor definitions, instead of the full PPC.td. Add
stub SchedMachineModel, as was recently done for AArch64 in #231954,
since the TargetParser usage does not need them.

llvm-min-tblgen -gen-target-features

                         Gigainstructions  Peak RSS  .td deps
  PPC.td                 1.72              85 MB     81
  PPCTargetParserDef.td  0.01               6 MB      7

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/include/llvm/TargetParser/CMakeLists.txt |  2 +-
 llvm/lib/Target/PowerPC/PPCTargetParserDef.td | 33 +++++++++++++++++++
 .../llvm/include/llvm/TargetParser/BUILD.gn   |  2 +-
 .../llvm-project-overlay/llvm/BUILD.bazel     |  2 +-
 4 files changed, 36 insertions(+), 3 deletions(-)
 create mode 100644 llvm/lib/Target/PowerPC/PPCTargetParserDef.td

diff --git a/llvm/include/llvm/TargetParser/CMakeLists.txt b/llvm/include/llvm/TargetParser/CMakeLists.txt
index b1056cdae9b60c..1ca79b7a365f05 100644
--- a/llvm/include/llvm/TargetParser/CMakeLists.txt
+++ b/llvm/include/llvm/TargetParser/CMakeLists.txt
@@ -4,7 +4,7 @@ tablegen(LLVM AArch64TargetParserDef.inc -gen-arm-target-def EXTRA_INCLUDES ${PR
 set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/RISCV.td)
 tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def EXTRA_INCLUDES ${PROJECT_SOURCE_DIR}/lib/Target/RISCV)
 
-set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/PowerPC/PPC.td)
+set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/PowerPC/PPCTargetParserDef.td)
 tablegen(LLVM PPCGenTargetFeatures.inc -gen-target-features EXTRA_INCLUDES ${PROJECT_SOURCE_DIR}/lib/Target/PowerPC)
 
 set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/AMDGPU/R600TargetParserDef.td)
diff --git a/llvm/lib/Target/PowerPC/PPCTargetParserDef.td b/llvm/lib/Target/PowerPC/PPCTargetParserDef.td
new file mode 100644
index 00000000000000..a9d374cab610b8
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCTargetParserDef.td
@@ -0,0 +1,33 @@
+//===-- PPCTargetParserDef.td - PowerPC TargetParser -------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+include "llvm/Target/TargetSubtarget.td"
+
+include "PPCFeatures.td"
+
+// The TargetParser tables do not use the itineraries or scheduling models,
+// which depend on the instruction definitions. Define placeholders for the
+// ones referenced by the processor definitions.
+def G3Itineraries : ProcessorItineraries<[], [], []>;
+def G4Itineraries : ProcessorItineraries<[], [], []>;
+def G4PlusItineraries : ProcessorItineraries<[], [], []>;
+def G5Model : SchedMachineModel;
+def P10Model : SchedMachineModel;
+def P7Model : SchedMachineModel;
+def P8Model : SchedMachineModel;
+def P9Model : SchedMachineModel;
+def PPC440Model : SchedMachineModel;
+def PPCA2Model : SchedMachineModel;
+def PPCE500Model : SchedMachineModel;
+def PPCE500mcModel : SchedMachineModel;
+def PPCE5500Model : SchedMachineModel;
+
+include "PPCProcessors.td"
+
+class Target;
+def PPC : Target;
diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
index 300d51c6253ada..7ec386f320bbb9 100644
--- a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
+++ b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn
@@ -10,7 +10,7 @@ tablegen("AArch64TargetParserDef") {
 tablegen("PPCGenTargetFeatures") {
   visibility = [ ":gen" ]
   args = [ "-gen-target-features" ]
-  td_file = "//llvm/lib/Target/PowerPC/PPC.td"
+  td_file = "//llvm/lib/Target/PowerPC/PPCTargetParserDef.td"
   tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen"
 }
 
diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
index 8cf568014a7b12..6aebc9aa1b097e 100644
--- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
+++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel
@@ -1784,7 +1784,7 @@ gentbl_cc_library(
     name = "PPCGenTargetFeaturesGen",
     tbl_outs = {"include/llvm/TargetParser/PPCGenTargetFeatures.inc": ["-gen-target-features"]},
     tblgen = ":llvm-tblgen",
-    td_file = "lib/Target/PowerPC/PPC.td",
+    td_file = "lib/Target/PowerPC/PPCTargetParserDef.td",
     deps = [
         ":CommonTargetTdFiles",
         ":PPCTargetTdFiles",