[llvm-branch-commits] [llvm] release/23.x: [LoongArch] fix more `sitofp` missing instruction issues (#234143) (PR #234248)
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llvm-branch-commits at lists.llvm.org
Wed Oct 21 08:52:03 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-loongarch
Author: llvmbot
<details>
<summary>Changes</summary>
Backport ee216ff7ed6326989dfbd8f206342657aa1fda84
Requested by: @<!-- -->folkertdev
---
Patch is 23.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/234248.diff
2 Files Affected:
- (modified) llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp (+4)
- (modified) llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll (+407-118)
``````````diff
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 675fa046a7011b..5f4a50f1d4d35d 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -8288,6 +8288,10 @@ static SDValue performSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG,
if (!SrcVT.isSimple() || !VT.isSimple())
return SDValue();
+ // [x]vffint.s.l needs LSX and at least one full 128-bit source register.
+ if (!Subtarget.hasExtLSX() || SrcVT.getSizeInBits() < 128)
+ return SDValue();
+
// Combine [x]vffint.s.l for vector si64 to float conversion.
return MergeBlocksConvert(N, DAG, LoongArchISD::VFFINT, BlockBits);
}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
index d6177d5ca0969b..b86299cccf9640 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
@@ -1,14 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=LSX,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=LSX,LA64
+; RUN: llc --mtriple=loongarch64 --mattr=-lsx < %s | FileCheck %s --check-prefix=LA64-NO-LSX
define void @sitofp_v4i32_v4f32(ptr %res, ptr %in){
-; CHECK-LABEL: sitofp_v4i32_v4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vffint.s.w $vr0, $vr0
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v4i32_v4f32:
+; LSX: # %bb.0:
+; LSX-NEXT: vld $vr0, $a1, 0
+; LSX-NEXT: vffint.s.w $vr0, $vr0
+; LSX-NEXT: vst $vr0, $a0, 0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v4i32_v4f32:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.w $a2, $a1, 0
+; LA64-NO-LSX-NEXT: ld.w $a3, $a1, 12
+; LA64-NO-LSX-NEXT: ld.w $a4, $a1, 4
+; LA64-NO-LSX-NEXT: ld.w $a1, $a1, 8
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a2
+; LA64-NO-LSX-NEXT: ffint.s.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a4
+; LA64-NO-LSX-NEXT: ffint.s.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa2, $a1
+; LA64-NO-LSX-NEXT: ffint.s.w $fa2, $fa2
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa3, $a3
+; LA64-NO-LSX-NEXT: ffint.s.w $fa3, $fa3
+; LA64-NO-LSX-NEXT: fst.s $fa3, $a0, 12
+; LA64-NO-LSX-NEXT: fst.s $fa2, $a0, 8
+; LA64-NO-LSX-NEXT: fst.s $fa1, $a0, 4
+; LA64-NO-LSX-NEXT: fst.s $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%v0 = load <4 x i32>, ptr %in
%v1 = sitofp <4 x i32> %v0 to <4 x float>
store <4 x float> %v1, ptr %res
@@ -16,12 +37,22 @@ define void @sitofp_v4i32_v4f32(ptr %res, ptr %in){
}
define void @sitofp_v2i64_v2f64(ptr %res, ptr %in){
-; CHECK-LABEL: sitofp_v2i64_v2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v2i64_v2f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vld $vr0, $a1, 0
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: vst $vr0, $a0, 0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v2i64_v2f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: fld.d $fa0, $a1, 0
+; LA64-NO-LSX-NEXT: fld.d $fa1, $a1, 8
+; LA64-NO-LSX-NEXT: ffint.d.l $fa0, $fa0
+; LA64-NO-LSX-NEXT: ffint.d.l $fa1, $fa1
+; LA64-NO-LSX-NEXT: fst.d $fa1, $a0, 8
+; LA64-NO-LSX-NEXT: fst.d $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%v0 = load <2 x i64>, ptr %in
%v1 = sitofp <2 x i64> %v0 to <2 x double>
store <2 x double> %v1, ptr %res
@@ -43,185 +74,419 @@ define void @sitofp_v2i64_v2f32(ptr %res, ptr %in){
; LA64-NEXT: vffint.s.l $vr0, $vr0, $vr0
; LA64-NEXT: vstelm.d $vr0, $a0, 0, 0
; LA64-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v2i64_v2f32:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.d $a2, $a1, 0
+; LA64-NO-LSX-NEXT: ld.d $a1, $a1, 8
+; LA64-NO-LSX-NEXT: movgr2fr.d $fa0, $a2
+; LA64-NO-LSX-NEXT: ffint.s.l $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.d $fa1, $a1
+; LA64-NO-LSX-NEXT: ffint.s.l $fa1, $fa1
+; LA64-NO-LSX-NEXT: fst.s $fa1, $a0, 4
+; LA64-NO-LSX-NEXT: fst.s $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%v0 = load <2 x i64>, ptr %in
%v1 = sitofp <2 x i64> %v0 to <2 x float>
store <2 x float> %v1, ptr %res
ret void
}
+define <1 x float> @sitofp_v1i64_v1f32(<1 x i64> %a) {
+; LA32-LABEL: sitofp_v1i64_v1f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -16
+; LA32-NEXT: .cfi_def_cfa_offset 16
+; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT: .cfi_offset 1, -4
+; LA32-NEXT: bl __floatdisf
+; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 16
+; LA32-NEXT: ret
+;
+; LA64-LABEL: sitofp_v1i64_v1f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: movgr2fr.d $fa0, $a0
+; LA64-NEXT: ffint.s.l $fa0, $fa0
+; LA64-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v1i64_v1f32:
+; LA64-NO-LSX: # %bb.0: # %entry
+; LA64-NO-LSX-NEXT: movgr2fr.d $fa0, $a0
+; LA64-NO-LSX-NEXT: ffint.s.l $fa0, $fa0
+; LA64-NO-LSX-NEXT: ret
+entry:
+ %v = sitofp <1 x i64> %a to <1 x float>
+ ret <1 x float> %v
+}
+
define <4 x double> @sitofp_v4i64_v4f64(<4 x i64> %a) {
-; CHECK-LABEL: sitofp_v4i64_v4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: vffint.d.l $vr1, $vr1
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v4i64_v4f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: vffint.d.l $vr1, $vr1
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v4i64_v4f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: fld.d $fa0, $a1, 0
+; LA64-NO-LSX-NEXT: fld.d $fa1, $a1, 8
+; LA64-NO-LSX-NEXT: fld.d $fa2, $a1, 16
+; LA64-NO-LSX-NEXT: fld.d $fa3, $a1, 24
+; LA64-NO-LSX-NEXT: ffint.d.l $fa0, $fa0
+; LA64-NO-LSX-NEXT: ffint.d.l $fa1, $fa1
+; LA64-NO-LSX-NEXT: ffint.d.l $fa2, $fa2
+; LA64-NO-LSX-NEXT: ffint.d.l $fa3, $fa3
+; LA64-NO-LSX-NEXT: fst.d $fa3, $a0, 24
+; LA64-NO-LSX-NEXT: fst.d $fa2, $a0, 16
+; LA64-NO-LSX-NEXT: fst.d $fa1, $a0, 8
+; LA64-NO-LSX-NEXT: fst.d $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <4 x i64> %a to <4 x double>
ret <4 x double> %cvt
}
define <4 x float> @sitofp_v4i64_v4f32(<4 x i64> %a) {
-; CHECK-LABEL: sitofp_v4i64_v4f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vffint.s.l $vr0, $vr1, $vr0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v4i64_v4f32:
+; LSX: # %bb.0:
+; LSX-NEXT: vffint.s.l $vr0, $vr1, $vr0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v4i64_v4f32:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.d $a2, $a1, 0
+; LA64-NO-LSX-NEXT: ld.d $a3, $a1, 24
+; LA64-NO-LSX-NEXT: ld.d $a4, $a1, 8
+; LA64-NO-LSX-NEXT: ld.d $a1, $a1, 16
+; LA64-NO-LSX-NEXT: movgr2fr.d $fa0, $a2
+; LA64-NO-LSX-NEXT: ffint.s.l $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.d $fa1, $a4
+; LA64-NO-LSX-NEXT: ffint.s.l $fa1, $fa1
+; LA64-NO-LSX-NEXT: movgr2fr.d $fa2, $a1
+; LA64-NO-LSX-NEXT: ffint.s.l $fa2, $fa2
+; LA64-NO-LSX-NEXT: movgr2fr.d $fa3, $a3
+; LA64-NO-LSX-NEXT: ffint.s.l $fa3, $fa3
+; LA64-NO-LSX-NEXT: fst.s $fa3, $a0, 12
+; LA64-NO-LSX-NEXT: fst.s $fa2, $a0, 8
+; LA64-NO-LSX-NEXT: fst.s $fa1, $a0, 4
+; LA64-NO-LSX-NEXT: fst.s $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <4 x i64> %a to <4 x float>
ret <4 x float> %cvt
}
define <4 x double> @sitofp_v4i32_v4f64(<4 x i32> %a) {
-; CHECK-LABEL: sitofp_v4i32_v4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vslti.w $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.w $vr2, $vr1, $vr0
-; CHECK-NEXT: vffint.d.l $vr2, $vr2
-; CHECK-NEXT: vilvh.w $vr0, $vr1, $vr0
-; CHECK-NEXT: vffint.d.l $vr1, $vr0
-; CHECK-NEXT: vori.b $vr0, $vr2, 0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v4i32_v4f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vslti.w $vr1, $vr0, 0
+; LSX-NEXT: vilvl.w $vr2, $vr1, $vr0
+; LSX-NEXT: vffint.d.l $vr2, $vr2
+; LSX-NEXT: vilvh.w $vr0, $vr1, $vr0
+; LSX-NEXT: vffint.d.l $vr1, $vr0
+; LSX-NEXT: vori.b $vr0, $vr2, 0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v4i32_v4f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.w $a2, $a1, 0
+; LA64-NO-LSX-NEXT: ld.w $a3, $a1, 24
+; LA64-NO-LSX-NEXT: ld.w $a4, $a1, 8
+; LA64-NO-LSX-NEXT: ld.w $a1, $a1, 16
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a2
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a4
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa2, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa2, $fa2
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa3, $a3
+; LA64-NO-LSX-NEXT: ffint.d.w $fa3, $fa3
+; LA64-NO-LSX-NEXT: fst.d $fa3, $a0, 24
+; LA64-NO-LSX-NEXT: fst.d $fa2, $a0, 16
+; LA64-NO-LSX-NEXT: fst.d $fa1, $a0, 8
+; LA64-NO-LSX-NEXT: fst.d $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <4 x i32> %a to <4 x double>
ret <4 x double> %cvt
}
define <2 x float> @sitofp_v2i32_v2f32(<2 x i32> %a) {
-; CHECK-LABEL: sitofp_v2i32_v2f32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vffint.s.w $vr0, $vr0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v2i32_v2f32:
+; LSX: # %bb.0:
+; LSX-NEXT: vffint.s.w $vr0, $vr0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v2i32_v2f32:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a0
+; LA64-NO-LSX-NEXT: ffint.s.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a1
+; LA64-NO-LSX-NEXT: ffint.s.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <2 x i32> %a to <2 x float>
ret <2 x float> %cvt
}
define <2 x double> @sitofp_v4i32_v2f64(<4 x i32> %a) {
-; CHECK-LABEL: sitofp_v4i32_v2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vslti.w $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v4i32_v2f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vslti.w $vr1, $vr0, 0
+; LSX-NEXT: vilvl.w $vr0, $vr1, $vr0
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v4i32_v2f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.w $a1, $a0, 0
+; LA64-NO-LSX-NEXT: ld.w $a0, $a0, 8
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a0
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <4 x i32> %a to <4 x double>
%shuf = shufflevector <4 x double> %cvt, <4 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <2 x double> @sitofp_v2i16_v2f64(<8 x i16> %a) {
-; CHECK-LABEL: sitofp_v2i16_v2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
-; CHECK-NEXT: vslli.d $vr0, $vr0, 48
-; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v2i16_v2f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vextrins.h $vr0, $vr0, 65
+; LSX-NEXT: vslli.d $vr0, $vr0, 48
+; LSX-NEXT: vsrai.d $vr0, $vr0, 48
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v2i16_v2f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.h $a1, $a0, 0
+; LA64-NO-LSX-NEXT: ld.h $a0, $a0, 8
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a0
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: ret
%shuf = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i16> %shuf to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @sitofp_v8i16_v2f64(<8 x i16> %a) {
-; CHECK-LABEL: sitofp_v8i16_v2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vslti.h $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
-; CHECK-NEXT: vslti.w $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v8i16_v2f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vslti.h $vr1, $vr0, 0
+; LSX-NEXT: vilvl.h $vr0, $vr1, $vr0
+; LSX-NEXT: vslti.w $vr1, $vr0, 0
+; LSX-NEXT: vilvl.w $vr0, $vr1, $vr0
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v8i16_v2f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.h $a1, $a0, 0
+; LA64-NO-LSX-NEXT: ld.h $a0, $a0, 8
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a0
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <8 x i16> %a to <8 x double>
%shuf = shufflevector <8 x double> %cvt, <8 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <2 x double> @sitofp_v2i8_v2f64(<16 x i8> %a) {
-; CHECK-LABEL: sitofp_v2i8_v2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
-; CHECK-NEXT: vslli.d $vr0, $vr0, 56
-; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v2i8_v2f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vextrins.b $vr0, $vr0, 129
+; LSX-NEXT: vslli.d $vr0, $vr0, 56
+; LSX-NEXT: vsrai.d $vr0, $vr0, 56
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v2i8_v2f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.b $a1, $a0, 0
+; LA64-NO-LSX-NEXT: ld.b $a0, $a0, 8
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a0
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: ret
%shuf = shufflevector <16 x i8> %a, <16 x i8> poison, <2 x i32> <i32 0, i32 1>
%cvt = sitofp <2 x i8> %shuf to <2 x double>
ret <2 x double> %cvt
}
define <2 x double> @sitofp_v16i8_v2f64(<16 x i8> %a) {
-; CHECK-LABEL: sitofp_v16i8_v2f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vslti.b $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
-; CHECK-NEXT: vslti.h $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
-; CHECK-NEXT: vslti.w $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v16i8_v2f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vslti.b $vr1, $vr0, 0
+; LSX-NEXT: vilvl.b $vr0, $vr1, $vr0
+; LSX-NEXT: vslti.h $vr1, $vr0, 0
+; LSX-NEXT: vilvl.h $vr0, $vr1, $vr0
+; LSX-NEXT: vslti.w $vr1, $vr0, 0
+; LSX-NEXT: vilvl.w $vr0, $vr1, $vr0
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v16i8_v2f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.b $a1, $a0, 0
+; LA64-NO-LSX-NEXT: ld.b $a0, $a0, 8
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a0
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <16 x i8> %a to <16 x double>
%shuf = shufflevector <16 x double> %cvt, <16 x double> poison, <2 x i32> <i32 0, i32 1>
ret <2 x double> %shuf
}
define <4 x double> @sitofp_v4i16_v4f64(<8 x i16> %a) {
-; CHECK-LABEL: sitofp_v4i16_v4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vslti.h $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.h $vr1, $vr1, $vr0
-; CHECK-NEXT: vslti.w $vr2, $vr1, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr1
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: vilvh.w $vr1, $vr2, $vr1
-; CHECK-NEXT: vffint.d.l $vr1, $vr1
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v4i16_v4f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vslti.h $vr1, $vr0, 0
+; LSX-NEXT: vilvl.h $vr1, $vr1, $vr0
+; LSX-NEXT: vslti.w $vr2, $vr1, 0
+; LSX-NEXT: vilvl.w $vr0, $vr2, $vr1
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: vilvh.w $vr1, $vr2, $vr1
+; LSX-NEXT: vffint.d.l $vr1, $vr1
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v4i16_v4f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.h $a2, $a1, 0
+; LA64-NO-LSX-NEXT: ld.h $a3, $a1, 24
+; LA64-NO-LSX-NEXT: ld.h $a4, $a1, 8
+; LA64-NO-LSX-NEXT: ld.h $a1, $a1, 16
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a2
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a4
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa2, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa2, $fa2
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa3, $a3
+; LA64-NO-LSX-NEXT: ffint.d.w $fa3, $fa3
+; LA64-NO-LSX-NEXT: fst.d $fa3, $a0, 24
+; LA64-NO-LSX-NEXT: fst.d $fa2, $a0, 16
+; LA64-NO-LSX-NEXT: fst.d $fa1, $a0, 8
+; LA64-NO-LSX-NEXT: fst.d $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%shuf = shufflevector <8 x i16> %a, <8 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
%cvt = sitofp <4 x i16> %shuf to <4 x double>
ret <4 x double> %cvt
}
define <4 x double> @sitofp_v8i16_v4f64(<8 x i16> %a) {
-; CHECK-LABEL: sitofp_v8i16_v4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vslti.h $vr1, $vr0, 0
-; CHECK-NEXT: vilvl.h $vr1, $vr1, $vr0
-; CHECK-NEXT: vslti.w $vr2, $vr1, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr1
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: vilvh.w $vr1, $vr2, $vr1
-; CHECK-NEXT: vffint.d.l $vr1, $vr1
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v8i16_v4f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vslti.h $vr1, $vr0, 0
+; LSX-NEXT: vilvl.h $vr1, $vr1, $vr0
+; LSX-NEXT: vslti.w $vr2, $vr1, 0
+; LSX-NEXT: vilvl.w $vr0, $vr2, $vr1
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: vilvh.w $vr1, $vr2, $vr1
+; LSX-NEXT: vffint.d.l $vr1, $vr1
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v8i16_v4f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.h $a2, $a1, 0
+; LA64-NO-LSX-NEXT: ld.h $a3, $a1, 24
+; LA64-NO-LSX-NEXT: ld.h $a4, $a1, 8
+; LA64-NO-LSX-NEXT: ld.h $a1, $a1, 16
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a2
+; LA64-NO-LSX-NEXT: ffint.d.w $fa0, $fa0
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa1, $a4
+; LA64-NO-LSX-NEXT: ffint.d.w $fa1, $fa1
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa2, $a1
+; LA64-NO-LSX-NEXT: ffint.d.w $fa2, $fa2
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa3, $a3
+; LA64-NO-LSX-NEXT: ffint.d.w $fa3, $fa3
+; LA64-NO-LSX-NEXT: fst.d $fa3, $a0, 24
+; LA64-NO-LSX-NEXT: fst.d $fa2, $a0, 16
+; LA64-NO-LSX-NEXT: fst.d $fa1, $a0, 8
+; LA64-NO-LSX-NEXT: fst.d $fa0, $a0, 0
+; LA64-NO-LSX-NEXT: ret
%cvt = sitofp <8 x i16> %a to <8 x double>
%shuf = shufflevector <8 x double> %cvt, <8 x double> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
ret <4 x double> %shuf
}
define <4 x double> @sitofp_v4i8_v4f64(<16 x i8> %a) {
-; CHECK-LABEL: sitofp_v4i8_v4f64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
-; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
-; CHECK-NEXT: vslli.w $vr0, $vr0, 24
-; CHECK-NEXT: vsrai.w $vr1, $vr0, 24
-; CHECK-NEXT: vslti.w $vr2, $vr1, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr2, $vr1
-; CHECK-NEXT: vffint.d.l $vr0, $vr0
-; CHECK-NEXT: vilvh.w $vr1, $vr2, $vr1
-; CHECK-NEXT: vffint.d.l $vr1, $vr1
-; CHECK-NEXT: ret
+; LSX-LABEL: sitofp_v4i8_v4f64:
+; LSX: # %bb.0:
+; LSX-NEXT: vilvl.b $vr0, $vr0, $vr0
+; LSX-NEXT: vilvl.h $vr0, $vr0, $vr0
+; LSX-NEXT: vslli.w $vr0, $vr0, 24
+; LSX-NEXT: vsrai.w $vr1, $vr0, 24
+; LSX-NEXT: vslti.w $vr2, $vr1, 0
+; LSX-NEXT: vilvl.w $vr0, $vr2, $vr1
+; LSX-NEXT: vffint.d.l $vr0, $vr0
+; LSX-NEXT: vilvh.w $vr1, $vr2, $vr1
+; LSX-NEXT: vffint.d.l $vr1, $vr1
+; LSX-NEXT: ret
+;
+; LA64-NO-LSX-LABEL: sitofp_v4i8_v4f64:
+; LA64-NO-LSX: # %bb.0:
+; LA64-NO-LSX-NEXT: ld.b $a2, $a1, 0
+; LA64-NO-LSX-NEXT: ld.b $a3, $a1, 24
+; LA64-NO-LSX-NEXT: ld.b $a4, $a1, 8
+; LA64-NO-LSX-NEXT: ld.b $a1, $a1, 16
+; LA64-NO-LSX-NEXT: movgr2fr.w $fa0, $a2...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/234248
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