[llvm-branch-commits] [llvm] [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms (PR #232526)

[Kieran B via llvm-branch-commits]

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@@ -25381,6 +25394,26 @@ static SDValue lowerPredCounterWhile(Intrinsic::ID IID, SDNode *N,
                      DAG.getTargetConstant(ElementSizeInBits, DL, MVT::i64));
 }
 
+static SDValue performSVEAndNotIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue Pg = N->getOperand(1);
+
+  // Fold matching predicates before lowering AND_U discards its predicate.
+  // NOT's inactive lanes cannot affect AND_U's active lanes.
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kieroxide wrote:

Thanks for having a look. Yes, I think the table-gen is still preferable. A good rule of thumb is that if we can do it in table gen, then it most likely belongs there. It is easier to read and declarative even if it is more verbose. 

https://github.com/llvm/llvm-project/pull/232526