[llvm-branch-commits] [llvm] AMDGPU: Stop adding kill flags on virtual registers (PR #234197)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Oct 21 05:49:16 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/234197
Fix misc. AMDGPU passes and hooks running before register allocation
introducing kill flags. There's no point in doing this anymore.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
>From 34fc14051533ac6fa4a73050ab58c4d325cc38a3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sat, 17 Oct 2026 19:47:22 +0200
Subject: [PATCH] AMDGPU: Stop adding kill flags on virtual registers
Fix misc. AMDGPU passes and hooks running before register allocation
introducing kill flags. There's no point in doing this anymore.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
.../lib/Target/AMDGPU/SIFormMemoryClauses.cpp | 5 +-
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 5 +-
llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp | 3 +-
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp | 8 +--
llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 2 +-
llvm/test/CodeGen/AMDGPU/collapse-endcf.mir | 58 +++++++++----------
.../CodeGen/AMDGPU/fold-fmac-to-fmaak.mir | 16 ++---
...local-stack-alloc-add-references.gfx10.mir | 4 +-
.../local-stack-alloc-add-references.gfx8.mir | 30 +++++-----
.../local-stack-alloc-add-references.gfx9.mir | 16 ++---
.../lower-control-flow-other-terminators.mir | 8 +--
11 files changed, 76 insertions(+), 79 deletions(-)
diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
index 68de9f4255fda..dfaf3ccf4c548 100644
--- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
@@ -348,8 +348,7 @@ bool SIFormMemoryClausesImpl::run(MachineFunction &MF) {
if (!LI.hasSubRanges()) {
if (!LI.liveAt(ClauseLiveOutIdx)) {
- KillOps.emplace_back(R.second.first | RegState::Kill,
- AMDGPU::NoSubRegister);
+ KillOps.emplace_back(R.second.first, AMDGPU::NoSubRegister);
}
} else {
LaneBitmask KilledMask;
@@ -367,7 +366,7 @@ bool SIFormMemoryClausesImpl::run(MachineFunction &MF) {
(void)Success;
assert(Success && "Failed to find subregister mask to cover lanes");
for (unsigned SubReg : KilledIndexes) {
- KillOps.emplace_back(R.second.first | RegState::Kill, SubReg);
+ KillOps.emplace_back(R.second.first, SubReg);
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d936636d36905..d6b14043f781a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4077,7 +4077,6 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
get(AMDGPU::COPY), Tmp)
.addReg(Reg);
MI.getOperand(OpNo).setReg(Tmp);
- MI.getOperand(OpNo).setIsKill();
};
// Multiplied part is the constant: Use v_madmk_{f16, f32}.
@@ -4142,7 +4141,7 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
BuildMI(*UseMI.getParent(), std::next(UseMI.getIterator()),
UseMI.getDebugLoc(), get(AMDGPU::COPY),
UseMI.getOperand(0).getReg())
- .addReg(Tmp, RegState::Kill);
+ .addReg(Tmp);
UseMI.getOperand(0).setReg(Tmp);
CopyRegOperandToNarrowerRC(UseMI, 1, NewRC);
CopyRegOperandToNarrowerRC(UseMI, 3, NewRC);
@@ -4222,7 +4221,7 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
BuildMI(*UseMI.getParent(), std::next(UseMI.getIterator()),
UseMI.getDebugLoc(), get(AMDGPU::COPY),
UseMI.getOperand(0).getReg())
- .addReg(Tmp, RegState::Kill);
+ .addReg(Tmp);
UseMI.getOperand(0).setReg(Tmp);
CopyRegOperandToNarrowerRC(UseMI, 1, NewRC);
CopyRegOperandToNarrowerRC(UseMI, 2, NewRC);
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index c54ac39b3444c..f2408f78bc62a 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -260,8 +260,7 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) {
// Use a copy that is a terminator to get correct spill code placement it with
// fast regalloc.
MachineInstr *SetExec =
- BuildMI(MBB, I, DL, TII->get(LMC.MovTermOpc), LMC.ExecReg)
- .addReg(Tmp, RegState::Kill);
+ BuildMI(MBB, I, DL, TII->get(LMC.MovTermOpc), LMC.ExecReg).addReg(Tmp);
// Skip ahead to the unconditional branch in case there are other terminators
// present.
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 0989263433f41..640b267e24698 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -972,16 +972,16 @@ Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
if (ST.hasFlatScratchEnabled()) {
// FIXME: Make sure scc isn't live in.
BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_I32), BaseReg)
- .addReg(OffsetReg, RegState::Kill)
+ .addReg(OffsetReg)
.addReg(FIReg)
.setOperandDead(3); // scc
return BaseReg;
}
TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
- .addReg(OffsetReg, RegState::Kill)
- .addReg(FIReg)
- .addImm(0); // clamp bit
+ .addReg(OffsetReg)
+ .addReg(FIReg)
+ .addImm(0); // clamp bit
return BaseReg;
}
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 5c41a2a563e0f..dbf3ad139940f 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1693,7 +1693,7 @@ void SIWholeQuadMode::lowerInitExec(MachineInstr &MI) {
.addReg(CountReg)
.addImm(0);
auto CmpMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_CMP_EQ_U32))
- .addReg(CountReg, RegState::Kill)
+ .addReg(CountReg)
.addImm(WavefrontSize);
auto CmovMI =
BuildMI(*MBB, FirstMI, DL, TII->get(LMC.CMovOpc), LMC.ExecReg).addImm(-1);
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
index 5c62c7886020b..f12f8499cd457 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
@@ -15,7 +15,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -23,7 +23,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -69,7 +69,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -77,7 +77,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -123,7 +123,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -131,7 +131,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -182,7 +182,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -190,7 +190,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -245,7 +245,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -253,7 +253,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -308,7 +308,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -316,7 +316,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -366,7 +366,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -375,7 +375,7 @@ body: |
; GCN-NEXT: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %4:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -425,7 +425,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -433,7 +433,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -527,7 +527,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -548,7 +548,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %4:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_2]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_2]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.4:
@@ -611,7 +611,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -638,7 +638,7 @@ body: |
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_1]], [[COPY1]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: S_BRANCH %bb.0
; GCN-NEXT: S_ENDPGM 0
@@ -681,7 +681,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -689,7 +689,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -743,7 +743,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -751,7 +751,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -818,7 +818,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF]], implicit $exec
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.14, implicit $exec
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
@@ -829,7 +829,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF1]], implicit $exec
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], killed [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.14, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}}
@@ -840,7 +840,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_2:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF2]], implicit $exec
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], killed [[V_CMP_EQ_U32_e64_2]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_2]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_2]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.7, implicit $exec
; GCN-NEXT: S_BRANCH %bb.3
; GCN-NEXT: {{ $}}
@@ -851,7 +851,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_3:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF3]], implicit $exec
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_3:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY3]], killed [[V_CMP_EQ_U32_e64_3]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_3]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_3]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.7, implicit $exec
; GCN-NEXT: S_BRANCH %bb.4
; GCN-NEXT: {{ $}}
@@ -879,7 +879,7 @@ body: |
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_4:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], killed [[V_CMP_EQ_U32_e64_4]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_4]], [[COPY4]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_4]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_4]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.12, implicit $exec
; GCN-NEXT: S_BRANCH %bb.11
; GCN-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir b/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir
index e31bbc39b733e..2cefc8201ce9f 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir
@@ -101,8 +101,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16_lo128 = COPY [[COPY]]
; CHECK-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16_lo128 = V_MOV_B16_t16_e64 0, 10526, 0, implicit $exec
- ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 [[V_MOV_B16_t16_e64_]], killed [[COPY1]], 8478, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY killed [[V_FMAAK_F16_t16_]]
+ ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 [[V_MOV_B16_t16_e64_]], [[COPY1]], 8478, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[V_FMAAK_F16_t16_]]
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%0:vgpr_16 = COPY $vgpr0
@@ -124,8 +124,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16_lo128 = COPY [[COPY]]
; CHECK-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16_lo128 = V_MOV_B16_t16_e64 0, 10526, 0, implicit $exec
- ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 [[V_MOV_B16_t16_e64_]], killed [[COPY1]], 8478, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY killed [[V_FMAAK_F16_t16_]]
+ ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 [[V_MOV_B16_t16_e64_]], [[COPY1]], 8478, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[V_FMAAK_F16_t16_]]
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%0:vgpr_16 = COPY $vgpr0
@@ -146,8 +146,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16_lo128 = COPY [[COPY]]
- ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 16384, killed [[COPY1]], 8478, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY killed [[V_FMAAK_F16_t16_]]
+ ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 16384, [[COPY1]], 8478, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[V_FMAAK_F16_t16_]]
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%0:vgpr_16 = COPY $vgpr0
@@ -168,8 +168,8 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16_lo128 = COPY [[COPY]]
- ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 16384, killed [[COPY1]], 8478, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY killed [[V_FMAAK_F16_t16_]]
+ ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 16384, [[COPY1]], 8478, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[V_FMAAK_F16_t16_]]
; CHECK-NEXT: $vgpr0 = COPY [[COPY2]]
; CHECK-NEXT: SI_RETURN implicit $vgpr0
%0:vgpr_16 = COPY $vgpr0
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
index 066336195004e..048a5f98dae87 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir
@@ -16,7 +16,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[V_ADD_U32_e64_]], 256, 0, implicit $exec
@@ -51,7 +51,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__literal_offsets_commute
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 100
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 156, [[V_ADD_U32_e64_]], 0, implicit $exec
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[V_ADD_U32_e64_1]]
; GFX10-NEXT: [[V_ADD_U32_e64_2:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 412, [[V_ADD_U32_e64_]], 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
index 6ab30195bea03..155aa2a6744a5 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir
@@ -19,7 +19,7 @@ body: |
; GFX803-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
; GFX803: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_CO_U32_e64_]], implicit-def dead $vcc, implicit $exec
@@ -29,7 +29,7 @@ body: |
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
; GFX900: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX900-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
@@ -39,7 +39,7 @@ body: |
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
; GFX942: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
- ; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
+ ; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX942-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
@@ -50,7 +50,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 256, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
@@ -60,7 +60,7 @@ body: |
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__literal_offsets
; GFX12: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
- ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
+ ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX12-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
@@ -142,7 +142,7 @@ body: |
; GFX803-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
; GFX803: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_CO_U32_e64_]], implicit-def dead $vcc, implicit $exec
@@ -152,7 +152,7 @@ body: |
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
; GFX900: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX900-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
@@ -162,7 +162,7 @@ body: |
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
; GFX942: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
- ; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
+ ; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX942-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX942-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
@@ -173,7 +173,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 8, [[V_ADD_U32_e64_]], implicit-def dead $vcc, implicit $exec
@@ -183,7 +183,7 @@ body: |
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e32__inline_imm_offsets
; GFX12: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
- ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
+ ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX12-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
@@ -212,7 +212,7 @@ body: |
; GFX803-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
; GFX803: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX803-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX803-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64 = V_ADD_CO_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX803-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_CO_U32_e64_]]
; GFX803-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX803-NEXT: [[V_ADD_CO_U32_e64_2:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_CO_U32_e64_]], 0, implicit $exec
@@ -222,7 +222,7 @@ body: |
; GFX900-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
; GFX900: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX900-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX900-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
@@ -232,7 +232,7 @@ body: |
; GFX942-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
; GFX942: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX942-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
- ; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
+ ; GFX942-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX942-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX942-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX942-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[S_ADD_I32_]], 0, implicit $exec
@@ -242,7 +242,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
@@ -252,7 +252,7 @@ body: |
; GFX12-LABEL: name: local_stack_alloc__v_add_co_u32_e64__inline_imm_offsets
; GFX12: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 %stack.0
- ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 killed [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
+ ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32_xexec_hi = S_ADD_I32 [[S_MOV_B32_]], [[S_MOV_B32_1]], implicit-def dead $scc
; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]]
; GFX12-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX12-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, dead [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_ADD_CO_U32_e64 8, [[S_ADD_I32_]], 0, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
index fcad27b6abf9b..3e631e66c31a7 100644
--- a/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
+++ b/llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir
@@ -18,7 +18,7 @@ body: |
; GFX900-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
; GFX900: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX900-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, [[V_ADD_U32_e64_]], implicit $exec
@@ -35,7 +35,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__literal_offsets
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 256
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 256, [[V_ADD_U32_e64_]], implicit $exec
@@ -70,7 +70,7 @@ body: |
; GFX900-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
; GFX900: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX900-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, [[V_ADD_U32_e64_]], implicit $exec
@@ -87,7 +87,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e32__inline_imm_offsets
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e32 8, [[V_ADD_U32_e64_]], implicit $exec
@@ -122,7 +122,7 @@ body: |
; GFX900-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
; GFX900: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX900-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
@@ -139,7 +139,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 0, implicit $exec
@@ -484,7 +484,7 @@ body: |
; GFX900-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
; GFX900: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX900-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX900-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX900-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX900-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX900-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 1, implicit $exec
@@ -501,7 +501,7 @@ body: |
; GFX10-LABEL: name: local_stack_alloc__v_add_u32_e64__inline_imm_offsets_clamp_modifier
; GFX10: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 8
; GFX10-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 %stack.0, implicit $exec
- ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 killed [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
+ ; GFX10-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[S_MOV_B32_]], [[V_MOV_B32_e32_]], 0, implicit $exec
; GFX10-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY [[V_ADD_U32_e64_]]
; GFX10-NEXT: INLINEASM &"; use $0", sideeffect attdialect, reguse:VGPR_32, [[COPY]]
; GFX10-NEXT: [[V_ADD_U32_e64_1:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 8, [[V_ADD_U32_e64_]], 1, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir b/llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
index c9be9238c2824..1001c065b47b7 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
+++ b/llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir
@@ -25,7 +25,7 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; CHECK-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term killed [[COPY1]], implicit $exec
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
; CHECK-NEXT: S_BRANCH %bb.2
@@ -72,7 +72,7 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; CHECK-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term killed [[COPY1]], implicit $exec
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
; CHECK-NEXT: {{ $}}
@@ -213,7 +213,7 @@ body: |
; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; CHECK-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_]], [[COPY2]], implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; CHECK-NEXT: [[S_MOV_B64_term1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_]], implicit $exec
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
@@ -239,7 +239,7 @@ body: |
; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; CHECK-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY5]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
; CHECK-NEXT: [[S_XOR_B64_1:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[S_AND_B64_1]], [[COPY5]], implicit-def dead $scc
- ; CHECK-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; CHECK-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; CHECK-NEXT: [[S_MOV_B64_term:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_1]], implicit $exec
; CHECK-NEXT: [[S_MOV_B64_term1:%[0-9]+]]:sreg_64_xexec = S_MOV_B64_term [[S_XOR_B64_1]], implicit $exec
; CHECK-NEXT: S_CBRANCH_EXECZ %bb.1, implicit $exec
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