[llvm-branch-commits] [llvm] [LoongArch] Load scalars into vector lane 0 with FLD/VLDREPL (PR #234119)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Oct 21 02:04:41 PDT 2026
https://github.com/heiher created https://github.com/llvm/llvm-project/pull/234119
Inserting a loaded integer into lane 0 of an undefined vector, which is also how sub-128-bit vector loads are legalized, was lowered to a scalar load plus [X]VINSGR2VR. VINSGR2VR merges into its destination, so it carries a false dependency on the previous value of that register, and it needs a GPR-to-vector move.
Use FLD.{S/D} for 32/64-bit elements and [X]VLDREPL.{B/H} for 8/16-bit elements instead. They write the whole register in one instruction.
When the register allocator reuses one vector register for several such loads, the false dependency serializes otherwise independent chains. In the GSM autocorrelation loop (9 x i64 multiply-accumulate over i16 taps) on LA664:
VF2: 0.953s -> 0.724s
VF4: 1.446s -> 0.856s
>From 3cbb9e41317502d640c2f88cd176053b14d6b44b Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Wed, 21 Oct 2026 14:21:55 +0800
Subject: [PATCH] [LoongArch] Load scalars into vector lane 0 with FLD/VLDREPL
Inserting a loaded integer into lane 0 of an undefined vector, which is
also how sub-128-bit vector loads are legalized, was lowered to a scalar
load plus [X]VINSGR2VR. VINSGR2VR merges into its destination, so it
carries a false dependency on the previous value of that register, and
it needs a GPR-to-vector move.
Use FLD.{S/D} for 32/64-bit elements and [X]VLDREPL.{B/H} for 8/16-bit
elements instead. They write the whole register in one instruction.
When the register allocator reuses one vector register for several such
loads, the false dependency serializes otherwise independent chains. In
the GSM autocorrelation loop (9 x i64 multiply-accumulate over i16 taps)
on LA664:
VF2: 0.953s -> 0.724s
VF4: 1.446s -> 0.856s
---
.../LoongArch/LoongArchISelLowering.cpp | 39 +++++
.../CodeGen/LoongArch/lasx/broadcast-load.ll | 21 +--
.../CodeGen/LoongArch/lasx/build-vector.ll | 156 +++++++++---------
.../LoongArch/lasx/scalar-load-to-vector.ll | 45 +++--
.../LoongArch/lasx/vec-sext-invec-mask.ll | 52 +++---
llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll | 39 ++---
.../LoongArch/lasx/vec-trunc-combine.ll | 10 +-
llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll | 39 ++---
.../CodeGen/LoongArch/lsx/broadcast-load.ll | 21 +--
.../LoongArch/lsx/ir-instruction/sitofp.ll | 68 ++++----
.../LoongArch/lsx/ir-instruction/uitofp.ll | 66 ++++----
.../LoongArch/lsx/scalar-load-to-vector.ll | 61 ++++---
.../CodeGen/LoongArch/lsx/vec-reduce-add.ll | 48 ++----
.../CodeGen/LoongArch/lsx/vec-reduce-and.ll | 35 ++--
.../CodeGen/LoongArch/lsx/vec-reduce-or.ll | 35 ++--
.../CodeGen/LoongArch/lsx/vec-reduce-smax.ll | 39 ++---
.../CodeGen/LoongArch/lsx/vec-reduce-smin.ll | 39 ++---
.../CodeGen/LoongArch/lsx/vec-reduce-umax.ll | 39 ++---
.../CodeGen/LoongArch/lsx/vec-reduce-umin.ll | 39 ++---
.../CodeGen/LoongArch/lsx/vec-reduce-xor.ll | 35 ++--
llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll | 39 ++---
.../LoongArch/lsx/vec-shuffle-any-ext.ll | 39 ++---
.../LoongArch/lsx/vec-shuffle-sign-ext.ll | 32 ++--
llvm/test/CodeGen/LoongArch/lsx/vec-trunc.ll | 36 ++--
llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll | 32 ++--
llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll | 20 +--
llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll | 20 +--
27 files changed, 500 insertions(+), 644 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 1d01e76a5ebd2d..c5a390cf163ee9 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -4024,6 +4024,45 @@ LoongArchTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
SDValue Op1 = Op.getOperand(1);
SDValue Op2 = Op.getOperand(2);
+ // Lower inserting a loaded integer into lane 0 of an undefined vector as a
+ // vector load that writes the whole register: FLD.{S/D} for 32/64-bit
+ // elements and [X]VLDREPL.{B/H} for 8/16-bit ones. Unlike a scalar load +
+ // [X]VINSGR2VR, it has no false dependency on the previous value of the
+ // destination and doesn't need to move the value from a GPR.
+ // For example:
+ // %a = load i64, ptr %ptr
+ // %b = insert_vector_elt undef, %a, 0
+ // is lowered to:
+ // (FLD_D $a0, 0)
+ if (Op0.isUndef() && isNullConstant(Op2) && EltVT.isInteger() &&
+ Op1.getOpcode() == ISD::LOAD && Op1.hasOneUse()) {
+ auto *LN = cast<LoadSDNode>(Op1);
+ auto ExtType = LN->getExtensionType();
+ if (LN->isSimple() &&
+ (ExtType == ISD::EXTLOAD || ExtType == ISD::NON_EXTLOAD) &&
+ LN->getMemoryVT().getSizeInBits() == EltSizeInBits) {
+ // Indexed loads and stores are not supported on LoongArch.
+ assert(LN->isUnindexed() && "Unexpected indexed load.");
+ SDValue Res;
+ if (EltSizeInBits >= 32) {
+ MVT FltVT = MVT::getFloatingPointVT(EltSizeInBits);
+ SDValue Ld = DAG.getLoad(FltVT, DL, LN->getChain(), LN->getBasePtr(),
+ LN->getMemOperand());
+ Res = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL,
+ MVT::getVectorVT(FltVT, NumElts), Ld);
+ Res = DAG.getBitcast(VT, Res);
+ DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), Ld.getValue(1));
+ } else {
+ SDVTList Tys = DAG.getVTList(VT, MVT::Other);
+ SDValue Ops[] = {LN->getChain(), LN->getBasePtr()};
+ Res = DAG.getMemIntrinsicNode(LoongArchISD::VLDREPL, DL, Tys, Ops,
+ LN->getMemoryVT(), LN->getMemOperand());
+ DAG.ReplaceAllUsesOfValueWith(SDValue(LN, 1), Res.getValue(1));
+ }
+ return Res;
+ }
+ }
+
if (isa<ConstantSDNode>(Op2))
return Op;
diff --git a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
index 7407e0d5f4195d..7b622ee62bb540 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
@@ -57,10 +57,9 @@ define <16 x i16> @should_not_be_optimized_zext_load(ptr %ptr) {
define <4 x i64> @xvldrepl_d_unaligned_offset(ptr %ptr) {
; LA32-LABEL: xvldrepl_d_unaligned_offset:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 4
-; LA32-NEXT: ld.w $a0, $a0, 8
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 8
+; LA32-NEXT: fld.s $fa0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: xvreplve0.d $xr0, $xr0
; LA32-NEXT: ret
;
@@ -150,10 +149,9 @@ define <8 x i32> @xvldrepl_w_offset(ptr %ptr) {
define <4 x i64> @xvldrepl_d(ptr %ptr) {
; LA32-LABEL: xvldrepl_d:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: xvreplve0.d $xr0, $xr0
; LA32-NEXT: ret
;
@@ -170,10 +168,9 @@ define <4 x i64> @xvldrepl_d(ptr %ptr) {
define <4 x i64> @xvldrepl_d_offset(ptr %ptr) {
; LA32-LABEL: xvldrepl_d_offset:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 264
-; LA32-NEXT: ld.w $a0, $a0, 268
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 268
+; LA32-NEXT: fld.s $fa0, $a0, 264
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: xvreplve0.d $xr0, $xr0
; LA32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
index d09ef0e2c6ac0d..9da1ca4e80aa1b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
@@ -380,38 +380,37 @@ entry:
define void @buildvector_v32i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31) nounwind {
; LA32-LABEL: buildvector_v32i8:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.b $t0, $sp, 36
+; LA32-NEXT: ld.b $t0, $sp, 40
+; LA32-NEXT: vldrepl.b $vr0, $sp, 36
; LA32-NEXT: ld.b $t1, $sp, 92
-; LA32-NEXT: ld.b $t2, $sp, 40
-; LA32-NEXT: ld.b $t3, $sp, 44
-; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 0
-; LA32-NEXT: ld.b $t0, $sp, 48
-; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 1
-; LA32-NEXT: ld.b $t2, $sp, 52
-; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 2
-; LA32-NEXT: ld.b $t3, $sp, 56
-; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 3
-; LA32-NEXT: ld.b $t0, $sp, 60
-; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 4
-; LA32-NEXT: ld.b $t2, $sp, 64
-; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 5
-; LA32-NEXT: ld.b $t3, $sp, 68
-; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 6
-; LA32-NEXT: ld.b $t0, $sp, 72
-; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 7
-; LA32-NEXT: ld.b $t2, $sp, 76
-; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 8
-; LA32-NEXT: ld.b $t3, $sp, 80
-; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 9
-; LA32-NEXT: ld.b $t0, $sp, 84
-; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 10
-; LA32-NEXT: ld.b $t2, $sp, 88
-; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 11
-; LA32-NEXT: ld.b $t3, $sp, 96
-; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 12
-; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 13
+; LA32-NEXT: ld.b $t2, $sp, 44
+; LA32-NEXT: ld.b $t3, $sp, 48
+; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 1
+; LA32-NEXT: ld.b $t0, $sp, 52
+; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 2
+; LA32-NEXT: ld.b $t2, $sp, 56
+; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 3
+; LA32-NEXT: ld.b $t3, $sp, 60
+; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 4
+; LA32-NEXT: ld.b $t0, $sp, 64
+; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 5
+; LA32-NEXT: ld.b $t2, $sp, 68
+; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 6
+; LA32-NEXT: ld.b $t3, $sp, 72
+; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 7
+; LA32-NEXT: ld.b $t0, $sp, 76
+; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 8
+; LA32-NEXT: ld.b $t2, $sp, 80
+; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 9
+; LA32-NEXT: ld.b $t3, $sp, 84
+; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 10
+; LA32-NEXT: ld.b $t0, $sp, 88
+; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 11
+; LA32-NEXT: ld.b $t2, $sp, 96
+; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 12
+; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 13
; LA32-NEXT: vinsgr2vr.b $vr0, $t1, 14
-; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 15
+; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 15
; LA32-NEXT: vinsgr2vr.b $vr1, $a1, 0
; LA32-NEXT: vinsgr2vr.b $vr1, $a2, 1
; LA32-NEXT: vinsgr2vr.b $vr1, $a3, 2
@@ -443,38 +442,37 @@ define void @buildvector_v32i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4,
;
; LA64-LABEL: buildvector_v32i8:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.b $t0, $sp, 72
+; LA64-NEXT: ld.b $t0, $sp, 80
+; LA64-NEXT: vldrepl.b $vr0, $sp, 72
; LA64-NEXT: ld.b $t1, $sp, 184
-; LA64-NEXT: ld.b $t2, $sp, 80
-; LA64-NEXT: ld.b $t3, $sp, 88
-; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 0
-; LA64-NEXT: ld.b $t0, $sp, 96
-; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 1
-; LA64-NEXT: ld.b $t2, $sp, 104
-; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 2
-; LA64-NEXT: ld.b $t3, $sp, 112
-; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 3
-; LA64-NEXT: ld.b $t0, $sp, 120
-; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 4
-; LA64-NEXT: ld.b $t2, $sp, 128
-; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 5
-; LA64-NEXT: ld.b $t3, $sp, 136
-; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 6
-; LA64-NEXT: ld.b $t0, $sp, 144
-; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 7
-; LA64-NEXT: ld.b $t2, $sp, 152
-; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 8
-; LA64-NEXT: ld.b $t3, $sp, 160
-; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 9
-; LA64-NEXT: ld.b $t0, $sp, 168
-; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 10
-; LA64-NEXT: ld.b $t2, $sp, 176
-; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 11
-; LA64-NEXT: ld.b $t3, $sp, 192
-; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 12
-; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 13
+; LA64-NEXT: ld.b $t2, $sp, 88
+; LA64-NEXT: ld.b $t3, $sp, 96
+; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 1
+; LA64-NEXT: ld.b $t0, $sp, 104
+; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 2
+; LA64-NEXT: ld.b $t2, $sp, 112
+; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 3
+; LA64-NEXT: ld.b $t3, $sp, 120
+; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 4
+; LA64-NEXT: ld.b $t0, $sp, 128
+; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 5
+; LA64-NEXT: ld.b $t2, $sp, 136
+; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 6
+; LA64-NEXT: ld.b $t3, $sp, 144
+; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 7
+; LA64-NEXT: ld.b $t0, $sp, 152
+; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 8
+; LA64-NEXT: ld.b $t2, $sp, 160
+; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 9
+; LA64-NEXT: ld.b $t3, $sp, 168
+; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 10
+; LA64-NEXT: ld.b $t0, $sp, 176
+; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 11
+; LA64-NEXT: ld.b $t2, $sp, 192
+; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 12
+; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 13
; LA64-NEXT: vinsgr2vr.b $vr0, $t1, 14
-; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 15
+; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 15
; LA64-NEXT: vinsgr2vr.b $vr1, $a1, 0
; LA64-NEXT: vinsgr2vr.b $vr1, $a2, 1
; LA64-NEXT: vinsgr2vr.b $vr1, $a3, 2
@@ -1040,16 +1038,15 @@ define void @buildvector_v16i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i1
; LA32-NEXT: ld.h $t1, $sp, 32
; LA32-NEXT: ld.h $t2, $sp, 28
; LA32-NEXT: ld.h $t3, $sp, 24
-; LA32-NEXT: ld.h $t4, $sp, 20
-; LA32-NEXT: ld.h $t5, $sp, 4
-; LA32-NEXT: ld.h $t6, $sp, 8
-; LA32-NEXT: ld.h $t7, $sp, 12
-; LA32-NEXT: ld.h $t8, $sp, 16
-; LA32-NEXT: vinsgr2vr.h $vr0, $t5, 0
-; LA32-NEXT: vinsgr2vr.h $vr0, $t6, 1
-; LA32-NEXT: vinsgr2vr.h $vr0, $t7, 2
-; LA32-NEXT: vinsgr2vr.h $vr0, $t8, 3
-; LA32-NEXT: vinsgr2vr.h $vr0, $t4, 4
+; LA32-NEXT: ld.h $t4, $sp, 8
+; LA32-NEXT: vldrepl.h $vr0, $sp, 4
+; LA32-NEXT: ld.h $t5, $sp, 12
+; LA32-NEXT: ld.h $t6, $sp, 16
+; LA32-NEXT: ld.h $t7, $sp, 20
+; LA32-NEXT: vinsgr2vr.h $vr0, $t4, 1
+; LA32-NEXT: vinsgr2vr.h $vr0, $t5, 2
+; LA32-NEXT: vinsgr2vr.h $vr0, $t6, 3
+; LA32-NEXT: vinsgr2vr.h $vr0, $t7, 4
; LA32-NEXT: vinsgr2vr.h $vr0, $t3, 5
; LA32-NEXT: vinsgr2vr.h $vr0, $t2, 6
; LA32-NEXT: vinsgr2vr.h $vr0, $t1, 7
@@ -1071,16 +1068,15 @@ define void @buildvector_v16i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i1
; LA64-NEXT: ld.h $t1, $sp, 64
; LA64-NEXT: ld.h $t2, $sp, 56
; LA64-NEXT: ld.h $t3, $sp, 48
-; LA64-NEXT: ld.h $t4, $sp, 40
-; LA64-NEXT: ld.h $t5, $sp, 8
-; LA64-NEXT: ld.h $t6, $sp, 16
-; LA64-NEXT: ld.h $t7, $sp, 24
-; LA64-NEXT: ld.h $t8, $sp, 32
-; LA64-NEXT: vinsgr2vr.h $vr0, $t5, 0
-; LA64-NEXT: vinsgr2vr.h $vr0, $t6, 1
-; LA64-NEXT: vinsgr2vr.h $vr0, $t7, 2
-; LA64-NEXT: vinsgr2vr.h $vr0, $t8, 3
-; LA64-NEXT: vinsgr2vr.h $vr0, $t4, 4
+; LA64-NEXT: ld.h $t4, $sp, 16
+; LA64-NEXT: vldrepl.h $vr0, $sp, 8
+; LA64-NEXT: ld.h $t5, $sp, 24
+; LA64-NEXT: ld.h $t6, $sp, 32
+; LA64-NEXT: ld.h $t7, $sp, 40
+; LA64-NEXT: vinsgr2vr.h $vr0, $t4, 1
+; LA64-NEXT: vinsgr2vr.h $vr0, $t5, 2
+; LA64-NEXT: vinsgr2vr.h $vr0, $t6, 3
+; LA64-NEXT: vinsgr2vr.h $vr0, $t7, 4
; LA64-NEXT: vinsgr2vr.h $vr0, $t3, 5
; LA64-NEXT: vinsgr2vr.h $vr0, $t2, 6
; LA64-NEXT: vinsgr2vr.h $vr0, $t1, 7
diff --git a/llvm/test/CodeGen/LoongArch/lasx/scalar-load-to-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/scalar-load-to-vector.ll
index 34aba5aa829258..4a750298e5ccca 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/scalar-load-to-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/scalar-load-to-vector.ll
@@ -7,8 +7,7 @@
define <32 x i8> @load_to_32xi8(ptr %p) {
; CHECK-LABEL: load_to_32xi8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.b $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.b $vr0, $a0, 0
; CHECK-NEXT: ret
%v = load i8, ptr %p
%ret = insertelement <32 x i8> poison, i8 %v, i32 0
@@ -18,8 +17,7 @@ define <32 x i8> @load_to_32xi8(ptr %p) {
define <16 x i16> @load_to_16xi16(ptr %p) {
; CHECK-LABEL: load_to_16xi16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: ret
%v = load i16, ptr %p
%ret = insertelement <16 x i16> poison, i16 %v, i32 0
@@ -29,8 +27,7 @@ define <16 x i16> @load_to_16xi16(ptr %p) {
define <8 x i32> @load_to_8xi32(ptr %p) {
; CHECK-LABEL: load_to_8xi32:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: ret
%v = load i32, ptr %p
%ret = insertelement <8 x i32> poison, i32 %v, i32 0
@@ -40,16 +37,14 @@ define <8 x i32> @load_to_8xi32(ptr %p) {
define <4 x i64> @load_to_4xi64(ptr %p) {
; LA32-LABEL: load_to_4xi64:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: ret
;
; LA64-LABEL: load_to_4xi64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: ret
%v = load i64, ptr %p
%ret = insertelement <4 x i64> poison, i64 %v, i32 0
@@ -58,11 +53,17 @@ define <4 x i64> @load_to_4xi64(ptr %p) {
;; Offsets that aren't a multiple of the element size.
define <16 x i16> @load_to_16xi16_offset(ptr %p) {
-; CHECK-LABEL: load_to_16xi16_offset:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, -3
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: load_to_16xi16_offset:
+; LA32: # %bb.0:
+; LA32-NEXT: addi.w $a0, $a0, -3
+; LA32-NEXT: vldrepl.h $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_to_16xi16_offset:
+; LA64: # %bb.0:
+; LA64-NEXT: addi.d $a0, $a0, -3
+; LA64-NEXT: vldrepl.h $vr0, $a0, 0
+; LA64-NEXT: ret
%gep = getelementptr i8, ptr %p, i64 -3
%v = load i16, ptr %gep
%ret = insertelement <16 x i16> poison, i16 %v, i32 0
@@ -72,16 +73,14 @@ define <16 x i16> @load_to_16xi16_offset(ptr %p) {
define <4 x i64> @load_to_4xi64_offset(ptr %p) {
; LA32-LABEL: load_to_4xi64_offset:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 6
-; LA32-NEXT: ld.w $a0, $a0, 10
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 10
+; LA32-NEXT: fld.s $fa0, $a0, 6
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: ret
;
; LA64-LABEL: load_to_4xi64_offset:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 6
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 6
; LA64-NEXT: ret
%gep = getelementptr i8, ptr %p, i64 6
%v = load i64, ptr %gep
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll
index 4536027edc3aa2..172962a8cc0e84 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-sext-invec-mask.ll
@@ -10,8 +10,7 @@
define void @zext_or_masks_v4i8_to_v4i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: zext_or_masks_v4i8_to_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 1
; CHECK-NEXT: vslt.b $vr1, $vr1, $vr0
; CHECK-NEXT: vseqi.b $vr0, $vr0, 0
@@ -33,10 +32,9 @@ define void @zext_or_masks_v4i8_to_v4i64(ptr %ptr, ptr %dst) {
define void @zext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) {
; LA32-LABEL: zext_or_masks_v4i16_to_v4i64:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.h $vr1, 1
; LA32-NEXT: vslt.h $vr1, $vr1, $vr0
; LA32-NEXT: vseqi.h $vr0, $vr0, 0
@@ -49,8 +47,7 @@ define void @zext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: zext_or_masks_v4i16_to_v4i64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.h $vr1, 1
; LA64-NEXT: vslt.h $vr1, $vr1, $vr0
; LA64-NEXT: vseqi.h $vr0, $vr0, 0
@@ -72,10 +69,9 @@ define void @zext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) {
define void @zext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) {
; LA32-LABEL: zext_or_masks_v8i8_to_v8i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.b $vr1, 1
; LA32-NEXT: vslt.b $vr1, $vr1, $vr0
; LA32-NEXT: vseqi.b $vr0, $vr0, 0
@@ -88,8 +84,7 @@ define void @zext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: zext_or_masks_v8i8_to_v8i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 1
; LA64-NEXT: vslt.b $vr1, $vr1, $vr0
; LA64-NEXT: vseqi.b $vr0, $vr0, 0
@@ -111,8 +106,7 @@ define void @zext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) {
define void @sext_or_masks_v4i8_to_v4i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: sext_or_masks_v4i8_to_v4i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 1
; CHECK-NEXT: vslt.b $vr1, $vr1, $vr0
; CHECK-NEXT: vseqi.b $vr0, $vr0, 0
@@ -132,10 +126,9 @@ define void @sext_or_masks_v4i8_to_v4i64(ptr %ptr, ptr %dst) {
define void @sext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) {
; LA32-LABEL: sext_or_masks_v4i16_to_v4i64:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.h $vr1, 1
; LA32-NEXT: vslt.h $vr1, $vr1, $vr0
; LA32-NEXT: vseqi.h $vr0, $vr0, 0
@@ -146,8 +139,7 @@ define void @sext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: sext_or_masks_v4i16_to_v4i64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.h $vr1, 1
; LA64-NEXT: vslt.h $vr1, $vr1, $vr0
; LA64-NEXT: vseqi.h $vr0, $vr0, 0
@@ -167,10 +159,9 @@ define void @sext_or_masks_v4i16_to_v4i64(ptr %ptr, ptr %dst) {
define void @sext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) {
; LA32-LABEL: sext_or_masks_v8i8_to_v8i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.b $vr1, 1
; LA32-NEXT: vslt.b $vr1, $vr1, $vr0
; LA32-NEXT: vseqi.b $vr0, $vr0, 0
@@ -181,8 +172,7 @@ define void @sext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: sext_or_masks_v8i8_to_v8i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 1
; LA64-NEXT: vslt.b $vr1, $vr1, $vr0
; LA64-NEXT: vseqi.b $vr0, $vr0, 0
@@ -204,9 +194,8 @@ define void @sext_or_masks_v8i8_to_v8i32(ptr %ptr, ptr %dst) {
define void @mixed_masks_wide_lhs(ptr %ptr, ptr %dst) {
; CHECK-LABEL: mixed_masks_wide_lhs:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a2, $a0, 0
; CHECK-NEXT: xvld $xr0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr1, $a2, 0
+; CHECK-NEXT: fld.s $fa1, $a0, 0
; CHECK-NEXT: xvrepli.d $xr2, 1
; CHECK-NEXT: xvslt.d $xr0, $xr2, $xr0
; CHECK-NEXT: vseqi.b $vr1, $vr1, 0
@@ -227,9 +216,8 @@ define void @mixed_masks_wide_lhs(ptr %ptr, ptr %dst) {
define void @mixed_masks_wide_rhs(ptr %ptr, ptr %dst) {
; CHECK-LABEL: mixed_masks_wide_rhs:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a2, $a0, 0
; CHECK-NEXT: xvld $xr0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr1, $a2, 0
+; CHECK-NEXT: fld.s $fa1, $a0, 0
; CHECK-NEXT: xvrepli.d $xr2, 1
; CHECK-NEXT: xvslt.d $xr0, $xr2, $xr0
; CHECK-NEXT: xvpickev.w $xr0, $xr0, $xr0
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
index a0d4ab009f0ceb..40d171057ff89a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-sext.ll
@@ -5,8 +5,7 @@
define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_2i8_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vext2xv.d.b $xr0, $xr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -20,8 +19,7 @@ entry:
define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_4i8_to_4i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vext2xv.w.b $xr0, $xr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -35,18 +33,16 @@ entry:
define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_8i8_to_8i16:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vext2xv.h.b $xr0, $xr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_sext_8i8_to_8i16:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vext2xv.h.b $xr0, $xr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
@@ -60,8 +56,7 @@ entry:
define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_2i16_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vext2xv.d.h $xr0, $xr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -75,18 +70,16 @@ entry:
define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_4i16_to_4i32:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vext2xv.w.h $xr0, $xr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_sext_4i16_to_4i32:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vext2xv.w.h $xr0, $xr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
@@ -100,18 +93,16 @@ entry:
define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_2i32_to_2i64:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vext2xv.d.w $xr0, $xr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_sext_2i32_to_2i64:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vext2xv.d.w $xr0, $xr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-trunc-combine.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-trunc-combine.ll
index a152053eceb065..9af27abf73118f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vec-trunc-combine.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-trunc-combine.ll
@@ -5,10 +5,9 @@
define void @test_trunc_v4i16_to_v4i8(ptr %src, ptr %dst) {
; LA32-LABEL: test_trunc_v4i16_to_v4i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vpickev.b $vr0, $vr0, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
@@ -16,8 +15,7 @@ define void @test_trunc_v4i16_to_v4i8(ptr %src, ptr %dst) {
;
; LA64-LABEL: test_trunc_v4i16_to_v4i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vpickev.b $vr0, $vr0, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
index e2dfe308742513..f6b03fbf26aefc 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-zext.ll
@@ -6,8 +6,7 @@
define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_zext_2i8_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vext2xv.du.bu $xr0, $xr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -21,8 +20,7 @@ entry:
define void @load_zext_4i8_to_4i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_zext_4i8_to_4i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vext2xv.wu.bu $xr0, $xr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -36,18 +34,16 @@ entry:
define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_zext_8i8_to_8i16:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vext2xv.hu.bu $xr0, $xr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_zext_8i8_to_8i16:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vext2xv.hu.bu $xr0, $xr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
@@ -61,8 +57,7 @@ entry:
define void @load_zext_2i16_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_zext_2i16_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vext2xv.du.hu $xr0, $xr0
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -76,18 +71,16 @@ entry:
define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_zext_4i16_to_4i32:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vext2xv.wu.hu $xr0, $xr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_zext_4i16_to_4i32:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vext2xv.wu.hu $xr0, $xr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
@@ -101,18 +94,16 @@ entry:
define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_zext_2i32_to_2i64:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vext2xv.du.wu $xr0, $xr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_zext_2i32_to_2i64:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vext2xv.du.wu $xr0, $xr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
index 41c38b01ce98e0..4eb7ddaed148a4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
@@ -57,10 +57,9 @@ define <8 x i16> @should_not_be_optimized_zext_load(ptr %ptr) {
define <2 x i64> @vldrepl_d_unaligned_offset(ptr %ptr) {
; LA32-LABEL: vldrepl_d_unaligned_offset:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 4
-; LA32-NEXT: ld.w $a0, $a0, 8
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 8
+; LA32-NEXT: fld.s $fa0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: vreplvei.d $vr0, $vr0, 0
; LA32-NEXT: ret
;
@@ -149,10 +148,9 @@ define <4 x i32> @vldrepl_w_offset(ptr %ptr) {
define <2 x i64> @vldrepl_d(ptr %ptr) {
; LA32-LABEL: vldrepl_d:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: vreplvei.d $vr0, $vr0, 0
; LA32-NEXT: ret
;
@@ -169,10 +167,9 @@ define <2 x i64> @vldrepl_d(ptr %ptr) {
define <2 x i64> @vldrepl_d_offset(ptr %ptr) {
; LA32-LABEL: vldrepl_d_offset:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 264
-; LA32-NEXT: ld.w $a0, $a0, 268
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 268
+; LA32-NEXT: fld.s $fa0, $a0, 264
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: vreplvei.d $vr0, $vr0, 0
; LA32-NEXT: ret
;
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
index d6177d5ca0969b..3a3df57ce310f1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
@@ -230,51 +230,47 @@ define <4 x double> @sitofp_v16i8_v4f64(<16 x i8> %a) {
define <5 x double> @sitofp_v5i32_v5f64(<5 x i32> %a) {
; LA32-LABEL: sitofp_v5i32_v5f64:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a1, 16
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: ld.w $a2, $a1, 0
-; LA32-NEXT: ld.w $a3, $a1, 4
-; LA32-NEXT: ld.w $a4, $a1, 8
-; LA32-NEXT: ld.w $a1, $a1, 12
-; LA32-NEXT: vinsgr2vr.w $vr1, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 1
-; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 2
-; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 3
-; LA32-NEXT: vslti.w $vr2, $vr1, 0
-; LA32-NEXT: vilvl.w $vr3, $vr2, $vr1
-; LA32-NEXT: vffint.d.l $vr3, $vr3
-; LA32-NEXT: vilvh.w $vr1, $vr2, $vr1
-; LA32-NEXT: vffint.d.l $vr1, $vr1
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: fld.s $fa0, $a1, 0
+; LA32-NEXT: ld.w $a3, $a1, 8
+; LA32-NEXT: ld.w $a4, $a1, 12
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 3
+; LA32-NEXT: fld.s $fa1, $a1, 16
; LA32-NEXT: vslti.w $vr2, $vr0, 0
-; LA32-NEXT: vilvl.w $vr0, $vr2, $vr0
+; LA32-NEXT: vilvl.w $vr3, $vr2, $vr0
+; LA32-NEXT: vffint.d.l $vr3, $vr3
+; LA32-NEXT: vilvh.w $vr0, $vr2, $vr0
; LA32-NEXT: vffint.d.l $vr0, $vr0
-; LA32-NEXT: vstelm.d $vr0, $a0, 32, 0
-; LA32-NEXT: vst $vr1, $a0, 16
+; LA32-NEXT: vslti.w $vr2, $vr1, 0
+; LA32-NEXT: vilvl.w $vr1, $vr2, $vr1
+; LA32-NEXT: vffint.d.l $vr1, $vr1
+; LA32-NEXT: vstelm.d $vr1, $a0, 32, 0
+; LA32-NEXT: vst $vr0, $a0, 16
; LA32-NEXT: vst $vr3, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: sitofp_v5i32_v5f64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.w $a2, $a1, 32
-; LA64-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA64-NEXT: ld.w $a2, $a1, 0
-; LA64-NEXT: ld.w $a3, $a1, 8
-; LA64-NEXT: ld.w $a4, $a1, 16
-; LA64-NEXT: ld.w $a1, $a1, 24
-; LA64-NEXT: vinsgr2vr.w $vr1, $a2, 0
-; LA64-NEXT: vinsgr2vr.w $vr1, $a3, 1
-; LA64-NEXT: vinsgr2vr.w $vr1, $a4, 2
-; LA64-NEXT: vinsgr2vr.w $vr1, $a1, 3
-; LA64-NEXT: vslti.w $vr2, $vr1, 0
-; LA64-NEXT: vilvl.w $vr3, $vr2, $vr1
-; LA64-NEXT: vffint.d.l $vr3, $vr3
-; LA64-NEXT: vilvh.w $vr1, $vr2, $vr1
-; LA64-NEXT: vffint.d.l $vr1, $vr1
+; LA64-NEXT: ld.w $a2, $a1, 8
+; LA64-NEXT: fld.s $fa0, $a1, 0
+; LA64-NEXT: ld.w $a3, $a1, 16
+; LA64-NEXT: ld.w $a4, $a1, 24
+; LA64-NEXT: vinsgr2vr.w $vr0, $a2, 1
+; LA64-NEXT: vinsgr2vr.w $vr0, $a3, 2
+; LA64-NEXT: vinsgr2vr.w $vr0, $a4, 3
+; LA64-NEXT: fld.s $fa1, $a1, 32
; LA64-NEXT: vslti.w $vr2, $vr0, 0
-; LA64-NEXT: vilvl.w $vr0, $vr2, $vr0
+; LA64-NEXT: vilvl.w $vr3, $vr2, $vr0
+; LA64-NEXT: vffint.d.l $vr3, $vr3
+; LA64-NEXT: vilvh.w $vr0, $vr2, $vr0
; LA64-NEXT: vffint.d.l $vr0, $vr0
-; LA64-NEXT: vstelm.d $vr0, $a0, 32, 0
-; LA64-NEXT: vst $vr1, $a0, 16
+; LA64-NEXT: vslti.w $vr2, $vr1, 0
+; LA64-NEXT: vilvl.w $vr1, $vr2, $vr1
+; LA64-NEXT: vffint.d.l $vr1, $vr1
+; LA64-NEXT: vstelm.d $vr1, $a0, 32, 0
+; LA64-NEXT: vst $vr0, $a0, 16
; LA64-NEXT: vst $vr3, $a0, 0
; LA64-NEXT: ret
%v = sitofp <5 x i32> %a to <5 x double>
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
index dd526904af4151..9ffe0a0bfd5638 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
@@ -91,50 +91,44 @@ define <4 x double> @uitofp_v16i8_v4f64(<16 x i8> %a) {
define <5 x double> @uitofp_v5i32_v5f64(<5 x i32> %a) {
; LA32-LABEL: uitofp_v5i32_v5f64:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a1, 16
-; LA32-NEXT: ld.w $a3, $a1, 0
-; LA32-NEXT: ld.w $a4, $a1, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr1, $a3, 0
-; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 1
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: fld.s $fa0, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
+; LA32-NEXT: fld.s $fa1, $a1, 16
; LA32-NEXT: ld.w $a2, $a1, 12
-; LA32-NEXT: ld.w $a1, $a1, 8
-; LA32-NEXT: vrepli.b $vr2, 0
-; LA32-NEXT: vilvl.w $vr1, $vr2, $vr1
-; LA32-NEXT: vffint.d.lu $vr1, $vr1
-; LA32-NEXT: vinsgr2vr.w $vr3, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr3, $a2, 1
-; LA32-NEXT: vilvl.w $vr3, $vr2, $vr3
-; LA32-NEXT: vffint.d.lu $vr3, $vr3
-; LA32-NEXT: vilvl.w $vr0, $vr2, $vr0
+; LA32-NEXT: fld.s $fa2, $a1, 8
+; LA32-NEXT: vrepli.b $vr3, 0
+; LA32-NEXT: vilvl.w $vr0, $vr3, $vr0
; LA32-NEXT: vffint.d.lu $vr0, $vr0
-; LA32-NEXT: vstelm.d $vr0, $a0, 32, 0
-; LA32-NEXT: vst $vr3, $a0, 16
-; LA32-NEXT: vst $vr1, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr2, $a2, 1
+; LA32-NEXT: vilvl.w $vr2, $vr3, $vr2
+; LA32-NEXT: vffint.d.lu $vr2, $vr2
+; LA32-NEXT: vilvl.w $vr1, $vr3, $vr1
+; LA32-NEXT: vffint.d.lu $vr1, $vr1
+; LA32-NEXT: vstelm.d $vr1, $a0, 32, 0
+; LA32-NEXT: vst $vr2, $a0, 16
+; LA32-NEXT: vst $vr0, $a0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: uitofp_v5i32_v5f64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.w $a2, $a1, 32
-; LA64-NEXT: ld.w $a3, $a1, 0
-; LA64-NEXT: ld.w $a4, $a1, 8
-; LA64-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA64-NEXT: vinsgr2vr.w $vr1, $a3, 0
-; LA64-NEXT: vinsgr2vr.w $vr1, $a4, 1
+; LA64-NEXT: ld.w $a2, $a1, 8
+; LA64-NEXT: fld.s $fa0, $a1, 0
+; LA64-NEXT: vinsgr2vr.w $vr0, $a2, 1
+; LA64-NEXT: fld.s $fa1, $a1, 32
; LA64-NEXT: ld.w $a2, $a1, 24
-; LA64-NEXT: ld.w $a1, $a1, 16
-; LA64-NEXT: vrepli.b $vr2, 0
-; LA64-NEXT: vilvl.w $vr1, $vr2, $vr1
-; LA64-NEXT: vffint.d.lu $vr1, $vr1
-; LA64-NEXT: vinsgr2vr.w $vr3, $a1, 0
-; LA64-NEXT: vinsgr2vr.w $vr3, $a2, 1
-; LA64-NEXT: vilvl.w $vr3, $vr2, $vr3
-; LA64-NEXT: vffint.d.lu $vr3, $vr3
-; LA64-NEXT: vilvl.w $vr0, $vr2, $vr0
+; LA64-NEXT: fld.s $fa2, $a1, 16
+; LA64-NEXT: vrepli.b $vr3, 0
+; LA64-NEXT: vilvl.w $vr0, $vr3, $vr0
; LA64-NEXT: vffint.d.lu $vr0, $vr0
-; LA64-NEXT: vstelm.d $vr0, $a0, 32, 0
-; LA64-NEXT: vst $vr3, $a0, 16
-; LA64-NEXT: vst $vr1, $a0, 0
+; LA64-NEXT: vinsgr2vr.w $vr2, $a2, 1
+; LA64-NEXT: vilvl.w $vr2, $vr3, $vr2
+; LA64-NEXT: vffint.d.lu $vr2, $vr2
+; LA64-NEXT: vilvl.w $vr1, $vr3, $vr1
+; LA64-NEXT: vffint.d.lu $vr1, $vr1
+; LA64-NEXT: vstelm.d $vr1, $a0, 32, 0
+; LA64-NEXT: vst $vr2, $a0, 16
+; LA64-NEXT: vst $vr0, $a0, 0
; LA64-NEXT: ret
%v = uitofp <5 x i32> %a to <5 x double>
ret <5 x double> %v
diff --git a/llvm/test/CodeGen/LoongArch/lsx/scalar-load-to-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/scalar-load-to-vector.ll
index dfb92679124dc8..b3e78e98d7c08a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/scalar-load-to-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/scalar-load-to-vector.ll
@@ -7,8 +7,7 @@
define <16 x i8> @load_to_16xi8(ptr %p) {
; CHECK-LABEL: load_to_16xi8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.b $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.b $vr0, $a0, 0
; CHECK-NEXT: ret
%v = load i8, ptr %p
%ret = insertelement <16 x i8> poison, i8 %v, i32 0
@@ -18,8 +17,7 @@ define <16 x i8> @load_to_16xi8(ptr %p) {
define <8 x i16> @load_to_8xi16(ptr %p) {
; CHECK-LABEL: load_to_8xi16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: ret
%v = load i16, ptr %p
%ret = insertelement <8 x i16> poison, i16 %v, i32 0
@@ -29,8 +27,7 @@ define <8 x i16> @load_to_8xi16(ptr %p) {
define <4 x i32> @load_to_4xi32(ptr %p) {
; CHECK-LABEL: load_to_4xi32:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: ret
%v = load i32, ptr %p
%ret = insertelement <4 x i32> poison, i32 %v, i32 0
@@ -40,16 +37,14 @@ define <4 x i32> @load_to_4xi32(ptr %p) {
define <2 x i64> @load_to_2xi64(ptr %p) {
; LA32-LABEL: load_to_2xi64:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: ret
;
; LA64-LABEL: load_to_2xi64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: ret
%v = load i64, ptr %p
%ret = insertelement <2 x i64> poison, i64 %v, i32 0
@@ -58,11 +53,17 @@ define <2 x i64> @load_to_2xi64(ptr %p) {
;; Offsets that aren't a multiple of the element size.
define <8 x i16> @load_to_8xi16_offset(ptr %p) {
-; CHECK-LABEL: load_to_8xi16_offset:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, -3
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: load_to_8xi16_offset:
+; LA32: # %bb.0:
+; LA32-NEXT: addi.w $a0, $a0, -3
+; LA32-NEXT: vldrepl.h $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_to_8xi16_offset:
+; LA64: # %bb.0:
+; LA64-NEXT: addi.d $a0, $a0, -3
+; LA64-NEXT: vldrepl.h $vr0, $a0, 0
+; LA64-NEXT: ret
%gep = getelementptr i8, ptr %p, i64 -3
%v = load i16, ptr %gep
%ret = insertelement <8 x i16> poison, i16 %v, i32 0
@@ -72,16 +73,14 @@ define <8 x i16> @load_to_8xi16_offset(ptr %p) {
define <2 x i64> @load_to_2xi64_offset(ptr %p) {
; LA32-LABEL: load_to_2xi64_offset:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 6
-; LA32-NEXT: ld.w $a0, $a0, 10
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 10
+; LA32-NEXT: fld.s $fa0, $a0, 6
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: ret
;
; LA64-LABEL: load_to_2xi64_offset:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 6
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 6
; LA64-NEXT: ret
%gep = getelementptr i8, ptr %p, i64 6
%v = load i64, ptr %gep
@@ -111,8 +110,7 @@ define <2 x i64> @load_4xi16_sext(ptr %p) {
;
; LA64-LABEL: load_4xi16_sext:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vslti.h $vr1, $vr0, 0
; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0
; LA64-NEXT: vslti.w $vr1, $vr0, 0
@@ -127,18 +125,16 @@ define <2 x i64> @load_4xi16_sext(ptr %p) {
define <2 x i64> @load_2xi32_sext(ptr %p) {
; LA32-LABEL: load_2xi32_sext:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a1, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a1, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
; LA32-NEXT: vslti.w $vr1, $vr0, 0
; LA32-NEXT: vilvl.w $vr0, $vr1, $vr0
; LA32-NEXT: ret
;
; LA64-LABEL: load_2xi32_sext:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vslti.w $vr1, $vr0, 0
; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0
; LA64-NEXT: ret
@@ -150,8 +146,7 @@ define <2 x i64> @load_2xi32_sext(ptr %p) {
define <4 x i32> @load_2xi16_zext(ptr %p) {
; CHECK-LABEL: load_2xi16_zext:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 0
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
; CHECK-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll
index 9c3a6f7be0542a..b0b174b13bdf69 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-add.ll
@@ -33,10 +33,9 @@ define void @vec_reduce_add_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_add_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vhaddw.h.b $vr0, $vr0, $vr0
; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr0
@@ -46,8 +45,7 @@ define void @vec_reduce_add_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_add_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vhaddw.h.b $vr0, $vr0, $vr0
; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr0
@@ -63,8 +61,7 @@ define void @vec_reduce_add_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_add_v4i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v4i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a0, $a0, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; LA32-NEXT: fld.s $fa0, $a0, 0
; LA32-NEXT: vhaddw.h.b $vr0, $vr0, $vr0
; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
@@ -73,8 +70,7 @@ define void @vec_reduce_add_v4i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_add_v4i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.w $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; LA64-NEXT: fld.s $fa0, $a0, 0
; LA64-NEXT: vhaddw.h.b $vr0, $vr0, $vr0
; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
@@ -89,8 +85,7 @@ define void @vec_reduce_add_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_add_v2i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v2i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.h $a0, $a0, 0
-; LA32-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; LA32-NEXT: vldrepl.h $vr0, $a0, 0
; LA32-NEXT: vhaddw.h.b $vr0, $vr0, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.b $a0, $a1, 0
@@ -98,8 +93,7 @@ define void @vec_reduce_add_v2i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_add_v2i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.h $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; LA64-NEXT: vldrepl.h $vr0, $a0, 0
; LA64-NEXT: vhaddw.h.b $vr0, $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
; LA64-NEXT: st.b $a0, $a1, 0
@@ -139,10 +133,9 @@ define void @vec_reduce_add_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_add_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
@@ -151,8 +144,7 @@ define void @vec_reduce_add_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_add_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
@@ -167,8 +159,7 @@ define void @vec_reduce_add_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_add_v2i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v2i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a0, $a0, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; LA32-NEXT: fld.s $fa0, $a0, 0
; LA32-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.h $a0, $a1, 0
@@ -176,8 +167,7 @@ define void @vec_reduce_add_v2i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_add_v2i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.w $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; LA64-NEXT: fld.s $fa0, $a0, 0
; LA64-NEXT: vhaddw.w.h $vr0, $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
; LA64-NEXT: st.h $a0, $a1, 0
@@ -215,10 +205,9 @@ define void @vec_reduce_add_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_add_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_add_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vhaddw.d.w $vr0, $vr0, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
@@ -226,8 +215,7 @@ define void @vec_reduce_add_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_add_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vhaddw.d.w $vr0, $vr0, $vr0
; LA64-NEXT: vpickve2gr.d $a0, $vr0, 0
; LA64-NEXT: st.w $a0, $a1, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
index 734ecba843a4e6..38d37fc929bf08 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-and.ll
@@ -25,10 +25,9 @@ define void @vec_reduce_and_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_and_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_and_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vand.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -40,8 +39,7 @@ define void @vec_reduce_and_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_and_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vand.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -59,8 +57,7 @@ define void @vec_reduce_and_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_and_v4i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_and_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vand.v $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
@@ -76,8 +73,7 @@ define void @vec_reduce_and_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_and_v2i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_and_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT: vand.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
@@ -109,10 +105,9 @@ define void @vec_reduce_and_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_and_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_and_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vand.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -122,8 +117,7 @@ define void @vec_reduce_and_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_and_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vand.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -139,8 +133,7 @@ define void @vec_reduce_and_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_and_v2i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_and_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vand.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
@@ -181,9 +174,8 @@ define void @vec_reduce_and_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_and_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_and_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: fld.s $fa0, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
; LA32-NEXT: vori.b $vr1, $vr0, 0
; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
; LA32-NEXT: vbsrl.v $vr1, $vr1, 4
@@ -194,8 +186,7 @@ define void @vec_reduce_and_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_and_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vand.v $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
index e833930830c3f7..66f5e0e2d1791c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-or.ll
@@ -25,10 +25,9 @@ define void @vec_reduce_or_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_or_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_or_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vor.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -40,8 +39,7 @@ define void @vec_reduce_or_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_or_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vor.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -59,8 +57,7 @@ define void @vec_reduce_or_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_or_v4i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_or_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
@@ -76,8 +73,7 @@ define void @vec_reduce_or_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_or_v2i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_or_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
@@ -109,10 +105,9 @@ define void @vec_reduce_or_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_or_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_or_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vor.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -122,8 +117,7 @@ define void @vec_reduce_or_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_or_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vor.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -139,8 +133,7 @@ define void @vec_reduce_or_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_or_v2i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_or_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
@@ -181,9 +174,8 @@ define void @vec_reduce_or_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_or_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_or_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: fld.s $fa0, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
; LA32-NEXT: vori.b $vr1, $vr0, 0
; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
; LA32-NEXT: vbsrl.v $vr1, $vr1, 4
@@ -194,8 +186,7 @@ define void @vec_reduce_or_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_or_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vor.v $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
index 2220df68cddfd4..5283e03810af01 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smax.ll
@@ -25,10 +25,9 @@ define void @vec_reduce_smax_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smax_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smax_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.b $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -40,8 +39,7 @@ define void @vec_reduce_smax_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_smax_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.b $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -59,8 +57,7 @@ define void @vec_reduce_smax_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smax_v4i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_smax_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
@@ -76,8 +73,7 @@ define void @vec_reduce_smax_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smax_v2i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_smax_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT: vmax.b $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
@@ -109,10 +105,9 @@ define void @vec_reduce_smax_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smax_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smax_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.h $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -122,8 +117,7 @@ define void @vec_reduce_smax_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_smax_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.h $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -139,8 +133,7 @@ define void @vec_reduce_smax_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smax_v2i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_smax_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmax.h $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
@@ -181,10 +174,9 @@ define void @vec_reduce_smax_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smax_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smax_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.w $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
@@ -193,8 +185,7 @@ define void @vec_reduce_smax_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_smax_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.w $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
index 50d76a3872e1e5..6385ca378582b1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-smin.ll
@@ -25,10 +25,9 @@ define void @vec_reduce_smin_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smin_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smin_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.b $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -40,8 +39,7 @@ define void @vec_reduce_smin_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_smin_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.b $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -59,8 +57,7 @@ define void @vec_reduce_smin_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smin_v4i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_smin_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
@@ -76,8 +73,7 @@ define void @vec_reduce_smin_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smin_v2i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_smin_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT: vmin.b $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
@@ -109,10 +105,9 @@ define void @vec_reduce_smin_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smin_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smin_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.h $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -122,8 +117,7 @@ define void @vec_reduce_smin_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_smin_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.h $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -139,8 +133,7 @@ define void @vec_reduce_smin_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smin_v2i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_smin_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmin.h $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
@@ -181,10 +174,9 @@ define void @vec_reduce_smin_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_smin_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_smin_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.w $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
@@ -193,8 +185,7 @@ define void @vec_reduce_smin_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_smin_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.w $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
index 88146c78a969d0..7ca0025d4d0e9b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umax.ll
@@ -25,10 +25,9 @@ define void @vec_reduce_umax_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umax_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umax_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.bu $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -40,8 +39,7 @@ define void @vec_reduce_umax_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_umax_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.bu $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -59,8 +57,7 @@ define void @vec_reduce_umax_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umax_v4i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umax_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
@@ -76,8 +73,7 @@ define void @vec_reduce_umax_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umax_v2i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umax_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT: vmax.bu $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
@@ -109,10 +105,9 @@ define void @vec_reduce_umax_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umax_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umax_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.hu $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -122,8 +117,7 @@ define void @vec_reduce_umax_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_umax_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.hu $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -139,8 +133,7 @@ define void @vec_reduce_umax_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umax_v2i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umax_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmax.hu $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
@@ -181,10 +174,9 @@ define void @vec_reduce_umax_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umax_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umax_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmax.wu $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
@@ -193,8 +185,7 @@ define void @vec_reduce_umax_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_umax_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmax.wu $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
index e9d4b4aab6f910..dccb97e6ebebdb 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-umin.ll
@@ -25,10 +25,9 @@ define void @vec_reduce_umin_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umin_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umin_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.bu $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -40,8 +39,7 @@ define void @vec_reduce_umin_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_umin_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.bu $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -59,8 +57,7 @@ define void @vec_reduce_umin_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umin_v4i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umin_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
@@ -76,8 +73,7 @@ define void @vec_reduce_umin_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umin_v2i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umin_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT: vmin.bu $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
@@ -109,10 +105,9 @@ define void @vec_reduce_umin_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umin_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umin_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.hu $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -122,8 +117,7 @@ define void @vec_reduce_umin_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_umin_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.hu $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -139,8 +133,7 @@ define void @vec_reduce_umin_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umin_v2i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_umin_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vmin.hu $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
@@ -181,10 +174,9 @@ define void @vec_reduce_umin_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_umin_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_umin_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vmin.wu $vr0, $vr1, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
@@ -193,8 +185,7 @@ define void @vec_reduce_umin_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_umin_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vmin.wu $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
index ed965e9e10ee7c..38ca431296f854 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-reduce-xor.ll
@@ -25,10 +25,9 @@ define void @vec_reduce_xor_v16i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_xor_v8i8(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_xor_v8i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vxor.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -40,8 +39,7 @@ define void @vec_reduce_xor_v8i8(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_xor_v8i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vxor.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -59,8 +57,7 @@ define void @vec_reduce_xor_v8i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_xor_v4i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_xor_v4i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
@@ -76,8 +73,7 @@ define void @vec_reduce_xor_v4i8(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_xor_v2i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_xor_v2i8:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 1
; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.b $vr0, $a1, 0, 0
@@ -109,10 +105,9 @@ define void @vec_reduce_xor_v8i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_xor_v4i16(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_xor_v4i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vbsrl.v $vr1, $vr0, 4
; LA32-NEXT: vxor.v $vr0, $vr1, $vr0
; LA32-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -122,8 +117,7 @@ define void @vec_reduce_xor_v4i16(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_xor_v4i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vxor.v $vr0, $vr1, $vr0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 2
@@ -139,8 +133,7 @@ define void @vec_reduce_xor_v4i16(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_xor_v2i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: vec_reduce_xor_v2i16:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vbsrl.v $vr1, $vr0, 2
; CHECK-NEXT: vxor.v $vr0, $vr1, $vr0
; CHECK-NEXT: vstelm.h $vr0, $a1, 0, 0
@@ -181,9 +174,8 @@ define void @vec_reduce_xor_v4i32(ptr %src, ptr %dst) nounwind {
define void @vec_reduce_xor_v2i32(ptr %src, ptr %dst) nounwind {
; LA32-LABEL: vec_reduce_xor_v2i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: fld.s $fa0, $a0, 0
; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
; LA32-NEXT: vori.b $vr1, $vr0, 0
; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
; LA32-NEXT: vbsrl.v $vr1, $vr1, 4
@@ -194,8 +186,7 @@ define void @vec_reduce_xor_v2i32(ptr %src, ptr %dst) nounwind {
;
; LA64-LABEL: vec_reduce_xor_v2i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vbsrl.v $vr1, $vr0, 4
; LA64-NEXT: vxor.v $vr0, $vr1, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
index 22e87d812eafa1..157242951c8577 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-sext.ll
@@ -5,8 +5,7 @@
define void @load_sext_2i8_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_2i8_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
; CHECK-NEXT: vslli.d $vr0, $vr0, 56
; CHECK-NEXT: vsrai.d $vr0, $vr0, 56
@@ -22,8 +21,7 @@ entry:
define void @load_sext_4i8_to_4i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_4i8_to_4i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
; CHECK-NEXT: vslli.w $vr0, $vr0, 24
@@ -40,10 +38,9 @@ entry:
define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_8i8_to_8i16:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vslti.b $vr1, $vr0, 0
; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
@@ -51,8 +48,7 @@ define void @load_sext_8i8_to_8i16(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: load_sext_8i8_to_8i16:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vslti.b $vr1, $vr0, 0
; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
@@ -67,8 +63,7 @@ entry:
define void @load_sext_2i16_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_sext_2i16_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
; CHECK-NEXT: vslli.d $vr0, $vr0, 48
; CHECK-NEXT: vsrai.d $vr0, $vr0, 48
@@ -84,10 +79,9 @@ entry:
define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_4i16_to_4i32:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vslti.h $vr1, $vr0, 0
; LA32-NEXT: vilvl.h $vr0, $vr1, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
@@ -95,8 +89,7 @@ define void @load_sext_4i16_to_4i32(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: load_sext_4i16_to_4i32:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vslti.h $vr1, $vr0, 0
; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
@@ -111,10 +104,9 @@ entry:
define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_sext_2i32_to_2i64:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vslti.w $vr1, $vr0, 0
; LA32-NEXT: vilvl.w $vr0, $vr1, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
@@ -122,8 +114,7 @@ define void @load_sext_2i32_to_2i64(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: load_sext_2i32_to_2i64:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vslti.w $vr1, $vr0, 0
; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-any-ext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-any-ext.ll
index 06ab85a84fb283..7279c0c3dfe064 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-any-ext.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-any-ext.ll
@@ -5,8 +5,7 @@
define void @shuffle_any_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind {
; CHECK-LABEL: shuffle_any_ext_2i8_to_2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vextrins.b $vr0, $vr0, 129
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -20,8 +19,7 @@ define void @shuffle_any_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_any_ext_2i16_to_2i64(ptr %ptr, ptr %dst) nounwind {
; CHECK-LABEL: shuffle_any_ext_2i16_to_2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vextrins.h $vr0, $vr0, 65
; CHECK-NEXT: vst $vr0, $a1, 0
; CHECK-NEXT: ret
@@ -35,17 +33,15 @@ define void @shuffle_any_ext_2i16_to_2i64(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_any_ext_2i32_to_2i64(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: shuffle_any_ext_2i32_to_2i64:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 2
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: shuffle_any_ext_2i32_to_2i64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vshuf4i.w $vr0, $vr0, 16
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
@@ -59,8 +55,7 @@ define void @shuffle_any_ext_2i32_to_2i64(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_any_ext_4i8_to_4i32(ptr %ptr, ptr %dst) nounwind {
; CHECK-LABEL: shuffle_any_ext_4i8_to_4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vilvl.b $vr0, $vr0, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr0, $vr0
; CHECK-NEXT: vst $vr0, $a1, 0
@@ -75,18 +70,16 @@ define void @shuffle_any_ext_4i8_to_4i32(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_any_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: shuffle_any_ext_4i16_to_4i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vilvl.h $vr0, $vr0, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: shuffle_any_ext_4i16_to_4i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vilvl.h $vr0, $vr0, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
@@ -100,18 +93,16 @@ define void @shuffle_any_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_any_ext_8i8_to_8i16(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: shuffle_any_ext_8i8_to_8i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vilvl.b $vr0, $vr0, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
; LA32-NEXT: ret
;
; LA64-LABEL: shuffle_any_ext_8i8_to_8i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vilvl.b $vr0, $vr0, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
index 5e0ff9a07585fc..76da774053c25d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
@@ -5,8 +5,7 @@
define void @shuffle_sign_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind {
; CHECK-LABEL: shuffle_sign_ext_2i8_to_2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 0
; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
@@ -23,8 +22,7 @@ define void @shuffle_sign_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_sign_ext_2i16_to_2i64(ptr %ptr, ptr %dst) nounwind {
; CHECK-LABEL: shuffle_sign_ext_2i16_to_2i64:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 0
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
@@ -50,8 +48,7 @@ define void @shuffle_sign_ext_2i32_to_2i64(ptr %ptr, ptr %dst) nounwind {
;
; LA64-LABEL: shuffle_sign_ext_2i32_to_2i64:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 0
; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
@@ -66,8 +63,7 @@ define void @shuffle_sign_ext_2i32_to_2i64(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_sign_ext_4i8_to_4i32(ptr %ptr, ptr %dst) nounwind {
; CHECK-LABEL: shuffle_sign_ext_4i8_to_4i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 0
; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
@@ -83,10 +79,9 @@ define void @shuffle_sign_ext_4i8_to_4i32(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: shuffle_sign_ext_4i16_to_4i32:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.b $vr1, 0
; LA32-NEXT: vilvl.h $vr0, $vr1, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
@@ -94,8 +89,7 @@ define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {
;
; LA64-LABEL: shuffle_sign_ext_4i16_to_4i32:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 0
; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
@@ -110,10 +104,9 @@ define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {
define void @shuffle_sign_ext_8i8_to_8i16(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: shuffle_sign_ext_8i8_to_8i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.b $vr1, 0
; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
@@ -121,8 +114,7 @@ define void @shuffle_sign_ext_8i8_to_8i16(ptr %ptr, ptr %dst) nounwind {
;
; LA64-LABEL: shuffle_sign_ext_8i8_to_8i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 0
; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-trunc.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-trunc.ll
index 8d94b76b061c74..55076cddd53d0d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-trunc.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-trunc.ll
@@ -139,10 +139,9 @@ define void @load_trunc_8i16_to_8i8(ptr %ptr, ptr %dst) nounwind {
define void @load_trunc_2i32_to_2i16(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: load_trunc_2i32_to_2i16:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vshuf4i.h $vr0, $vr0, 8
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
@@ -150,8 +149,7 @@ define void @load_trunc_2i32_to_2i16(ptr %ptr, ptr %dst) nounwind {
;
; LA64-LABEL: load_trunc_2i32_to_2i16:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vshuf4i.h $vr0, $vr0, 8
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
@@ -164,18 +162,16 @@ define void @load_trunc_2i32_to_2i16(ptr %ptr, ptr %dst) nounwind {
define void @load_trunc_2i32_to_2i8(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: load_trunc_2i32_to_2i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vextrins.b $vr0, $vr0, 20
; LA32-NEXT: vstelm.h $vr0, $a1, 0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_trunc_2i32_to_2i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vextrins.b $vr0, $vr0, 20
; LA64-NEXT: vstelm.h $vr0, $a1, 0, 0
; LA64-NEXT: ret
@@ -188,10 +184,9 @@ define void @load_trunc_2i32_to_2i8(ptr %ptr, ptr %dst) nounwind {
define void @load_trunc_4i16_to_4i8(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: load_trunc_4i16_to_4i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vpickev.b $vr0, $vr0, $vr0
; LA32-NEXT: vpickve2gr.w $a0, $vr0, 0
; LA32-NEXT: st.w $a0, $a1, 0
@@ -199,8 +194,7 @@ define void @load_trunc_4i16_to_4i8(ptr %ptr, ptr %dst) nounwind {
;
; LA64-LABEL: load_trunc_4i16_to_4i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vpickev.b $vr0, $vr0, $vr0
; LA64-NEXT: vstelm.w $vr0, $a1, 0, 0
; LA64-NEXT: ret
@@ -213,16 +207,14 @@ define void @load_trunc_4i16_to_4i8(ptr %ptr, ptr %dst) nounwind {
define void @load_trunc_2i16_to_2i8(ptr %ptr, ptr %dst) nounwind {
; LA32-LABEL: load_trunc_2i16_to_2i8:
; LA32: # %bb.0:
-; LA32-NEXT: ld.w $a0, $a0, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; LA32-NEXT: fld.s $fa0, $a0, 0
; LA32-NEXT: vshuf4i.b $vr0, $vr0, 8
; LA32-NEXT: vstelm.h $vr0, $a1, 0, 0
; LA32-NEXT: ret
;
; LA64-LABEL: load_trunc_2i16_to_2i8:
; LA64: # %bb.0:
-; LA64-NEXT: ld.w $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; LA64-NEXT: fld.s $fa0, $a0, 0
; LA64-NEXT: vshuf4i.b $vr0, $vr0, 8
; LA64-NEXT: vstelm.h $vr0, $a1, 0, 0
; LA64-NEXT: ret
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
index 602c0f1a5a9107..0bb0d65e9ef559 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
@@ -6,8 +6,7 @@
define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_zext_2i8_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.h $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a0, 0
+; CHECK-NEXT: vldrepl.h $vr0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 0
; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
@@ -24,8 +23,7 @@ entry:
define void @load_zext_4i8_to_4i32(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_zext_4i8_to_4i32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 0
; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
@@ -41,10 +39,9 @@ entry:
define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_zext_8i8_to_8i16:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.b $vr1, 0
; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
@@ -52,8 +49,7 @@ define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: load_zext_8i8_to_8i16:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 0
; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
@@ -68,8 +64,7 @@ entry:
define void @load_zext_2i16_to_2i64(ptr %ptr, ptr %dst) {
; CHECK-LABEL: load_zext_2i16_to_2i64:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.w $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; CHECK-NEXT: fld.s $fa0, $a0, 0
; CHECK-NEXT: vrepli.b $vr1, 0
; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
@@ -85,10 +80,9 @@ entry:
define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {
; LA32-LABEL: load_zext_4i16_to_4i32:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a2, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: ld.w $a2, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
; LA32-NEXT: vrepli.b $vr1, 0
; LA32-NEXT: vilvl.h $vr0, $vr1, $vr0
; LA32-NEXT: vst $vr0, $a1, 0
@@ -96,8 +90,7 @@ define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: load_zext_4i16_to_4i32:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 0
; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
@@ -122,8 +115,7 @@ define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) {
;
; LA64-LABEL: load_zext_2i32_to_2i64:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
; LA64-NEXT: vrepli.b $vr1, 0
; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0
; LA64-NEXT: vst $vr0, $a1, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll b/llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
index 8a75f7c234e8b7..0a36a685f1dfea 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vhaddw.ll
@@ -5,14 +5,12 @@
define void @vhaddw_h_b_illegal(ptr %a, ptr %b, ptr %r) nounwind {
; LA32-LABEL: vhaddw_h_b_illegal:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a3, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: ld.w $a4, $a1, 0
-; LA32-NEXT: ld.w $a1, $a1, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
-; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 0
-; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1
+; LA32-NEXT: ld.w $a3, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: ld.w $a0, $a1, 4
+; LA32-NEXT: fld.s $fa1, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 1
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
; LA32-NEXT: vpickod.b $vr0, $vr0, $vr0
; LA32-NEXT: vpickev.b $vr1, $vr1, $vr1
; LA32-NEXT: vslti.b $vr2, $vr0, 0
@@ -28,10 +26,8 @@ define void @vhaddw_h_b_illegal(ptr %a, ptr %b, ptr %r) nounwind {
;
; LA64-LABEL: vhaddw_h_b_illegal:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: ld.d $a1, $a1, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
+; LA64-NEXT: fld.d $fa1, $a1, 0
; LA64-NEXT: vpickod.b $vr0, $vr0, $vr0
; LA64-NEXT: vpickev.b $vr1, $vr1, $vr1
; LA64-NEXT: vslti.b $vr2, $vr0, 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll b/llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
index 6960c043163c71..1a372f2932bb56 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vhsubw.ll
@@ -5,14 +5,12 @@
define void @vhsubw_h_b_illegal(ptr %a, ptr %b, ptr %r) nounwind {
; LA32-LABEL: vhsubw_h_b_illegal:
; LA32: # %bb.0: # %entry
-; LA32-NEXT: ld.w $a3, $a0, 0
-; LA32-NEXT: ld.w $a0, $a0, 4
-; LA32-NEXT: ld.w $a4, $a1, 0
-; LA32-NEXT: ld.w $a1, $a1, 4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
-; LA32-NEXT: vinsgr2vr.w $vr1, $a4, 0
-; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1
+; LA32-NEXT: ld.w $a3, $a0, 4
+; LA32-NEXT: fld.s $fa0, $a0, 0
+; LA32-NEXT: ld.w $a0, $a1, 4
+; LA32-NEXT: fld.s $fa1, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 1
+; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 1
; LA32-NEXT: vpickod.b $vr0, $vr0, $vr0
; LA32-NEXT: vpickev.b $vr1, $vr1, $vr1
; LA32-NEXT: vslti.b $vr2, $vr0, 0
@@ -28,10 +26,8 @@ define void @vhsubw_h_b_illegal(ptr %a, ptr %b, ptr %r) nounwind {
;
; LA64-LABEL: vhsubw_h_b_illegal:
; LA64: # %bb.0: # %entry
-; LA64-NEXT: ld.d $a0, $a0, 0
-; LA64-NEXT: ld.d $a1, $a1, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; LA64-NEXT: vinsgr2vr.d $vr1, $a1, 0
+; LA64-NEXT: fld.d $fa0, $a0, 0
+; LA64-NEXT: fld.d $fa1, $a1, 0
; LA64-NEXT: vpickod.b $vr0, $vr0, $vr0
; LA64-NEXT: vpickev.b $vr1, $vr1, $vr1
; LA64-NEXT: vslti.b $vr2, $vr0, 0
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