[llvm-branch-commits] [llvm] AMDGPU: Stop adding kill flags on virtual registers (PR #234197)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Oct 21 05:50:00 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
Fix misc. AMDGPU passes and hooks running before register allocation
introducing kill flags. There's no point in doing this anymore.
Co-authored-by: Claude Opus 5.5 <noreply@<!-- -->anthropic.com>
---
Patch is 46.90 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/234197.diff
11 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp (+2-3)
- (modified) llvm/lib/Target/AMDGPU/SIInstrInfo.cpp (+2-3)
- (modified) llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp (+1-2)
- (modified) llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp (+4-4)
- (modified) llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp (+1-1)
- (modified) llvm/test/CodeGen/AMDGPU/collapse-endcf.mir (+29-29)
- (modified) llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx10.mir (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx8.mir (+15-15)
- (modified) llvm/test/CodeGen/AMDGPU/local-stack-alloc-add-references.gfx9.mir (+8-8)
- (modified) llvm/test/CodeGen/AMDGPU/lower-control-flow-other-terminators.mir (+4-4)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
index 68de9f4255fda..dfaf3ccf4c548 100644
--- a/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFormMemoryClauses.cpp
@@ -348,8 +348,7 @@ bool SIFormMemoryClausesImpl::run(MachineFunction &MF) {
if (!LI.hasSubRanges()) {
if (!LI.liveAt(ClauseLiveOutIdx)) {
- KillOps.emplace_back(R.second.first | RegState::Kill,
- AMDGPU::NoSubRegister);
+ KillOps.emplace_back(R.second.first, AMDGPU::NoSubRegister);
}
} else {
LaneBitmask KilledMask;
@@ -367,7 +366,7 @@ bool SIFormMemoryClausesImpl::run(MachineFunction &MF) {
(void)Success;
assert(Success && "Failed to find subregister mask to cover lanes");
for (unsigned SubReg : KilledIndexes) {
- KillOps.emplace_back(R.second.first | RegState::Kill, SubReg);
+ KillOps.emplace_back(R.second.first, SubReg);
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
index d936636d36905..d6b14043f781a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -4077,7 +4077,6 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
get(AMDGPU::COPY), Tmp)
.addReg(Reg);
MI.getOperand(OpNo).setReg(Tmp);
- MI.getOperand(OpNo).setIsKill();
};
// Multiplied part is the constant: Use v_madmk_{f16, f32}.
@@ -4142,7 +4141,7 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
BuildMI(*UseMI.getParent(), std::next(UseMI.getIterator()),
UseMI.getDebugLoc(), get(AMDGPU::COPY),
UseMI.getOperand(0).getReg())
- .addReg(Tmp, RegState::Kill);
+ .addReg(Tmp);
UseMI.getOperand(0).setReg(Tmp);
CopyRegOperandToNarrowerRC(UseMI, 1, NewRC);
CopyRegOperandToNarrowerRC(UseMI, 3, NewRC);
@@ -4222,7 +4221,7 @@ bool SIInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
BuildMI(*UseMI.getParent(), std::next(UseMI.getIterator()),
UseMI.getDebugLoc(), get(AMDGPU::COPY),
UseMI.getOperand(0).getReg())
- .addReg(Tmp, RegState::Kill);
+ .addReg(Tmp);
UseMI.getOperand(0).setReg(Tmp);
CopyRegOperandToNarrowerRC(UseMI, 1, NewRC);
CopyRegOperandToNarrowerRC(UseMI, 2, NewRC);
diff --git a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
index c54ac39b3444c..f2408f78bc62a 100644
--- a/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
+++ b/llvm/lib/Target/AMDGPU/SILowerControlFlow.cpp
@@ -260,8 +260,7 @@ void SILowerControlFlow::emitIf(MachineInstr &MI) {
// Use a copy that is a terminator to get correct spill code placement it with
// fast regalloc.
MachineInstr *SetExec =
- BuildMI(MBB, I, DL, TII->get(LMC.MovTermOpc), LMC.ExecReg)
- .addReg(Tmp, RegState::Kill);
+ BuildMI(MBB, I, DL, TII->get(LMC.MovTermOpc), LMC.ExecReg).addReg(Tmp);
// Skip ahead to the unconditional branch in case there are other terminators
// present.
diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
index 0989263433f41..640b267e24698 100644
--- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
@@ -972,16 +972,16 @@ Register SIRegisterInfo::materializeFrameBaseRegister(MachineBasicBlock *MBB,
if (ST.hasFlatScratchEnabled()) {
// FIXME: Make sure scc isn't live in.
BuildMI(*MBB, Ins, DL, TII->get(AMDGPU::S_ADD_I32), BaseReg)
- .addReg(OffsetReg, RegState::Kill)
+ .addReg(OffsetReg)
.addReg(FIReg)
.setOperandDead(3); // scc
return BaseReg;
}
TII->getAddNoCarry(*MBB, Ins, DL, BaseReg)
- .addReg(OffsetReg, RegState::Kill)
- .addReg(FIReg)
- .addImm(0); // clamp bit
+ .addReg(OffsetReg)
+ .addReg(FIReg)
+ .addImm(0); // clamp bit
return BaseReg;
}
diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 5c41a2a563e0f..dbf3ad139940f 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -1693,7 +1693,7 @@ void SIWholeQuadMode::lowerInitExec(MachineInstr &MI) {
.addReg(CountReg)
.addImm(0);
auto CmpMI = BuildMI(*MBB, FirstMI, DL, TII->get(AMDGPU::S_CMP_EQ_U32))
- .addReg(CountReg, RegState::Kill)
+ .addReg(CountReg)
.addImm(WavefrontSize);
auto CmovMI =
BuildMI(*MBB, FirstMI, DL, TII->get(LMC.CMovOpc), LMC.ExecReg).addImm(-1);
diff --git a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
index 5c62c7886020b..f12f8499cd457 100644
--- a/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
+++ b/llvm/test/CodeGen/AMDGPU/collapse-endcf.mir
@@ -15,7 +15,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -23,7 +23,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -69,7 +69,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -77,7 +77,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -123,7 +123,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -131,7 +131,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -182,7 +182,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -190,7 +190,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -245,7 +245,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -253,7 +253,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -308,7 +308,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -316,7 +316,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -366,7 +366,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -375,7 +375,7 @@ body: |
; GCN-NEXT: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %4:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -425,7 +425,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -433,7 +433,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -527,7 +527,7 @@ body: |
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_]], [[COPY]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -548,7 +548,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %4:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_2]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_2]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.4:
@@ -611,7 +611,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -638,7 +638,7 @@ body: |
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_1]], [[COPY1]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: S_BRANCH %bb.0
; GCN-NEXT: S_ENDPGM 0
@@ -681,7 +681,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -689,7 +689,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -743,7 +743,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], undef %1:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.4, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.1:
@@ -751,7 +751,7 @@ body: |
; GCN-NEXT: {{ $}}
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], undef %3:sreg_64, implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.5, implicit $exec
; GCN-NEXT: {{ $}}
; GCN-NEXT: bb.2:
@@ -818,7 +818,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF]], implicit $exec
; GCN-NEXT: [[COPY:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.14, implicit $exec
; GCN-NEXT: S_BRANCH %bb.1
; GCN-NEXT: {{ $}}
@@ -829,7 +829,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF1]], implicit $exec
; GCN-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY1]], killed [[V_CMP_EQ_U32_e64_1]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_1]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_1]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.14, implicit $exec
; GCN-NEXT: S_BRANCH %bb.2
; GCN-NEXT: {{ $}}
@@ -840,7 +840,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_2:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF2]], implicit $exec
; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_2:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY2]], killed [[V_CMP_EQ_U32_e64_2]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_2]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_2]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.7, implicit $exec
; GCN-NEXT: S_BRANCH %bb.3
; GCN-NEXT: {{ $}}
@@ -851,7 +851,7 @@ body: |
; GCN-NEXT: [[V_CMP_EQ_U32_e64_3:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 0, killed [[DEF3]], implicit $exec
; GCN-NEXT: [[COPY3:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_3:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY3]], killed [[V_CMP_EQ_U32_e64_3]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_3]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_3]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.7, implicit $exec
; GCN-NEXT: S_BRANCH %bb.4
; GCN-NEXT: {{ $}}
@@ -879,7 +879,7 @@ body: |
; GCN-NEXT: [[COPY4:%[0-9]+]]:sreg_64 = COPY $exec, implicit-def $exec
; GCN-NEXT: [[S_AND_B64_4:%[0-9]+]]:sreg_64 = S_AND_B64 [[COPY4]], killed [[V_CMP_EQ_U32_e64_4]], implicit-def dead $scc
; GCN-NEXT: [[S_XOR_B64_:%[0-9]+]]:sreg_64 = S_XOR_B64 [[S_AND_B64_4]], [[COPY4]], implicit-def dead $scc
- ; GCN-NEXT: $exec = S_MOV_B64_term killed [[S_AND_B64_4]]
+ ; GCN-NEXT: $exec = S_MOV_B64_term [[S_AND_B64_4]]
; GCN-NEXT: S_CBRANCH_EXECZ %bb.12, implicit $exec
; GCN-NEXT: S_BRANCH %bb.11
; GCN-NEXT: {{ $}}
diff --git a/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir b/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir
index e31bbc39b733e..2cefc8201ce9f 100644
--- a/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir
+++ b/llvm/test/CodeGen/AMDGPU/fold-fmac-to-fmaak.mir
@@ -101,8 +101,8 @@ body: |
; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_16 = COPY $vgpr0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_16_lo128 = COPY [[COPY]]
; CHECK-NEXT: [[V_MOV_B16_t16_e64_:%[0-9]+]]:vgpr_16_lo128 = V_MOV_B16_t16_e64 0, 10526, 0, implicit $exec
- ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 [[V_MOV_B16_t16_e64_]], killed [[COPY1]], 8478, implicit $mode, implicit $exec
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY killed [[V_FMAAK_F16_t16_]]
+ ; CHECK-NEXT: [[V_FMAAK_F16_t16_:%[0-9]+]]:vgpr_16_lo128 = contract nofpexcept V_FMAAK_F16_t16 [[V_MOV_B16_t16_e64_]], [[COPY1]], 8478, implicit $mode, implicit $exec
+ ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_16 = COPY [[V_FMAAK_F16_t16_]]
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/234197
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