[llvm-branch-commits] [llvm] [LoongArch] Lower FP_TO_SINT_SAT to [X]VFTINTRZ/FTINTRZ (PR #233760)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Oct 20 02:29:04 PDT 2026
https://github.com/heiher created https://github.com/llvm/llvm-project/pull/233760
The ftintrz.{w,l}.{s,d} and [x]vftintrz.{w.s,l.d} instructions saturate out-of-range inputs to the minimum/maximum integer and convert NaN to 0 (when the invalid operation exception is not trapped), which matches the semantics of llvm.fptosi.sat when the saturation width is the native 32/64 bits. This was verified on LA664 for all scalar, LSX and LASX variants and matches QEMU's LoongArch model. Use them instead of the generic expansion, which emits three compares and selects per element and fully scalarizes vectors.
Also override shouldConvertFpToSat so DAGCombiner only folds min/max clamps and NaN-guarded selects into FP_TO_SINT_SAT when that lowers to a single ftintrz, avoiding the generic expansion for mismatched vector element widths and for i64 results without the D extension.
This is what Rust emits for `f32 as i32`. rustc-perf svg-render-1 on LA664: instructions -6.4%, cycles -4.0%.
>From 439208a58dba00b8fa4ad512517273f442e33824 Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Tue, 20 Oct 2026 15:42:12 +0800
Subject: [PATCH] [LoongArch] Lower FP_TO_SINT_SAT to [X]VFTINTRZ/FTINTRZ
The ftintrz.{w,l}.{s,d} and [x]vftintrz.{w.s,l.d} instructions saturate
out-of-range inputs to the minimum/maximum integer and convert NaN to 0
(when the invalid operation exception is not trapped), which matches the
semantics of llvm.fptosi.sat when the saturation width is the native
32/64 bits. This was verified on LA664 for all scalar, LSX and LASX variants
and matches QEMU's LoongArch model. Use them instead of the generic
expansion, which emits three compares and selects per element and fully
scalarizes vectors.
Also override shouldConvertFpToSat so DAGCombiner only folds min/max
clamps and NaN-guarded selects into FP_TO_SINT_SAT when that lowers to
a single ftintrz, avoiding the generic expansion for mismatched vector
element widths and for i64 results without the D extension.
This is what Rust emits for `f32 as i32`. rustc-perf svg-render-1 on
LA664: instructions -6.4%, cycles -4.0%.
---
.../LoongArch/LoongArchISelLowering.cpp | 58 ++
.../Target/LoongArch/LoongArchISelLowering.h | 3 +
.../LoongArch/LoongArchLASXInstrInfo.td | 2 +
.../Target/LoongArch/LoongArchLSXInstrInfo.td | 2 +
llvm/test/CodeGen/LoongArch/fptosi-sat.ll | 183 +----
.../test/CodeGen/LoongArch/lasx/fptosi-sat.ll | 658 ++----------------
llvm/test/CodeGen/LoongArch/lsx/fptosi-sat.ll | 380 +---------
7 files changed, 158 insertions(+), 1128 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 1d01e76a5ebd2d..700b1a07b718c6 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -111,6 +111,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::SRA_PARTS, GRLenVT, Custom);
setOperationAction(ISD::SRL_PARTS, GRLenVT, Custom);
setOperationAction(ISD::FP_TO_SINT, GRLenVT, Custom);
+ if (Subtarget.hasBasicF())
+ setOperationAction(ISD::FP_TO_SINT_SAT, GRLenVT, Custom);
setOperationAction(ISD::ROTL, GRLenVT, Expand);
setOperationAction(ISD::CTPOP, GRLenVT, Expand);
@@ -364,6 +366,7 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
for (MVT VT : {MVT::v4i32, MVT::v2i64}) {
setOperationAction({ISD::SINT_TO_FP, ISD::UINT_TO_FP}, VT, Legal);
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal);
+ setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
}
setOperationAction(ISD::UINT_TO_FP, GRLenVT, Custom);
for (MVT VT : {MVT::v4f32, MVT::v2f64}) {
@@ -464,6 +467,8 @@ LoongArchTargetLowering::LoongArchTargetLowering(const TargetMachine &TM,
setOperationAction(ISD::BITREVERSE, VT, Custom);
for (MVT VT : {MVT::v16i16, MVT::v8i32, MVT::v4i64})
setOperationAction(ISD::BSWAP, VT, Legal);
+ for (MVT VT : {MVT::v8i32, MVT::v4i64})
+ setOperationAction(ISD::FP_TO_SINT_SAT, VT, Custom);
for (MVT VT : {MVT::v8i32, MVT::v4i32, MVT::v4i64}) {
setOperationAction({ISD::FP_TO_SINT, ISD::FP_TO_UINT}, VT, Legal);
setOperationAction(ISD::SINT_TO_FP, VT, Legal);
@@ -619,6 +624,8 @@ SDValue LoongArchTargetLowering::LowerOperation(SDValue Op,
return lowerFP_TO_SINT(Op, DAG);
case ISD::FP_TO_UINT:
return lowerFP_TO_UINT(Op, DAG);
+ case ISD::FP_TO_SINT_SAT:
+ return lowerFP_TO_SINT_SAT(Op, DAG);
case ISD::BITCAST:
return lowerBITCAST(Op, DAG);
case ISD::UINT_TO_FP:
@@ -4381,6 +4388,43 @@ SDValue LoongArchTargetLowering::lowerFP_TO_SINT(SDValue Op,
return DAG.getNode(ISD::BITCAST, DL, Op.getValueType(), Trunc);
}
+// [X]VFTINTRZ and FTINTRZ saturate out-of-range values and convert NaN to 0,
+// which is exactly the semantics of FP_TO_SINT_SAT with a native saturation
+// width.
+SDValue LoongArchTargetLowering::lowerFP_TO_SINT_SAT(SDValue Op,
+ SelectionDAG &DAG) const {
+ SDLoc DL(Op);
+ SDValue Src = Op.getOperand(0);
+ EVT VT = Op.getValueType();
+ EVT SrcVT = Src.getValueType();
+ unsigned SatWidth = cast<VTSDNode>(Op.getOperand(1))->getVT().getSizeInBits();
+
+ // Vectors are selected by patterns.
+ if (VT.isVector()) {
+ if (SatWidth == VT.getScalarSizeInBits() &&
+ SatWidth == SrcVT.getScalarSizeInBits())
+ return Op;
+ return SDValue();
+ }
+
+ if (SrcVT != MVT::f32 && SrcVT != MVT::f64)
+ return SDValue();
+
+ if (SatWidth == 32) {
+ SDValue Ftint = DAG.getNode(LoongArchISD::FTINT, DL, MVT::f32, Src);
+ if (Subtarget.is64Bit())
+ return DAG.getNode(LoongArchISD::MOVFR2GR_S_LA64, DL, VT, Ftint);
+ return DAG.getBitcast(VT, Ftint);
+ }
+
+ if (SatWidth == 64 && Subtarget.is64Bit() && Subtarget.hasBasicD()) {
+ SDValue Ftint = DAG.getNode(LoongArchISD::FTINT, DL, MVT::f64, Src);
+ return DAG.getBitcast(VT, Ftint);
+ }
+
+ return SDValue();
+}
+
SDValue LoongArchTargetLowering::lowerFP_TO_UINT(SDValue Op,
SelectionDAG &DAG) const {
if (!Subtarget.hasExtLSX())
@@ -11018,6 +11062,20 @@ bool LoongArchTargetLowering::isFPImmVLDILegal(const APFloat &Imm,
return false;
}
+// Only form FP_TO_SINT_SAT from clamp/NaN-guard idioms when it will be lowered
+// to a single [X]VFTINTRZ/FTINTRZ, otherwise the generic expansion is worse
+// than the original sequence.
+bool LoongArchTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
+ EVT VT) const {
+ if (!isOperationLegalOrCustom(Op, VT))
+ return false;
+ if (VT.isVector())
+ return FPVT.getScalarSizeInBits() == VT.getScalarSizeInBits();
+ if (FPVT == MVT::f32)
+ return VT.getSizeInBits() == 32 || Subtarget.hasBasicD();
+ return FPVT == MVT::f64 && Subtarget.hasBasicD();
+}
+
bool LoongArchTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const {
// TODO: Maybe need more checks here after vector extension is supported.
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
index 7c3ae7d6aac14a..ee66fb191c2429 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.h
@@ -229,6 +229,7 @@ class LoongArchTargetLowering : public TargetLowering {
SDValue lowerEH_DWARF_CFA(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerFP_TO_UINT(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerFP_TO_SINT_SAT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
@@ -269,6 +270,8 @@ class LoongArchTargetLowering : public TargetLowering {
bool isFPImmLegal(const APFloat &Imm, EVT VT,
bool ForCodeSize) const override;
+ bool shouldConvertFpToSat(unsigned Op, EVT FPVT, EVT VT) const override;
+
bool shouldInsertFencesForAtomic(const Instruction *I) const override;
ConstraintType getConstraintType(StringRef Constraint) const override;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
index fcd134770332de..690fe4afff212a 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLASXInstrInfo.td
@@ -2193,6 +2193,8 @@ def : Pat<(v8f32 (loongarch_vffint_s_l (v4i64 LASX256:$xj), (v4i64 LASX256:$xk))
// XVFTINTRZ_{W_S/L_D}
def : Pat<(v8i32 (fp_to_sint v8f32:$vj)), (XVFTINTRZ_W_S v8f32:$vj)>;
def : Pat<(v4i64 (fp_to_sint v4f64:$vj)), (XVFTINTRZ_L_D v4f64:$vj)>;
+def : Pat<(v8i32 (fp_to_sint_sat v8f32:$vj, i32)), (XVFTINTRZ_W_S v8f32:$vj)>;
+def : Pat<(v4i64 (fp_to_sint_sat v4f64:$vj, i64)), (XVFTINTRZ_L_D v4f64:$vj)>;
def : Pat<(v4i64 (fp_to_sint v4f32:$vj)),
(XVFTINTRZL_L_S
(XVPERMI_D (SUBREG_TO_REG v4f32:$vj, sub_128), 216))>;
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index e1489f9e36d69b..d6eb050de12776 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -2412,6 +2412,8 @@ def : Pat<(v4f32 (loongarch_vffint_s_l (v2i64 LSX128:$vj), (v2i64 LSX128:$vk))),
// VFTINTRZ_{W_S/L_D}
def : Pat<(v4i32 (fp_to_sint v4f32:$vj)), (VFTINTRZ_W_S v4f32:$vj)>;
def : Pat<(v2i64 (fp_to_sint v2f64:$vj)), (VFTINTRZ_L_D v2f64:$vj)>;
+def : Pat<(v4i32 (fp_to_sint_sat v4f32:$vj, i32)), (VFTINTRZ_W_S v4f32:$vj)>;
+def : Pat<(v2i64 (fp_to_sint_sat v2f64:$vj, i64)), (VFTINTRZ_L_D v2f64:$vj)>;
// VFTINTRZ_{W_SU/L_DU}
def : Pat<(v4i32 (fp_to_uint v4f32:$vj)), (VFTINTRZ_WU_S v4f32:$vj)>;
diff --git a/llvm/test/CodeGen/LoongArch/fptosi-sat.ll b/llvm/test/CodeGen/LoongArch/fptosi-sat.ll
index 96c563a48ef000..73889aed522c2f 100644
--- a/llvm/test/CodeGen/LoongArch/fptosi-sat.ll
+++ b/llvm/test/CodeGen/LoongArch/fptosi-sat.ll
@@ -141,110 +141,26 @@ entry:
define i32 @fptosi_sat_f32_to_i32(float %a) nounwind {
; LA32F-LABEL: fptosi_sat_f32_to_i32:
; LA32F: # %bb.0: # %entry
-; LA32F-NEXT: lu12i.w $a0, -200704
-; LA32F-NEXT: movgr2fr.w $fa1, $a0
-; LA32F-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA32F-NEXT: ftintrz.w.s $fa1, $fa0
-; LA32F-NEXT: movfr2gr.s $a0, $fa1
-; LA32F-NEXT: movcf2gr $a1, $fcc0
-; LA32F-NEXT: masknez $a0, $a0, $a1
-; LA32F-NEXT: lu12i.w $a2, -524288
-; LA32F-NEXT: maskeqz $a1, $a2, $a1
-; LA32F-NEXT: lu12i.w $a2, 323583
-; LA32F-NEXT: ori $a2, $a2, 4095
-; LA32F-NEXT: movgr2fr.w $fa1, $a2
-; LA32F-NEXT: fcmp.clt.s $fcc0, $fa1, $fa0
-; LA32F-NEXT: or $a0, $a1, $a0
-; LA32F-NEXT: movcf2gr $a1, $fcc0
-; LA32F-NEXT: masknez $a0, $a0, $a1
-; LA32F-NEXT: lu12i.w $a2, 524287
-; LA32F-NEXT: ori $a2, $a2, 4095
-; LA32F-NEXT: maskeqz $a1, $a2, $a1
-; LA32F-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA32F-NEXT: or $a0, $a1, $a0
-; LA32F-NEXT: movcf2gr $a1, $fcc0
-; LA32F-NEXT: masknez $a0, $a0, $a1
+; LA32F-NEXT: ftintrz.w.s $fa0, $fa0
+; LA32F-NEXT: movfr2gr.s $a0, $fa0
; LA32F-NEXT: ret
;
; LA32D-LABEL: fptosi_sat_f32_to_i32:
; LA32D: # %bb.0: # %entry
-; LA32D-NEXT: lu12i.w $a0, -200704
-; LA32D-NEXT: movgr2fr.w $fa1, $a0
-; LA32D-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA32D-NEXT: ftintrz.w.s $fa1, $fa0
-; LA32D-NEXT: movfr2gr.s $a0, $fa1
-; LA32D-NEXT: movcf2gr $a1, $fcc0
-; LA32D-NEXT: masknez $a0, $a0, $a1
-; LA32D-NEXT: lu12i.w $a2, -524288
-; LA32D-NEXT: maskeqz $a1, $a2, $a1
-; LA32D-NEXT: lu12i.w $a2, 323583
-; LA32D-NEXT: ori $a2, $a2, 4095
-; LA32D-NEXT: movgr2fr.w $fa1, $a2
-; LA32D-NEXT: fcmp.clt.s $fcc0, $fa1, $fa0
-; LA32D-NEXT: or $a0, $a1, $a0
-; LA32D-NEXT: movcf2gr $a1, $fcc0
-; LA32D-NEXT: masknez $a0, $a0, $a1
-; LA32D-NEXT: lu12i.w $a2, 524287
-; LA32D-NEXT: ori $a2, $a2, 4095
-; LA32D-NEXT: maskeqz $a1, $a2, $a1
-; LA32D-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA32D-NEXT: or $a0, $a1, $a0
-; LA32D-NEXT: movcf2gr $a1, $fcc0
-; LA32D-NEXT: masknez $a0, $a0, $a1
+; LA32D-NEXT: ftintrz.w.s $fa0, $fa0
+; LA32D-NEXT: movfr2gr.s $a0, $fa0
; LA32D-NEXT: ret
;
; LA64F-LABEL: fptosi_sat_f32_to_i32:
; LA64F: # %bb.0: # %entry
-; LA64F-NEXT: lu12i.w $a0, -200704
-; LA64F-NEXT: movgr2fr.w $fa1, $a0
-; LA64F-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA64F-NEXT: ftintrz.w.s $fa1, $fa0
-; LA64F-NEXT: movfr2gr.s $a0, $fa1
-; LA64F-NEXT: movcf2gr $a1, $fcc0
-; LA64F-NEXT: masknez $a0, $a0, $a1
-; LA64F-NEXT: lu12i.w $a2, -524288
-; LA64F-NEXT: maskeqz $a1, $a2, $a1
-; LA64F-NEXT: lu12i.w $a2, 323583
-; LA64F-NEXT: ori $a2, $a2, 4095
-; LA64F-NEXT: movgr2fr.w $fa1, $a2
-; LA64F-NEXT: fcmp.clt.s $fcc0, $fa1, $fa0
-; LA64F-NEXT: or $a0, $a1, $a0
-; LA64F-NEXT: movcf2gr $a1, $fcc0
-; LA64F-NEXT: masknez $a0, $a0, $a1
-; LA64F-NEXT: lu12i.w $a2, 524287
-; LA64F-NEXT: ori $a2, $a2, 4095
-; LA64F-NEXT: maskeqz $a1, $a2, $a1
-; LA64F-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA64F-NEXT: or $a0, $a1, $a0
-; LA64F-NEXT: movcf2gr $a1, $fcc0
-; LA64F-NEXT: masknez $a0, $a0, $a1
+; LA64F-NEXT: ftintrz.w.s $fa0, $fa0
+; LA64F-NEXT: movfr2gr.s $a0, $fa0
; LA64F-NEXT: ret
;
; LA64D-LABEL: fptosi_sat_f32_to_i32:
; LA64D: # %bb.0: # %entry
-; LA64D-NEXT: lu12i.w $a0, -200704
-; LA64D-NEXT: movgr2fr.w $fa1, $a0
-; LA64D-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA64D-NEXT: ftintrz.l.s $fa1, $fa0
-; LA64D-NEXT: movfr2gr.d $a0, $fa1
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
-; LA64D-NEXT: lu12i.w $a2, -524288
-; LA64D-NEXT: maskeqz $a1, $a2, $a1
-; LA64D-NEXT: lu12i.w $a2, 323583
-; LA64D-NEXT: ori $a2, $a2, 4095
-; LA64D-NEXT: movgr2fr.w $fa1, $a2
-; LA64D-NEXT: fcmp.clt.s $fcc0, $fa1, $fa0
-; LA64D-NEXT: or $a0, $a1, $a0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
-; LA64D-NEXT: lu12i.w $a2, 524287
-; LA64D-NEXT: ori $a2, $a2, 4095
-; LA64D-NEXT: maskeqz $a1, $a2, $a1
-; LA64D-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA64D-NEXT: or $a0, $a1, $a0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
+; LA64D-NEXT: ftintrz.w.s $fa0, $fa0
+; LA64D-NEXT: movfr2gr.s $a0, $fa0
; LA64D-NEXT: ret
entry:
%r = call i32 @llvm.fptosi.sat.i32.f32(float %a)
@@ -377,29 +293,8 @@ define i64 @fptosi_sat_f32_to_i64(float %a) nounwind {
;
; LA64D-LABEL: fptosi_sat_f32_to_i64:
; LA64D: # %bb.0: # %entry
-; LA64D-NEXT: lu12i.w $a0, -135168
-; LA64D-NEXT: movgr2fr.w $fa1, $a0
-; LA64D-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA64D-NEXT: ftintrz.l.s $fa1, $fa0
-; LA64D-NEXT: movfr2gr.d $a0, $fa1
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
-; LA64D-NEXT: lu52i.d $a2, $zero, -2048
-; LA64D-NEXT: maskeqz $a1, $a2, $a1
-; LA64D-NEXT: lu12i.w $a2, 389119
-; LA64D-NEXT: ori $a2, $a2, 4095
-; LA64D-NEXT: movgr2fr.w $fa1, $a2
-; LA64D-NEXT: fcmp.clt.s $fcc0, $fa1, $fa0
-; LA64D-NEXT: or $a0, $a1, $a0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
-; LA64D-NEXT: addi.w $a2, $zero, -1
-; LA64D-NEXT: lu52i.d $a2, $a2, 2047
-; LA64D-NEXT: maskeqz $a1, $a2, $a1
-; LA64D-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA64D-NEXT: or $a0, $a1, $a0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
+; LA64D-NEXT: ftintrz.l.s $fa0, $fa0
+; LA64D-NEXT: movfr2gr.d $a0, $fa0
; LA64D-NEXT: ret
entry:
%r = call i64 @llvm.fptosi.sat.i64.f32(float %a)
@@ -700,18 +595,8 @@ define i32 @fptosi_sat_f64_to_i32(double %a) nounwind {
;
; LA32D-LABEL: fptosi_sat_f64_to_i32:
; LA32D: # %bb.0: # %entry
-; LA32D-NEXT: movgr2fr.w $fa1, $zero
-; LA32D-NEXT: pcalau12i $a0, %pc_hi20(.LCPI6_0)
-; LA32D-NEXT: fld.d $fa2, $a0, %pc_lo12(.LCPI6_0)
-; LA32D-NEXT: lu12i.w $a0, -254464
-; LA32D-NEXT: movgr2frh.w $fa1, $a0
-; LA32D-NEXT: fmax.d $fa1, $fa0, $fa1
-; LA32D-NEXT: fmin.d $fa1, $fa1, $fa2
-; LA32D-NEXT: ftintrz.w.d $fa1, $fa1
-; LA32D-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA32D-NEXT: movfr2gr.s $a0, $fa1
-; LA32D-NEXT: movcf2gr $a1, $fcc0
-; LA32D-NEXT: masknez $a0, $a0, $a1
+; LA32D-NEXT: ftintrz.w.d $fa0, $fa0
+; LA32D-NEXT: movfr2gr.s $a0, $fa0
; LA32D-NEXT: ret
;
; LA64F-LABEL: fptosi_sat_f64_to_i32:
@@ -757,18 +642,8 @@ define i32 @fptosi_sat_f64_to_i32(double %a) nounwind {
;
; LA64D-LABEL: fptosi_sat_f64_to_i32:
; LA64D: # %bb.0: # %entry
-; LA64D-NEXT: lu52i.d $a0, $zero, -994
-; LA64D-NEXT: movgr2fr.d $fa1, $a0
-; LA64D-NEXT: fmax.d $fa1, $fa0, $fa1
-; LA64D-NEXT: lu12i.w $a0, -1024
-; LA64D-NEXT: lu52i.d $a0, $a0, 1053
-; LA64D-NEXT: movgr2fr.d $fa2, $a0
-; LA64D-NEXT: fmin.d $fa1, $fa1, $fa2
-; LA64D-NEXT: ftintrz.l.d $fa1, $fa1
-; LA64D-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA64D-NEXT: movfr2gr.d $a0, $fa1
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
+; LA64D-NEXT: ftintrz.w.d $fa0, $fa0
+; LA64D-NEXT: movfr2gr.s $a0, $fa0
; LA64D-NEXT: ret
entry:
%r = call i32 @llvm.fptosi.sat.i32.f64(double %a)
@@ -928,28 +803,8 @@ define i64 @fptosi_sat_f64_to_i64(double %a) nounwind {
;
; LA64D-LABEL: fptosi_sat_f64_to_i64:
; LA64D: # %bb.0: # %entry
-; LA64D-NEXT: lu52i.d $a0, $zero, -962
-; LA64D-NEXT: movgr2fr.d $fa1, $a0
-; LA64D-NEXT: fcmp.cult.d $fcc0, $fa0, $fa1
-; LA64D-NEXT: ftintrz.l.d $fa1, $fa0
-; LA64D-NEXT: movfr2gr.d $a0, $fa1
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
-; LA64D-NEXT: lu52i.d $a2, $zero, -2048
-; LA64D-NEXT: maskeqz $a1, $a2, $a1
-; LA64D-NEXT: addi.w $a2, $zero, -1
-; LA64D-NEXT: lu52i.d $a3, $a2, 1085
-; LA64D-NEXT: movgr2fr.d $fa1, $a3
-; LA64D-NEXT: fcmp.clt.d $fcc0, $fa1, $fa0
-; LA64D-NEXT: or $a0, $a1, $a0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
-; LA64D-NEXT: lu52i.d $a2, $a2, 2047
-; LA64D-NEXT: maskeqz $a1, $a2, $a1
-; LA64D-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA64D-NEXT: or $a0, $a1, $a0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
+; LA64D-NEXT: ftintrz.l.d $fa0, $fa0
+; LA64D-NEXT: movfr2gr.d $a0, $fa0
; LA64D-NEXT: ret
entry:
%r = call i64 @llvm.fptosi.sat.i64.f64(double %a)
@@ -1002,11 +857,8 @@ define i64 @fptosi_nanguard_f32_to_i64(float %a) nounwind {
;
; LA64D-LABEL: fptosi_nanguard_f32_to_i64:
; LA64D: # %bb.0: # %entry
-; LA64D-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
; LA64D-NEXT: ftintrz.l.s $fa0, $fa0
; LA64D-NEXT: movfr2gr.d $a0, $fa0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
; LA64D-NEXT: ret
entry:
%c = fcmp uno float %a, 0.0
@@ -1081,11 +933,8 @@ define i64 @fptosi_nanguard_f64_to_i64(double %a) nounwind {
;
; LA64D-LABEL: fptosi_nanguard_f64_to_i64:
; LA64D: # %bb.0: # %entry
-; LA64D-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
; LA64D-NEXT: ftintrz.l.d $fa0, $fa0
; LA64D-NEXT: movfr2gr.d $a0, $fa0
-; LA64D-NEXT: movcf2gr $a1, $fcc0
-; LA64D-NEXT: masknez $a0, $a0, $a1
; LA64D-NEXT: ret
entry:
%c = fcmp uno double %a, 0.0
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fptosi-sat.ll b/llvm/test/CodeGen/LoongArch/lasx/fptosi-sat.ll
index 3ee311b5fd7546..d5266e4c07981d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/fptosi-sat.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/fptosi-sat.ll
@@ -1,309 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @fptosi_sat_v8f32_to_v8i32(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_sat_v8f32_to_v8i32:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: xvld $xr0, $a1, 0
-; LA32-NEXT: xvpickve.w $xr3, $xr0, 5
-; LA32-NEXT: lu12i.w $a1, -200704
-; LA32-NEXT: movgr2fr.w $fa1, $a1
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA32-NEXT: lu12i.w $a1, -524288
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: maskeqz $a3, $a1, $a2
-; LA32-NEXT: ftintrz.w.s $fa2, $fa3
-; LA32-NEXT: movfr2gr.s $a4, $fa2
-; LA32-NEXT: masknez $a2, $a4, $a2
-; LA32-NEXT: lu12i.w $a4, 323583
-; LA32-NEXT: ori $a4, $a4, 4095
-; LA32-NEXT: movgr2fr.w $fa2, $a4
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA32-NEXT: or $a2, $a3, $a2
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a4, $a2, $a3
-; LA32-NEXT: lu12i.w $a2, 524287
-; LA32-NEXT: ori $a2, $a2, 4095
-; LA32-NEXT: maskeqz $a3, $a2, $a3
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA32-NEXT: or $a3, $a3, $a4
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: xvpickve.w $xr3, $xr0, 4
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: maskeqz $a5, $a1, $a4
-; LA32-NEXT: ftintrz.w.s $fa4, $fa3
-; LA32-NEXT: movfr2gr.s $a6, $fa4
-; LA32-NEXT: masknez $a4, $a6, $a4
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA32-NEXT: or $a4, $a5, $a4
-; LA32-NEXT: movcf2gr $a5, $fcc0
-; LA32-NEXT: masknez $a4, $a4, $a5
-; LA32-NEXT: maskeqz $a5, $a2, $a5
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA32-NEXT: or $a4, $a5, $a4
-; LA32-NEXT: movcf2gr $a5, $fcc0
-; LA32-NEXT: masknez $a4, $a4, $a5
-; LA32-NEXT: vinsgr2vr.w $vr3, $a4, 0
-; LA32-NEXT: xvpickve.w $xr4, $xr0, 6
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA32-NEXT: vinsgr2vr.w $vr3, $a3, 1
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: maskeqz $a4, $a1, $a3
-; LA32-NEXT: ftintrz.w.s $fa5, $fa4
-; LA32-NEXT: movfr2gr.s $a5, $fa5
-; LA32-NEXT: masknez $a3, $a5, $a3
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: maskeqz $a4, $a2, $a4
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: xvpickve.w $xr4, $xr0, 7
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA32-NEXT: vinsgr2vr.w $vr3, $a3, 2
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: maskeqz $a4, $a1, $a3
-; LA32-NEXT: ftintrz.w.s $fa5, $fa4
-; LA32-NEXT: movfr2gr.s $a5, $fa5
-; LA32-NEXT: masknez $a3, $a5, $a3
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: maskeqz $a4, $a2, $a4
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: xvpickve.w $xr4, $xr0, 1
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA32-NEXT: vinsgr2vr.w $vr3, $a3, 3
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: maskeqz $a4, $a1, $a3
-; LA32-NEXT: ftintrz.w.s $fa5, $fa4
-; LA32-NEXT: movfr2gr.s $a5, $fa5
-; LA32-NEXT: masknez $a3, $a5, $a3
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: maskeqz $a4, $a2, $a4
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: xvpickve.w $xr4, $xr0, 0
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: maskeqz $a5, $a1, $a4
-; LA32-NEXT: ftintrz.w.s $fa5, $fa4
-; LA32-NEXT: movfr2gr.s $a6, $fa5
-; LA32-NEXT: masknez $a4, $a6, $a4
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA32-NEXT: or $a4, $a5, $a4
-; LA32-NEXT: movcf2gr $a5, $fcc0
-; LA32-NEXT: masknez $a4, $a4, $a5
-; LA32-NEXT: maskeqz $a5, $a2, $a5
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA32-NEXT: or $a4, $a5, $a4
-; LA32-NEXT: movcf2gr $a5, $fcc0
-; LA32-NEXT: masknez $a4, $a4, $a5
-; LA32-NEXT: vinsgr2vr.w $vr4, $a4, 0
-; LA32-NEXT: xvpickve.w $xr5, $xr0, 2
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa5, $fa1
-; LA32-NEXT: vinsgr2vr.w $vr4, $a3, 1
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: maskeqz $a4, $a1, $a3
-; LA32-NEXT: ftintrz.w.s $fa6, $fa5
-; LA32-NEXT: movfr2gr.s $a5, $fa6
-; LA32-NEXT: masknez $a3, $a5, $a3
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa5
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: maskeqz $a4, $a2, $a4
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa5, $fa5
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: xvpickve.w $xr0, $xr0, 3
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA32-NEXT: vinsgr2vr.w $vr4, $a3, 2
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: maskeqz $a1, $a1, $a3
-; LA32-NEXT: ftintrz.w.s $fa1, $fa0
-; LA32-NEXT: movfr2gr.s $a4, $fa1
-; LA32-NEXT: masknez $a3, $a4, $a3
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa0
-; LA32-NEXT: or $a1, $a1, $a3
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a3
-; LA32-NEXT: maskeqz $a2, $a2, $a3
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA32-NEXT: or $a1, $a2, $a1
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a2
-; LA32-NEXT: vinsgr2vr.w $vr4, $a1, 3
-; LA32-NEXT: xvpermi.q $xr4, $xr3, 2
-; LA32-NEXT: xvst $xr4, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_sat_v8f32_to_v8i32:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: xvld $xr0, $a1, 0
-; LA64-NEXT: xvpickve.w $xr3, $xr0, 5
-; LA64-NEXT: lu12i.w $a1, -200704
-; LA64-NEXT: movgr2fr.w $fa1, $a1
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA64-NEXT: lu12i.w $a1, -524288
-; LA64-NEXT: movcf2gr $a2, $fcc0
-; LA64-NEXT: maskeqz $a3, $a1, $a2
-; LA64-NEXT: ftintrz.l.s $fa2, $fa3
-; LA64-NEXT: movfr2gr.d $a4, $fa2
-; LA64-NEXT: masknez $a2, $a4, $a2
-; LA64-NEXT: lu12i.w $a4, 323583
-; LA64-NEXT: ori $a4, $a4, 4095
-; LA64-NEXT: movgr2fr.w $fa2, $a4
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA64-NEXT: or $a2, $a3, $a2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a4, $a2, $a3
-; LA64-NEXT: lu12i.w $a2, 524287
-; LA64-NEXT: ori $a2, $a2, 4095
-; LA64-NEXT: maskeqz $a3, $a2, $a3
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA64-NEXT: or $a3, $a3, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: xvpickve.w $xr3, $xr0, 4
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: maskeqz $a5, $a1, $a4
-; LA64-NEXT: ftintrz.l.s $fa4, $fa3
-; LA64-NEXT: movfr2gr.d $a6, $fa4
-; LA64-NEXT: masknez $a4, $a6, $a4
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: maskeqz $a5, $a2, $a5
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: vinsgr2vr.w $vr3, $a4, 0
-; LA64-NEXT: xvpickve.w $xr4, $xr0, 6
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA64-NEXT: vinsgr2vr.w $vr3, $a3, 1
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a4, $a1, $a3
-; LA64-NEXT: ftintrz.l.s $fa5, $fa4
-; LA64-NEXT: movfr2gr.d $a5, $fa5
-; LA64-NEXT: masknez $a3, $a5, $a3
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: maskeqz $a4, $a2, $a4
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: xvpickve.w $xr4, $xr0, 7
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA64-NEXT: vinsgr2vr.w $vr3, $a3, 2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a4, $a1, $a3
-; LA64-NEXT: ftintrz.l.s $fa5, $fa4
-; LA64-NEXT: movfr2gr.d $a5, $fa5
-; LA64-NEXT: masknez $a3, $a5, $a3
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: maskeqz $a4, $a2, $a4
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: xvpickve.w $xr4, $xr0, 1
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA64-NEXT: vinsgr2vr.w $vr3, $a3, 3
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a4, $a1, $a3
-; LA64-NEXT: ftintrz.l.s $fa5, $fa4
-; LA64-NEXT: movfr2gr.d $a5, $fa5
-; LA64-NEXT: masknez $a3, $a5, $a3
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: maskeqz $a4, $a2, $a4
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: xvpickve.w $xr4, $xr0, 0
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: maskeqz $a5, $a1, $a4
-; LA64-NEXT: ftintrz.l.s $fa5, $fa4
-; LA64-NEXT: movfr2gr.d $a6, $fa5
-; LA64-NEXT: masknez $a4, $a6, $a4
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: maskeqz $a5, $a2, $a5
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: vinsgr2vr.w $vr4, $a4, 0
-; LA64-NEXT: xvpickve.w $xr5, $xr0, 2
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa5, $fa1
-; LA64-NEXT: vinsgr2vr.w $vr4, $a3, 1
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a4, $a1, $a3
-; LA64-NEXT: ftintrz.l.s $fa6, $fa5
-; LA64-NEXT: movfr2gr.d $a5, $fa6
-; LA64-NEXT: masknez $a3, $a5, $a3
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa5
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: maskeqz $a4, $a2, $a4
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa5, $fa5
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: xvpickve.w $xr0, $xr0, 3
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA64-NEXT: vinsgr2vr.w $vr4, $a3, 2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a1, $a1, $a3
-; LA64-NEXT: ftintrz.l.s $fa1, $fa0
-; LA64-NEXT: movfr2gr.d $a4, $fa1
-; LA64-NEXT: masknez $a3, $a4, $a3
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa0
-; LA64-NEXT: or $a1, $a1, $a3
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a3
-; LA64-NEXT: maskeqz $a2, $a2, $a3
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA64-NEXT: or $a1, $a2, $a1
-; LA64-NEXT: movcf2gr $a2, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a2
-; LA64-NEXT: vinsgr2vr.w $vr4, $a1, 3
-; LA64-NEXT: xvpermi.q $xr4, $xr3, 2
-; LA64-NEXT: xvst $xr4, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_sat_v8f32_to_v8i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvftintrz.w.s $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <8 x float>, ptr %a
%r = call <8 x i32> @llvm.fptosi.sat.v8i32.v8f32(<8 x float> %v)
@@ -312,254 +17,12 @@ entry:
}
define void @fptosi_sat_v4f64_to_v4i64(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_sat_v4f64_to_v4i64:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: addi.w $sp, $sp, -160
-; LA32-NEXT: st.w $ra, $sp, 156 # 4-byte Folded Spill
-; LA32-NEXT: st.w $fp, $sp, 152 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s0, $sp, 148 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s1, $sp, 144 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s2, $sp, 140 # 4-byte Folded Spill
-; LA32-NEXT: fst.d $fs0, $sp, 128 # 8-byte Folded Spill
-; LA32-NEXT: fst.d $fs1, $sp, 120 # 8-byte Folded Spill
-; LA32-NEXT: xvld $xr0, $a1, 0
-; LA32-NEXT: xvst $xr0, $sp, 80 # 32-byte Folded Spill
-; LA32-NEXT: move $fp, $a0
-; LA32-NEXT: xvpickve.d $xr0, $xr0, 2
-; LA32-NEXT: xvst $xr0, $sp, 48 # 32-byte Folded Spill
-; LA32-NEXT: movgr2fr.w $fs0, $zero
-; LA32-NEXT: lu12i.w $a0, -246272
-; LA32-NEXT: movgr2frh.w $fs0, $a0
-; LA32-NEXT: fcmp.cult.d $fcc0, $fa0, $fs0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 16
-; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $xr0
-; LA32-NEXT: bl __fixdfdi
-; LA32-NEXT: ld.w $a2, $sp, 16
-; LA32-NEXT: movgr2cf $fcc0, $a2
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI1_0)
-; LA32-NEXT: fld.d $fs1, $a3, %pc_lo12(.LCPI1_0)
-; LA32-NEXT: masknez $a1, $a1, $a2
-; LA32-NEXT: lu12i.w $s0, -524288
-; LA32-NEXT: maskeqz $a3, $s0, $a2
-; LA32-NEXT: xvld $xr0, $sp, 48 # 32-byte Folded Reload
-; LA32-NEXT: fcmp.clt.d $fcc0, $fs1, $fa0
-; LA32-NEXT: or $a1, $a3, $a1
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a3
-; LA32-NEXT: lu12i.w $a4, 524287
-; LA32-NEXT: ori $s1, $a4, 4095
-; LA32-NEXT: maskeqz $a4, $s1, $a3
-; LA32-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA32-NEXT: or $a1, $a4, $a1
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a4
-; LA32-NEXT: masknez $a0, $a0, $a2
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: addi.w $s2, $zero, -1
-; LA32-NEXT: maskeqz $a2, $s2, $a3
-; LA32-NEXT: or $a0, $a2, $a0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
-; LA32-NEXT: xvst $xr0, $sp, 48 # 32-byte Folded Spill
-; LA32-NEXT: xvld $xr0, $sp, 80 # 32-byte Folded Reload
-; LA32-NEXT: xvpickve.d $xr0, $xr0, 3
-; LA32-NEXT: xvst $xr0, $sp, 16 # 32-byte Folded Spill
-; LA32-NEXT: fcmp.clt.d $fcc0, $fs1, $fa0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 12
-; LA32-NEXT: fcmp.cult.d $fcc0, $fa0, $fs0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 8
-; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $xr0
-; LA32-NEXT: bl __fixdfdi
-; LA32-NEXT: ld.w $a2, $sp, 8
-; LA32-NEXT: movgr2cf $fcc0, $a2
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a2
-; LA32-NEXT: ld.w $a3, $sp, 12
-; LA32-NEXT: movgr2cf $fcc0, $a3
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: maskeqz $a4, $s2, $a3
-; LA32-NEXT: xvld $xr0, $sp, 16 # 32-byte Folded Reload
-; LA32-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA32-NEXT: or $a0, $a4, $a0
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: xvld $xr0, $sp, 48 # 32-byte Folded Reload
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2
-; LA32-NEXT: masknez $a0, $a1, $a2
-; LA32-NEXT: maskeqz $a1, $s0, $a2
-; LA32-NEXT: or $a0, $a1, $a0
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: maskeqz $a1, $s1, $a3
-; LA32-NEXT: or $a0, $a1, $a0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3
-; LA32-NEXT: xvst $xr0, $sp, 48 # 32-byte Folded Spill
-; LA32-NEXT: xvld $xr0, $sp, 80 # 32-byte Folded Reload
-; LA32-NEXT: xvpickve.d $xr0, $xr0, 0
-; LA32-NEXT: xvst $xr0, $sp, 16 # 32-byte Folded Spill
-; LA32-NEXT: fcmp.cult.d $fcc0, $fa0, $fs0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 12
-; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $xr0
-; LA32-NEXT: bl __fixdfdi
-; LA32-NEXT: ld.w $a2, $sp, 12
-; LA32-NEXT: movgr2cf $fcc0, $a2
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a2
-; LA32-NEXT: maskeqz $a3, $s0, $a2
-; LA32-NEXT: xvld $xr0, $sp, 16 # 32-byte Folded Reload
-; LA32-NEXT: fcmp.clt.d $fcc0, $fs1, $fa0
-; LA32-NEXT: or $a1, $a3, $a1
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a3
-; LA32-NEXT: maskeqz $a4, $s1, $a3
-; LA32-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA32-NEXT: or $a1, $a4, $a1
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a4
-; LA32-NEXT: masknez $a0, $a0, $a2
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: maskeqz $a2, $s2, $a3
-; LA32-NEXT: or $a0, $a2, $a0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0
-; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
-; LA32-NEXT: xvst $xr0, $sp, 16 # 32-byte Folded Spill
-; LA32-NEXT: xvld $xr0, $sp, 80 # 32-byte Folded Reload
-; LA32-NEXT: xvpickve.d $xr0, $xr0, 1
-; LA32-NEXT: xvst $xr0, $sp, 80 # 32-byte Folded Spill
-; LA32-NEXT: fcmp.clt.d $fcc0, $fs1, $fa0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 12
-; LA32-NEXT: fcmp.cult.d $fcc0, $fa0, $fs0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 8
-; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $xr0
-; LA32-NEXT: bl __fixdfdi
-; LA32-NEXT: ld.w $a2, $sp, 8
-; LA32-NEXT: movgr2cf $fcc0, $a2
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a2
-; LA32-NEXT: ld.w $a3, $sp, 12
-; LA32-NEXT: movgr2cf $fcc0, $a3
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: maskeqz $a4, $s2, $a3
-; LA32-NEXT: xvld $xr0, $sp, 80 # 32-byte Folded Reload
-; LA32-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA32-NEXT: or $a0, $a4, $a0
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: xvld $xr1, $sp, 16 # 32-byte Folded Reload
-; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 2
-; LA32-NEXT: masknez $a0, $a1, $a2
-; LA32-NEXT: maskeqz $a1, $s0, $a2
-; LA32-NEXT: or $a0, $a1, $a0
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: maskeqz $a1, $s1, $a3
-; LA32-NEXT: or $a0, $a1, $a0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 3
-; LA32-NEXT: xvld $xr0, $sp, 48 # 32-byte Folded Reload
-; LA32-NEXT: xvpermi.q $xr1, $xr0, 2
-; LA32-NEXT: xvst $xr1, $fp, 0
-; LA32-NEXT: fld.d $fs1, $sp, 120 # 8-byte Folded Reload
-; LA32-NEXT: fld.d $fs0, $sp, 128 # 8-byte Folded Reload
-; LA32-NEXT: ld.w $s2, $sp, 140 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s1, $sp, 144 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s0, $sp, 148 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $fp, $sp, 152 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $ra, $sp, 156 # 4-byte Folded Reload
-; LA32-NEXT: addi.w $sp, $sp, 160
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_sat_v4f64_to_v4i64:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: xvld $xr0, $a1, 0
-; LA64-NEXT: xvpickve.d $xr3, $xr0, 3
-; LA64-NEXT: lu52i.d $a1, $zero, -962
-; LA64-NEXT: movgr2fr.d $fa1, $a1
-; LA64-NEXT: fcmp.cult.d $fcc0, $fa3, $fa1
-; LA64-NEXT: lu52i.d $a1, $zero, -2048
-; LA64-NEXT: movcf2gr $a2, $fcc0
-; LA64-NEXT: maskeqz $a3, $a1, $a2
-; LA64-NEXT: ftintrz.l.d $fa2, $fa3
-; LA64-NEXT: movfr2gr.d $a4, $fa2
-; LA64-NEXT: masknez $a2, $a4, $a2
-; LA64-NEXT: addi.w $a4, $zero, -1
-; LA64-NEXT: lu52i.d $a5, $a4, 1085
-; LA64-NEXT: movgr2fr.d $fa2, $a5
-; LA64-NEXT: fcmp.clt.d $fcc0, $fa2, $fa3
-; LA64-NEXT: or $a2, $a3, $a2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a5, $a2, $a3
-; LA64-NEXT: lu52i.d $a2, $a4, 2047
-; LA64-NEXT: maskeqz $a3, $a2, $a3
-; LA64-NEXT: fcmp.cun.d $fcc0, $fa3, $fa3
-; LA64-NEXT: or $a3, $a3, $a5
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: xvpickve.d $xr3, $xr0, 2
-; LA64-NEXT: fcmp.cult.d $fcc0, $fa3, $fa1
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: maskeqz $a5, $a1, $a4
-; LA64-NEXT: ftintrz.l.d $fa4, $fa3
-; LA64-NEXT: movfr2gr.d $a6, $fa4
-; LA64-NEXT: masknez $a4, $a6, $a4
-; LA64-NEXT: fcmp.clt.d $fcc0, $fa2, $fa3
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: maskeqz $a5, $a2, $a5
-; LA64-NEXT: fcmp.cun.d $fcc0, $fa3, $fa3
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: vinsgr2vr.d $vr3, $a4, 0
-; LA64-NEXT: xvpickve.d $xr4, $xr0, 1
-; LA64-NEXT: fcmp.cult.d $fcc0, $fa4, $fa1
-; LA64-NEXT: vinsgr2vr.d $vr3, $a3, 1
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a4, $a1, $a3
-; LA64-NEXT: ftintrz.l.d $fa5, $fa4
-; LA64-NEXT: movfr2gr.d $a5, $fa5
-; LA64-NEXT: masknez $a3, $a5, $a3
-; LA64-NEXT: fcmp.clt.d $fcc0, $fa2, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: maskeqz $a4, $a2, $a4
-; LA64-NEXT: fcmp.cun.d $fcc0, $fa4, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: xvpickve.d $xr0, $xr0, 0
-; LA64-NEXT: fcmp.cult.d $fcc0, $fa0, $fa1
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: maskeqz $a1, $a1, $a4
-; LA64-NEXT: ftintrz.l.d $fa1, $fa0
-; LA64-NEXT: movfr2gr.d $a5, $fa1
-; LA64-NEXT: masknez $a4, $a5, $a4
-; LA64-NEXT: fcmp.clt.d $fcc0, $fa2, $fa0
-; LA64-NEXT: or $a1, $a1, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a4
-; LA64-NEXT: maskeqz $a2, $a2, $a4
-; LA64-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA64-NEXT: or $a1, $a2, $a1
-; LA64-NEXT: movcf2gr $a2, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a2
-; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a3, 1
-; LA64-NEXT: xvpermi.q $xr0, $xr3, 2
-; LA64-NEXT: xvst $xr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_sat_v4f64_to_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvftintrz.l.d $xr0, $xr0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <4 x double>, ptr %a
%r = call <4 x i64> @llvm.fptosi.sat.v4i64.v4f64(<4 x double> %v)
@@ -568,21 +31,13 @@ entry:
}
define void @fptosi_clamp_v4f64_to_v4i32(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_clamp_v4f64_to_v4i32:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: xvld $xr0, $a1, 0
-; LA32-NEXT: xvftintrz.w.d $xr0, $xr0, $xr0
-; LA32-NEXT: xvpermi.d $xr0, $xr0, 8
-; LA32-NEXT: vst $vr0, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_clamp_v4f64_to_v4i32:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: xvld $xr0, $a1, 0
-; LA64-NEXT: xvftintrz.w.d $xr0, $xr0, $xr0
-; LA64-NEXT: xvpermi.d $xr0, $xr0, 8
-; LA64-NEXT: vst $vr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_clamp_v4f64_to_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvftintrz.w.d $xr0, $xr0, $xr0
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 8
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <4 x double>, ptr %a
%i = fptosi <4 x double> %v to <4 x i32>
@@ -593,31 +48,18 @@ entry:
}
define void @fptosi_nanguard_v4f64_to_v4i32(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_nanguard_v4f64_to_v4i32:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: xvld $xr0, $a1, 0
-; LA32-NEXT: xvrepli.b $xr1, 0
-; LA32-NEXT: xvfcmp.cun.d $xr1, $xr0, $xr1
-; LA32-NEXT: xvpickev.w $xr1, $xr1, $xr1
-; LA32-NEXT: xvpermi.d $xr1, $xr1, 216
-; LA32-NEXT: xvftintrz.w.d $xr0, $xr0, $xr0
-; LA32-NEXT: xvpermi.d $xr0, $xr0, 8
-; LA32-NEXT: vandn.v $vr0, $vr1, $vr0
-; LA32-NEXT: vst $vr0, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_nanguard_v4f64_to_v4i32:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: xvld $xr0, $a1, 0
-; LA64-NEXT: xvrepli.b $xr1, 0
-; LA64-NEXT: xvfcmp.cun.d $xr1, $xr0, $xr1
-; LA64-NEXT: xvpickev.w $xr1, $xr1, $xr1
-; LA64-NEXT: xvpermi.d $xr1, $xr1, 216
-; LA64-NEXT: xvftintrz.w.d $xr0, $xr0, $xr0
-; LA64-NEXT: xvpermi.d $xr0, $xr0, 8
-; LA64-NEXT: vandn.v $vr0, $vr1, $vr0
-; LA64-NEXT: vst $vr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_nanguard_v4f64_to_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvrepli.b $xr1, 0
+; CHECK-NEXT: xvfcmp.cun.d $xr1, $xr0, $xr1
+; CHECK-NEXT: xvpickev.w $xr1, $xr1, $xr1
+; CHECK-NEXT: xvpermi.d $xr1, $xr1, 216
+; CHECK-NEXT: xvftintrz.w.d $xr0, $xr0, $xr0
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 8
+; CHECK-NEXT: vandn.v $vr0, $vr1, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <4 x double>, ptr %a
%c = fcmp uno <4 x double> %v, zeroinitializer
@@ -628,29 +70,17 @@ entry:
}
define void @fptosi_nanguard_v4f32_to_v4i64(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_nanguard_v4f32_to_v4i64:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: vrepli.b $vr1, 0
-; LA32-NEXT: vfcmp.cun.s $vr1, $vr0, $vr1
-; LA32-NEXT: vext2xv.d.w $xr1, $xr1
-; LA32-NEXT: xvpermi.d $xr0, $xr0, 216
-; LA32-NEXT: xvftintrzl.l.s $xr0, $xr0
-; LA32-NEXT: xvandn.v $xr0, $xr1, $xr0
-; LA32-NEXT: xvst $xr0, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_nanguard_v4f32_to_v4i64:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: vrepli.b $vr1, 0
-; LA64-NEXT: vfcmp.cun.s $vr1, $vr0, $vr1
-; LA64-NEXT: vext2xv.d.w $xr1, $xr1
-; LA64-NEXT: xvpermi.d $xr0, $xr0, 216
-; LA64-NEXT: xvftintrzl.l.s $xr0, $xr0
-; LA64-NEXT: xvandn.v $xr0, $xr1, $xr0
-; LA64-NEXT: xvst $xr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_nanguard_v4f32_to_v4i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vrepli.b $vr1, 0
+; CHECK-NEXT: vfcmp.cun.s $vr1, $vr0, $vr1
+; CHECK-NEXT: vext2xv.d.w $xr1, $xr1
+; CHECK-NEXT: xvpermi.d $xr0, $xr0, 216
+; CHECK-NEXT: xvftintrzl.l.s $xr0, $xr0
+; CHECK-NEXT: xvandn.v $xr0, $xr1, $xr0
+; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <4 x float>, ptr %a
%c = fcmp uno <4 x float> %v, zeroinitializer
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fptosi-sat.ll b/llvm/test/CodeGen/LoongArch/lsx/fptosi-sat.ll
index 7a801b9fabd938..712ded72aaf5a7 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fptosi-sat.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fptosi-sat.ll
@@ -1,171 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=LA32
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=LA64
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @fptosi_sat_v4f32_to_v4i32(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_sat_v4f32_to_v4i32:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: vreplvei.w $vr3, $vr0, 1
-; LA32-NEXT: lu12i.w $a1, -200704
-; LA32-NEXT: movgr2fr.w $fa1, $a1
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA32-NEXT: lu12i.w $a1, -524288
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: maskeqz $a3, $a1, $a2
-; LA32-NEXT: ftintrz.w.s $fa2, $fa3
-; LA32-NEXT: movfr2gr.s $a4, $fa2
-; LA32-NEXT: masknez $a2, $a4, $a2
-; LA32-NEXT: lu12i.w $a4, 323583
-; LA32-NEXT: ori $a4, $a4, 4095
-; LA32-NEXT: movgr2fr.w $fa2, $a4
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA32-NEXT: or $a2, $a3, $a2
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a4, $a2, $a3
-; LA32-NEXT: lu12i.w $a2, 524287
-; LA32-NEXT: ori $a2, $a2, 4095
-; LA32-NEXT: maskeqz $a3, $a2, $a3
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA32-NEXT: or $a3, $a3, $a4
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: vreplvei.w $vr3, $vr0, 0
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: maskeqz $a5, $a1, $a4
-; LA32-NEXT: ftintrz.w.s $fa4, $fa3
-; LA32-NEXT: movfr2gr.s $a6, $fa4
-; LA32-NEXT: masknez $a4, $a6, $a4
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA32-NEXT: or $a4, $a5, $a4
-; LA32-NEXT: movcf2gr $a5, $fcc0
-; LA32-NEXT: masknez $a4, $a4, $a5
-; LA32-NEXT: maskeqz $a5, $a2, $a5
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA32-NEXT: or $a4, $a5, $a4
-; LA32-NEXT: movcf2gr $a5, $fcc0
-; LA32-NEXT: masknez $a4, $a4, $a5
-; LA32-NEXT: vinsgr2vr.w $vr3, $a4, 0
-; LA32-NEXT: vreplvei.w $vr4, $vr0, 2
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA32-NEXT: vinsgr2vr.w $vr3, $a3, 1
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: maskeqz $a4, $a1, $a3
-; LA32-NEXT: ftintrz.w.s $fa5, $fa4
-; LA32-NEXT: movfr2gr.s $a5, $fa5
-; LA32-NEXT: masknez $a3, $a5, $a3
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: maskeqz $a4, $a2, $a4
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA32-NEXT: or $a3, $a4, $a3
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a3, $a3, $a4
-; LA32-NEXT: vreplvei.w $vr0, $vr0, 3
-; LA32-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA32-NEXT: vinsgr2vr.w $vr3, $a3, 2
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: maskeqz $a1, $a1, $a3
-; LA32-NEXT: ftintrz.w.s $fa1, $fa0
-; LA32-NEXT: movfr2gr.s $a4, $fa1
-; LA32-NEXT: masknez $a3, $a4, $a3
-; LA32-NEXT: fcmp.clt.s $fcc0, $fa2, $fa0
-; LA32-NEXT: or $a1, $a1, $a3
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a3
-; LA32-NEXT: maskeqz $a2, $a2, $a3
-; LA32-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA32-NEXT: or $a1, $a2, $a1
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a2
-; LA32-NEXT: vinsgr2vr.w $vr3, $a1, 3
-; LA32-NEXT: vst $vr3, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_sat_v4f32_to_v4i32:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: vreplvei.w $vr3, $vr0, 1
-; LA64-NEXT: lu12i.w $a1, -200704
-; LA64-NEXT: movgr2fr.w $fa1, $a1
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA64-NEXT: lu12i.w $a1, -524288
-; LA64-NEXT: movcf2gr $a2, $fcc0
-; LA64-NEXT: maskeqz $a3, $a1, $a2
-; LA64-NEXT: ftintrz.l.s $fa2, $fa3
-; LA64-NEXT: movfr2gr.d $a4, $fa2
-; LA64-NEXT: masknez $a2, $a4, $a2
-; LA64-NEXT: lu12i.w $a4, 323583
-; LA64-NEXT: ori $a4, $a4, 4095
-; LA64-NEXT: movgr2fr.w $fa2, $a4
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA64-NEXT: or $a2, $a3, $a2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a4, $a2, $a3
-; LA64-NEXT: lu12i.w $a2, 524287
-; LA64-NEXT: ori $a2, $a2, 4095
-; LA64-NEXT: maskeqz $a3, $a2, $a3
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA64-NEXT: or $a3, $a3, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: vreplvei.w $vr3, $vr0, 0
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa3, $fa1
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: maskeqz $a5, $a1, $a4
-; LA64-NEXT: ftintrz.l.s $fa4, $fa3
-; LA64-NEXT: movfr2gr.d $a6, $fa4
-; LA64-NEXT: masknez $a4, $a6, $a4
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa3
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: maskeqz $a5, $a2, $a5
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa3, $fa3
-; LA64-NEXT: or $a4, $a5, $a4
-; LA64-NEXT: movcf2gr $a5, $fcc0
-; LA64-NEXT: masknez $a4, $a4, $a5
-; LA64-NEXT: vinsgr2vr.w $vr3, $a4, 0
-; LA64-NEXT: vreplvei.w $vr4, $vr0, 2
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa4, $fa1
-; LA64-NEXT: vinsgr2vr.w $vr3, $a3, 1
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a4, $a1, $a3
-; LA64-NEXT: ftintrz.l.s $fa5, $fa4
-; LA64-NEXT: movfr2gr.d $a5, $fa5
-; LA64-NEXT: masknez $a3, $a5, $a3
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: maskeqz $a4, $a2, $a4
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa4, $fa4
-; LA64-NEXT: or $a3, $a4, $a3
-; LA64-NEXT: movcf2gr $a4, $fcc0
-; LA64-NEXT: masknez $a3, $a3, $a4
-; LA64-NEXT: vreplvei.w $vr0, $vr0, 3
-; LA64-NEXT: fcmp.cult.s $fcc0, $fa0, $fa1
-; LA64-NEXT: vinsgr2vr.w $vr3, $a3, 2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a1, $a1, $a3
-; LA64-NEXT: ftintrz.l.s $fa1, $fa0
-; LA64-NEXT: movfr2gr.d $a4, $fa1
-; LA64-NEXT: masknez $a3, $a4, $a3
-; LA64-NEXT: fcmp.clt.s $fcc0, $fa2, $fa0
-; LA64-NEXT: or $a1, $a1, $a3
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a3
-; LA64-NEXT: maskeqz $a2, $a2, $a3
-; LA64-NEXT: fcmp.cun.s $fcc0, $fa0, $fa0
-; LA64-NEXT: or $a1, $a2, $a1
-; LA64-NEXT: movcf2gr $a2, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a2
-; LA64-NEXT: vinsgr2vr.w $vr3, $a1, 3
-; LA64-NEXT: vst $vr3, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_sat_v4f32_to_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vftintrz.w.s $vr0, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <4 x float>, ptr %a
%r = call <4 x i32> @llvm.fptosi.sat.v4i32.v4f32(<4 x float> %v)
@@ -174,148 +17,12 @@ entry:
}
define void @fptosi_sat_v2f64_to_v2i64(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_sat_v2f64_to_v2i64:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: addi.w $sp, $sp, -80
-; LA32-NEXT: st.w $ra, $sp, 76 # 4-byte Folded Spill
-; LA32-NEXT: st.w $fp, $sp, 72 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s0, $sp, 68 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s1, $sp, 64 # 4-byte Folded Spill
-; LA32-NEXT: st.w $s2, $sp, 60 # 4-byte Folded Spill
-; LA32-NEXT: fst.d $fs0, $sp, 48 # 8-byte Folded Spill
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: vst $vr0, $sp, 32 # 16-byte Folded Spill
-; LA32-NEXT: move $fp, $a0
-; LA32-NEXT: vreplvei.d $vr0, $vr0, 0
-; LA32-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
-; LA32-NEXT: movgr2fr.w $fs0, $zero
-; LA32-NEXT: lu12i.w $a0, -246272
-; LA32-NEXT: movgr2frh.w $fs0, $a0
-; LA32-NEXT: fcmp.cult.d $fcc0, $fa0, $fs0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 12
-; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
-; LA32-NEXT: bl __fixdfdi
-; LA32-NEXT: ld.w $a2, $sp, 12
-; LA32-NEXT: movgr2cf $fcc0, $a2
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI1_0)
-; LA32-NEXT: fld.d $fa2, $a3, %pc_lo12(.LCPI1_0)
-; LA32-NEXT: masknez $a1, $a1, $a2
-; LA32-NEXT: lu12i.w $s0, -524288
-; LA32-NEXT: maskeqz $a3, $s0, $a2
-; LA32-NEXT: vld $vr1, $sp, 16 # 16-byte Folded Reload
-; LA32-NEXT: fcmp.clt.d $fcc0, $fa2, $fa1
-; LA32-NEXT: or $a1, $a3, $a1
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a3
-; LA32-NEXT: lu12i.w $a4, 524287
-; LA32-NEXT: ori $s1, $a4, 4095
-; LA32-NEXT: maskeqz $a4, $s1, $a3
-; LA32-NEXT: fcmp.cun.d $fcc0, $fa1, $fa1
-; LA32-NEXT: or $a1, $a4, $a1
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a1, $a1, $a4
-; LA32-NEXT: masknez $a0, $a0, $a2
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: addi.w $s2, $zero, -1
-; LA32-NEXT: maskeqz $a2, $s2, $a3
-; LA32-NEXT: or $a0, $a2, $a0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: vinsgr2vr.w $vr1, $a0, 0
-; LA32-NEXT: vinsgr2vr.w $vr1, $a1, 1
-; LA32-NEXT: vst $vr1, $sp, 16 # 16-byte Folded Spill
-; LA32-NEXT: vld $vr1, $sp, 32 # 16-byte Folded Reload
-; LA32-NEXT: vreplvei.d $vr0, $vr1, 1
-; LA32-NEXT: vst $vr0, $sp, 32 # 16-byte Folded Spill
-; LA32-NEXT: fcmp.clt.d $fcc0, $fa2, $fa0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 12
-; LA32-NEXT: fcmp.cult.d $fcc0, $fa0, $fs0
-; LA32-NEXT: movcf2gr $a0, $fcc0
-; LA32-NEXT: st.w $a0, $sp, 8
-; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
-; LA32-NEXT: bl __fixdfdi
-; LA32-NEXT: ld.w $a2, $sp, 8
-; LA32-NEXT: movgr2cf $fcc0, $a2
-; LA32-NEXT: movcf2gr $a2, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a2
-; LA32-NEXT: ld.w $a3, $sp, 12
-; LA32-NEXT: movgr2cf $fcc0, $a3
-; LA32-NEXT: movcf2gr $a3, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: maskeqz $a4, $s2, $a3
-; LA32-NEXT: vld $vr0, $sp, 32 # 16-byte Folded Reload
-; LA32-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA32-NEXT: or $a0, $a4, $a0
-; LA32-NEXT: movcf2gr $a4, $fcc0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2
-; LA32-NEXT: masknez $a0, $a1, $a2
-; LA32-NEXT: maskeqz $a1, $s0, $a2
-; LA32-NEXT: or $a0, $a1, $a0
-; LA32-NEXT: masknez $a0, $a0, $a3
-; LA32-NEXT: maskeqz $a1, $s1, $a3
-; LA32-NEXT: or $a0, $a1, $a0
-; LA32-NEXT: masknez $a0, $a0, $a4
-; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3
-; LA32-NEXT: vst $vr0, $fp, 0
-; LA32-NEXT: fld.d $fs0, $sp, 48 # 8-byte Folded Reload
-; LA32-NEXT: ld.w $s2, $sp, 60 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s1, $sp, 64 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $s0, $sp, 68 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $fp, $sp, 72 # 4-byte Folded Reload
-; LA32-NEXT: ld.w $ra, $sp, 76 # 4-byte Folded Reload
-; LA32-NEXT: addi.w $sp, $sp, 80
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_sat_v2f64_to_v2i64:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: vreplvei.d $vr1, $vr0, 1
-; LA64-NEXT: lu52i.d $a1, $zero, -962
-; LA64-NEXT: movgr2fr.d $fa2, $a1
-; LA64-NEXT: fcmp.cult.d $fcc0, $fa1, $fa2
-; LA64-NEXT: lu52i.d $a1, $zero, -2048
-; LA64-NEXT: movcf2gr $a2, $fcc0
-; LA64-NEXT: maskeqz $a3, $a1, $a2
-; LA64-NEXT: ftintrz.l.d $fa3, $fa1
-; LA64-NEXT: movfr2gr.d $a4, $fa3
-; LA64-NEXT: masknez $a2, $a4, $a2
-; LA64-NEXT: addi.w $a4, $zero, -1
-; LA64-NEXT: lu52i.d $a5, $a4, 1085
-; LA64-NEXT: movgr2fr.d $fa3, $a5
-; LA64-NEXT: fcmp.clt.d $fcc0, $fa3, $fa1
-; LA64-NEXT: or $a2, $a3, $a2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a2, $a2, $a3
-; LA64-NEXT: lu52i.d $a4, $a4, 2047
-; LA64-NEXT: maskeqz $a3, $a4, $a3
-; LA64-NEXT: fcmp.cun.d $fcc0, $fa1, $fa1
-; LA64-NEXT: or $a2, $a3, $a2
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: vreplvei.d $vr0, $vr0, 0
-; LA64-NEXT: fcmp.cult.d $fcc0, $fa0, $fa2
-; LA64-NEXT: masknez $a2, $a2, $a3
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: maskeqz $a1, $a1, $a3
-; LA64-NEXT: ftintrz.l.d $fa1, $fa0
-; LA64-NEXT: movfr2gr.d $a5, $fa1
-; LA64-NEXT: masknez $a3, $a5, $a3
-; LA64-NEXT: fcmp.clt.d $fcc0, $fa3, $fa0
-; LA64-NEXT: or $a1, $a1, $a3
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a3
-; LA64-NEXT: maskeqz $a3, $a4, $a3
-; LA64-NEXT: fcmp.cun.d $fcc0, $fa0, $fa0
-; LA64-NEXT: or $a1, $a3, $a1
-; LA64-NEXT: movcf2gr $a3, $fcc0
-; LA64-NEXT: masknez $a1, $a1, $a3
-; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0
-; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 1
-; LA64-NEXT: vst $vr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_sat_v2f64_to_v2i64:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vftintrz.l.d $vr0, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <2 x double>, ptr %a
%r = call <2 x i64> @llvm.fptosi.sat.v2i64.v2f64(<2 x double> %v)
@@ -428,21 +135,13 @@ entry:
}
define void @fptosi_clamp_v4f64_to_v4i32(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_clamp_v4f64_to_v4i32:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: vld $vr1, $a1, 16
-; LA32-NEXT: vftintrz.w.d $vr0, $vr1, $vr0
-; LA32-NEXT: vst $vr0, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_clamp_v4f64_to_v4i32:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: vld $vr1, $a1, 16
-; LA64-NEXT: vftintrz.w.d $vr0, $vr1, $vr0
-; LA64-NEXT: vst $vr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_clamp_v4f64_to_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a1, 16
+; CHECK-NEXT: vftintrz.w.d $vr0, $vr1, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <4 x double>, ptr %a
%i = fptosi <4 x double> %v to <4 x i32>
@@ -453,31 +152,18 @@ entry:
}
define void @fptosi_nanguard_v4f64_to_v4i32(ptr %res, ptr %a) nounwind {
-; LA32-LABEL: fptosi_nanguard_v4f64_to_v4i32:
-; LA32: # %bb.0: # %entry
-; LA32-NEXT: vld $vr0, $a1, 0
-; LA32-NEXT: vld $vr1, $a1, 16
-; LA32-NEXT: vrepli.b $vr2, 0
-; LA32-NEXT: vfcmp.cun.d $vr3, $vr0, $vr2
-; LA32-NEXT: vfcmp.cun.d $vr2, $vr1, $vr2
-; LA32-NEXT: vpickev.w $vr2, $vr2, $vr3
-; LA32-NEXT: vftintrz.w.d $vr0, $vr1, $vr0
-; LA32-NEXT: vandn.v $vr0, $vr2, $vr0
-; LA32-NEXT: vst $vr0, $a0, 0
-; LA32-NEXT: ret
-;
-; LA64-LABEL: fptosi_nanguard_v4f64_to_v4i32:
-; LA64: # %bb.0: # %entry
-; LA64-NEXT: vld $vr0, $a1, 0
-; LA64-NEXT: vld $vr1, $a1, 16
-; LA64-NEXT: vrepli.b $vr2, 0
-; LA64-NEXT: vfcmp.cun.d $vr3, $vr0, $vr2
-; LA64-NEXT: vfcmp.cun.d $vr2, $vr1, $vr2
-; LA64-NEXT: vpickev.w $vr2, $vr2, $vr3
-; LA64-NEXT: vftintrz.w.d $vr0, $vr1, $vr0
-; LA64-NEXT: vandn.v $vr0, $vr2, $vr0
-; LA64-NEXT: vst $vr0, $a0, 0
-; LA64-NEXT: ret
+; CHECK-LABEL: fptosi_nanguard_v4f64_to_v4i32:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vld $vr1, $a1, 16
+; CHECK-NEXT: vrepli.b $vr2, 0
+; CHECK-NEXT: vfcmp.cun.d $vr3, $vr0, $vr2
+; CHECK-NEXT: vfcmp.cun.d $vr2, $vr1, $vr2
+; CHECK-NEXT: vpickev.w $vr2, $vr2, $vr3
+; CHECK-NEXT: vftintrz.w.d $vr0, $vr1, $vr0
+; CHECK-NEXT: vandn.v $vr0, $vr2, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: ret
entry:
%v = load <4 x double>, ptr %a
%c = fcmp uno <4 x double> %v, zeroinitializer
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