[llvm-branch-commits] [clang] [llvm] [openmp] [clang][OpenMP] Add grid-stride loop SPMD kernel promotion (PR #229079)
Nicole Aschenbrenner via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Tue Oct 20 08:00:46 PDT 2026
https://github.com/nicebert updated https://github.com/llvm/llvm-project/pull/229079
>From aa4cb63f8c13218d4318a19d331536028a27c0f2 Mon Sep 17 00:00:00 2001
From: Nicole Aschenbrenner <nicole.aschenbrenner at amd.com>
Date: Fri, 25 Sep 2026 10:11:10 -0500
Subject: [PATCH 1/2] [clang][OpenMP] Add strided-loop SPMD kernel promotion
A target teams distribute parallel for is only promoted when every
iteration is guaranteed a thread. Without the oversubscription
assumptions, or with a num_teams clause, it is emitted as nested
worksharing loops, while Flang runs the same region as a grid-stride
loop.
Promote these kernels too, so the loop body strides across the grid,
and tag them SPMD_STRIDED_LOOP so the launch can be told apart from
plain SPMD. This allows teams loop and target teams loop to always get
optimized. Since those can carry lastprivate(conditional:), the
promoted path has to track it.
---
clang/lib/CodeGen/CGOpenMPRuntime.h | 6 +
clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp | 74 +-
clang/lib/CodeGen/CGOpenMPRuntimeGPU.h | 14 +
clang/lib/CodeGen/CGStmtOpenMP.cpp | 40 +-
.../test/OpenMP/amdgcn_target_device_vla.cpp | 383 +-
.../amdgpu_target_with_aligned_attribute.c | 217 +-
.../metadirective_device_arch_codegen.cpp | 19 +-
clang/test/OpenMP/nvptx_SPMD_codegen.cpp | 12453 +++++++---------
..._teams_distribute_parallel_for_codegen.cpp | 1771 +--
...s_distribute_parallel_for_simd_codegen.cpp | 1006 +-
...vptx_target_teams_generic_loop_codegen.cpp | 1907 +--
clang/test/OpenMP/target_loop_promotion.cpp | 444 +
clang/test/OpenMP/target_no_loop.cpp | 356 -
...s_generic_loop_codegen_as_parallel_for.cpp | 552 +-
.../llvm/Frontend/OpenMP/OMPDeviceConstants.h | 7 +-
.../include/llvm/Frontend/OpenMP/OMPKinds.def | 12 +-
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 7 +-
offload/include/device.h | 5 +
offload/libompaccsupport/device.cpp | 2 +-
.../common/include/PluginInterface.h | 1 +
.../test/offloading/gpupgo/pgo_atomic_teams.c | 46 +-
offload/test/offloading/small_trip_count.c | 16 +-
.../small_trip_count_thread_limit.cpp | 2 +-
offload/test/offloading/target-no-loop.c | 19 +-
openmp/device/src/Kernel.cpp | 7 +-
25 files changed, 7649 insertions(+), 11717 deletions(-)
create mode 100644 clang/test/OpenMP/target_loop_promotion.cpp
delete mode 100644 clang/test/OpenMP/target_no_loop.cpp
diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h
index cc37d813a6dc58..d931e75e9da37f 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntime.h
+++ b/clang/lib/CodeGen/CGOpenMPRuntime.h
@@ -676,6 +676,12 @@ class CGOpenMPRuntime {
return false;
}
+ /// Check whether \a S is the loop the target kernel being emitted was
+ /// promoted for, to complete the promotion to a strided-loop SPMD kernel.
+ virtual bool canPromoteToStridedLoop(const OMPLoopDirective &S) const {
+ return false;
+ }
+
/// Get call to __kmpc_alloc_shared
virtual std::pair<llvm::Value *, llvm::Value *>
getKmpcAllocShared(CodeGenFunction &CGF, const VarDecl *VD) {
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 1dd2616f79bf0d..7cc383b76af0b5 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -706,8 +706,8 @@ static bool supportsSPMDExecutionMode(ASTContext &Ctx,
"Unknown programming model for OpenMP directive on NVPTX target.");
}
-static bool isNoLoopCompatibleSchedule(ASTContext &Ctx,
- const OMPLoopDirective &LD) {
+static bool isPromotableLoopSchedule(ASTContext &Ctx,
+ const OMPLoopDirective &LD) {
const auto *C = LD.getSingleClause<OMPScheduleClause>();
if (!C)
return true;
@@ -728,17 +728,24 @@ static bool isNoLoopCompatibleSchedule(ASTContext &Ctx,
}
}
-static const OMPLoopDirective *
-checkAndGetNoLoopDirective(ASTContext &Ctx, const OMPExecutableDirective &D) {
+void CGOpenMPRuntimeGPU::checkAndSetPromotableLoopDirective(
+ const OMPExecutableDirective &D) {
+ NoLoopDirective = nullptr;
+ StridedLoopDirective = nullptr;
+
+ ASTContext &Ctx = CGM.getContext();
const LangOptions &LangOpts = Ctx.getLangOpts();
- if (!LangOpts.OpenMPTeamSubscription || !LangOpts.OpenMPThreadSubscription)
- return nullptr;
+ bool OneIterationPerThread =
+ LangOpts.OpenMPTeamSubscription && LangOpts.OpenMPThreadSubscription;
const OMPExecutableDirective *Nested = &D;
while (true) {
- if (Nested->hasClausesOfKind<OMPNumTeamsClause>() ||
- Nested->hasClausesOfKind<OMPReductionClause>())
- return nullptr;
+ if (Nested->hasClausesOfKind<OMPReductionClause>())
+ return;
+
+ if (Nested->hasClausesOfKind<OMPNumTeamsClause>())
+ OneIterationPerThread = false;
+
OpenMPDirectiveKind DKind = Nested->getDirectiveKind();
if (DKind != OMPD_target && DKind != OMPD_target_teams &&
DKind != OMPD_teams)
@@ -750,15 +757,14 @@ checkAndGetNoLoopDirective(ASTContext &Ctx, const OMPExecutableDirective &D) {
CGOpenMPRuntime::getSingleCompoundChild(Ctx, Body))
: nullptr;
if (!Nested)
- return nullptr;
+ return;
}
const auto *LD = dyn_cast<OMPLoopDirective>(Nested);
// Do not filter out 'ordered' since Sema rejects it on these directives.
- if (!LD || LD->getLoopsNumber() != 1 ||
- !isNoLoopCompatibleSchedule(Ctx, *LD) ||
+ if (!LD || LD->getLoopsNumber() != 1 || !isPromotableLoopSchedule(Ctx, *LD) ||
LD->getSingleClause<OMPDistScheduleClause>())
- return nullptr;
+ return;
for (const auto *C : LD->getClausesOfKind<OMPIfClause>()) {
if (C->getNameModifier() != OMPD_unknown &&
@@ -768,28 +774,36 @@ checkAndGetNoLoopDirective(ASTContext &Ctx, const OMPExecutableDirective &D) {
bool CondVal;
if (!C->getCondition()->EvaluateAsBooleanCondition(CondVal, Ctx) ||
!CondVal)
- return nullptr;
+ return;
}
- auto getNoLoopDirective = [LD](bool Promotable) -> const OMPLoopDirective * {
- return Promotable ? LD : nullptr;
+ auto setPromotableLoop = [&](bool Promotable = true) {
+ if (!Promotable)
+ return;
+ if (OneIterationPerThread)
+ NoLoopDirective = LD;
+ else
+ StridedLoopDirective = LD;
};
if (const auto *TTLD = dyn_cast<OMPTargetTeamsGenericLoopDirective>(LD))
- return getNoLoopDirective(TTLD->canBeParallelFor());
+ return setPromotableLoop(TTLD->canBeParallelFor());
if (const auto *TLD = dyn_cast<OMPTeamsGenericLoopDirective>(LD))
- return getNoLoopDirective(TLD->canBeParallelFor());
+ return setPromotableLoop(TLD->canBeParallelFor());
+
if (!isOpenMPDistributeDirective(LD->getDirectiveKind()) ||
!isOpenMPParallelDirective(LD->getDirectiveKind()))
- return nullptr;
+ return;
+
if (const auto *TTD =
dyn_cast<OMPTargetTeamsDistributeParallelForDirective>(LD))
- return getNoLoopDirective(!TTD->hasCancel());
+ return setPromotableLoop(!TTD->hasCancel());
if (const auto *TD = dyn_cast<OMPTeamsDistributeParallelForDirective>(LD))
- return getNoLoopDirective(!TD->hasCancel());
+ return setPromotableLoop(!TD->hasCancel());
if (const auto *DD = dyn_cast<OMPDistributeParallelForDirective>(LD))
- return getNoLoopDirective(!DD->hasCancel());
- return LD;
+ return setPromotableLoop(!DD->hasCancel());
+
+ setPromotableLoop();
}
void CGOpenMPRuntimeGPU::emitNonSPMDKernel(const OMPExecutableDirective &D,
@@ -853,11 +867,15 @@ void CGOpenMPRuntimeGPU::emitKernelInit(const OMPExecutableDirective &D,
IsSPMD ? llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD
: llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_GENERIC;
- NoLoopDirective =
- IsSPMD ? checkAndGetNoLoopDirective(CGM.getContext(), D) : nullptr;
- if (NoLoopDirective)
- Attrs.ExecFlags =
- llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP;
+ if (IsSPMD) {
+ checkAndSetPromotableLoopDirective(D);
+ if (NoLoopDirective)
+ Attrs.ExecFlags =
+ llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP;
+ else if (StridedLoopDirective)
+ Attrs.ExecFlags =
+ llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP;
+ }
computeMinAndMaxThreadsAndTeams(D, CGF, Attrs);
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
index 5a3334b7bf11a9..93b95e5908a25b 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
@@ -64,6 +64,10 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime {
void emitBareKernelEnvironment(const OMPExecutableDirective &D,
CodeGenFunction &CGF);
+ /// Set NoLoopDirective or StridedLoopDirective to the loop the SPMD target
+ /// directive \a D can be promoted for, resetting both first.
+ void checkAndSetPromotableLoopDirective(const OMPExecutableDirective &D);
+
/// Helper for target directive initialization.
void emitKernelInit(const OMPExecutableDirective &D, CodeGenFunction &CGF,
EntryFunctionState &EST, bool IsSPMD);
@@ -153,6 +157,12 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime {
return &S == NoLoopDirective;
}
+ /// Check whether \a S is the loop the target kernel being emitted was
+ /// promoted for, to complete the promotion to a strided-loop SPMD kernel.
+ bool canPromoteToStridedLoop(const OMPLoopDirective &S) const override {
+ return &S == StridedLoopDirective;
+ }
+
/// Get call to __kmpc_alloc_shared
std::pair<llvm::Value *, llvm::Value *>
getKmpcAllocShared(CodeGenFunction &CGF, const VarDecl *VD) override;
@@ -389,6 +399,10 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime {
/// by the kernel prologue and read back while the region's body is emitted.
const OMPLoopDirective *NoLoopDirective = nullptr;
+ /// The loop the target region being emitted was promoted to strided-loop
+ /// for, set and read like NoLoopDirective.
+ const OMPLoopDirective *StridedLoopDirective = nullptr;
+
/// Map between an outlined function and its wrapper.
llvm::DenseMap<llvm::Function *, llvm::Function *> WrapperFunctionsMap;
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index e654e711db4517..29981c95b475ca 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -3985,8 +3985,9 @@ emitInnerParallelForWhenCombined(CodeGenFunction &CGF,
}
CodeGenFunction::OMPCancelStackRAII CancelRegion(CGF, EKind, HasCancel);
- CodeGenModule &CGM = CGF.CGM;
- if (CGM.getOpenMPRuntime().canPromoteToNoLoop(S)) {
+ CGOpenMPRuntime &RT = CGF.CGM.getOpenMPRuntime();
+ bool NoLoop = RT.canPromoteToNoLoop(S);
+ if (NoLoop || RT.canPromoteToStridedLoop(S)) {
// Prepare the loop variables and their privatization.
emitLoopIterationspaceVars(CGF, S);
OMPLoopScope PreInitScope(CGF, S);
@@ -3997,11 +3998,13 @@ emitInnerParallelForWhenCombined(CodeGenFunction &CGF,
(void)PrivateScope.Privatize();
CodeGenFunction::OMPPrivateScope LastprivateScope(CGF);
+ CGOpenMPRuntime::LastprivateConditionalRAII LPCRegion(
+ CGF, S, CGF.EmitLValue(S.getIterationVariable()));
(void)CGF.EmitOMPLastprivateClauseInit(S, LastprivateScope);
(void)LastprivateScope.Privatize();
if (isOpenMPTargetExecutionDirective(EKind))
- CGM.getOpenMPRuntime().adjustTargetSpecificDataForLambdas(CGF, S);
+ RT.adjustTargetSpecificDataForLambdas(CGF, S);
// Rebuild what the OMPCanonicalLoop node supplies under the IRBuilder
// flag: iteration count, loop, index-to-variable mapping, body.
@@ -4021,8 +4024,7 @@ emitInnerParallelForWhenCombined(CodeGenFunction &CGF,
llvm::OpenMPIRBuilder::InsertPointTy AllocaIP(
CGF.AllocaInsertPt->getIterator());
- llvm::OpenMPIRBuilder &OMPBuilder =
- CGM.getOpenMPRuntime().getOMPBuilder();
+ llvm::OpenMPIRBuilder &OMPBuilder = RT.getOMPBuilder();
bool NeedsLastprivateFinalCopy = hasLoopLastprivateVariable(
S, [&S](const Expr *E) { return !isLoopCounter(S, E); });
@@ -4035,7 +4037,7 @@ emitInnerParallelForWhenCombined(CodeGenFunction &CGF,
/*HasMonotonicModifier=*/false, /*HasNonmonotonicModifier=*/false,
/*HasOrderedClause=*/false,
llvm::omp::WorksharingLoopType::DistributeForStaticLoop,
- /*NoLoop=*/true, /*HasDistSchedule=*/false,
+ /*NoLoop=*/NoLoop, /*HasDistSchedule=*/false,
/*DistScheduleChunkSize=*/nullptr,
/*NeedsLastIter=*/NeedsLastprivateFinalCopy));
@@ -6635,8 +6637,11 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S,
!isOpenMPTeamsDirective(S.getDirectiveKind()))
EmitOMPReductionClauseInit(S, LoopScope);
- const bool NoLoopKernel = CGM.getOpenMPRuntime().canPromoteToNoLoop(S);
- if (!NoLoopKernel)
+ // Defer lastprivate init to the parallel region for no-loop or
+ // strided-loop
+ const bool IsPromotedLoopKernel =
+ RT.canPromoteToNoLoop(S) || RT.canPromoteToStridedLoop(S);
+ if (!IsPromotedLoopKernel)
HasLastprivateClause = EmitOMPLastprivateClauseInit(S, LoopScope);
EmitOMPPrivateLoopCounters(S, LoopScope);
@@ -6666,9 +6671,9 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S,
// omit the outer distribute loop and let the inner worksharing loop
// schedule the flattened team/thread iteration space, necessary for
- // GPU fused schedule and no-loop optimization
+ // GPU fused schedule and loop-grid optimization (no-loop & strided-loop).
if (canEmitGPUFusedDistSchedule(CGM, S, S.getDirectiveKind()) ||
- NoLoopKernel) {
+ IsPromotedLoopKernel) {
JumpDest LoopExit =
getJumpDestInCurrentScope(createBasicBlock("omp.loop.exit"));
CodeGenLoop(*this, S, LoopExit);
@@ -6775,12 +6780,14 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S,
}
}
if (isOpenMPSimdDirective(S.getDirectiveKind()) ||
- (NoLoopKernel && hasLoopLastprivateVariable(S, [&S](const Expr *E) {
- return isLoopCounter(S, E);
- }))) {
+ (IsPromotedLoopKernel &&
+ hasLoopLastprivateVariable(
+ S, [&S](const Expr *E) { return isLoopCounter(S, E); }))) {
EmitOMPSimdFinal(
- S, [IL, &S, NoLoopKernel](CodeGenFunction &CGF) -> llvm::Value * {
- if (NoLoopKernel)
+ S,
+ [IL, &S,
+ IsPromotedLoopKernel](CodeGenFunction &CGF) -> llvm::Value * {
+ if (IsPromotedLoopKernel)
return nullptr;
return CGF.Builder.CreateIsNotNull(
CGF.EmitLoadOfScalar(IL, S.getBeginLoc()));
@@ -9105,7 +9112,8 @@ emitTeamsGenericLoopAsDistributeParallelFor(CodeGenFunction &CGF,
void CodeGenFunction::EmitOMPTeamsGenericLoopDirective(
const OMPTeamsGenericLoopDirective &S) {
- if (CGM.getOpenMPRuntime().canPromoteToNoLoop(S)) {
+ if (CGM.getOpenMPRuntime().canPromoteToNoLoop(S) ||
+ CGM.getOpenMPRuntime().canPromoteToStridedLoop(S)) {
emitTeamsGenericLoopAsDistributeParallelFor(*this, S);
return;
}
diff --git a/clang/test/OpenMP/amdgcn_target_device_vla.cpp b/clang/test/OpenMP/amdgcn_target_device_vla.cpp
index 8b05f0aba04cec..3e6ae9ff4e61cc 100644
--- a/clang/test/OpenMP/amdgcn_target_device_vla.cpp
+++ b/clang/test/OpenMP/amdgcn_target_device_vla.cpp
@@ -208,7 +208,7 @@ int main() {
// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4
// CHECK-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
-// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined(ptr [[TMP6]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR5:[0-9]+]]
+// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined(ptr [[TMP6]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR8:[0-9]+]]
// CHECK-NEXT: call void @__kmpc_target_deinit()
// CHECK-NEXT: ret void
// CHECK: worker.exit:
@@ -276,100 +276,42 @@ int main() {
// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP7]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]]
-// CHECK-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK: cond.true:
-// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-NEXT: br label [[COND_END:%.*]]
-// CHECK: cond.false:
-// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: br label [[COND_END]]
-// CHECK: cond.end:
-// CHECK-NEXT: [[COND:%.*]] = phi i32 [ [[TMP10]], [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ]
-// CHECK-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK: omp.inner.for.cond:
-// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], 1
-// CHECK-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP13]], [[ADD]]
-// CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK: omp.inner.for.body:
-// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
-// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4
-// CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(5) [[M_CASTED]], align 4
-// CHECK-NEXT: [[TMP20:%.*]] = load i64, ptr addrspace(5) [[M_CASTED]], align 8
-// CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
-// CHECK-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP16]] to ptr
-// CHECK-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8
-// CHECK-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
-// CHECK-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr
-// CHECK-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8
-// CHECK-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
-// CHECK-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr
-// CHECK-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8
-// CHECK-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
-// CHECK-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP0]] to ptr
-// CHECK-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8
-// CHECK-NEXT: [[TMP29:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4
-// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP29]], align 8
-// CHECK-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
-// CHECK-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP31]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 5, i32 0)
-// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK: omp.inner.for.inc:
-// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP32]], [[TMP33]]
-// CHECK-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP34]], [[TMP35]]
-// CHECK-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP36]], [[TMP37]]
-// CHECK-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP38]], [[TMP39]]
-// CHECK-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK: cond.true10:
-// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-NEXT: br label [[COND_END12:%.*]]
-// CHECK: cond.false11:
-// CHECK-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: br label [[COND_END12]]
-// CHECK: cond.end12:
-// CHECK-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP40]], [[COND_TRUE10]] ], [ [[TMP41]], [[COND_FALSE11]] ]
-// CHECK-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-NEXT: store i32 [[TMP42]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK: omp.inner.for.end:
+// CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
+// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[M_ADDR_ASCAST]], align 4
+// CHECK-NEXT: store i32 [[TMP10]], ptr addrspace(5) [[M_CASTED]], align 4
+// CHECK-NEXT: [[TMP11:%.*]] = load i64, ptr addrspace(5) [[M_CASTED]], align 8
+// CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
+// CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP7]] to ptr
+// CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
+// CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
+// CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP9]] to ptr
+// CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
+// CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
+// CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP11]] to ptr
+// CHECK-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
+// CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
+// CHECK-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP0]] to ptr
+// CHECK-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8
+// CHECK-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4
+// CHECK-NEXT: store ptr [[TMP1]], ptr [[TMP20]], align 8
+// CHECK-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
+// CHECK-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP22]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 5, i32 0)
// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK: omp.loop.exit:
-// CHECK-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
-// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP44]])
// CHECK-NEXT: br label [[OMP_PRECOND_END]]
// CHECK: omp.precond.end:
// CHECK-NEXT: ret void
//
//
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined_omp_outlined
-// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[M:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[RESULT:%.*]]) #[[ATTR5:[0-9]+]] {
// CHECK-NEXT: entry:
+// CHECK-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, align 8, addrspace(5)
+// CHECK-NEXT: [[STRUCTARG_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[STRUCTARG]] to ptr
// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5)
@@ -382,16 +324,11 @@ int main() {
// CHECK-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-NEXT: [[I4:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[N:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[SAVED_STACK:%.*]] = alloca ptr addrspace(5), align 4, addrspace(5)
// CHECK-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8, addrspace(5)
// CHECK-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-NEXT: [[J11:%.*]] = alloca i32, align 4, addrspace(5)
+// CHECK-NEXT: [[J7:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
// CHECK-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
// CHECK-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr
@@ -404,16 +341,11 @@ int main() {
// CHECK-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr
// CHECK-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr
// CHECK-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
-// CHECK-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr
-// CHECK-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr
-// CHECK-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
-// CHECK-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
-// CHECK-NEXT: [[I4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I4]] to ptr
// CHECK-NEXT: [[N_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[N]] to ptr
// CHECK-NEXT: [[SAVED_STACK_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SAVED_STACK]] to ptr
// CHECK-NEXT: [[__VLA_EXPR0_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[__VLA_EXPR0]] to ptr
// CHECK-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr
-// CHECK-NEXT: [[J11_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J11]] to ptr
+// CHECK-NEXT: [[J7_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J7]] to ptr
// CHECK-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
@@ -430,116 +362,127 @@ int main() {
// CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-NEXT: store i32 0, ptr [[I_ASCAST]], align 4
-// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
-// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP4]]
-// CHECK-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK: omp.precond.then:
-// CHECK-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[CONV:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP7]] to i32
-// CHECK-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4
-// CHECK-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// CHECK-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
-// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP9]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
-// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
-// CHECK-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK: omp.inner.for.cond:
-// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: [[CONV5:%.*]] = sext i32 [[TMP11]] to i64
-// CHECK-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP12]]
-// CHECK-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK: omp.inner.for.body:
-// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP13]], 1
-// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-NEXT: store i32 [[ADD]], ptr [[I4_ASCAST]], align 4
-// CHECK-NEXT: store i32 10, ptr [[N_ASCAST]], align 4
-// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[N_ASCAST]], align 4
-// CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK-NEXT: [[TMP16:%.*]] = call ptr addrspace(5) @llvm.stacksave.p5()
-// CHECK-NEXT: store ptr addrspace(5) [[TMP16]], ptr [[SAVED_STACK_ASCAST]], align 4
-// CHECK-NEXT: [[VLA7:%.*]] = alloca i32, i64 [[TMP15]], align 4, addrspace(5)
-// CHECK-NEXT: [[VLA7_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA7]] to ptr
-// CHECK-NEXT: store i64 [[TMP15]], ptr [[__VLA_EXPR0_ASCAST]], align 8
-// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
-// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
-// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64
-// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM]]
-// CHECK-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX]], align 4
-// CHECK-NEXT: store i32 0, ptr [[J_ASCAST]], align 4
+// CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK: omp_loop.preheader:
+// CHECK-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 0
+// CHECK-NEXT: store ptr [[DOTOMP_IV_ASCAST]], ptr addrspace(5) [[GEP__OMP_IV_ASCAST]], align 8
+// CHECK-NEXT: [[GEP_I_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 1
+// CHECK-NEXT: store ptr [[I_ASCAST]], ptr addrspace(5) [[GEP_I_ASCAST]], align 8
+// CHECK-NEXT: [[GEP_N_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 2
+// CHECK-NEXT: store ptr [[N_ASCAST]], ptr addrspace(5) [[GEP_N_ASCAST]], align 8
+// CHECK-NEXT: [[GEP_SAVED_STACK_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 3
+// CHECK-NEXT: store ptr [[SAVED_STACK_ASCAST]], ptr addrspace(5) [[GEP_SAVED_STACK_ASCAST]], align 8
+// CHECK-NEXT: [[GEP___VLA_EXPR0_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 4
+// CHECK-NEXT: store ptr [[__VLA_EXPR0_ASCAST]], ptr addrspace(5) [[GEP___VLA_EXPR0_ASCAST]], align 8
+// CHECK-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 5
+// CHECK-NEXT: store ptr [[TMP1]], ptr addrspace(5) [[GEP_]], align 8
+// CHECK-NEXT: [[GEP_J_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 6
+// CHECK-NEXT: store ptr [[J_ASCAST]], ptr addrspace(5) [[GEP_J_ASCAST]], align 8
+// CHECK-NEXT: [[GEP_J7_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 7
+// CHECK-NEXT: store ptr [[J7_ASCAST]], ptr addrspace(5) [[GEP_J7_ASCAST]], align 8
+// CHECK-NEXT: [[TMP5:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG_ASCAST]], i32 [[ADD]], i32 [[TMP5]], i32 0, i32 0, i8 0)
+// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK: omp_loop.exit:
+// CHECK-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr))
+// CHECK-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+//
+//
+// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo2v_l30_omp_outlined_omp_outlined..omp_par
+// CHECK-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK-NEXT: omp_loop.body:
+// CHECK-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-NEXT: [[LOADGEP__OMP_IV_ASCAST:%.*]] = load ptr, ptr [[GEP__OMP_IV_ASCAST]], align 8, !align [[META9]]
+// CHECK-NEXT: [[GEP_I_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-NEXT: [[LOADGEP_I_ASCAST:%.*]] = load ptr, ptr [[GEP_I_ASCAST]], align 8, !align [[META9]]
+// CHECK-NEXT: [[GEP_N_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK-NEXT: [[LOADGEP_N_ASCAST:%.*]] = load ptr, ptr [[GEP_N_ASCAST]], align 8, !align [[META9]]
+// CHECK-NEXT: [[GEP_SAVED_STACK_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK-NEXT: [[LOADGEP_SAVED_STACK_ASCAST:%.*]] = load ptr, ptr [[GEP_SAVED_STACK_ASCAST]], align 8, !align [[META9]]
+// CHECK-NEXT: [[GEP___VLA_EXPR0_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 4
+// CHECK-NEXT: [[LOADGEP___VLA_EXPR0_ASCAST:%.*]] = load ptr, ptr [[GEP___VLA_EXPR0_ASCAST]], align 8, !align [[META13:![0-9]+]]
+// CHECK-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 5
+// CHECK-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META9]]
+// CHECK-NEXT: [[GEP_J_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 6
+// CHECK-NEXT: [[LOADGEP_J_ASCAST:%.*]] = load ptr, ptr [[GEP_J_ASCAST]], align 8, !align [[META9]]
+// CHECK-NEXT: [[GEP_J7_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 7
+// CHECK-NEXT: [[LOADGEP_J7_ASCAST:%.*]] = load ptr, ptr [[GEP_J7_ASCAST]], align 8, !align [[META9]]
+// CHECK-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I_ASCAST]], align 4
+// CHECK-NEXT: store i32 10, ptr [[LOADGEP_N_ASCAST]], align 4
+// CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_N_ASCAST]], align 4
+// CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK-NEXT: [[TMP5:%.*]] = call ptr addrspace(5) @llvm.stacksave.p5()
+// CHECK-NEXT: store ptr addrspace(5) [[TMP5]], ptr [[LOADGEP_SAVED_STACK_ASCAST]], align 4
+// CHECK-NEXT: [[VLA4:%.*]] = alloca i32, i64 [[TMP4]], align 4, addrspace(5)
+// CHECK-NEXT: [[VLA4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[VLA4]] to ptr
+// CHECK-NEXT: store i64 [[TMP4]], ptr [[LOADGEP___VLA_EXPR0_ASCAST]], align 8
+// CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I_ASCAST]], align 4
+// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[LOADGEP_I_ASCAST]], align 4
+// CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP7]] to i64
+// CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_]], i64 [[IDXPROM]]
+// CHECK-NEXT: store i32 [[TMP6]], ptr [[ARRAYIDX]], align 4
+// CHECK-NEXT: store i32 0, ptr [[LOADGEP_J_ASCAST]], align 4
// CHECK-NEXT: br label [[FOR_COND:%.*]]
// CHECK: for.cond:
-// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[N_ASCAST]], align 4
-// CHECK-NEXT: [[CMP8:%.*]] = icmp slt i32 [[TMP19]], [[TMP20]]
-// CHECK-NEXT: br i1 [[CMP8]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
-// CHECK: for.body:
-// CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// CHECK-NEXT: [[TMP22:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// CHECK-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP22]] to i64
-// CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[VLA7_ASCAST]], i64 [[IDXPROM9]]
-// CHECK-NEXT: store i32 [[TMP21]], ptr [[ARRAYIDX10]], align 4
-// CHECK-NEXT: br label [[FOR_INC:%.*]]
-// CHECK: for.inc:
-// CHECK-NEXT: [[TMP23:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP23]], 1
-// CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4
-// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]]
+// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[LOADGEP_N_ASCAST]], align 4
+// CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP8]], [[TMP9]]
+// CHECK-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
// CHECK: for.end:
-// CHECK-NEXT: store i32 0, ptr [[J11_ASCAST]], align 4
-// CHECK-NEXT: br label [[FOR_COND12:%.*]]
-// CHECK: for.cond12:
-// CHECK-NEXT: [[TMP24:%.*]] = load i32, ptr [[J11_ASCAST]], align 4
-// CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr [[N_ASCAST]], align 4
-// CHECK-NEXT: [[CMP13:%.*]] = icmp slt i32 [[TMP24]], [[TMP25]]
-// CHECK-NEXT: br i1 [[CMP13]], label [[FOR_BODY14:%.*]], label [[FOR_END22:%.*]]
-// CHECK: for.body14:
-// CHECK-NEXT: [[TMP26:%.*]] = load i32, ptr [[J11_ASCAST]], align 4
-// CHECK-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP26]] to i64
-// CHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds i32, ptr [[VLA7_ASCAST]], i64 [[IDXPROM15]]
-// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[ARRAYIDX16]], align 4
-// CHECK-NEXT: [[TMP28:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
-// CHECK-NEXT: [[IDXPROM17:%.*]] = sext i32 [[TMP28]] to i64
-// CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM17]]
-// CHECK-NEXT: [[TMP29:%.*]] = load i32, ptr [[ARRAYIDX18]], align 4
-// CHECK-NEXT: [[ADD19:%.*]] = add nsw i32 [[TMP29]], [[TMP27]]
-// CHECK-NEXT: store i32 [[ADD19]], ptr [[ARRAYIDX18]], align 4
-// CHECK-NEXT: br label [[FOR_INC20:%.*]]
-// CHECK: for.inc20:
-// CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr [[J11_ASCAST]], align 4
-// CHECK-NEXT: [[INC21:%.*]] = add nsw i32 [[TMP30]], 1
-// CHECK-NEXT: store i32 [[INC21]], ptr [[J11_ASCAST]], align 4
-// CHECK-NEXT: br label [[FOR_COND12]], !llvm.loop [[LOOP14:![0-9]+]]
-// CHECK: for.end22:
-// CHECK-NEXT: [[TMP31:%.*]] = load ptr addrspace(5), ptr [[SAVED_STACK_ASCAST]], align 4
-// CHECK-NEXT: call void @llvm.stackrestore.p5(ptr addrspace(5) [[TMP31]])
+// CHECK-NEXT: store i32 0, ptr [[LOADGEP_J7_ASCAST]], align 4
+// CHECK-NEXT: br label [[FOR_COND8:%.*]]
+// CHECK: for.cond8:
+// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[LOADGEP_J7_ASCAST]], align 4
+// CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[LOADGEP_N_ASCAST]], align 4
+// CHECK-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP10]], [[TMP11]]
+// CHECK-NEXT: br i1 [[CMP9]], label [[FOR_BODY10:%.*]], label [[FOR_END18:%.*]]
+// CHECK: for.end18:
+// CHECK-NEXT: [[TMP12:%.*]] = load ptr addrspace(5), ptr [[LOADGEP_SAVED_STACK_ASCAST]], align 4
+// CHECK-NEXT: call void @llvm.stackrestore.p5(ptr addrspace(5) [[TMP12]])
// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK: omp.body.continue:
-// CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK: omp.inner.for.inc:
-// CHECK-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP32]], [[TMP33]]
-// CHECK-NEXT: store i32 [[ADD23]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK: omp.inner.for.end:
-// CHECK-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK: omp.loop.exit:
-// CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-NEXT: [[TMP35:%.*]] = load i32, ptr [[TMP34]], align 4
-// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP35]])
-// CHECK-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK: omp.precond.end:
+// CHECK-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK: omp_loop.body.cont:
+// CHECK-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK: for.body10:
+// CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr [[LOADGEP_J7_ASCAST]], align 4
+// CHECK-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP13]] to i64
+// CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i32, ptr [[VLA4_ASCAST]], i64 [[IDXPROM11]]
+// CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[ARRAYIDX12]], align 4
+// CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr [[LOADGEP_I_ASCAST]], align 4
+// CHECK-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP15]] to i64
+// CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_]], i64 [[IDXPROM13]]
+// CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr [[ARRAYIDX14]], align 4
+// CHECK-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], [[TMP14]]
+// CHECK-NEXT: store i32 [[ADD15]], ptr [[ARRAYIDX14]], align 4
+// CHECK-NEXT: br label [[FOR_INC16:%.*]]
+// CHECK: for.inc16:
+// CHECK-NEXT: [[TMP17:%.*]] = load i32, ptr [[LOADGEP_J7_ASCAST]], align 4
+// CHECK-NEXT: [[INC17:%.*]] = add nsw i32 [[TMP17]], 1
+// CHECK-NEXT: store i32 [[INC17]], ptr [[LOADGEP_J7_ASCAST]], align 4
+// CHECK-NEXT: br label [[FOR_COND8]], !llvm.loop [[LOOP14:![0-9]+]]
+// CHECK: for.body:
+// CHECK-NEXT: [[TMP18:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// CHECK-NEXT: [[TMP19:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// CHECK-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64
+// CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i32, ptr [[VLA4_ASCAST]], i64 [[IDXPROM5]]
+// CHECK-NEXT: store i32 [[TMP18]], ptr [[ARRAYIDX6]], align 4
+// CHECK-NEXT: br label [[FOR_INC:%.*]]
+// CHECK: for.inc:
+// CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP20]], 1
+// CHECK-NEXT: store i32 [[INC]], ptr [[LOADGEP_J_ASCAST]], align 4
+// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK: omp.prelatch.exitStub:
// CHECK-NEXT: ret void
//
//
@@ -575,7 +518,7 @@ int main() {
// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4
// CHECK-NEXT: [[TMP6:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
-// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined(ptr [[TMP6]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR5]]
+// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined(ptr [[TMP6]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR8]]
// CHECK-NEXT: call void @__kmpc_target_deinit()
// CHECK-NEXT: ret void
// CHECK: worker.exit:
@@ -648,7 +591,7 @@ int main() {
// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// CHECK-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
+// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB4:[0-9]+]] to ptr), i32 [[TMP7]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
// CHECK-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP8]], [[TMP9]]
@@ -722,7 +665,7 @@ int main() {
// CHECK-NEXT: [[TMP36:%.*]] = load i32, ptr [[J_ASCAST]], align 4
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP36]], 1
// CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4
-// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]]
+// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
// CHECK: for.end:
// CHECK-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 [[TMP21]])
// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
@@ -738,7 +681,7 @@ int main() {
// CHECK: omp.loop.exit:
// CHECK-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
-// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP39]])
+// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[TMP39]])
// CHECK-NEXT: br label [[OMP_PRECOND_END]]
// CHECK: omp.precond.end:
// CHECK-NEXT: call void @__kmpc_free_shared(ptr [[N]], i64 4)
@@ -746,7 +689,7 @@ int main() {
//
//
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined_omp_outlined
-// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR6]] {
+// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR5]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
@@ -805,7 +748,7 @@ int main() {
// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
+// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB5:[0-9]+]] to ptr), i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
// CHECK-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK: omp.dispatch.cond:
// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
@@ -867,14 +810,14 @@ int main() {
// CHECK: omp.dispatch.end:
// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
-// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP27]])
+// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB5]] to ptr), i32 [[TMP27]])
// CHECK-NEXT: br label [[OMP_PRECOND_END]]
// CHECK: omp.precond.end:
// CHECK-NEXT: ret void
//
//
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined_omp_outlined_wrapper
-// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR9:[0-9]+]] {
+// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR11:[0-9]+]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5)
// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5)
@@ -895,7 +838,7 @@ int main() {
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8
// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 2
// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined_omp_outlined(ptr [[DOTADDR1_ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]]) #[[ATTR5]]
+// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo3v_l52_omp_outlined_omp_outlined(ptr [[DOTADDR1_ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]]) #[[ATTR8]]
// CHECK-NEXT: ret void
//
//
@@ -938,7 +881,7 @@ int main() {
// CHECK-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
// CHECK-NEXT: store i32 [[TMP3]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4
// CHECK-NEXT: [[TMP8:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
-// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined(ptr [[TMP8]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR5]]
+// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined(ptr [[TMP8]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP5]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]]) #[[ATTR8]]
// CHECK-NEXT: call void @__kmpc_target_deinit()
// CHECK-NEXT: ret void
// CHECK: worker.exit:
@@ -1016,7 +959,7 @@ int main() {
// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
+// CHECK-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[TMP8]], i32 92, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
// CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_2_ASCAST]], align 4
// CHECK-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]]
@@ -1089,7 +1032,7 @@ int main() {
// CHECK-NEXT: [[TMP37:%.*]] = load i32, ptr [[J_ASCAST]], align 4
// CHECK-NEXT: [[INC:%.*]] = add nsw i32 [[TMP37]], 1
// CHECK-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4
-// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP16:![0-9]+]]
+// CHECK-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP17:![0-9]+]]
// CHECK: for.end:
// CHECK-NEXT: call void @__kmpc_free_shared(ptr [[A]], i64 [[TMP22]])
// CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
@@ -1105,7 +1048,7 @@ int main() {
// CHECK: omp.loop.exit:
// CHECK-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4
-// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP40]])
+// CHECK-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[TMP40]])
// CHECK-NEXT: br label [[OMP_PRECOND_END]]
// CHECK: omp.precond.end:
// CHECK-NEXT: call void @__kmpc_free_shared(ptr [[N1]], i64 4)
@@ -1113,7 +1056,7 @@ int main() {
//
//
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined_omp_outlined
-// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR6]] {
+// CHECK-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]]) #[[ATTR5]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
@@ -1172,7 +1115,7 @@ int main() {
// CHECK-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// CHECK-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
+// CHECK-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB5]] to ptr), i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
// CHECK-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK: omp.dispatch.cond:
// CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB_ASCAST]], align 4
@@ -1234,14 +1177,14 @@ int main() {
// CHECK: omp.dispatch.end:
// CHECK-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
-// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP27]])
+// CHECK-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB5]] to ptr), i32 [[TMP27]])
// CHECK-NEXT: br label [[OMP_PRECOND_END]]
// CHECK: omp.precond.end:
// CHECK-NEXT: ret void
//
//
// CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined_omp_outlined_wrapper
-// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR9]] {
+// CHECK-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR11]] {
// CHECK-NEXT: entry:
// CHECK-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2, addrspace(5)
// CHECK-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4, addrspace(5)
@@ -1262,6 +1205,6 @@ int main() {
// CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[TMP5]], align 8
// CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr, ptr [[TMP2]], i64 2
// CHECK-NEXT: [[TMP8:%.*]] = load ptr, ptr [[TMP7]], align 8
-// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined_omp_outlined(ptr [[DOTADDR1_ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]]) #[[ATTR5]]
+// CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z4foo4v_l76_omp_outlined_omp_outlined(ptr [[DOTADDR1_ASCAST]], ptr [[DOTZERO_ADDR_ASCAST]], ptr [[TMP4]], i64 [[TMP6]], ptr [[TMP8]]) #[[ATTR8]]
// CHECK-NEXT: ret void
//
diff --git a/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c b/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
index 1a641a118e2cdc..d831e05cda936d 100644
--- a/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
+++ b/clang/test/OpenMP/amdgpu_target_with_aligned_attribute.c
@@ -46,7 +46,7 @@ void write_to_aligned_array(int *a, int N) {
// CHECK-AMD-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
// CHECK-AMD-NEXT: store i32 [[TMP1]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4
// CHECK-AMD-NEXT: [[TMP5:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
-// CHECK-AMD-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined(ptr [[TMP5]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP3]], ptr [[TMP4]]) #[[ATTR2:[0-9]+]]
+// CHECK-AMD-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined(ptr [[TMP5]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP3]], ptr [[TMP4]]) #[[ATTR4:[0-9]+]]
// CHECK-AMD-NEXT: call void @__kmpc_target_deinit()
// CHECK-AMD-NEXT: ret void
// CHECK-AMD: worker.exit:
@@ -109,98 +109,40 @@ void write_to_aligned_array(int *a, int N) {
// CHECK-AMD-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// CHECK-AMD-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-AMD-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-AMD-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP5]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-AMD-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
// CHECK-AMD-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP6]], [[TMP7]]
-// CHECK-AMD-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-AMD: cond.true:
-// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[COND_END:%.*]]
-// CHECK-AMD: cond.false:
-// CHECK-AMD-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[COND_END]]
-// CHECK-AMD: cond.end:
-// CHECK-AMD-NEXT: [[COND:%.*]] = phi i32 [ [[TMP8]], [[COND_TRUE]] ], [ [[TMP9]], [[COND_FALSE]] ]
-// CHECK-AMD-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 [[TMP10]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-AMD: omp.inner.for.cond:
-// CHECK-AMD-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 1
-// CHECK-AMD-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP11]], [[ADD]]
-// CHECK-AMD-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-AMD: omp.inner.for.body:
-// CHECK-AMD-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP14:%.*]] = zext i32 [[TMP13]] to i64
-// CHECK-AMD-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
-// CHECK-AMD-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 [[TMP17]], ptr addrspace(5) [[N_CASTED]], align 4
-// CHECK-AMD-NEXT: [[TMP18:%.*]] = load i64, ptr addrspace(5) [[N_CASTED]], align 8
-// CHECK-AMD-NEXT: [[TMP19:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
-// CHECK-AMD-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP14]] to ptr
-// CHECK-AMD-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
-// CHECK-AMD-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
-// CHECK-AMD-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP16]] to ptr
-// CHECK-AMD-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8
-// CHECK-AMD-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
-// CHECK-AMD-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP18]] to ptr
-// CHECK-AMD-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8
-// CHECK-AMD-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
-// CHECK-AMD-NEXT: store ptr [[TMP19]], ptr [[TMP26]], align 8
-// CHECK-AMD-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK-AMD-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4, i32 0)
-// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-AMD: omp.inner.for.inc:
-// CHECK-AMD-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK-AMD-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK-AMD-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK-AMD-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK-AMD-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK-AMD: cond.true10:
-// CHECK-AMD-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[COND_END12:%.*]]
-// CHECK-AMD: cond.false11:
-// CHECK-AMD-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[COND_END12]]
-// CHECK-AMD: cond.end12:
-// CHECK-AMD-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK-AMD-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-AMD: omp.inner.for.end:
+// CHECK-AMD-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
+// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
+// CHECK-AMD-NEXT: store i32 [[TMP8]], ptr addrspace(5) [[N_CASTED]], align 4
+// CHECK-AMD-NEXT: [[TMP9:%.*]] = load i64, ptr addrspace(5) [[N_CASTED]], align 8
+// CHECK-AMD-NEXT: [[TMP10:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
+// CHECK-AMD-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP5]] to ptr
+// CHECK-AMD-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
+// CHECK-AMD-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
+// CHECK-AMD-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP7]] to ptr
+// CHECK-AMD-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
+// CHECK-AMD-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
+// CHECK-AMD-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP9]] to ptr
+// CHECK-AMD-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
+// CHECK-AMD-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
+// CHECK-AMD-NEXT: store ptr [[TMP10]], ptr [[TMP17]], align 8
+// CHECK-AMD-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK-AMD-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 4, i32 0)
// CHECK-AMD-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-AMD: omp.loop.exit:
-// CHECK-AMD-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK-AMD-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP41]])
// CHECK-AMD-NEXT: br label [[OMP_PRECOND_END]]
// CHECK-AMD: omp.precond.end:
// CHECK-AMD-NEXT: ret void
//
//
// CHECK-AMD-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined_omp_outlined
-// CHECK-AMD-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK-AMD-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef [[APTR:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK-AMD-NEXT: entry:
+// CHECK-AMD-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8, addrspace(5)
+// CHECK-AMD-NEXT: [[STRUCTARG_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[STRUCTARG]] to ptr
// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// CHECK-AMD-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5)
@@ -212,11 +154,6 @@ void write_to_aligned_array(int *a, int N) {
// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-AMD-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-AMD-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-AMD-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-AMD-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
-// CHECK-AMD-NEXT: [[I4:%.*]] = alloca i32, align 4, addrspace(5)
// CHECK-AMD-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
// CHECK-AMD-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
// CHECK-AMD-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr
@@ -228,11 +165,6 @@ void write_to_aligned_array(int *a, int N) {
// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr
// CHECK-AMD-NEXT: [[DOTCAPTURE_EXPR_1_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_1]] to ptr
// CHECK-AMD-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
-// CHECK-AMD-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr
-// CHECK-AMD-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr
-// CHECK-AMD-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
-// CHECK-AMD-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
-// CHECK-AMD-NEXT: [[I4_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I4]] to ptr
// CHECK-AMD-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// CHECK-AMD-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
// CHECK-AMD-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
@@ -246,61 +178,52 @@ void write_to_aligned_array(int *a, int N) {
// CHECK-AMD-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK-AMD-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK-AMD-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 0, ptr [[I_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
-// CHECK-AMD-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP2]]
-// CHECK-AMD-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK-AMD: omp.precond.then:
-// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[CONV:%.*]] = trunc i64 [[TMP4]] to i32
-// CHECK-AMD-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK-AMD-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
-// CHECK-AMD-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP7]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
-// CHECK-AMD-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
-// CHECK-AMD-NEXT: store i32 [[TMP8]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-AMD: omp.inner.for.cond:
-// CHECK-AMD-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[CONV5:%.*]] = sext i32 [[TMP9]] to i64
-// CHECK-AMD-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP10]]
-// CHECK-AMD-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-AMD: omp.inner.for.body:
-// CHECK-AMD-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 1
-// CHECK-AMD-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-AMD-NEXT: store i32 [[ADD]], ptr [[I4_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP12:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP13:%.*]] = load ptr, ptr [[APTR_ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[TMP14:%.*]] = load i32, ptr [[I4_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
-// CHECK-AMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK-AMD-NEXT: store i32 [[TMP12]], ptr [[ARRAYIDX]], align 4
+// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], 1
+// CHECK-AMD-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-AMD: omp_loop.preheader:
+// CHECK-AMD-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 0
+// CHECK-AMD-NEXT: store ptr [[DOTOMP_IV_ASCAST]], ptr addrspace(5) [[GEP__OMP_IV_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[GEP_I_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 1
+// CHECK-AMD-NEXT: store ptr [[I_ASCAST]], ptr addrspace(5) [[GEP_I_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[GEP_APTR_ADDR_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 2
+// CHECK-AMD-NEXT: store ptr [[APTR_ADDR_ASCAST]], ptr addrspace(5) [[GEP_APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP3:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-AMD-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG_ASCAST]], i32 [[ADD]], i32 [[TMP3]], i32 0, i32 0, i8 0)
+// CHECK-AMD-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-AMD: omp_loop.exit:
+// CHECK-AMD-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr))
+// CHECK-AMD-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-AMD-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-AMD: omp_loop.after:
+// CHECK-AMD-NEXT: ret void
+//
+//
+// CHECK-AMD-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_write_to_aligned_array_l14_omp_outlined_omp_outlined..omp_par
+// CHECK-AMD-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK-AMD-NEXT: omp_loop.body:
+// CHECK-AMD-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-AMD-NEXT: [[LOADGEP__OMP_IV_ASCAST:%.*]] = load ptr, ptr [[GEP__OMP_IV_ASCAST]], align 8, !align [[META5:![0-9]+]]
+// CHECK-AMD-NEXT: [[GEP_I_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-AMD-NEXT: [[LOADGEP_I_ASCAST:%.*]] = load ptr, ptr [[GEP_I_ASCAST]], align 8, !align [[META5]]
+// CHECK-AMD-NEXT: [[GEP_APTR_ADDR_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK-AMD-NEXT: [[LOADGEP_APTR_ADDR_ASCAST:%.*]] = load ptr, ptr [[GEP_APTR_ADDR_ASCAST]], align 8, !align [[META6:![0-9]+]]
+// CHECK-AMD-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-AMD-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-AMD-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[TMP4:%.*]] = load ptr, ptr [[LOADGEP_APTR_ADDR_ASCAST]], align 8
+// CHECK-AMD-NEXT: [[TMP5:%.*]] = load i32, ptr [[LOADGEP_I_ASCAST]], align 4
+// CHECK-AMD-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP5]] to i64
+// CHECK-AMD-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[IDXPROM]]
+// CHECK-AMD-NEXT: store i32 [[TMP3]], ptr [[ARRAYIDX]], align 4
// CHECK-AMD-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-AMD: omp.body.continue:
-// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-AMD: omp.inner.for.inc:
-// CHECK-AMD-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// CHECK-AMD-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK-AMD-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// CHECK-AMD-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-AMD: omp.inner.for.end:
-// CHECK-AMD-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-AMD: omp.loop.exit:
-// CHECK-AMD-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// CHECK-AMD-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK-AMD-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP18]])
-// CHECK-AMD-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK-AMD: omp.precond.end:
+// CHECK-AMD-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-AMD: omp_loop.body.cont:
+// CHECK-AMD-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-AMD: omp.prelatch.exitStub:
// CHECK-AMD-NEXT: ret void
//
diff --git a/clang/test/OpenMP/metadirective_device_arch_codegen.cpp b/clang/test/OpenMP/metadirective_device_arch_codegen.cpp
index 4f89767f29a6b4..af05a8314131c4 100644
--- a/clang/test/OpenMP/metadirective_device_arch_codegen.cpp
+++ b/clang/test/OpenMP/metadirective_device_arch_codegen.cpp
@@ -53,18 +53,17 @@ int metadirective1() {
// CHECK: ret void
-// CHECK: define internal {{(spir_func )?}}void @[[METADIRECTIVE]]_omp_outlined
+// CHECK: define internal {{(spir_func )?}}void @[[METADIRECTIVE]]_omp_outlined(
// CHECK: entry:
-// CHECK: call{{.*}} void @__kmpc_distribute_static_init
-// CHECK: omp.loop.exit:
-// CHECK: call{{.*}} void @__kmpc_distribute_static_fini
+// CHECK: call{{.*}} void @__kmpc_parallel_60
+// CHECK: ret void
-// CHECK: define internal {{(spir_func )?}}void @[[METADIRECTIVE]]_omp_outlined_omp_outlined
+// CHECK: define internal {{(spir_func )?}}void @[[METADIRECTIVE]]_omp_outlined_omp_outlined(
// CHECK: entry:
-// CHECK: call{{.*}} void @__kmpc_for_static_init_4
-// CHECK: omp.inner.for.body:
+// CHECK: call{{.*}} void @__kmpc_distribute_for_static_loop_4u({{.*}}@[[METADIRECTIVE]]_omp_outlined_omp_outlined..omp_par
+// CHECK: ret void
+
+// CHECK: define internal {{(spir_func )?}}void @[[METADIRECTIVE]]_omp_outlined_omp_outlined..omp_par
// CHECK: store atomic {{.*}} monotonic
-// CHECK: omp.loop.exit:
-// CHECK-NEXT: call{{.*}} void @__kmpc_for_static_fini
-// CHECK-NEXT: ret void
+// CHECK: ret void
diff --git a/clang/test/OpenMP/nvptx_SPMD_codegen.cpp b/clang/test/OpenMP/nvptx_SPMD_codegen.cpp
index d15539a4712130..6e3bdef348bad9 100644
--- a/clang/test/OpenMP/nvptx_SPMD_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_SPMD_codegen.cpp
@@ -925,146 +925,75 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86:![0-9]+]]
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP87:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
-// CHECK-64-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
// CHECK-64-NEXT: ret void
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89:![0-9]+]]
-// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP89]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86:![0-9]+]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP89]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP90:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
-// CHECK-64-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
@@ -1109,154 +1038,75 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92:![0-9]+]]
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP93:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
-// CHECK-64-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
// CHECK-64-NEXT: ret void
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP95]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP96:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-64-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
@@ -1319,49 +1169,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87:![0-9]+]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-64: cond.true5:
// CHECK-64-NEXT: br label [[COND_END7:%.*]]
// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-64-NEXT: br label [[COND_END7]]
// CHECK-64: cond.end7:
// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP99:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP88:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -1419,23 +1269,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP102:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP91:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -1511,49 +1361,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93:![0-9]+]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-64: cond.true5:
// CHECK-64-NEXT: br label [[COND_END7:%.*]]
// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-64-NEXT: br label [[COND_END7]]
// CHECK-64: cond.end7:
// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP105:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP94:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -1611,23 +1461,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP108:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP97:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -1703,49 +1553,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99:![0-9]+]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-64: cond.true5:
// CHECK-64-NEXT: br label [[COND_END7:%.*]]
// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-64-NEXT: br label [[COND_END7]]
// CHECK-64: cond.end7:
// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP111:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP100:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -1803,23 +1653,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP114:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP103:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -1887,85 +1737,27 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-64-NEXT: store i32 [[TMP10]], ptr [[A_CASTED]], align 4
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i64, ptr [[A_CASTED]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
-// CHECK-64-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK-64-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP11]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
-// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 9
-// CHECK-64-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
-// CHECK-64: cond.true6:
-// CHECK-64-NEXT: br label [[COND_END8:%.*]]
-// CHECK-64: cond.false7:
-// CHECK-64-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END8]]
-// CHECK-64: cond.end8:
-// CHECK-64-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ]
-// CHECK-64-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[A_CASTED]], align 4
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i64, ptr [[A_CASTED]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP9:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 8
+// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP5]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
+// CHECK-64-NEXT: [[TMP12:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP12]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
-// CHECK-64-NEXT: br i1 [[TMP28]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
-// CHECK-64: .omp.lastprivate.then:
-// CHECK-64-NEXT: [[TMP29:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-64-NEXT: store i32 [[TMP29]], ptr [[A_ADDR]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
-// CHECK-64: .omp.lastprivate.done:
// CHECK-64-NEXT: call void @__kmpc_free_shared(ptr [[A1]], i64 4)
// CHECK-64-NEXT: ret void
//
@@ -1973,6 +1765,7 @@ int a;
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -1980,70 +1773,74 @@ int a;
// CHECK-64-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[A2:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[A1:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[A]], ptr [[A_ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CONV3:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
-// CHECK-64-NEXT: store i32 [[TMP8]], ptr [[A2]], align 4
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
-// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: store i32 0, ptr [[P_LASTITER]], align 4
+// CHECK-64-NEXT: [[GEP_P_LASTITER:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[P_LASTITER]], ptr [[GEP_P_LASTITER]], align 8
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[GEP_A1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK-64-NEXT: store ptr [[A1]], ptr [[GEP_A1]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
-// CHECK-64-NEXT: br i1 [[TMP12]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = load i32, ptr [[P_LASTITER]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = icmp ne i32 [[DOTOMP_IS_LAST]], 0
+// CHECK-64-NEXT: br i1 [[TMP1]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK-64: .omp.lastprivate.then:
-// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[A2]], align 4
-// CHECK-64-NEXT: store i32 [[TMP13]], ptr [[A_ADDR]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[A1]], align 4
+// CHECK-64-NEXT: store i32 [[TMP2]], ptr [[A_ADDR]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK-64: .omp.lastprivate.done:
// CHECK-64-NEXT: ret void
//
//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP_P_LASTITER:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP_P_LASTITER:%.*]] = load ptr, ptr [[GEP_P_LASTITER]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_A1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK-64-NEXT: [[LOADGEP_A1:%.*]] = load ptr, ptr [[GEP_A1]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[OMP_IS_LAST_ITER:%.*]] = icmp eq i32 [[TMP0]], 9
+// CHECK-64-NEXT: [[TMP2:%.*]] = zext i1 [[OMP_IS_LAST_ITER]] to i32
+// CHECK-64-NEXT: store i32 [[TMP2]], ptr [[LOADGEP_P_LASTITER]], align 4
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[LOADGEP_A1]], align 4
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
+// CHECK-64-NEXT: ret void
+//
+//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
@@ -2264,132 +2061,74 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
@@ -2434,140 +2173,74 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP116]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP117:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
@@ -2723,23 +2396,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP120:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP106:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -2901,23 +2574,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP123:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP109:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -3079,23 +2752,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP126:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP112:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -3147,146 +2820,75 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128:![0-9]+]]
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP129:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
-// CHECK-64-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
// CHECK-64-NEXT: ret void
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131:![0-9]+]]
-// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP131]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP131]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP132:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
-// CHECK-64-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
@@ -3351,49 +2953,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114:![0-9]+]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l66_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l66_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-64: cond.true5:
// CHECK-64-NEXT: br label [[COND_END7:%.*]]
// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-64-NEXT: br label [[COND_END7]]
// CHECK-64: cond.end7:
// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP135:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP115:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -3454,23 +3056,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137:![0-9]+]]
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117:![0-9]+]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP138:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP118:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -3486,7 +3088,7 @@ int a;
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7:[0-9]+]] {
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR10:[0-9]+]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
@@ -3545,29 +3147,29 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140:![0-9]+]]
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120:![0-9]+]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-64-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-64-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
// CHECK-64-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP140]]
+// CHECK-64-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP120]]
// CHECK-64-NEXT: [[TMP13:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP140]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP140]]
+// CHECK-64-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP120]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP120]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP141:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP121:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -3620,25 +3222,25 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123:![0-9]+]]
// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP143]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP123]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP144:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP124:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -3654,7 +3256,7 @@ int a;
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper
-// CHECK-64-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] {
+// CHECK-64-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR11:[0-9]+]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
// CHECK-64-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
@@ -3714,154 +3316,75 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146:![0-9]+]]
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP147:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
-// CHECK-64-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
// CHECK-64-NEXT: ret void
//
//
// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP149]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP150:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-64-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
@@ -3924,49 +3447,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126:![0-9]+]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l85_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l85_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-64: cond.true5:
// CHECK-64-NEXT: br label [[COND_END7:%.*]]
// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-64-NEXT: br label [[COND_END7]]
// CHECK-64: cond.end7:
// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP153:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP127:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -4024,23 +3547,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP156:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP130:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -4116,49 +3639,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132:![0-9]+]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l89_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l89_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-64: cond.true5:
// CHECK-64-NEXT: br label [[COND_END7:%.*]]
// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-64-NEXT: br label [[COND_END7]]
// CHECK-64: cond.end7:
// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP159:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP133:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -4216,23 +3739,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP162:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP136:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -4308,49 +3831,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138:![0-9]+]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l93_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l93_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0), !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-64: cond.true5:
// CHECK-64-NEXT: br label [[COND_END7:%.*]]
// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-64-NEXT: br label [[COND_END7]]
// CHECK-64: cond.end7:
// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP165:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP139:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -4408,23 +3931,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP168:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP142:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -4482,6 +4005,118 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp.loop.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-64: user_code.entry:
+// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @__kmpc_target_deinit()
+// CHECK-64-NEXT: ret void
+// CHECK-64: worker.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
@@ -4514,7 +4149,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -4550,7 +4185,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -4580,28 +4215,37 @@ int a;
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
+// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK-64: cond.true:
+// CHECK-64-NEXT: br label [[COND_END:%.*]]
+// CHECK-64: cond.false:
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: br label [[COND_END]]
+// CHECK-64: cond.end:
+// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
+// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
+// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64: omp.inner.for.body:
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
@@ -4611,28 +4255,252 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp.loop.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-64: user_code.entry:
+// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @__kmpc_target_deinit()
+// CHECK-64-NEXT: ret void
+// CHECK-64: worker.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp.loop.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-64: user_code.entry:
+// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @__kmpc_target_deinit()
+// CHECK-64-NEXT: ret void
+// CHECK-64: worker.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -4684,7 +4552,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -4720,7 +4588,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l101_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -4748,70 +4616,69 @@ int a;
// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741861, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
-// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP144]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
+// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP145:![0-9]+]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -4863,7 +4730,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -4899,7 +4766,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -4927,61 +4794,69 @@ int a;
// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741859, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP147]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP148:![0-9]+]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5033,7 +4908,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -5069,7 +4944,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5101,7 +4976,7 @@ int a;
// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741860, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK-64: omp.dispatch.cond:
// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
@@ -5112,23 +4987,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP170]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP170]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP171:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP151:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -5138,28 +5013,28 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5179,165 +5054,99 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l113_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741861, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP173]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP174:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5389,7 +5198,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -5425,7 +5234,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l117_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5453,69 +5262,70 @@ int a;
// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741859, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
+// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK-64: cond.true:
+// CHECK-64-NEXT: br label [[COND_END:%.*]]
+// CHECK-64: cond.false:
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: br label [[COND_END]]
+// CHECK-64: cond.end:
+// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
+// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP176]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
+// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP177:![0-9]+]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp.loop.exit:
+// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5535,165 +5345,211 @@ int a;
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l121_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-64: user_code.entry:
+// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @__kmpc_target_deinit()
+// CHECK-64-NEXT: ret void
+// CHECK-64: worker.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741860, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP179]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-64-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i32 [[TMP2]] to i64
+// CHECK-64-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK-64-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP1]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 8
+// CHECK-64-NEXT: [[TMP6:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP3]] to ptr
+// CHECK-64-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 8
+// CHECK-64-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp.loop.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
+// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
+// CHECK-64-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-64: omp_loop.preheader:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-64-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-64-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-64-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp_loop.exit:
+// CHECK-64-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-64: omp_loop.after:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined..omp_par
+// CHECK-64-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-64-NEXT: omp_loop.body:
+// CHECK-64-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-64-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META86]]
+// CHECK-64-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-64-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META86]]
+// CHECK-64-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP180:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-64: omp_loop.body.cont:
+// CHECK-64-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-64: omp.prelatch.exitStub:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5745,7 +5601,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -5781,7 +5637,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5809,61 +5665,69 @@ int a;
// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741861, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP153]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP154:![0-9]+]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5915,7 +5779,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -5951,7 +5815,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l130_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -5979,70 +5843,69 @@ int a;
// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741859, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
-// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP156]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
+// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP157:![0-9]+]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155
// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -6094,7 +5957,7 @@ int a;
// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -6130,7 +5993,7 @@ int a;
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -6158,155 +6021,170 @@ int a;
// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741860, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CONV2:%.*]] = sext i32 [[TMP5]] to i64
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP6]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159:![0-9]+]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP159]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP160:![0-9]+]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160
+// CHECK-64-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12:[0-9]+]] {
// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
+// CHECK-64-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
+// CHECK-64-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
+// CHECK-64-NEXT: [[TMP3:%.*]] = zext i1 [[LOADEDV]] to i32
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP3]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK-64: cond.true:
// CHECK-64-NEXT: br label [[COND_END:%.*]]
// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: br label [[COND_END]]
// CHECK-64: cond.end:
// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
+// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
+// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
+// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
+// CHECK-64-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
+// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-64: user_code.entry:
+// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_target_deinit()
+// CHECK-64-NEXT: ret void
+// CHECK-64: worker.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
@@ -6316,175 +6194,170 @@ int a;
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
+// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
+// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK-64: cond.true:
+// CHECK-64-NEXT: br label [[COND_END:%.*]]
+// CHECK-64: cond.false:
// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: br label [[COND_END]]
+// CHECK-64: cond.end:
+// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
+// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
+// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP182]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP183:![0-9]+]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-64: omp.loop.exit:
+// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
// CHECK-64: cond.true:
// CHECK-64-NEXT: br label [[COND_END:%.*]]
// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: br label [[COND_END]]
// CHECK-64: cond.end:
// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
+// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
+// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
+// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
+// CHECK-64-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l145_omp_outlined_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
+// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-64: user_code.entry:
+// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_target_deinit()
+// CHECK-64-NEXT: ret void
+// CHECK-64: worker.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
@@ -6494,175 +6367,147 @@ int a;
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741861, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741862, i32 0, i32 9, i32 1, i32 1)
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP185]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP162]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP186:![0-9]+]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
+// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP163:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741861, i32 0, i32 9, i32 1, i32 1)
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-64: omp.dispatch.cond:
+// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64: omp.dispatch.body:
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP165]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
+// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP165]]
+// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
+// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP166:![0-9]+]]
// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-64: omp.dispatch.end:
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l150_omp_outlined_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
+// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-64: user_code.entry:
+// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_target_deinit()
+// CHECK-64-NEXT: ret void
+// CHECK-64: worker.exit:
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
@@ -6672,175 +6517,72 @@ int a;
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741859, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741859, i32 0, i32 9, i32 1, i32 1)
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP188]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP168]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP189:![0-9]+]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
+// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP169:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-64-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-64-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP7:%.*]] = zext i32 [[TMP6]] to i64
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
-// CHECK-64-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK-64-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP7]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 8
-// CHECK-64-NEXT: [[TMP12:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK-64-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP9]] to ptr
-// CHECK-64-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 2, i32 0)
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK-64-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-64: cond.true5:
-// CHECK-64-NEXT: br label [[COND_END7:%.*]]
-// CHECK-64: cond.false6:
-// CHECK-64-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END7]]
-// CHECK-64: cond.end7:
-// CHECK-64-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK-64-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-64-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l155_omp_outlined_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178_omp_outlined
+// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
-// CHECK-64-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
@@ -6850,68 +6592,58 @@ int a;
// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV:%.*]] = trunc i64 [[TMP0]] to i32
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK-64-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK-64-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741860, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741860, i32 0, i32 9, i32 1, i32 1)
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191:![0-9]+]]
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP191]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP171]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP192:![0-9]+]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
+// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP172:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160
-// CHECK-64-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9:[0-9]+]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181
+// CHECK-64-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
@@ -6919,14 +6651,14 @@ int a;
// CHECK-64-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
// CHECK-64-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
// CHECK-64-NEXT: [[TMP3:%.*]] = zext i1 [[LOADEDV]] to i32
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP3]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP3]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -6969,23 +6701,23 @@ int a;
// CHECK-64: omp.dispatch.body:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174:![0-9]+]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP175:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -7000,28 +6732,36 @@ int a;
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
+// CHECK-64-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64: .omp.final.then:
+// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7057,49 +6797,57 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177:![0-9]+]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP178:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
+// CHECK-64-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64: .omp.final.then:
+// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7142,23 +6890,23 @@ int a;
// CHECK-64: omp.dispatch.body:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180:![0-9]+]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP181:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -7173,28 +6921,36 @@ int a;
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
+// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
+// CHECK-64-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64: .omp.final.then:
+// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
+// CHECK-64-NEXT: ret void
+//
+//
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
+// CHECK-64-NEXT: entry:
+// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7225,51 +6981,59 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP195:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP184:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
+// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64: .omp.final.then:
+// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7300,51 +7064,59 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP198:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP187:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
+// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64: .omp.final.then:
+// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7375,51 +7147,59 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP201:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP190:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
+// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64: .omp.final.then:
+// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7450,56 +7230,59 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP204:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP193:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
+// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64: .omp.final.then:
+// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-64: .omp.final.done:
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181
-// CHECK-64-SAME: (i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13:[0-9]+]] {
// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
-// CHECK-64-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
-// CHECK-64-NEXT: [[TMP3:%.*]] = zext i1 [[LOADEDV]] to i32
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP3]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7519,90 +7302,71 @@ int a;
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 65, i32 0, i32 9, i32 1, i32 1)
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
+// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
// CHECK-64: omp.dispatch.body:
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206:![0-9]+]]
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP206]]
-// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
-// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP195]]
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
+// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP207:![0-9]+]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
+// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
+// CHECK-64-NEXT: call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP1]]), !llvm.access.group [[ACC_GRP195]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP196:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
-// CHECK-64-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
-// CHECK-64-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
+// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK-64: .omp.final.then:
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7638,23 +7402,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209:![0-9]+]]
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198:![0-9]+]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP210:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP199:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
@@ -7666,29 +7430,29 @@ int a;
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7731,23 +7495,23 @@ int a;
// CHECK-64: omp.dispatch.body:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212:![0-9]+]]
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201:![0-9]+]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP213:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP202:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -7769,29 +7533,29 @@ int a;
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7822,23 +7586,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP216:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP205:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -7852,29 +7616,29 @@ int a;
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7905,23 +7669,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP219:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP208:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -7935,29 +7699,29 @@ int a;
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -7988,23 +7752,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP222:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP211:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -8018,29 +7782,29 @@ int a;
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8071,23 +7835,23 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP225:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP214:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -8101,29 +7865,29 @@ int a;
// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11:[0-9]+]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8143,71 +7907,82 @@ int a;
// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 65, i32 0, i32 9, i32 1, i32 1)
+// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
+// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK-64: cond.true:
+// CHECK-64-NEXT: br label [[COND_END:%.*]]
+// CHECK-64: cond.false:
+// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: br label [[COND_END]]
+// CHECK-64: cond.end:
+// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
+// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
+// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP227]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
+// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
-// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
-// CHECK-64-NEXT: call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP1]]), !llvm.access.group [[ACC_GRP227]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP228:![0-9]+]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
+// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
+// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
+// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-64-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
+// CHECK-64-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
-// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8243,57 +8018,49 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230:![0-9]+]]
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP231:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-64: omp.loop.exit:
// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
-// CHECK-64-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8336,23 +8103,23 @@ int a;
// CHECK-64: omp.dispatch.body:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233:![0-9]+]]
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP234:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
@@ -8367,36 +8134,28 @@ int a;
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0
-// CHECK-64-NEXT: br i1 [[TMP16]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8427,59 +8186,51 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP237:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP217:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
-// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8510,59 +8261,51 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP240:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP220:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
-// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8593,59 +8336,51 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP243:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP223:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
-// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268
+// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268_kernel_environment, ptr [[DYN_PTR]])
// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-64: user_code.entry:
// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
+// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
// CHECK-64-NEXT: call void @__kmpc_target_deinit()
// CHECK-64-NEXT: ret void
// CHECK-64: worker.exit:
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239_omp_outlined
+// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268_omp_outlined
// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
// CHECK-64-NEXT: entry:
// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -8676,1051 +8411,81 @@ int a;
// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225:![0-9]+]]
+// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-64: omp.body.continue:
// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP246:![0-9]+]]
+// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
+// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP226:![0-9]+]]
// CHECK-64: omp.inner.for.end:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-64: omp.dispatch.inc:
// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
// CHECK-64: omp.dispatch.end:
// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0
-// CHECK-64-NEXT: br i1 [[TMP9]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-64: .omp.final.then:
-// CHECK-64-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-64: .omp.final.done:
-// CHECK-64-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
-// CHECK-64-NEXT: call void @__kmpc_target_deinit()
-// CHECK-64-NEXT: ret void
-// CHECK-64: worker.exit:
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
-// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
-// CHECK-64-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
// CHECK-64-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
-// CHECK-64-NEXT: call void @__kmpc_target_deinit()
-// CHECK-64-NEXT: ret void
-// CHECK-64: worker.exit:
-// CHECK-64-NEXT: ret void
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15
+// CHECK-32-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-32: user_code.entry:
+// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
+// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
+// CHECK-32-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
+// CHECK-32-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2:[0-9]+]]
+// CHECK-32-NEXT: call void @__kmpc_target_deinit()
+// CHECK-32-NEXT: ret void
+// CHECK-32: worker.exit:
+// CHECK-32-NEXT: ret void
//
//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-64-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-64: omp.loop.exit:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
-// CHECK-64-NEXT: call void @__kmpc_target_deinit()
-// CHECK-64-NEXT: ret void
-// CHECK-64: worker.exit:
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP1]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-64-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-64: cond.true:
-// CHECK-64-NEXT: br label [[COND_END:%.*]]
-// CHECK-64: cond.false:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[COND_END]]
-// CHECK-64: cond.end:
-// CHECK-64-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-64-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
-// CHECK-64-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
-// CHECK-64-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-64-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK-64-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
-// CHECK-64-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
-// CHECK-64-NEXT: call void @__kmpc_target_deinit()
-// CHECK-64-NEXT: ret void
-// CHECK-64: worker.exit:
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741862, i32 0, i32 9, i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP248]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP248]]
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
-// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP249:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
-// CHECK-64-NEXT: call void @__kmpc_target_deinit()
-// CHECK-64-NEXT: ret void
-// CHECK-64: worker.exit:
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741861, i32 0, i32 9, i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP251]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP251]]
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
-// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP252:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
-// CHECK-64-NEXT: call void @__kmpc_target_deinit()
-// CHECK-64-NEXT: ret void
-// CHECK-64: worker.exit:
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741859, i32 0, i32 9, i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP254]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP254]]
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
-// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP255:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268
-// CHECK-64-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 8
-// CHECK-64-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK-64-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-64-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-64-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-64: user_code.entry:
-// CHECK-64-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-64-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 0, i32 0)
-// CHECK-64-NEXT: call void @__kmpc_target_deinit()
-// CHECK-64-NEXT: ret void
-// CHECK-64: worker.exit:
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-64-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268_omp_outlined
-// CHECK-64-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3]] {
-// CHECK-64-NEXT: entry:
-// CHECK-64-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
-// CHECK-64-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-64-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-64-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-64-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-64-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK-64-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-64-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP1]], i32 1073741860, i32 0, i32 9, i32 1, i32 1)
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-64: omp.dispatch.cond:
-// CHECK-64-NEXT: [[TMP2:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP1]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-64-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP2]], 0
-// CHECK-64-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-64: omp.dispatch.body:
-// CHECK-64-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-64-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-64: omp.inner.for.cond:
-// CHECK-64-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257:![0-9]+]]
-// CHECK-64-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP257]]
-// CHECK-64-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
-// CHECK-64-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-64: omp.inner.for.body:
-// CHECK-64-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
-// CHECK-64-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
-// CHECK-64-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-64-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP257]]
-// CHECK-64-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-64: omp.body.continue:
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-64: omp.inner.for.inc:
-// CHECK-64-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
-// CHECK-64-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-64-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
-// CHECK-64-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP258:![0-9]+]]
-// CHECK-64: omp.inner.for.end:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-64: omp.dispatch.inc:
-// CHECK-64-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-64: omp.dispatch.end:
-// CHECK-64-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP1]])
-// CHECK-64-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15
-// CHECK-32-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0:[0-9]+]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-32: user_code.entry:
-// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
-// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
-// CHECK-32-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV]] to i8
-// CHECK-32-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2:[0-9]+]]
-// CHECK-32-NEXT: call void @__kmpc_target_deinit()
-// CHECK-32-NEXT: ret void
-// CHECK-32: worker.exit:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
-// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__CASTED15:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS17:%.*]] = alloca [3 x ptr], align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
-// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP5]], 0
-// CHECK-32-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
-// CHECK-32: omp_if.then:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66:![0-9]+]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP9]], 0
-// CHECK-32-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV2]] to i8
-// CHECK-32-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK-32-NEXT: [[TMP16:%.*]] = inttoptr i32 [[TMP10]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[LOADEDV3:%.*]] = icmp ne i8 [[TMP17]], 0
-// CHECK-32-NEXT: [[TMP18:%.*]] = zext i1 [[LOADEDV3]] to i32
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP18]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0), !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
-// CHECK-32-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
-// CHECK-32-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP25]], 9
-// CHECK-32-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
-// CHECK-32: cond.true7:
-// CHECK-32-NEXT: br label [[COND_END9:%.*]]
-// CHECK-32: cond.false8:
-// CHECK-32-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: br label [[COND_END9]]
-// CHECK-32: cond.end9:
-// CHECK-32-NEXT: [[COND10:%.*]] = phi i32 [ 9, [[COND_TRUE7]] ], [ [[TMP26]], [[COND_FALSE8]] ]
-// CHECK-32-NEXT: store i32 [[COND10]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: store i32 [[TMP27]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP67:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_IF_END:%.*]]
-// CHECK-32: omp_if.else:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND11:%.*]]
-// CHECK-32: omp.inner.for.cond11:
-// CHECK-32-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP28]], 10
-// CHECK-32-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END28:%.*]]
-// CHECK-32: omp.inner.for.body13:
-// CHECK-32-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP31:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
-// CHECK-32-NEXT: [[LOADEDV14:%.*]] = icmp ne i8 [[TMP31]], 0
-// CHECK-32-NEXT: [[STOREDV16:%.*]] = zext i1 [[LOADEDV14]] to i8
-// CHECK-32-NEXT: store i8 [[STOREDV16]], ptr [[DOTCAPTURE_EXPR__CASTED15]], align 1
-// CHECK-32-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED15]], align 4
-// CHECK-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS17]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP34:%.*]] = inttoptr i32 [[TMP29]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP34]], ptr [[TMP33]], align 4
-// CHECK-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS17]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP36:%.*]] = inttoptr i32 [[TMP30]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP36]], ptr [[TMP35]], align 4
-// CHECK-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS17]], i32 0, i32 2
-// CHECK-32-NEXT: [[TMP38:%.*]] = inttoptr i32 [[TMP32]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP38]], ptr [[TMP37]], align 4
-// CHECK-32-NEXT: [[TMP39:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
-// CHECK-32-NEXT: [[LOADEDV18:%.*]] = icmp ne i8 [[TMP39]], 0
-// CHECK-32-NEXT: [[TMP40:%.*]] = zext i1 [[LOADEDV18]] to i32
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP40]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined1, ptr null, ptr [[CAPTURED_VARS_ADDRS17]], i32 3, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]
-// CHECK-32: omp.inner.for.inc19:
-// CHECK-32-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP41]], [[TMP42]]
-// CHECK-32-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP43]], [[TMP44]]
-// CHECK-32-NEXT: store i32 [[ADD21]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP45]], [[TMP46]]
-// CHECK-32-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP47]], 9
-// CHECK-32-NEXT: br i1 [[CMP23]], label [[COND_TRUE24:%.*]], label [[COND_FALSE25:%.*]]
-// CHECK-32: cond.true24:
-// CHECK-32-NEXT: br label [[COND_END26:%.*]]
-// CHECK-32: cond.false25:
-// CHECK-32-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END26]]
-// CHECK-32: cond.end26:
-// CHECK-32-NEXT: [[COND27:%.*]] = phi i32 [ 9, [[COND_TRUE24]] ], [ [[TMP48]], [[COND_FALSE25]] ]
-// CHECK-32-NEXT: store i32 [[COND27]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP49]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP70:![0-9]+]]
-// CHECK-32: omp.inner.for.end28:
-// CHECK-32-NEXT: br label [[OMP_IF_END]]
-// CHECK-32: omp_if.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
-// CHECK-32-NEXT: br i1 [[TMP51]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3:[0-9]+]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
-// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
-// CHECK-32-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
-// CHECK-32: omp_if.then:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72:![0-9]+]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP72]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP72]]
-// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP72]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP73:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_IF_END:%.*]]
-// CHECK-32: omp_if.else:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP12]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2:%.*]]
-// CHECK-32: omp.inner.for.cond2:
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY4:%.*]], label [[OMP_INNER_FOR_END10:%.*]]
-// CHECK-32: omp.inner.for.body4:
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP16]], 1
-// CHECK-32-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
-// CHECK-32-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE7:%.*]]
-// CHECK-32: omp.body.continue7:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC8:%.*]]
-// CHECK-32: omp.inner.for.inc8:
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2]], !llvm.loop [[LOOP75:![0-9]+]]
-// CHECK-32: omp.inner.for.end10:
-// CHECK-32-NEXT: br label [[OMP_IF_END]]
-// CHECK-32: omp_if.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined1
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
-// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
-// CHECK-32-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
-// CHECK-32: omp_if.then:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76:![0-9]+]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP76]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP76]]
-// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP76]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP77:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_IF_END:%.*]]
-// CHECK-32: omp_if.else:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP12]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2:%.*]]
-// CHECK-32: omp.inner.for.cond2:
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY4:%.*]], label [[OMP_INNER_FOR_END10:%.*]]
-// CHECK-32: omp.inner.for.body4:
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP16]], 1
-// CHECK-32-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
-// CHECK-32-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE7:%.*]]
-// CHECK-32: omp.body.continue7:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC8:%.*]]
-// CHECK-32: omp.inner.for.inc8:
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2]], !llvm.loop [[LOOP79:![0-9]+]]
-// CHECK-32: omp.inner.for.end10:
-// CHECK-32-NEXT: br label [[OMP_IF_END]]
-// CHECK-32: omp_if.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-32: user_code.entry:
-// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
-// CHECK-32-NEXT: call void @__kmpc_target_deinit()
-// CHECK-32-NEXT: ret void
-// CHECK-32: worker.exit:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
+// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__CASTED15:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS17:%.*]] = alloca [3 x ptr], align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -9728,7 +8493,7 @@ int a;
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
@@ -9742,56 +8507,130 @@ int a;
// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
+// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP5]], 0
+// CHECK-32-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
+// CHECK-32: omp_if.then:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80:![0-9]+]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66:![0-9]+]]
+// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[LOADEDV2:%.*]] = icmp ne i8 [[TMP9]], 0
+// CHECK-32-NEXT: [[STOREDV:%.*]] = zext i1 [[LOADEDV2]] to i8
+// CHECK-32-NEXT: store i8 [[STOREDV]], ptr [[DOTCAPTURE_EXPR__CASTED]], align 1, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP16:%.*]] = inttoptr i32 [[TMP10]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[LOADEDV3:%.*]] = icmp ne i8 [[TMP17]], 0
+// CHECK-32-NEXT: [[TMP18:%.*]] = zext i1 [[LOADEDV3]] to i32
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP18]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0), !llvm.access.group [[ACC_GRP66]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP81:![0-9]+]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP21]], [[TMP22]]
+// CHECK-32-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP23]], [[TMP24]]
+// CHECK-32-NEXT: store i32 [[ADD5]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP25]], 9
+// CHECK-32-NEXT: br i1 [[CMP6]], label [[COND_TRUE7:%.*]], label [[COND_FALSE8:%.*]]
+// CHECK-32: cond.true7:
+// CHECK-32-NEXT: br label [[COND_END9:%.*]]
+// CHECK-32: cond.false8:
+// CHECK-32-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: br label [[COND_END9]]
+// CHECK-32: cond.end9:
+// CHECK-32-NEXT: [[COND10:%.*]] = phi i32 [ 9, [[COND_TRUE7]] ], [ [[TMP26]], [[COND_FALSE8]] ]
+// CHECK-32-NEXT: store i32 [[COND10]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: store i32 [[TMP27]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP66]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP67:![0-9]+]]
// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: br label [[OMP_IF_END:%.*]]
+// CHECK-32: omp_if.else:
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND11:%.*]]
+// CHECK-32: omp.inner.for.cond11:
+// CHECK-32-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[CMP12:%.*]] = icmp slt i32 [[TMP28]], 10
+// CHECK-32-NEXT: br i1 [[CMP12]], label [[OMP_INNER_FOR_BODY13:%.*]], label [[OMP_INNER_FOR_END28:%.*]]
+// CHECK-32: omp.inner.for.body13:
+// CHECK-32-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP31:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
+// CHECK-32-NEXT: [[LOADEDV14:%.*]] = icmp ne i8 [[TMP31]], 0
+// CHECK-32-NEXT: [[STOREDV16:%.*]] = zext i1 [[LOADEDV14]] to i8
+// CHECK-32-NEXT: store i8 [[STOREDV16]], ptr [[DOTCAPTURE_EXPR__CASTED15]], align 1
+// CHECK-32-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED15]], align 4
+// CHECK-32-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS17]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP34:%.*]] = inttoptr i32 [[TMP29]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP34]], ptr [[TMP33]], align 4
+// CHECK-32-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS17]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP36:%.*]] = inttoptr i32 [[TMP30]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP36]], ptr [[TMP35]], align 4
+// CHECK-32-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS17]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP38:%.*]] = inttoptr i32 [[TMP32]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP38]], ptr [[TMP37]], align 4
+// CHECK-32-NEXT: [[TMP39:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
+// CHECK-32-NEXT: [[LOADEDV18:%.*]] = icmp ne i8 [[TMP39]], 0
+// CHECK-32-NEXT: [[TMP40:%.*]] = zext i1 [[LOADEDV18]] to i32
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 [[TMP40]], i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined1, ptr null, ptr [[CAPTURED_VARS_ADDRS17]], i32 3, i32 0)
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC19:%.*]]
+// CHECK-32: omp.inner.for.inc19:
+// CHECK-32-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP41]], [[TMP42]]
+// CHECK-32-NEXT: store i32 [[ADD20]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: [[ADD21:%.*]] = add nsw i32 [[TMP43]], [[TMP44]]
+// CHECK-32-NEXT: store i32 [[ADD21]], ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: [[ADD22:%.*]] = add nsw i32 [[TMP45]], [[TMP46]]
+// CHECK-32-NEXT: store i32 [[ADD22]], ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP47]], 9
+// CHECK-32-NEXT: br i1 [[CMP23]], label [[COND_TRUE24:%.*]], label [[COND_FALSE25:%.*]]
+// CHECK-32: cond.true24:
+// CHECK-32-NEXT: br label [[COND_END26:%.*]]
+// CHECK-32: cond.false25:
+// CHECK-32-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: br label [[COND_END26]]
+// CHECK-32: cond.end26:
+// CHECK-32-NEXT: [[COND27:%.*]] = phi i32 [ 9, [[COND_TRUE24]] ], [ [[TMP48]], [[COND_FALSE25]] ]
+// CHECK-32-NEXT: store i32 [[COND27]], ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP49]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND11]], !llvm.loop [[LOOP70:![0-9]+]]
+// CHECK-32: omp.inner.for.end28:
+// CHECK-32-NEXT: br label [[OMP_IF_END]]
+// CHECK-32: omp_if.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-32-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0
+// CHECK-32-NEXT: br i1 [[TMP51]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK-32: .omp.final.then:
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
@@ -9799,13 +8638,14 @@ int a;
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3:[0-9]+]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
@@ -9817,6 +8657,7 @@ int a;
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -9825,159 +8666,71 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
+// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
+// CHECK-32-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
+// CHECK-32: omp_if.then:
+// CHECK-32-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83:![0-9]+]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP83]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72:![0-9]+]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP72]]
+// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
+// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72]]
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP83]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP72]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83]]
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP84:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
-// CHECK-32-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-32: user_code.entry:
-// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
-// CHECK-32-NEXT: call void @__kmpc_target_deinit()
-// CHECK-32-NEXT: ret void
-// CHECK-32: worker.exit:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86:![0-9]+]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP87:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP72]]
+// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP72]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP73:![0-9]+]]
// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: br label [[OMP_IF_END:%.*]]
+// CHECK-32: omp_if.else:
+// CHECK-32-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP12]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2:%.*]]
+// CHECK-32: omp.inner.for.cond2:
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]]
+// CHECK-32-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY4:%.*]], label [[OMP_INNER_FOR_END10:%.*]]
+// CHECK-32: omp.inner.for.body4:
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP16]], 1
+// CHECK-32-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
+// CHECK-32-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE7:%.*]]
+// CHECK-32: omp.body.continue7:
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC8:%.*]]
+// CHECK-32: omp.inner.for.inc8:
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
+// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2]], !llvm.loop [[LOOP75:![0-9]+]]
+// CHECK-32: omp.inner.for.end10:
+// CHECK-32-NEXT: br label [[OMP_IF_END]]
+// CHECK-32: omp_if.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
+// CHECK-32-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
@@ -9987,14 +8740,15 @@ int a;
// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l15_omp_outlined_omp_outlined1
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
@@ -10006,6 +8760,7 @@ int a;
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -10014,38 +8769,74 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i8, ptr [[DOTCAPTURE_EXPR__ADDR]], align 1
+// CHECK-32-NEXT: [[LOADEDV:%.*]] = icmp ne i8 [[TMP2]], 0
+// CHECK-32-NEXT: br i1 [[LOADEDV]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
+// CHECK-32: omp_if.then:
+// CHECK-32-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89:![0-9]+]]
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76:![0-9]+]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP76]]
+// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76]]
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP89]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP76]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP90:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP76]]
+// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP76]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP77:![0-9]+]]
// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: br label [[OMP_IF_END:%.*]]
+// CHECK-32: omp_if.else:
+// CHECK-32-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP12]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP13]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2:%.*]]
+// CHECK-32: omp.inner.for.cond2:
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]]
+// CHECK-32-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY4:%.*]], label [[OMP_INNER_FOR_END10:%.*]]
+// CHECK-32: omp.inner.for.body4:
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL5:%.*]] = mul nsw i32 [[TMP16]], 1
+// CHECK-32-NEXT: [[ADD6:%.*]] = add nsw i32 0, [[MUL5]]
+// CHECK-32-NEXT: store i32 [[ADD6]], ptr [[I]], align 4
+// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE7:%.*]]
+// CHECK-32: omp.body.continue7:
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC8:%.*]]
+// CHECK-32: omp.inner.for.inc8:
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
+// CHECK-32-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND2]], !llvm.loop [[LOOP79:![0-9]+]]
+// CHECK-32: omp.inner.for.end10:
+// CHECK-32-NEXT: br label [[OMP_IF_END]]
+// CHECK-32: omp_if.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
-// CHECK-32-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
+// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
+// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK-32: .omp.final.then:
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
@@ -10053,28 +8844,28 @@ int a;
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -10112,47 +8903,47 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80:![0-9]+]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32: cond.true5:
// CHECK-32-NEXT: br label [[COND_END7:%.*]]
// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
// CHECK-32-NEXT: br label [[COND_END7]]
// CHECK-32: cond.end7:
// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP93:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP80]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP81:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -10167,7 +8958,7 @@ int a;
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l18_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -10193,47 +8984,48 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32: omp.dispatch.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32: omp.dispatch.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
+// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK-32: cond.true:
+// CHECK-32-NEXT: br label [[COND_END:%.*]]
+// CHECK-32: cond.false:
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: br label [[COND_END]]
+// CHECK-32: cond.end:
+// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
+// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83:![0-9]+]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP83]]
+// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
+// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83]]
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP95]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP83]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP96:![0-9]+]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83]]
+// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP83]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP84:![0-9]+]]
// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32: omp.dispatch.inc:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32: omp.dispatch.end:
-// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-32-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp.loop.exit:
+// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
+// CHECK-32-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
// CHECK-32: .omp.final.then:
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
@@ -10241,28 +9033,28 @@ int a;
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -10282,175 +9074,98 @@ int a;
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98:![0-9]+]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP99:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741861, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32: omp.dispatch.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32: omp.dispatch.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP101]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86:![0-9]+]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP102:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32: omp.dispatch.inc:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32: omp.dispatch.end:
-// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-32-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -10470,175 +9185,98 @@ int a;
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104:![0-9]+]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP105:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741859, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32: omp.dispatch.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32: omp.dispatch.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP107]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP108:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32: omp.dispatch.inc:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32: omp.dispatch.end:
-// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-32-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -10676,47 +9314,47 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87:![0-9]+]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32: cond.true5:
// CHECK-32-NEXT: br label [[COND_END7:%.*]]
// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-NEXT: br label [[COND_END7]]
// CHECK-32: cond.end7:
// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP111:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP88:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -10731,7 +9369,7 @@ int a;
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -10761,7 +9399,7 @@ int a;
// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741860, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741861, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
// CHECK-32: omp.dispatch.cond:
// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
@@ -10772,23 +9410,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP114:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP91:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -10805,39 +9443,32 @@ int a;
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37
-// CHECK-32-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
@@ -10845,12 +9476,9 @@ int a;
// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK-32-NEXT: [[A1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4)
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
@@ -10874,90 +9502,79 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93:![0-9]+]]
+// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
+// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-32-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP13:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK-32-NEXT: [[TMP15:%.*]] = inttoptr i32 [[TMP9]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP93]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK-32-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP22]], 9
-// CHECK-32-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
-// CHECK-32: cond.true6:
-// CHECK-32-NEXT: br label [[COND_END8:%.*]]
-// CHECK-32: cond.false7:
-// CHECK-32-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END8]]
-// CHECK-32: cond.end8:
-// CHECK-32-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP23]], [[COND_FALSE7]] ]
-// CHECK-32-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
+// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
+// CHECK-32: cond.true5:
+// CHECK-32-NEXT: br label [[COND_END7:%.*]]
+// CHECK-32: cond.false6:
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: br label [[COND_END7]]
+// CHECK-32: cond.end7:
+// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP94:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
-// CHECK-32-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
-// CHECK-32: .omp.lastprivate.then:
-// CHECK-32-NEXT: [[TMP27:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-32-NEXT: store i32 [[TMP27]], ptr [[A_ADDR]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
-// CHECK-32: .omp.lastprivate.done:
-// CHECK-32-NEXT: call void @__kmpc_free_shared(ptr [[A1]], i32 4)
+// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
+// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-32: .omp.final.then:
+// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[A1:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -10966,70 +9583,76 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741859, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-32: omp.dispatch.cond:
+// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-32: omp.dispatch.body:
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP96]]
+// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
-// CHECK-32-NEXT: store i32 [[TMP8]], ptr [[A1]], align 4
-// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
-// CHECK-32-NEXT: br i1 [[TMP12]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
-// CHECK-32: .omp.lastprivate.then:
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-32-NEXT: store i32 [[TMP13]], ptr [[A_ADDR]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
-// CHECK-32: .omp.lastprivate.done:
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP96]]
+// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-32: omp.body.continue:
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
+// CHECK-32: omp.inner.for.inc:
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
+// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP97:![0-9]+]]
+// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-32: omp.dispatch.inc:
+// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-32: omp.dispatch.end:
+// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
+// CHECK-32-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-32: .omp.final.then:
+// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -11067,55 +9690,62 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99:![0-9]+]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32: cond.true5:
// CHECK-32-NEXT: br label [[COND_END7:%.*]]
// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-NEXT: br label [[COND_END7]]
// CHECK-32: cond.end7:
// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP100:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
+// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
+// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-32: .omp.final.then:
+// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -11141,74 +9771,87 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
+// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741860, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
+// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
+// CHECK-32: omp.dispatch.cond:
+// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
+// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
+// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
+// CHECK-32: omp.dispatch.body:
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP102]]
+// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
+// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
+// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP103:![0-9]+]]
// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
+// CHECK-32: omp.dispatch.inc:
+// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
+// CHECK-32: omp.dispatch.end:
+// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
+// CHECK-32-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
+// CHECK-32: .omp.final.then:
+// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
+// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
+// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37
+// CHECK-32-SAME: (i32 noundef [[A:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP3]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
@@ -11216,160 +9859,141 @@ int a;
// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [3 x ptr], align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
+// CHECK-32-NEXT: [[A1:%.*]] = call align 8 ptr @__kmpc_alloc_shared(i32 4)
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP7:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 4
+// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP3]] to ptr
// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP11]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_free_shared(ptr [[A1]], i32 4)
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[A1:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: store i32 0, ptr [[P_LASTITER]], align 4
+// CHECK-32-NEXT: [[GEP_P_LASTITER:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[P_LASTITER]], ptr [[GEP_P_LASTITER]], align 4
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[GEP_A1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK-32-NEXT: store ptr [[A1]], ptr [[GEP_A1]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = load i32, ptr [[P_LASTITER]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = icmp ne i32 [[DOTOMP_IS_LAST]], 0
+// CHECK-32-NEXT: br i1 [[TMP1]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
+// CHECK-32: .omp.lastprivate.then:
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[A1]], align 4
+// CHECK-32-NEXT: store i32 [[TMP2]], ptr [[A_ADDR]], align 4
+// CHECK-32-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
+// CHECK-32: .omp.lastprivate.done:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP_P_LASTITER:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP_P_LASTITER:%.*]] = load ptr, ptr [[GEP_P_LASTITER]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_A1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK-32-NEXT: [[LOADGEP_A1:%.*]] = load ptr, ptr [[GEP_A1]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[OMP_IS_LAST_ITER:%.*]] = icmp eq i32 [[TMP0]], 9
+// CHECK-32-NEXT: [[TMP2:%.*]] = zext i1 [[OMP_IS_LAST_ITER]] to i32
+// CHECK-32-NEXT: store i32 [[TMP2]], ptr [[LOADGEP_P_LASTITER]], align 4
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[LOADGEP_A1]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40
// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_kernel_environment, ptr [[DYN_PTR]])
// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
// CHECK-32: user_code.entry:
// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
// CHECK-32-NEXT: ret void
// CHECK-32: worker.exit:
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -11419,7 +10043,7 @@ int a;
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
@@ -11455,7 +10079,7 @@ int a;
// CHECK-32-NEXT: ret void
//
//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -11481,44 +10105,265 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32: omp.dispatch.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32: omp.dispatch.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
+// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 34, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 9
+// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
+// CHECK-32: cond.true:
+// CHECK-32-NEXT: br label [[COND_END:%.*]]
+// CHECK-32: cond.false:
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: br label [[COND_END]]
+// CHECK-32: cond.end:
+// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ]
+// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
+// CHECK-32-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
+// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
+// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP116]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP117:![0-9]+]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32: omp.dispatch.inc:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32: omp.dispatch.end:
-// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp.loop.exit:
+// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-32: user_code.entry:
+// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @__kmpc_target_deinit()
+// CHECK-32-NEXT: ret void
+// CHECK-32: worker.exit:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp.loop.exit:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
+// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-32: omp.body.continue:
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-32: user_code.entry:
+// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @__kmpc_target_deinit()
+// CHECK-32-NEXT: ret void
+// CHECK-32: worker.exit:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp.loop.exit:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
+// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-32: omp.body.continue:
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -11670,23 +10515,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP120:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP106:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -11844,23 +10689,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP123:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP109:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -12018,23 +10863,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP126:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP112:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -12066,161 +10911,93 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[B:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128:![0-9]+]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP129:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[B:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131:![0-9]+]]
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP131]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP132:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
-// CHECK-32-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -12285,47 +11062,47 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114:![0-9]+]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l66_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l66_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32: cond.true5:
// CHECK-32-NEXT: br label [[COND_END7:%.*]]
// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-NEXT: br label [[COND_END7]]
// CHECK-32: cond.end7:
// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP135:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP115:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -12384,23 +11161,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137:![0-9]+]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117:![0-9]+]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP138:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP118:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -12416,7 +11193,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7:[0-9]+]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR10:[0-9]+]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
@@ -12475,27 +11252,27 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140:![0-9]+]]
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120:![0-9]+]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP120]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP141:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP121:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -12546,24 +11323,24 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143:![0-9]+]]
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123:![0-9]+]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP144:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP124:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -12579,7 +11356,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper
-// CHECK-32-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] {
+// CHECK-32-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR11:[0-9]+]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
// CHECK-32-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
@@ -12639,150 +11416,73 @@ int a;
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146:![0-9]+]]
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP147:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32: omp.dispatch.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32: omp.dispatch.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP149]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP150:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32: omp.dispatch.inc:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32: omp.dispatch.end:
-// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-32-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32: .omp.final.then:
-// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32: .omp.final.done:
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -12845,47 +11545,47 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126:![0-9]+]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l85_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l85_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32: cond.true5:
// CHECK-32-NEXT: br label [[COND_END7:%.*]]
// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-NEXT: br label [[COND_END7]]
// CHECK-32: cond.end7:
// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP153:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP127:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -12941,23 +11641,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP156:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP130:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -13033,47 +11733,47 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132:![0-9]+]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l89_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l89_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32: cond.true5:
// CHECK-32-NEXT: br label [[COND_END7:%.*]]
// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-NEXT: br label [[COND_END7]]
// CHECK-32: cond.end7:
// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP159:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP133:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -13129,23 +11829,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP162:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP136:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -13221,47 +11921,47 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138:![0-9]+]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l93_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l93_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32: cond.true5:
// CHECK-32-NEXT: br label [[COND_END7:%.*]]
// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-NEXT: br label [[COND_END7]]
// CHECK-32: cond.end7:
// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP165:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP139:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -13317,23 +12017,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP168:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP142:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -13358,160 +12058,105 @@ int a;
// CHECK-32-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-32: user_code.entry:
-// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
-// CHECK-32-NEXT: call void @__kmpc_target_deinit()
-// CHECK-32-NEXT: ret void
-// CHECK-32: worker.exit:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-32-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-32: user_code.entry:
+// CHECK-32-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-NEXT: call void @__kmpc_target_deinit()
+// CHECK-32-NEXT: ret void
+// CHECK-32: worker.exit:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -13731,127 +12376,72 @@ int a;
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -13871,161 +12461,97 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
// CHECK-32-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
// CHECK-32-NEXT: call void @__kmpc_target_deinit()
-// CHECK-32-NEXT: ret void
-// CHECK-32: worker.exit:
-// CHECK-32-NEXT: ret void
-//
-//
-// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined
-// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
-// CHECK-32-NEXT: entry:
-// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
-// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: ret void
+// CHECK-32: worker.exit:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined
+// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32: omp.dispatch.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32: omp.dispatch.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP170]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP171:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32: omp.dispatch.inc:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32: omp.dispatch.end:
-// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -14177,23 +12703,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP174:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP145:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -14351,23 +12877,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP177:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP148:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -14525,23 +13051,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP180:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP151:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -14592,127 +13118,72 @@ int a;
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -14932,127 +13403,72 @@ int a;
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -15097,136 +13513,72 @@ int a;
// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32: cond.true:
-// CHECK-32-NEXT: br label [[COND_END:%.*]]
-// CHECK-32: cond.false:
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END]]
-// CHECK-32: cond.end:
-// CHECK-32-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32: cond.true5:
-// CHECK-32-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32: cond.false6:
-// CHECK-32-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: br label [[COND_END7]]
-// CHECK-32: cond.end7:
-// CHECK-32-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32: omp.inner.for.end:
+// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
-// CHECK-32-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined
// CHECK-32-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-NEXT: entry:
+// CHECK-32-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32: omp.dispatch.cond:
-// CHECK-32-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32: omp.dispatch.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32: omp_loop.preheader:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32: omp_loop.exit:
+// CHECK-32-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32: omp_loop.after:
+// CHECK-32-NEXT: ret void
+//
+//
+// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined..omp_par
+// CHECK-32-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-NEXT: omp_loop.body:
+// CHECK-32-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP182]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP183:![0-9]+]]
-// CHECK-32: omp.inner.for.end:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32: omp.dispatch.inc:
-// CHECK-32-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32: omp.dispatch.end:
-// CHECK-32-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32: omp_loop.body.cont:
+// CHECK-32-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32: omp.prelatch.exitStub:
// CHECK-32-NEXT: ret void
//
//
@@ -15378,23 +13730,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP186:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP154:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -15552,23 +13904,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP189:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP157:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -15726,23 +14078,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191:![0-9]+]]
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159:![0-9]+]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP192:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP160:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -15753,7 +14105,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160
-// CHECK-32-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9:[0-9]+]] {
+// CHECK-32-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12:[0-9]+]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
@@ -15853,7 +14205,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -15931,7 +14283,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16026,7 +14378,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16074,23 +14426,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP195:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP163:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16101,7 +14453,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16149,23 +14501,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP198:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP166:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16176,7 +14528,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16224,23 +14576,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP201:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP169:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16251,7 +14603,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16299,23 +14651,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP204:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP172:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16326,7 +14678,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181
-// CHECK-32-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
@@ -16391,23 +14743,23 @@ int a;
// CHECK-32: omp.dispatch.body:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206:![0-9]+]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174:![0-9]+]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP207:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP175:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16429,12 +14781,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16487,23 +14839,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209:![0-9]+]]
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177:![0-9]+]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP210:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP178:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -16515,12 +14867,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16580,23 +14932,23 @@ int a;
// CHECK-32: omp.dispatch.body:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212:![0-9]+]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180:![0-9]+]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP213:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP181:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16618,12 +14970,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16671,23 +15023,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP216:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP184:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16701,12 +15053,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16754,23 +15106,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP219:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP187:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16784,12 +15136,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16837,23 +15189,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP222:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP190:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16867,12 +15219,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -16920,23 +15272,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP225:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP193:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -16950,12 +15302,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11:[0-9]+]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13:[0-9]+]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17003,24 +15355,24 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
-// CHECK-32-NEXT: call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP1]]), !llvm.access.group [[ACC_GRP227]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP228:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
+// CHECK-32-NEXT: call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP1]]), !llvm.access.group [[ACC_GRP195]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP196:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17034,12 +15386,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17092,23 +15444,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230:![0-9]+]]
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198:![0-9]+]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-32-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP231:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP199:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32: omp.loop.exit:
@@ -17120,12 +15472,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17185,23 +15537,23 @@ int a;
// CHECK-32: omp.dispatch.body:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233:![0-9]+]]
-// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201:![0-9]+]]
+// CHECK-32-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP234:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP202:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17223,12 +15575,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17276,23 +15628,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP237:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP205:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17306,12 +15658,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17359,23 +15711,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP240:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP208:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17389,12 +15741,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17442,23 +15794,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP243:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP211:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17472,12 +15824,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17525,23 +15877,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP246:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP214:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17555,12 +15907,12 @@ int a;
// CHECK-32-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32: .omp.final.done:
-// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-NEXT: ret void
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17655,7 +16007,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17733,7 +16085,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17828,7 +16180,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17876,23 +16228,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP249:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP217:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17903,7 +16255,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -17951,23 +16303,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP252:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP220:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -17978,7 +16330,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -18026,23 +16378,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP255:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP223:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -18053,7 +16405,7 @@ int a;
//
//
// CHECK-32-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268
-// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-NEXT: entry:
// CHECK-32-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -18101,23 +16453,23 @@ int a;
// CHECK-32-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32: omp.inner.for.cond:
-// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257:![0-9]+]]
-// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225:![0-9]+]]
+// CHECK-32-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32: omp.inner.for.body:
-// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32: omp.body.continue:
// CHECK-32-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32: omp.inner.for.inc:
-// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
-// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP258:![0-9]+]]
+// CHECK-32-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
+// CHECK-32-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP226:![0-9]+]]
// CHECK-32: omp.inner.for.end:
// CHECK-32-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32: omp.dispatch.inc:
@@ -18764,141 +17116,73 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86:![0-9]+]]
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP86]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP87:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-EX-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l21_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86:![0-9]+]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP89]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP89]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP90:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
-// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -18927,166 +17211,89 @@ int a;
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92:![0-9]+]]
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP92]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP93:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-EX-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32-EX: omp.dispatch.cond:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-EX-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-EX-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32-EX: omp.dispatch.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l24_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP95]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP95]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP96:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32-EX: omp.dispatch.inc:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32-EX: omp.dispatch.end:
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
-// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -19149,47 +17356,47 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87:![0-9]+]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l27_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32-EX: cond.true5:
// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
+// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
// CHECK-32-EX-NEXT: br label [[COND_END7]]
// CHECK-32-EX: cond.end7:
// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP98]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP99:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP87]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP88:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -19245,23 +17452,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP101]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP102:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP90]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP91:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -19337,47 +17544,47 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93:![0-9]+]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l30_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32-EX: cond.true5:
// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
+// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
// CHECK-32-EX-NEXT: br label [[COND_END7]]
// CHECK-32-EX: cond.end7:
// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP104]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP105:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP93]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP94:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -19433,23 +17640,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP107]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP108:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP96]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP97:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -19525,47 +17732,47 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99:![0-9]+]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32-EX: cond.true5:
// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
+// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
// CHECK-32-EX-NEXT: br label [[COND_END7]]
// CHECK-32-EX: cond.end7:
// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP110]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP111:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP99]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP100:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -19621,23 +17828,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP113]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP114:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP102]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP103:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -19705,83 +17912,25 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP8]], ptr [[A_CASTED]], align 4
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[A_CASTED]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = inttoptr i32 [[TMP9]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK-32-EX-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP22]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
-// CHECK-32-EX: cond.true6:
-// CHECK-32-EX-NEXT: br label [[COND_END8:%.*]]
-// CHECK-32-EX: cond.false7:
-// CHECK-32-EX-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END8]]
-// CHECK-32-EX: cond.end8:
-// CHECK-32-EX-NEXT: [[COND9:%.*]] = phi i32 [ 9, [[COND_TRUE6]] ], [ [[TMP23]], [[COND_FALSE7]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[A_ADDR]], align 4
+// CHECK-32-EX-NEXT: store i32 [[TMP2]], ptr [[A_CASTED]], align 4
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[A_CASTED]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP7]], ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP3]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP11]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-EX-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP26]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
-// CHECK-32-EX: .omp.lastprivate.then:
-// CHECK-32-EX-NEXT: [[TMP27:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP27]], ptr [[A_ADDR]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
-// CHECK-32-EX: .omp.lastprivate.done:
// CHECK-32-EX-NEXT: call void @__kmpc_free_shared(ptr [[A1]], i32 4)
// CHECK-32-EX-NEXT: ret void
//
@@ -19789,6 +17938,7 @@ int a;
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -19796,67 +17946,74 @@ int a;
// CHECK-32-EX-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[A1:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[A1:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[P_LASTITER:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[A]], ptr [[A_ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP8]], ptr [[A1]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], [[TMP10]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: store i32 0, ptr [[P_LASTITER]], align 4
+// CHECK-32-EX-NEXT: [[GEP_P_LASTITER:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[P_LASTITER]], ptr [[GEP_P_LASTITER]], align 4
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[GEP_A1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK-32-EX-NEXT: store ptr [[A1]], ptr [[GEP_A1]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP12]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = load i32, ptr [[P_LASTITER]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = icmp ne i32 [[DOTOMP_IS_LAST]], 0
+// CHECK-32-EX-NEXT: br i1 [[TMP1]], label [[DOTOMP_LASTPRIVATE_THEN:%.*]], label [[DOTOMP_LASTPRIVATE_DONE:%.*]]
// CHECK-32-EX: .omp.lastprivate.then:
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[A1]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP13]], ptr [[A_ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[A1]], align 4
+// CHECK-32-EX-NEXT: store i32 [[TMP2]], ptr [[A_ADDR]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_LASTPRIVATE_DONE]]
// CHECK-32-EX: .omp.lastprivate.done:
// CHECK-32-EX-NEXT: ret void
//
//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l37_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP_P_LASTITER:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP_P_LASTITER:%.*]] = load ptr, ptr [[GEP_P_LASTITER]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_A1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK-32-EX-NEXT: [[LOADGEP_A1:%.*]] = load ptr, ptr [[GEP_A1]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[OMP_IS_LAST_ITER:%.*]] = icmp eq i32 [[TMP0]], 9
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = zext i1 [[OMP_IS_LAST_ITER]] to i32
+// CHECK-32-EX-NEXT: store i32 [[TMP2]], ptr [[LOADGEP_P_LASTITER]], align 4
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP3]], 1
+// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[LOADGEP_A1]], align 4
+// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK-32-EX: omp.body.continue:
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
+// CHECK-32-EX-NEXT: ret void
+//
+//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l40
// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
// CHECK-32-EX-NEXT: entry:
@@ -20073,127 +18230,72 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
-// CHECK-32-EX-NEXT: entry:
-// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
+// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
+// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l43_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -20238,136 +18340,72 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32-EX: omp.dispatch.cond:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-EX-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-EX-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32-EX: omp.dispatch.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l46_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP116]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP116]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP117:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32-EX: omp.dispatch.inc:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32-EX: omp.dispatch.end:
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -20519,23 +18557,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP119]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP120:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP105]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP106:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -20693,23 +18731,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP122]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP123:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP108]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP109:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -20867,23 +18905,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP125]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP126:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP111]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP112:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -20935,141 +18973,73 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128:![0-9]+]]
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP128]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP129:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-EX-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l58_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP131]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP131]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP132:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP11]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
-// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -21134,47 +19104,47 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114:![0-9]+]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l66_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l66_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32-EX: cond.true5:
// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
+// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
// CHECK-32-EX-NEXT: br label [[COND_END7]]
// CHECK-32-EX: cond.end7:
// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP134]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP135:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP114]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP115:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -21233,23 +19203,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP137]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP138:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP117]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP118:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -21265,7 +19235,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7:[0-9]+]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR10:[0-9]+]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
@@ -21324,27 +19294,27 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-EX-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-EX-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP120]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP140]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP120]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], [[TMP14]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP140]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP141:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP120]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP121:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -21395,24 +19365,24 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP143]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP123]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP143]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP144:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP123]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP124:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -21428,7 +19398,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l73_omp_outlined_omp_outlined_wrapper
-// CHECK-32-EX-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR8:[0-9]+]] {
+// CHECK-32-EX-SAME: (i16 noundef zeroext [[TMP0:%.*]], i32 noundef [[TMP1:%.*]]) #[[ATTR11:[0-9]+]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DOTADDR:%.*]] = alloca i16, align 2
// CHECK-32-EX-NEXT: [[DOTADDR1:%.*]] = alloca i32, align 4
@@ -21487,151 +19457,74 @@ int a;
// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146:![0-9]+]]
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP146]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP147:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
-// CHECK-32-EX-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP22:%.*]] = icmp ne i32 [[TMP21]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP22]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32-EX: omp.dispatch.cond:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-EX-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-EX-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32-EX: omp.dispatch.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l81_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP149]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP149]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP150:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32-EX: omp.dispatch.inc:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32-EX: omp.dispatch.end:
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0
-// CHECK-32-EX-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK-32-EX: .omp.final.then:
-// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK-32-EX: .omp.final.done:
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -21694,47 +19587,47 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126:![0-9]+]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l85_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l85_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32-EX: cond.true5:
// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
+// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
// CHECK-32-EX-NEXT: br label [[COND_END7]]
// CHECK-32-EX: cond.end7:
// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP152]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP153:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP126]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP127:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -21790,23 +19683,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP155]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP156:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP129]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP130:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -21882,47 +19775,47 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132:![0-9]+]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l89_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l89_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32-EX: cond.true5:
// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
+// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
// CHECK-32-EX-NEXT: br label [[COND_END7]]
// CHECK-32-EX: cond.end7:
// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP158]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP159:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP132]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP133:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -21978,23 +19871,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP161]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP162:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP135]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP136:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -22070,47 +19963,47 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138:![0-9]+]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l93_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l93_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0), !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
// CHECK-32-EX: cond.true5:
// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
+// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
// CHECK-32-EX-NEXT: br label [[COND_END7]]
// CHECK-32-EX: cond.end7:
// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP164]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP165:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP138]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP139:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -22166,23 +20059,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP167]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP168:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP141]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP142:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -22240,127 +20133,72 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l97_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -22540,167 +20378,112 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
-// CHECK-32-EX-NEXT: entry:
-// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-EX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_kernel_environment, ptr [[DYN_PTR]])
-// CHECK-32-EX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
-// CHECK-32-EX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
-// CHECK-32-EX: user_code.entry:
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
-// CHECK-32-EX-NEXT: call void @__kmpc_target_deinit()
-// CHECK-32-EX-NEXT: ret void
-// CHECK-32-EX: worker.exit:
-// CHECK-32-EX-NEXT: ret void
-//
-//
-// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
-// CHECK-32-EX-NEXT: entry:
-// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR0]] {
+// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-EX-NEXT: [[DOTZERO_ADDR:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_kernel_environment, ptr [[DYN_PTR]])
+// CHECK-32-EX-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP0]], -1
+// CHECK-32-EX-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
+// CHECK-32-EX: user_code.entry:
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
+// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTTHREADID_TEMP_]], align 4
+// CHECK-32-EX-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]]) #[[ATTR2]]
+// CHECK-32-EX-NEXT: call void @__kmpc_target_deinit()
+// CHECK-32-EX-NEXT: ret void
+// CHECK-32-EX: worker.exit:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
+// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l105_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -22745,136 +20528,72 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32-EX: omp.dispatch.cond:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-EX-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-EX-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32-EX: omp.dispatch.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l109_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP170]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP170]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP171:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32-EX: omp.dispatch.inc:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32-EX: omp.dispatch.end:
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -23026,23 +20745,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP173]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP174:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP144]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP145:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -23200,23 +20919,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP176]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP177:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP147]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP148:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -23374,23 +21093,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP179]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP180:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP150]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP151:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -23427,141 +21146,86 @@ int a;
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
+// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [2 x ptr], align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
+// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
+// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l125_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -23781,127 +21445,72 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[TMP2]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP3]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP5]], [[TMP6]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l135_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP3]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -23946,136 +21555,72 @@ int a;
// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK-32-EX-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[TMP0]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP1]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK-32-EX: cond.true:
-// CHECK-32-EX-NEXT: br label [[COND_END:%.*]]
-// CHECK-32-EX: cond.false:
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END]]
-// CHECK-32-EX: cond.end:
-// CHECK-32-EX-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP5]], 10
-// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = inttoptr i32 [[TMP6]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP9]], ptr [[TMP8]], align 4
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK-32-EX-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP1]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], [[TMP13]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP18]], 9
-// CHECK-32-EX-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK-32-EX: cond.true5:
-// CHECK-32-EX-NEXT: br label [[COND_END7:%.*]]
-// CHECK-32-EX: cond.false6:
-// CHECK-32-EX-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: br label [[COND_END7]]
-// CHECK-32-EX: cond.end7:
-// CHECK-32-EX-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP19]], [[COND_FALSE6]] ]
-// CHECK-32-EX-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP20]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK-32-EX: omp.inner.for.end:
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[TMP3:%.*]] = inttoptr i32 [[TMP0]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP3]], ptr [[TMP2]], align 4
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = getelementptr inbounds [2 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK-32-EX-NEXT: store ptr [[TMP5]], ptr [[TMP4]], align 4
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+// CHECK-32-EX-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP7]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 2, i32 0)
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
-// CHECK-32-EX-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined
// CHECK-32-EX-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]]) #[[ATTR3]] {
// CHECK-32-EX-NEXT: entry:
+// CHECK-32-EX-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr }, align 8
// CHECK-32-EX-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK-32-EX-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
// CHECK-32-EX-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP0:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK-32-EX-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[TMP4]], align 4
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_init_4(ptr @[[GLOB1]], i32 [[TMP5]], i32 1073741862, i32 [[TMP2]], i32 [[TMP3]], i32 1, i32 1)
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND:%.*]]
-// CHECK-32-EX: omp.dispatch.cond:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(ptr @[[GLOB1]], i32 [[TMP5]], ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]])
-// CHECK-32-EX-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0
-// CHECK-32-EX-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]]
-// CHECK-32-EX: omp.dispatch.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
-// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK-32-EX: omp_loop.preheader:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK-32-EX-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK-32-EX-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK-32-EX-NEXT: [[TMP0:%.*]] = call i32 @omp_get_num_threads()
+// CHECK-32-EX-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP0]], i32 0, i32 0, i8 0)
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK-32-EX: omp_loop.exit:
+// CHECK-32-EX-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK-32-EX: omp_loop.after:
+// CHECK-32-EX-NEXT: ret void
+//
+//
+// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l140_omp_outlined_omp_outlined..omp_par
+// CHECK-32-EX-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR5]] {
+// CHECK-32-EX-NEXT: omp_loop.body:
+// CHECK-32-EX-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK-32-EX-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK-32-EX-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META86]]
+// CHECK-32-EX-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP182]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP182]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP183:![0-9]+]]
-// CHECK-32-EX: omp.inner.for.end:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
-// CHECK-32-EX: omp.dispatch.inc:
-// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_COND]]
-// CHECK-32-EX: omp.dispatch.end:
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_deinit(ptr @[[GLOB1]], i32 [[TMP5]])
+// CHECK-32-EX-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK-32-EX: omp_loop.body.cont:
+// CHECK-32-EX-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK-32-EX: omp.prelatch.exitStub:
// CHECK-32-EX-NEXT: ret void
//
//
@@ -24227,23 +21772,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP185]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP186:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP153]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP154:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -24401,23 +21946,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP188]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP189:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP156]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP157:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -24575,23 +22120,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP10]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
+// CHECK-32-EX-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP11]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP191]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP192:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP159]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP160:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -24602,7 +22147,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l160
-// CHECK-32-EX-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9:[0-9]+]] {
+// CHECK-32-EX-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12:[0-9]+]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
@@ -24702,7 +22247,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l163
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -24780,7 +22325,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l166
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -24875,7 +22420,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l169
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -24923,23 +22468,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP194]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP195:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP162]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP163:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -24950,7 +22495,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l172
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -24998,23 +22543,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP197]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP198:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP165]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP166:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25025,7 +22570,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l175
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25073,23 +22618,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP200]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP201:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP168]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP169:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25100,7 +22645,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l178
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25148,23 +22693,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP203]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP204:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP171]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP172:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25175,7 +22720,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l181
-// CHECK-32-EX-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
@@ -25240,23 +22785,23 @@ int a;
// CHECK-32-EX: omp.dispatch.body:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-EX-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-EX-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP206]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP207:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP174]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP175:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25278,12 +22823,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4:[0-9]+]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l185
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25336,23 +22881,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP209]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP210:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP177]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP178:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -25364,12 +22909,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l189
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25429,23 +22974,23 @@ int a;
// CHECK-32-EX: omp.dispatch.body:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-EX-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-EX-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP212]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP213:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP180]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP181:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25467,12 +23012,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l193
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25520,23 +23065,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP215]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP216:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP183]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP184:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25550,12 +23095,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l197
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25603,23 +23148,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP218]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP219:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP186]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP187:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25633,12 +23178,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l201
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25686,23 +23231,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP221]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP222:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP189]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP190:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25716,12 +23261,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l205
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25769,23 +23314,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP224]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP225:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP192]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP193:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25799,12 +23344,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l209
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11:[0-9]+]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13:[0-9]+]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25852,24 +23397,24 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP227]]
-// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP1]]), !llvm.access.group [[ACC_GRP227]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP228:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP195]]
+// CHECK-32-EX-NEXT: call void @__kmpc_dispatch_fini_4(ptr @[[GLOB1]], i32 [[TMP1]]), !llvm.access.group [[ACC_GRP195]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP196:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -25883,12 +23428,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l214
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -25941,23 +23486,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-EX-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]]
// CHECK-32-EX-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
// CHECK-32-EX-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP230]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP231:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP198]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP199:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK-32-EX: omp.loop.exit:
@@ -25969,12 +23514,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l219
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26034,23 +23579,23 @@ int a;
// CHECK-32-EX: omp.dispatch.body:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-EX-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]]
// CHECK-32-EX-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-EX-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
+// CHECK-32-EX-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
// CHECK-32-EX-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP233]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP234:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP201]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP202:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26072,12 +23617,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l224
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26125,23 +23670,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP236]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP237:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP204]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP205:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26155,12 +23700,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l229
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26208,23 +23753,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP239]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP240:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP207]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP208:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26238,12 +23783,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l234
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26291,23 +23836,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP242]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP243:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP210]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP211:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26321,12 +23866,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l239
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR11]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR13]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26374,23 +23919,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP245]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP246:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP213]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP214:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26404,12 +23949,12 @@ int a;
// CHECK-32-EX-NEXT: store i32 10, ptr [[I]], align 4
// CHECK-32-EX-NEXT: br label [[DOTOMP_FINAL_DONE]]
// CHECK-32-EX: .omp.final.done:
-// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB4]], i32 [[TMP1]])
+// CHECK-32-EX-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[TMP1]])
// CHECK-32-EX-NEXT: ret void
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l244
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26504,7 +24049,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l248
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26582,7 +24127,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l252
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26677,7 +24222,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l256
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26725,23 +24270,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP248]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP249:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP216]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP217:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26752,7 +24297,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l260
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26800,23 +24345,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP251]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP252:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP219]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP220:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26827,7 +24372,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l264
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26875,23 +24420,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP254]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP255:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP222]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP223:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
@@ -26902,7 +24447,7 @@ int a;
//
//
// CHECK-32-EX-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3foov_l268
-// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR9]] {
+// CHECK-32-EX-SAME: (ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR12]] {
// CHECK-32-EX-NEXT: entry:
// CHECK-32-EX-NEXT: [[DYN_PTR_ADDR:%.*]] = alloca ptr, align 4
// CHECK-32-EX-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [0 x ptr], align 4
@@ -26950,23 +24495,23 @@ int a;
// CHECK-32-EX-NEXT: store i32 [[TMP3]], ptr [[DOTOMP_IV]], align 4
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK-32-EX: omp.inner.for.cond:
-// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257:![0-9]+]]
-// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-EX-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225:![0-9]+]]
+// CHECK-32-EX-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-EX-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]]
// CHECK-32-EX-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK-32-EX: omp.inner.for.body:
-// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-EX-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-EX-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1
// CHECK-32-EX-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-EX-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-EX-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK-32-EX: omp.body.continue:
// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK-32-EX: omp.inner.for.inc:
-// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
+// CHECK-32-EX-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
// CHECK-32-EX-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP7]], 1
-// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP257]]
-// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP258:![0-9]+]]
+// CHECK-32-EX-NEXT: store i32 [[ADD1]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP225]]
+// CHECK-32-EX-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP226:![0-9]+]]
// CHECK-32-EX: omp.inner.for.end:
// CHECK-32-EX-NEXT: br label [[OMP_DISPATCH_INC:%.*]]
// CHECK-32-EX: omp.dispatch.inc:
diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
index 8ebe1fcad87abb..37c0abfb693521 100644
--- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_codegen.cpp
@@ -457,89 +457,29 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
-// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8
-// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8
-// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8
-// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK1: cond.true10:
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END12:%.*]]
-// CHECK1: cond.false11:
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END12]]
-// CHECK1: cond.end12:
-// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void
@@ -548,6 +488,7 @@ int bar(int n){
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -559,11 +500,6 @@ int bar(int n){
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -578,64 +514,55 @@ int bar(int n){
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK1: omp.precond.then:
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
-// CHECK1-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
-// CHECK1-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
-// CHECK1-NEXT: store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META11]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK1: omp.precond.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
@@ -686,79 +613,30 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
-// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
-// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
-// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
-// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 8
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK1: cond.true5:
-// CHECK1-NEXT: br label [[COND_END7:%.*]]
-// CHECK1: cond.false6:
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END7]]
-// CHECK1: cond.end7:
-// CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
-// CHECK1-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP2]] to ptr
+// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP4]] to ptr
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP9]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP11]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -766,10 +644,6 @@ int bar(int n){
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
@@ -777,52 +651,51 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
-// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
@@ -1443,92 +1316,32 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK1-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8
-// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8
-// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8
-// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP27]], align 8
-// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
-// CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP28]], align 8
-// CHECK1-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
-// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK1: cond.true10:
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END12:%.*]]
-// CHECK1: cond.false11:
-// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END12]]
-// CHECK1: cond.end12:
-// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
-// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[V_ADDR]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP18]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
+// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP21]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP43]])
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void
@@ -1537,6 +1350,7 @@ int bar(int n){
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -1549,11 +1363,6 @@ int bar(int n){
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -1569,65 +1378,60 @@ int bar(int n){
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK1: omp.precond.then:
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
-// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
-// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
-// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[V_ADDR]], ptr [[GEP_V_ADDR]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK1: omp.precond.end:
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_V_ADDR:%.*]] = load ptr, ptr [[GEP_V_ADDR]], align 8, !align [[META12:![0-9]+]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_V_ADDR]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP6]] to i64
+// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM4]]
+// CHECK1-NEXT: store i32 [[TMP5]], ptr [[ARRAYIDX5]], align 4
+// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
+// CHECK1: omp.body.continue:
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
@@ -2017,89 +1821,29 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK2-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
-// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8
-// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK2-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK2-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8
-// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8
-// CHECK2-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK2: cond.true10:
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END12:%.*]]
-// CHECK2: cond.false11:
-// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END12]]
-// CHECK2: cond.end12:
-// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
+// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK2-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK2-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
+// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void
@@ -2108,6 +1852,7 @@ int bar(int n){
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -2119,11 +1864,6 @@ int bar(int n){
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -2138,64 +1878,55 @@ int bar(int n){
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK2: omp.precond.then:
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK2-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
-// CHECK2-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
-// CHECK2-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
-// CHECK2-NEXT: store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META11]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK2-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK2: omp.precond.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
@@ -2246,79 +1977,30 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
-// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
-// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
-// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
-// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 8
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK2: cond.true5:
-// CHECK2-NEXT: br label [[COND_END7:%.*]]
-// CHECK2: cond.false6:
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END7]]
-// CHECK2: cond.end7:
-// CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
-// CHECK2-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK2-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP2]] to ptr
+// CHECK2-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK2-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP4]] to ptr
+// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP9]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP11]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -2326,10 +2008,6 @@ int bar(int n){
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
@@ -2337,52 +2015,51 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META9]], !align [[META10]]
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK2-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
-// CHECK2-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
-// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
-// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK2-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
@@ -2998,92 +2675,32 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK2-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK2-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8
-// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK2-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK2-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8
-// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK2-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK2-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8
-// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP27]], align 8
-// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
-// CHECK2-NEXT: store ptr [[TMP20]], ptr [[TMP28]], align 8
-// CHECK2-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
-// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
-// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK2: cond.true10:
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END12:%.*]]
-// CHECK2: cond.false11:
-// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END12]]
-// CHECK2: cond.end12:
-// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
-// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[V_ADDR]], align 8
+// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK2-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
+// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK2-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK2-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
+// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK2-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP18]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
+// CHECK2-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP21]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP43]])
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void
@@ -3092,6 +2709,7 @@ int bar(int n){
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -3104,11 +2722,6 @@ int bar(int n){
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -3124,65 +2737,60 @@ int bar(int n){
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK2: omp.precond.then:
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK2-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
-// CHECK2-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK2-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[V_ADDR]], ptr [[GEP_V_ADDR]], align 8
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_V_ADDR:%.*]] = load ptr, ptr [[GEP_V_ADDR]], align 8, !align [[META12:![0-9]+]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_V_ADDR]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]]
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP6]] to i64
+// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM4]]
+// CHECK2-NEXT: store i32 [[TMP5]], ptr [[ARRAYIDX5]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK2: omp.precond.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
@@ -3565,87 +3173,27 @@ int bar(int n){
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK3: cond.true:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END:%.*]]
-// CHECK3: cond.false:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END]]
-// CHECK3: cond.end:
-// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK3-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to ptr
-// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 4
-// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to ptr
-// CHECK3-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4
-// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to ptr
-// CHECK3-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4
-// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
-// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP24]], align 4
-// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0)
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], [[TMP28]]
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP33]], [[TMP34]]
-// CHECK3-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK3: cond.true10:
-// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END12:%.*]]
-// CHECK3: cond.false11:
-// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END12]]
-// CHECK3: cond.end12:
-// CHECK3-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP35]], [[COND_TRUE10]] ], [ [[TMP36]], [[COND_FALSE11]] ]
-// CHECK3-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[TMP7]], ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP5]] to ptr
+// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP6]] to ptr
+// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4
+// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
+// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4
+// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
+// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP17]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0)
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP39]])
// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
// CHECK3: omp.precond.end:
// CHECK3-NEXT: ret void
@@ -3654,6 +3202,7 @@ int bar(int n){
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3]] {
// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -3665,11 +3214,6 @@ int bar(int n){
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -3684,60 +3228,54 @@ int bar(int n){
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK3: omp.precond.then:
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I3]], align 4
-// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]]
-// CHECK3-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
-// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1
-// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX]], align 2
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK3: omp_loop.preheader:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK3-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK3: omp_loop.exit:
+// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK3: omp_loop.after:
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l34_omp_outlined_omp_outlined..omp_par
+// CHECK3-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK3-NEXT: omp_loop.body:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK3-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK3-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META11]]
+// CHECK3-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK3-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i32 0, i32 [[TMP3]]
+// CHECK3-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
-// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK3: omp.precond.end:
+// CHECK3-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK3: omp_loop.body.cont:
+// CHECK3-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK3: omp.prelatch.exitStub:
// CHECK3-NEXT: ret void
//
//
@@ -3788,77 +3326,28 @@ int bar(int n){
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK3: cond.true:
-// CHECK3-NEXT: br label [[COND_END:%.*]]
-// CHECK3: cond.false:
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END]]
-// CHECK3: cond.end:
-// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr
-// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP13]], align 4
-// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK3: cond.true5:
-// CHECK3-NEXT: br label [[COND_END7:%.*]]
-// CHECK3: cond.false6:
-// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END7]]
-// CHECK3: cond.end7:
-// CHECK3-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK3-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP2]] to ptr
+// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -3866,10 +3355,6 @@ int bar(int n){
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
@@ -3877,48 +3362,50 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META9]], !align [[META10]]
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
-// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK3: omp_loop.preheader:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK3-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK3: omp_loop.exit:
+// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK3: omp_loop.after:
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l39_omp_outlined_omp_outlined..omp_par
+// CHECK3-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK3-NEXT: omp_loop.body:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK3-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK3-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META10]]
+// CHECK3-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
-// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i32 0, i32 [[TMP3]]
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK3-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
-// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK3-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK3: omp_loop.body.cont:
+// CHECK3-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK3: omp.prelatch.exitStub:
// CHECK3-NEXT: ret void
//
//
@@ -4535,90 +4022,30 @@ int bar(int n){
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK3: cond.true:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END:%.*]]
-// CHECK3: cond.false:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END]]
-// CHECK3: cond.end:
-// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK3-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[V_ADDR]], align 4
-// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr
-// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4
-// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP15]] to ptr
-// CHECK3-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 4
-// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP24:%.*]] = inttoptr i32 [[TMP17]] to ptr
-// CHECK3-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 4
-// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
-// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP25]], align 4
-// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
-// CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP26]], align 4
-// CHECK3-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5, i32 0)
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK3-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK3: cond.true10:
-// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END12:%.*]]
-// CHECK3: cond.false11:
-// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END12]]
-// CHECK3: cond.end12:
-// CHECK3-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK3-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[TMP7]], ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[V_ADDR]], align 4
+// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP5]] to ptr
+// CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
+// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP13:%.*]] = inttoptr i32 [[TMP6]] to ptr
+// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 4
+// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP15:%.*]] = inttoptr i32 [[TMP8]] to ptr
+// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP16]], align 4
+// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
+// CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP17]], align 4
+// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5, i32 0)
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
// CHECK3: omp.precond.end:
// CHECK3-NEXT: ret void
@@ -4627,6 +4054,7 @@ int bar(int n){
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined
// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR3]] {
// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -4639,11 +4067,6 @@ int bar(int n){
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -4659,59 +4082,57 @@ int bar(int n){
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK3: omp.precond.then:
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 4
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I3]], align 4
-// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i32 [[TMP14]]
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4
-// CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]]
-// CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX5]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK3: omp_loop.preheader:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK3-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[V_ADDR]], ptr [[GEP_V_ADDR]], align 4
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK3-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK3: omp_loop.exit:
+// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK3: omp_loop.after:
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l59_omp_outlined_omp_outlined..omp_par
+// CHECK3-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK3-NEXT: omp_loop.body:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK3-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK3-NEXT: [[LOADGEP_V_ADDR:%.*]] = load ptr, ptr [[GEP_V_ADDR]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK3-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META10]]
+// CHECK3-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK3-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_V_ADDR]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i32 [[TMP4]]
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [1000 x i32], ptr [[LOADGEP_]], i32 0, i32 [[TMP6]]
+// CHECK3-NEXT: store i32 [[TMP5]], ptr [[ARRAYIDX4]], align 4
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
-// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK3: omp.precond.end:
+// CHECK3-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK3: omp_loop.body.cont:
+// CHECK3-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK3: omp.prelatch.exitStub:
// CHECK3-NEXT: ret void
//
diff --git a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
index 1dfb22fac6f3b2..7ca2cdfb506d1f 100644
--- a/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_teams_distribute_parallel_for_simd_codegen.cpp
@@ -469,101 +469,35 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK1: cond.true10:
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: br label [[COND_END12:%.*]]
-// CHECK1: cond.false11:
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: br label [[COND_END12]]
-// CHECK1: cond.end12:
-// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
-// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP43:%.*]] = icmp ne i32 [[TMP42]], 0
-// CHECK1-NEXT: br i1 [[TMP43]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK1: .omp.final.then:
-// CHECK1-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP44]], 0
-// CHECK1-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1
-// CHECK1-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4
-// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK1: .omp.final.done:
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK1-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP20]], 0
+// CHECK1-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV5]], 1
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I3]], align 4
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void
@@ -572,6 +506,7 @@ int bar(int n){
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -583,11 +518,6 @@ int bar(int n){
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -602,76 +532,55 @@ int bar(int n){
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK1: omp.precond.then:
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
-// CHECK1-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
-// CHECK1-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
-// CHECK1-NEXT: store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META8]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META8]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META16]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
-// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
-// CHECK1-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK1: .omp.final.then:
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[SUB11:%.*]] = sub nsw i32 [[TMP21]], 0
-// CHECK1-NEXT: [[DIV12:%.*]] = sdiv i32 [[SUB11]], 1
-// CHECK1-NEXT: [[MUL13:%.*]] = mul nsw i32 [[DIV12]], 1
-// CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 0, [[MUL13]]
-// CHECK1-NEXT: store i32 [[ADD14]], ptr [[I4]], align 4
-// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK1: .omp.final.done:
-// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK1: omp.precond.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
@@ -722,86 +631,31 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]
-// CHECK1-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
-// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
-// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0), !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK1: cond.true5:
-// CHECK1-NEXT: br label [[COND_END7:%.*]]
-// CHECK1: cond.false6:
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: br label [[COND_END7]]
-// CHECK1: cond.end7:
-// CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
-// CHECK1-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP2]] to ptr
+// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP4]] to ptr
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP9]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP11]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP26:%.*]] = icmp ne i32 [[TMP25]], 0
-// CHECK1-NEXT: br i1 [[TMP26]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK1: .omp.final.then:
// CHECK1-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK1: .omp.final.done:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined
// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -809,10 +663,6 @@ int bar(int n){
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
@@ -820,59 +670,51 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META7]], !align [[META8]]
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]]
-// CHECK1-NEXT: [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
-// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META8]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META8]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META8]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
-// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
-// CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK1: .omp.final.then:
-// CHECK1-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK1: .omp.final.done:
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
@@ -953,57 +795,57 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
// CHECK1-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
// CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: store i32 [[TMP11]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[F_CASTED]], align 8, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
-// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
// CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
-// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
// CHECK1-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP12]] to ptr
-// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0), !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP24]], [[TMP25]]
-// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 99
// CHECK1-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
// CHECK1: cond.true6:
// CHECK1-NEXT: br label [[COND_END8:%.*]]
// CHECK1: cond.false7:
-// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK1-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK1-NEXT: br label [[COND_END8]]
// CHECK1: cond.end8:
// CHECK1-NEXT: [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP27]], [[COND_FALSE7]] ]
-// CHECK1-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
+// CHECK1-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: store i32 [[TMP28]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1062,49 +904,49 @@ int bar(int n){
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
// CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[TMP6]] to i64
-// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV3]], [[TMP7]]
// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[DIV4:%.*]] = sdiv i32 [[TMP10]], 10
// CHECK1-NEXT: [[MUL5:%.*]] = mul nsw i32 [[DIV4]], 10
// CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL5]]
// CHECK1-NEXT: [[MUL6:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 0, [[MUL6]]
-// CHECK1-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: store i32 [[ADD7]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[MUL8:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP11]], [[MUL8]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[ADD9]], [[TMP14]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP15]] to i64
// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[IDXPROM11:%.*]] = sext i32 [[TMP16]] to i64
// CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i64 0, i64 [[IDXPROM11]]
-// CHECK1-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: store i32 [[ADD10]], ptr [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK1-NEXT: [[ADD13:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
+// CHECK1-NEXT: store i32 [[ADD13]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
@@ -1523,99 +1365,33 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK2-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to ptr
-// CHECK2-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to ptr
-// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to ptr
-// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP24]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0), !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], [[TMP28]]
-// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP33]], [[TMP34]]
-// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK2: cond.true10:
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: br label [[COND_END12:%.*]]
-// CHECK2: cond.false11:
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: br label [[COND_END12]]
-// CHECK2: cond.end12:
-// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP35]], [[COND_TRUE10]] ], [ [[TMP36]], [[COND_FALSE11]] ]
-// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP7]], ptr [[N_CASTED]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP5]] to ptr
+// CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4
+// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP6]] to ptr
+// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4
+// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
+// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4
+// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 4
+// CHECK2-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP17]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP39]])
-// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0
-// CHECK2-NEXT: br i1 [[TMP41]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK2: .omp.final.then:
-// CHECK2-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP42]], 0
-// CHECK2-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV15]], 1
-// CHECK2-NEXT: [[ADD16:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD16]], ptr [[I3]], align 4
-// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK2: .omp.final.done:
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
+// CHECK2-NEXT: [[SUB4:%.*]] = sub nsw i32 [[TMP18]], 0
+// CHECK2-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB4]], 1
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV5]], 1
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void
@@ -1624,6 +1400,7 @@ int bar(int n){
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -1635,11 +1412,6 @@ int bar(int n){
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK2-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -1654,72 +1426,54 @@ int bar(int n){
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK2: omp.precond.then:
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
-// CHECK2-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I3]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]]
-// CHECK2-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1
-// CHECK2-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK2-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX]], align 2, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l32_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6:[0-9]+]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META8]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META8]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META16]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i32 0, i32 [[TMP3]]
+// CHECK2-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP20:%.*]] = icmp ne i32 [[TMP19]], 0
-// CHECK2-NEXT: br i1 [[TMP20]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK2: .omp.final.then:
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[SUB8:%.*]] = sub nsw i32 [[TMP21]], 0
-// CHECK2-NEXT: [[DIV9:%.*]] = sdiv i32 [[SUB8]], 1
-// CHECK2-NEXT: [[MUL10:%.*]] = mul nsw i32 [[DIV9]], 1
-// CHECK2-NEXT: [[ADD11:%.*]] = add nsw i32 0, [[MUL10]]
-// CHECK2-NEXT: store i32 [[ADD11]], ptr [[I3]], align 4
-// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK2: .omp.final.done:
-// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK2: omp.precond.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
@@ -1770,84 +1524,29 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]]
-// CHECK2-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK2-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK2-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr
-// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0), !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK2: cond.true5:
-// CHECK2-NEXT: br label [[COND_END7:%.*]]
-// CHECK2: cond.false6:
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: br label [[COND_END7]]
-// CHECK2: cond.end7:
-// CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK2-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK2-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK2-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 4
+// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK2-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP2]] to ptr
+// CHECK2-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 4
+// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 4
+// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP24:%.*]] = icmp ne i32 [[TMP23]], 0
-// CHECK2-NEXT: br i1 [[TMP24]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK2: .omp.final.then:
// CHECK2-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK2: .omp.final.done:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined
// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -1855,10 +1554,6 @@ int bar(int n){
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
@@ -1866,55 +1561,50 @@ int bar(int n){
// CHECK2-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META7]], !align [[META8]]
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK2-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]]
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB4]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB5]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l37_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR6]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META8]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META8]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META8]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]]
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP26]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i32 0, i32 [[TMP3]]
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
-// CHECK2-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]]
-// CHECK2: .omp.final.then:
-// CHECK2-NEXT: store i32 10, ptr [[I]], align 4
-// CHECK2-NEXT: br label [[DOTOMP_FINAL_DONE]]
-// CHECK2: .omp.final.done:
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
@@ -1995,55 +1685,55 @@ int bar(int n){
// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29:![0-9]+]]
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17:![0-9]+]]
// CHECK2-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP6]], 100
// CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: store i32 [[TMP9]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[F_CASTED]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
// CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
// CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
-// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
// CHECK2-NEXT: [[TMP17:%.*]] = inttoptr i32 [[TMP10]] to ptr
-// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0), !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l42_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0), !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP22]], [[TMP23]]
-// CHECK2-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: [[CMP5:%.*]] = icmp sgt i32 [[TMP24]], 99
// CHECK2-NEXT: br i1 [[CMP5]], label [[COND_TRUE6:%.*]], label [[COND_FALSE7:%.*]]
// CHECK2: cond.true6:
// CHECK2-NEXT: br label [[COND_END8:%.*]]
// CHECK2: cond.false7:
-// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
+// CHECK2-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
// CHECK2-NEXT: br label [[COND_END8]]
// CHECK2: cond.end8:
// CHECK2-NEXT: [[COND9:%.*]] = phi i32 [ 99, [[COND_TRUE6]] ], [ [[TMP25]], [[COND_FALSE7]] ]
-// CHECK2-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP29]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]]
+// CHECK2-NEXT: store i32 [[COND9]], ptr [[DOTOMP_COMB_UB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: store i32 [[TMP26]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP17]]
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
@@ -2100,46 +1790,46 @@ int bar(int n){
// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]]
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]]
+// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP8]], 10
// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP10]], 10
// CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 10
// CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP9]], [[MUL3]]
// CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1
// CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL4]]
-// CHECK2-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: store i32 [[ADD5]], ptr [[J]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: store i32 10, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[F_ADDR]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP12]], [[TMP13]]
// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], [[MUL6]]
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[K]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[ADD7]], [[TMP14]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[I]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr [10 x [10 x i32]], ptr [[TMP0]], i32 0, i32 [[TMP15]]
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[J]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], ptr [[ARRAYIDX]], i32 0, i32 [[TMP16]]
-// CHECK2-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: store i32 [[ADD8]], ptr [[ARRAYIDX9]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP32]]
+// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4, !llvm.access.group [[ACC_GRP20]]
// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]]
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]]
+// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]]
+// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]]
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
diff --git a/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp b/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp
index c97fa6b2996888..55790e9e6b2af4 100644
--- a/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp
+++ b/clang/test/OpenMP/nvptx_target_teams_generic_loop_codegen.cpp
@@ -88,7 +88,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR4:[0-9]+]]
// CHECK1-NEXT: call void @__kmpc_target_deinit()
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
@@ -137,97 +137,38 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK1-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
-// CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK1-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8
-// CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK1-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8
-// CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8
-// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK1: cond.true10:
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END12:%.*]]
-// CHECK1: cond.false11:
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END12]]
-// CHECK1: cond.end12:
-// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
+// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
+// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK1-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
+// CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -239,11 +180,6 @@ int bar(int n){
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -258,69 +194,60 @@ int bar(int n){
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK1: omp.precond.then:
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
-// CHECK1-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
-// CHECK1-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
-// CHECK1-NEXT: store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10:![0-9]+]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META9]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK1-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK1-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK1-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK1: omp.precond.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5:[0-9]+]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7:[0-9]+]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
@@ -331,7 +258,7 @@ int bar(int n){
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10:![0-9]+]]
+// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
// CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
@@ -344,7 +271,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR4]]
// CHECK1-NEXT: call void @__kmpc_target_deinit()
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
@@ -376,79 +303,30 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
-// CHECK1-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
-// CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
-// CHECK1-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
-// CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 8
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK1-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK1: cond.true5:
-// CHECK1-NEXT: br label [[COND_END7:%.*]]
-// CHECK1: cond.false6:
-// CHECK1-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END7]]
-// CHECK1: cond.end7:
-// CHECK1-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
-// CHECK1-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP2]] to ptr
+// CHECK1-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8
+// CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP4]] to ptr
+// CHECK1-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
+// CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP9]], align 8
+// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP11]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -456,10 +334,6 @@ int bar(int n){
// CHECK1-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
@@ -467,57 +341,56 @@ int bar(int n){
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK1-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK1-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK1-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
-// CHECK1-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK1-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
+// CHECK1-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK1-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK1-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
-// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK1-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
@@ -539,7 +412,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR4]]
// CHECK1-NEXT: call void @__kmpc_target_deinit()
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
@@ -577,7 +450,7 @@ int bar(int n){
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK1-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB4:[0-9]+]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
// CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
@@ -647,12 +520,12 @@ int bar(int n){
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
+// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB4]], i32 [[TMP2]])
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR3]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -689,7 +562,7 @@ int bar(int n){
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB5:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK1-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
@@ -740,12 +613,12 @@ int bar(int n){
// CHECK1: omp.inner.for.end:
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5]], i32 [[TMP4]])
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
-// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
@@ -767,7 +640,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR4]]
// CHECK1-NEXT: call void @__kmpc_target_deinit()
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
@@ -836,7 +709,7 @@ int bar(int n){
// CHECK1-NEXT: [[CONV11:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64
// CHECK1-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_8(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
+// CHECK1-NEXT: call void @__kmpc_distribute_static_init_8(ptr @[[GLOB4]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
// CHECK1-NEXT: [[CMP12:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
@@ -914,14 +787,14 @@ int bar(int n){
// CHECK1: omp.loop.exit:
// CHECK1-NEXT: [[TMP41:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP42:%.*]] = load i32, ptr [[TMP41]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP42]])
+// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB4]], i32 [[TMP42]])
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR3]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -986,7 +859,7 @@ int bar(int n){
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK1-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB5]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK1-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK1-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_IV]], align 8
// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
@@ -1050,14 +923,14 @@ int bar(int n){
// CHECK1: omp.loop.exit:
// CHECK1-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP28]])
+// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5]], i32 [[TMP28]])
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
-// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK1-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK1-NEXT: entry:
// CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK1-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
@@ -1082,7 +955,7 @@ int bar(int n){
// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// CHECK1-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK1-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
+// CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR4]]
// CHECK1-NEXT: call void @__kmpc_target_deinit()
// CHECK1-NEXT: ret void
// CHECK1: worker.exit:
@@ -1133,100 +1006,41 @@ int bar(int n){
// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK1-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK1-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK1-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK1: cond.true:
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END:%.*]]
-// CHECK1: cond.false:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END]]
-// CHECK1: cond.end:
-// CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK1-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK1-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK1-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK1-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK1-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK1-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8
-// CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK1-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK1-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8
-// CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK1-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK1-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8
-// CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP27]], align 8
-// CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
-// CHECK1-NEXT: store ptr [[TMP20]], ptr [[TMP28]], align 8
-// CHECK1-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
-// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK1-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK1-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
-// CHECK1-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
-// CHECK1-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK1: cond.true10:
-// CHECK1-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: br label [[COND_END12:%.*]]
-// CHECK1: cond.false11:
-// CHECK1-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: br label [[COND_END12]]
-// CHECK1: cond.end12:
-// CHECK1-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
-// CHECK1-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK1-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
+// CHECK1-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK1-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK1-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK1-NEXT: [[TMP11:%.*]] = load ptr, ptr [[V_ADDR]], align 8
+// CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK1-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK1-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
+// CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK1-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK1-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
+// CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK1-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK1-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
+// CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[TMP18]], align 8
+// CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
+// CHECK1-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 8
+// CHECK1-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK1-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
+// CHECK1-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP21]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
-// CHECK1-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP43]])
// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
// CHECK1: omp.precond.end:
// CHECK1-NEXT: ret void
//
//
// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined
-// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR3]] {
+// CHECK1-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR2]] {
// CHECK1-NEXT: entry:
+// CHECK1-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -1239,11 +1053,6 @@ int bar(int n){
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK1-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK1-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK1-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -1259,65 +1068,60 @@ int bar(int n){
// CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK1-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK1: omp.precond.then:
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK1-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK1-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK1-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK1-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK1-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK1-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK1-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK1: omp.inner.for.cond:
-// CHECK1-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK1-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK1: omp.inner.for.body:
-// CHECK1-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK1-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK1-NEXT: [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK1-NEXT: [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
-// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK1-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK1-NEXT: [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK1-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
-// CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
-// CHECK1-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK1-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK1: omp_loop.preheader:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK1-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK1-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK1-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK1-NEXT: store ptr [[V_ADDR]], ptr [[GEP_V_ADDR]], align 8
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK1-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK1-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK1: omp_loop.exit:
+// CHECK1-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK1-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK1-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK1: omp_loop.after:
+// CHECK1-NEXT: ret void
+//
+//
+// CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined..omp_par
+// CHECK1-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3]] {
+// CHECK1-NEXT: omp_loop.body:
+// CHECK1-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK1-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK1-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK1-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK1-NEXT: [[LOADGEP_V_ADDR:%.*]] = load ptr, ptr [[GEP_V_ADDR]], align 8, !align [[META11:![0-9]+]]
+// CHECK1-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK1-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK1-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK1-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_V_ADDR]], align 8
+// CHECK1-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
+// CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]]
+// CHECK1-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK1-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK1-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP6]] to i64
+// CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM4]]
+// CHECK1-NEXT: store i32 [[TMP5]], ptr [[ARRAYIDX5]], align 4
// CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK1: omp.body.continue:
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK1: omp.inner.for.inc:
-// CHECK1-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK1-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
-// CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK1: omp.inner.for.end:
-// CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK1: omp.loop.exit:
-// CHECK1-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK1-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK1-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK1-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK1: omp.precond.end:
+// CHECK1-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK1: omp_loop.body.cont:
+// CHECK1-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK1: omp.prelatch.exitStub:
// CHECK1-NEXT: ret void
//
//
@@ -1344,7 +1148,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR4:[0-9]+]]
// CHECK2-NEXT: call void @__kmpc_target_deinit()
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
@@ -1393,97 +1197,38 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK2-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK2-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
-// CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK2-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK2-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8
-// CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK2-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK2-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8
-// CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP26]], align 8
-// CHECK2-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK2: cond.true10:
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END12:%.*]]
-// CHECK2: cond.false11:
-// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END12]]
-// CHECK2: cond.end12:
-// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
+// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
+// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK2-NEXT: [[TMP16:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK2-NEXT: store ptr [[TMP16]], ptr [[TMP15]], align 8
+// CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP17]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 4, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
-// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -1495,11 +1240,6 @@ int bar(int n){
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -1514,69 +1254,60 @@ int bar(int n){
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK2: omp.precond.then:
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK2-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
-// CHECK2-NEXT: [[CONV7:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], 1
-// CHECK2-NEXT: [[CONV9:%.*]] = trunc i32 [[ADD8]] to i16
-// CHECK2-NEXT: store i16 [[CONV9]], ptr [[ARRAYIDX]], align 2
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10:![0-9]+]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META9]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK2-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK2-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK2-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK2-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK2: omp.precond.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
-// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5:[0-9]+]] {
+// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7:[0-9]+]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
@@ -1587,7 +1318,7 @@ int bar(int n){
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 8
// CHECK2-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 8
-// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10:![0-9]+]]
+// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
// CHECK2-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK2-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
@@ -1600,7 +1331,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR__CASTED]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR4]]
// CHECK2-NEXT: call void @__kmpc_target_deinit()
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
@@ -1632,79 +1363,30 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP10:%.*]] = zext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP8]] to ptr
-// CHECK2-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 8
-// CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK2-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to ptr
-// CHECK2-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 8
-// CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 8
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK2-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP20]], [[TMP21]]
-// CHECK2-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP22]], 9
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK2: cond.true5:
-// CHECK2-NEXT: br label [[COND_END7:%.*]]
-// CHECK2: cond.false6:
-// CHECK2-NEXT: [[TMP23:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END7]]
-// CHECK2: cond.end7:
-// CHECK2-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP23]], [[COND_FALSE6]] ]
-// CHECK2-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP24:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP24]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
+// CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK2-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP2]] to ptr
+// CHECK2-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 8
+// CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK2-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP4]] to ptr
+// CHECK2-NEXT: store ptr [[TMP8]], ptr [[TMP7]], align 8
+// CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP9]], align 8
+// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP11]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 3, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined
-// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
+// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -1712,10 +1394,6 @@ int bar(int n){
// CHECK2-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
@@ -1723,57 +1401,56 @@ int bar(int n){
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 8
// CHECK2-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 8
// CHECK2-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 8, !nonnull [[META8]], !align [[META10]]
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP1:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP1]] to i32
-// CHECK2-NEXT: [[TMP2:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV1:%.*]] = trunc i64 [[TMP2]] to i32
-// CHECK2-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[CONV1]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CONV2:%.*]] = sext i32 [[TMP6]] to i64
-// CHECK2-NEXT: [[TMP7:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CMP:%.*]] = icmp ule i64 [[CONV2]], [[TMP7]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK2-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
-// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP10]], 1
-// CHECK2-NEXT: store i32 [[ADD3]], ptr [[ARRAYIDX]], align 4
+// CHECK2-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM]]
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
+// CHECK2-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK2-NEXT: store i32 [[ADD4]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
-// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK2-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i64, align 8
@@ -1795,7 +1472,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[F_CASTED]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR2]]
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i64 [[TMP4]]) #[[ATTR4]]
// CHECK2-NEXT: call void @__kmpc_target_deinit()
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
@@ -1833,7 +1510,7 @@ int bar(int n){
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK2-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB4:[0-9]+]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
// CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
@@ -1903,12 +1580,12 @@ int bar(int n){
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
+// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB4]], i32 [[TMP2]])
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined
-// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR3]] {
+// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i64 noundef [[F:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -1945,7 +1622,7 @@ int bar(int n){
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB5:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
@@ -1996,12 +1673,12 @@ int bar(int n){
// CHECK2: omp.inner.for.end:
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5]], i32 [[TMP4]])
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
-// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 8
@@ -2023,7 +1700,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP4:%.*]] = load i64, ptr [[N_CASTED]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]]) #[[ATTR4]]
// CHECK2-NEXT: call void @__kmpc_target_deinit()
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
@@ -2089,7 +1766,7 @@ int bar(int n){
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK2-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB4]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3]], align 4
// CHECK2-NEXT: [[CMP10:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
@@ -2169,14 +1846,14 @@ int bar(int n){
// CHECK2: omp.loop.exit:
// CHECK2-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP44]])
+// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB4]], i32 [[TMP44]])
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined
-// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR3]] {
+// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
@@ -2241,7 +1918,7 @@ int bar(int n){
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB5]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK2-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV]], align 4
// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
@@ -2301,14 +1978,14 @@ int bar(int n){
// CHECK2: omp.loop.exit:
// CHECK2-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP28]])
+// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5]], i32 [[TMP28]])
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
-// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK2-SAME: (i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK2-NEXT: entry:
// CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8
// CHECK2-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 8
@@ -2333,7 +2010,7 @@ int bar(int n){
// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 8
// CHECK2-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK2-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
+// CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i64 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR4]]
// CHECK2-NEXT: call void @__kmpc_target_deinit()
// CHECK2-NEXT: ret void
// CHECK2: worker.exit:
@@ -2384,100 +2061,41 @@ int bar(int n){
// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK2-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK2-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
// CHECK2-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK2: cond.true:
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END:%.*]]
-// CHECK2: cond.false:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END]]
-// CHECK2: cond.end:
-// CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK2-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK2-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK2-NEXT: store i32 [[TMP18]], ptr [[N_CASTED]], align 4
-// CHECK2-NEXT: [[TMP19:%.*]] = load i64, ptr [[N_CASTED]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
-// CHECK2-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP15]] to ptr
-// CHECK2-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 8
-// CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
-// CHECK2-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP17]] to ptr
-// CHECK2-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8
-// CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
-// CHECK2-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP19]] to ptr
-// CHECK2-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8
-// CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
-// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP27]], align 8
-// CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
-// CHECK2-NEXT: store ptr [[TMP20]], ptr [[TMP28]], align 8
-// CHECK2-NEXT: [[TMP29:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP30:%.*]] = load i32, ptr [[TMP29]], align 4
-// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP30]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK2-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK2-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP35]], [[TMP36]]
-// CHECK2-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP37]], [[TMP38]]
-// CHECK2-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK2: cond.true10:
-// CHECK2-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: br label [[COND_END12:%.*]]
-// CHECK2: cond.false11:
-// CHECK2-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: br label [[COND_END12]]
-// CHECK2: cond.end12:
-// CHECK2-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP39]], [[COND_TRUE10]] ], [ [[TMP40]], [[COND_FALSE11]] ]
-// CHECK2-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK2-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP41]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
+// CHECK2-NEXT: [[TMP8:%.*]] = zext i32 [[TMP7]] to i64
+// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK2-NEXT: store i32 [[TMP9]], ptr [[N_CASTED]], align 4
+// CHECK2-NEXT: [[TMP10:%.*]] = load i64, ptr [[N_CASTED]], align 8
+// CHECK2-NEXT: [[TMP11:%.*]] = load ptr, ptr [[V_ADDR]], align 8
+// CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 0
+// CHECK2-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP6]] to ptr
+// CHECK2-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 8
+// CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 1
+// CHECK2-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP8]] to ptr
+// CHECK2-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
+// CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 2
+// CHECK2-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP10]] to ptr
+// CHECK2-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
+// CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 3
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[TMP18]], align 8
+// CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i64 0, i64 4
+// CHECK2-NEXT: store ptr [[TMP11]], ptr [[TMP19]], align 8
+// CHECK2-NEXT: [[TMP20:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
+// CHECK2-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4
+// CHECK2-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP21]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i64 5, i32 0)
// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP42:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP43:%.*]] = load i32, ptr [[TMP42]], align 4
-// CHECK2-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP43]])
// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
// CHECK2: omp.precond.end:
// CHECK2-NEXT: ret void
//
//
// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined
-// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR3]] {
+// CHECK2-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR2]] {
// CHECK2-NEXT: entry:
+// CHECK2-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8
// CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8
@@ -2490,11 +2108,6 @@ int bar(int n){
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK2-NEXT: [[I4:%.*]] = alloca i32, align 4
// CHECK2-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 8
// CHECK2-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 8
// CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 8
@@ -2510,65 +2123,60 @@ int bar(int n){
// CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK2-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK2: omp.precond.then:
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK2-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: [[TMP5:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV:%.*]] = trunc i64 [[TMP5]] to i32
-// CHECK2-NEXT: [[TMP6:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP6]] to i32
-// CHECK2-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[CONV3]], ptr [[DOTOMP_UB]], align 4
-// CHECK2-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK2-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK2-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK2-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK2: omp.inner.for.cond:
-// CHECK2-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64
-// CHECK2-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR]], align 8
-// CHECK2-NEXT: [[CMP6:%.*]] = icmp ule i64 [[CONV5]], [[TMP11]]
-// CHECK2-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK2: omp.inner.for.body:
-// CHECK2-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK2-NEXT: store i32 [[ADD]], ptr [[I4]], align 4
-// CHECK2-NEXT: [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 8
-// CHECK2-NEXT: [[TMP14:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP14]] to i64
-// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i64 [[IDXPROM]]
-// CHECK2-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK2-NEXT: [[TMP16:%.*]] = load i32, ptr [[I4]], align 4
-// CHECK2-NEXT: [[IDXPROM7:%.*]] = sext i32 [[TMP16]] to i64
-// CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i64 0, i64 [[IDXPROM7]]
-// CHECK2-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX8]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK2-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK2: omp_loop.preheader:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK2-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 8
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK2-NEXT: store ptr [[I]], ptr [[GEP_I]], align 8
+// CHECK2-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK2-NEXT: store ptr [[V_ADDR]], ptr [[GEP_V_ADDR]], align 8
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK2-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK2-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK2: omp_loop.exit:
+// CHECK2-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK2-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK2-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK2: omp_loop.after:
+// CHECK2-NEXT: ret void
+//
+//
+// CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined..omp_par
+// CHECK2-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3]] {
+// CHECK2-NEXT: omp_loop.body:
+// CHECK2-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK2-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK2-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 8, !align [[META10]]
+// CHECK2-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK2-NEXT: [[LOADGEP_V_ADDR:%.*]] = load ptr, ptr [[GEP_V_ADDR]], align 8, !align [[META11:![0-9]+]]
+// CHECK2-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK2-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META10]]
+// CHECK2-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK2-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_V_ADDR]], align 8
+// CHECK2-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP4]] to i64
+// CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]]
+// CHECK2-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK2-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK2-NEXT: [[IDXPROM4:%.*]] = sext i32 [[TMP6]] to i64
+// CHECK2-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[LOADGEP_]], i64 0, i64 [[IDXPROM4]]
+// CHECK2-NEXT: store i32 [[TMP5]], ptr [[ARRAYIDX5]], align 4
// CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK2: omp.body.continue:
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK2: omp.inner.for.inc:
-// CHECK2-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK2-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_IV]], align 4
-// CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK2: omp.inner.for.end:
-// CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK2: omp.loop.exit:
-// CHECK2-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 8
-// CHECK2-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK2-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK2-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK2: omp.precond.end:
+// CHECK2-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK2: omp_loop.body.cont:
+// CHECK2-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK2: omp.prelatch.exitStub:
// CHECK2-NEXT: ret void
//
//
@@ -2595,7 +2203,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2:[0-9]+]]
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR4:[0-9]+]]
// CHECK3-NEXT: call void @__kmpc_target_deinit()
// CHECK3-NEXT: ret void
// CHECK3: worker.exit:
@@ -2644,95 +2252,36 @@ int bar(int n){
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2:[0-9]+]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK3: cond.true:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END:%.*]]
-// CHECK3: cond.false:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END]]
-// CHECK3: cond.end:
-// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK3-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP19:%.*]] = inttoptr i32 [[TMP14]] to ptr
-// CHECK3-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 4
-// CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP21:%.*]] = inttoptr i32 [[TMP15]] to ptr
-// CHECK3-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 4
-// CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP23:%.*]] = inttoptr i32 [[TMP17]] to ptr
-// CHECK3-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 4
-// CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
-// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP24]], align 4
-// CHECK3-NEXT: [[TMP25:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP25]], align 4
-// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP26]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0)
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP27:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP27]], [[TMP28]]
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP33]], [[TMP34]]
-// CHECK3-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK3: cond.true10:
-// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END12:%.*]]
-// CHECK3: cond.false11:
-// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END12]]
-// CHECK3: cond.end12:
-// CHECK3-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP35]], [[COND_TRUE10]] ], [ [[TMP36]], [[COND_FALSE11]] ]
-// CHECK3-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP37]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[TMP7]], ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP5]] to ptr
+// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4
+// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP6]] to ptr
+// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4
+// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP14:%.*]] = inttoptr i32 [[TMP8]] to ptr
+// CHECK3-NEXT: store ptr [[TMP14]], ptr [[TMP13]], align 4
+// CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP15]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 4
+// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP17]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 4, i32 0)
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP38:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[TMP38]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP39]])
// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
// CHECK3: omp.precond.end:
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined
-// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 2 dereferenceable(2000) [[AA:%.*]]) #[[ATTR2:[0-9]+]] {
// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -2744,11 +2293,6 @@ int bar(int n){
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -2763,65 +2307,59 @@ int bar(int n){
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK3: omp.precond.then:
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3:[0-9]+]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[I3]], align 4
-// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[TMP0]], i32 0, i32 [[TMP13]]
-// CHECK3-NEXT: [[TMP14:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
-// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP14]] to i32
-// CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV]], 1
-// CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16
-// CHECK3-NEXT: store i16 [[CONV6]], ptr [[ARRAYIDX]], align 2
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK3: omp_loop.preheader:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK3-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2:[0-9]+]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK3: omp_loop.exit:
+// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3:[0-9]+]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK3: omp_loop.after:
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l28_omp_outlined_omp_outlined..omp_par
+// CHECK3-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
+// CHECK3-NEXT: omp_loop.body:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK3-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META10:![0-9]+]]
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK3-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META9]]
+// CHECK3-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK3-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i16], ptr [[LOADGEP_]], i32 0, i32 [[TMP3]]
+// CHECK3-NEXT: [[TMP4:%.*]] = load i16, ptr [[ARRAYIDX]], align 2
+// CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP4]] to i32
+// CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV]], 1
+// CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
+// CHECK3-NEXT: store i16 [[CONV5]], ptr [[ARRAYIDX]], align 2
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP15]], [[TMP16]]
-// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
-// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP17:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP18]])
-// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK3: omp.precond.end:
+// CHECK3-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK3: omp_loop.body.cont:
+// CHECK3-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK3: omp.prelatch.exitStub:
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33
-// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5:[0-9]+]] {
+// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7:[0-9]+]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
@@ -2832,7 +2370,7 @@ int bar(int n){
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], ptr [[DOTCAPTURE_EXPR__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DYN_PTR]], ptr [[DYN_PTR_ADDR]], align 4
-// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10:![0-9]+]]
+// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @__kmpc_target_init(ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_kernel_environment, ptr [[DYN_PTR]])
// CHECK3-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP1]], -1
// CHECK3-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]]
@@ -2845,7 +2383,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__CASTED]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR4]]
// CHECK3-NEXT: call void @__kmpc_target_deinit()
// CHECK3-NEXT: ret void
// CHECK3: worker.exit:
@@ -2877,77 +2415,28 @@ int bar(int n){
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 9
-// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK3: cond.true:
-// CHECK3-NEXT: br label [[COND_END:%.*]]
-// CHECK3: cond.false:
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END]]
-// CHECK3: cond.end:
-// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ]
-// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[CMP1:%.*]] = icmp slt i32 [[TMP6]], 10
-// CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP10:%.*]] = inttoptr i32 [[TMP7]] to ptr
-// CHECK3-NEXT: store ptr [[TMP10]], ptr [[TMP9]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP12:%.*]] = inttoptr i32 [[TMP8]] to ptr
-// CHECK3-NEXT: store ptr [[TMP12]], ptr [[TMP11]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP13]], align 4
-// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP2]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP14]], [[TMP15]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP16]], [[TMP17]]
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP18]], [[TMP19]]
-// CHECK3-NEXT: store i32 [[ADD3]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP20]], 9
-// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE5:%.*]], label [[COND_FALSE6:%.*]]
-// CHECK3: cond.true5:
-// CHECK3-NEXT: br label [[COND_END7:%.*]]
-// CHECK3: cond.false6:
-// CHECK3-NEXT: [[TMP21:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END7]]
-// CHECK3: cond.end7:
-// CHECK3-NEXT: [[COND8:%.*]] = phi i32 [ 9, [[COND_TRUE5]] ], [ [[TMP21]], [[COND_FALSE6]] ]
-// CHECK3-NEXT: store i32 [[COND8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP22:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP22]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
+// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP4:%.*]] = inttoptr i32 [[TMP1]] to ptr
+// CHECK3-NEXT: store ptr [[TMP4]], ptr [[TMP3]], align 4
+// CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP6:%.*]] = inttoptr i32 [[TMP2]] to ptr
+// CHECK3-NEXT: store ptr [[TMP6]], ptr [[TMP5]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP7]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 3, i32 0)
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined
-// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] {
+// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr }, align 8
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -2955,10 +2444,6 @@ int bar(int n){
// CHECK3-NEXT: [[B_ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
@@ -2966,53 +2451,55 @@ int bar(int n){
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_UB_]], ptr [[DOTPREVIOUS_UB__ADDR]], align 4
// CHECK3-NEXT: store ptr [[B]], ptr [[B_ADDR]], align 4
// CHECK3-NEXT: [[TMP0:%.*]] = load ptr, ptr [[B_ADDR]], align 4, !nonnull [[META8]], !align [[META10]]
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 9, ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: [[TMP1:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP1]], ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP6]], [[TMP7]]
-// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1
+// CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK3: omp_loop.preheader:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK3-NEXT: [[TMP1:%.*]] = call i32 @omp_get_num_threads()
+// CHECK3-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 10, i32 [[TMP1]], i32 0, i32 0, i8 0)
+// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK3: omp_loop.exit:
+// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK3: omp_loop.after:
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l33_omp_outlined_omp_outlined..omp_par
+// CHECK3-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3]] {
+// CHECK3-NEXT: omp_loop.body:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK3-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK3-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META10]]
+// CHECK3-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I]], align 4
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[I]], align 4
-// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[TMP0]], i32 0, i32 [[TMP9]]
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP10]], 1
+// CHECK3-NEXT: store i32 [[ADD]], ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], ptr [[LOADGEP_]], i32 0, i32 [[TMP3]]
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1
// CHECK3-NEXT: store i32 [[ADD1]], ptr [[ARRAYIDX]], align 4
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP11]], [[TMP12]]
-// CHECK3-NEXT: store i32 [[ADD2]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
-// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK3-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK3: omp_loop.body.cont:
+// CHECK3-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK3: omp.prelatch.exitStub:
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38
-// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK3-SAME: (ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32, align 4
@@ -3034,7 +2521,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[F_CASTED]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR2]]
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], ptr [[TMP0]], i32 [[TMP4]]) #[[ATTR4]]
// CHECK3-NEXT: call void @__kmpc_target_deinit()
// CHECK3-NEXT: ret void
// CHECK3: worker.exit:
@@ -3072,7 +2559,7 @@ int bar(int n){
// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
// CHECK3-NEXT: [[TMP1:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[TMP1]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB4:[0-9]+]], i32 [[TMP2]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
// CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], 99
// CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
@@ -3140,12 +2627,12 @@ int bar(int n){
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP2]])
+// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB4]], i32 [[TMP2]])
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l38_omp_outlined_omp_outlined
-// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR3]] {
+// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[F:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -3180,7 +2667,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[TMP3]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
+// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB5:[0-9]+]], i32 [[TMP4]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_IV]], align 4
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
@@ -3228,12 +2715,12 @@ int bar(int n){
// CHECK3: omp.inner.for.end:
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP4]])
+// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5]], i32 [[TMP4]])
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46
-// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[C_ADDR:%.*]] = alloca ptr, align 4
@@ -3255,7 +2742,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[N_CASTED]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR2]]
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]]) #[[ATTR4]]
// CHECK3-NEXT: call void @__kmpc_target_deinit()
// CHECK3-NEXT: ret void
// CHECK3: worker.exit:
@@ -3324,7 +2811,7 @@ int bar(int n){
// CHECK3-NEXT: [[CONV11:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64
// CHECK3-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_8(ptr @[[GLOB2]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
+// CHECK3-NEXT: call void @__kmpc_distribute_static_init_8(ptr @[[GLOB4]], i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 [[CONV11]])
// CHECK3-NEXT: [[TMP10:%.*]] = load i64, ptr [[DOTOMP_COMB_UB]], align 8
// CHECK3-NEXT: [[TMP11:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_3]], align 8
// CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i64 [[TMP10]], [[TMP11]]
@@ -3404,14 +2891,14 @@ int bar(int n){
// CHECK3: omp.loop.exit:
// CHECK3-NEXT: [[TMP43:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP44:%.*]] = load i32, ptr [[TMP43]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP44]])
+// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB4]], i32 [[TMP44]])
// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
// CHECK3: omp.precond.end:
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l46_omp_outlined_omp_outlined
-// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR3]] {
+// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(400) [[C:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
@@ -3478,7 +2965,7 @@ int bar(int n){
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB3]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
+// CHECK3-NEXT: call void @__kmpc_for_static_init_8(ptr @[[GLOB5]], i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i64 1, i64 1)
// CHECK3-NEXT: [[TMP12:%.*]] = load i64, ptr [[DOTOMP_LB]], align 8
// CHECK3-NEXT: store i64 [[TMP12]], ptr [[DOTOMP_IV]], align 8
// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
@@ -3541,14 +3028,14 @@ int bar(int n){
// CHECK3: omp.loop.exit:
// CHECK3-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP28]])
+// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB5]], i32 [[TMP28]])
// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
// CHECK3: omp.precond.end:
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53
-// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5]] {
+// CHECK3-SAME: (i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7]] {
// CHECK3-NEXT: entry:
// CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[A_ADDR:%.*]] = alloca ptr, align 4
@@ -3573,7 +3060,7 @@ int bar(int n){
// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[V_ADDR]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTZERO_ADDR]], align 4
// CHECK3-NEXT: store i32 [[TMP2]], ptr [[DOTTHREADID_TEMP_]], align 4
-// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR2]]
+// CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined(ptr [[DOTTHREADID_TEMP_]], ptr [[DOTZERO_ADDR]], i32 [[TMP4]], ptr [[TMP0]], ptr [[TMP5]]) #[[ATTR4]]
// CHECK3-NEXT: call void @__kmpc_target_deinit()
// CHECK3-NEXT: ret void
// CHECK3: worker.exit:
@@ -3624,98 +3111,39 @@ int bar(int n){
// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
// CHECK3-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// CHECK3-NEXT: [[TMP5:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_init_4(ptr @[[GLOB2]], i32 [[TMP6]], i32 91, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_COMB_LB]], ptr [[DOTOMP_COMB_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 [[NVPTX_NUM_THREADS]])
-// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// CHECK3: cond.true:
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END:%.*]]
-// CHECK3: cond.false:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END]]
-// CHECK3: cond.end:
-// CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ]
-// CHECK3-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP11]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP13]], 1
-// CHECK3-NEXT: [[CMP5:%.*]] = icmp slt i32 [[TMP12]], [[ADD]]
-// CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[N_ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP16]], ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[N_CASTED]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[V_ADDR]], align 4
-// CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
-// CHECK3-NEXT: [[TMP20:%.*]] = inttoptr i32 [[TMP14]] to ptr
-// CHECK3-NEXT: store ptr [[TMP20]], ptr [[TMP19]], align 4
-// CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
-// CHECK3-NEXT: [[TMP22:%.*]] = inttoptr i32 [[TMP15]] to ptr
-// CHECK3-NEXT: store ptr [[TMP22]], ptr [[TMP21]], align 4
-// CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
-// CHECK3-NEXT: [[TMP24:%.*]] = inttoptr i32 [[TMP17]] to ptr
-// CHECK3-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 4
-// CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
-// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP25]], align 4
-// CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
-// CHECK3-NEXT: store ptr [[TMP18]], ptr [[TMP26]], align 4
-// CHECK3-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP28]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5, i32 0)
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP29:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP30:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP29]], [[TMP30]]
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP31:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP32:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP31]], [[TMP32]]
-// CHECK3-NEXT: store i32 [[ADD7]], ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: [[TMP33:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP34:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP33]], [[TMP34]]
-// CHECK3-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP35:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP36:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[TMP35]], [[TMP36]]
-// CHECK3-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]]
-// CHECK3: cond.true10:
-// CHECK3-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: br label [[COND_END12:%.*]]
-// CHECK3: cond.false11:
-// CHECK3-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: br label [[COND_END12]]
-// CHECK3: cond.end12:
-// CHECK3-NEXT: [[COND13:%.*]] = phi i32 [ [[TMP37]], [[COND_TRUE10]] ], [ [[TMP38]], [[COND_FALSE11]] ]
-// CHECK3-NEXT: store i32 [[COND13]], ptr [[DOTOMP_COMB_UB]], align 4
-// CHECK3-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP39]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTOMP_COMB_LB]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTOMP_COMB_UB]], align 4
+// CHECK3-NEXT: [[TMP7:%.*]] = load i32, ptr [[N_ADDR]], align 4
+// CHECK3-NEXT: store i32 [[TMP7]], ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[N_CASTED]], align 4
+// CHECK3-NEXT: [[TMP9:%.*]] = load ptr, ptr [[V_ADDR]], align 4
+// CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 0
+// CHECK3-NEXT: [[TMP11:%.*]] = inttoptr i32 [[TMP5]] to ptr
+// CHECK3-NEXT: store ptr [[TMP11]], ptr [[TMP10]], align 4
+// CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 1
+// CHECK3-NEXT: [[TMP13:%.*]] = inttoptr i32 [[TMP6]] to ptr
+// CHECK3-NEXT: store ptr [[TMP13]], ptr [[TMP12]], align 4
+// CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 2
+// CHECK3-NEXT: [[TMP15:%.*]] = inttoptr i32 [[TMP8]] to ptr
+// CHECK3-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 4
+// CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 3
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[TMP16]], align 4
+// CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [5 x ptr], ptr [[CAPTURED_VARS_ADDRS]], i32 0, i32 4
+// CHECK3-NEXT: store ptr [[TMP9]], ptr [[TMP17]], align 4
+// CHECK3-NEXT: [[TMP18:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
+// CHECK3-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP18]], align 4
+// CHECK3-NEXT: call void @__kmpc_parallel_60(ptr @[[GLOB1]], i32 [[TMP19]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS]], i32 5, i32 0)
// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP40:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP41:%.*]] = load i32, ptr [[TMP40]], align 4
-// CHECK3-NEXT: call void @__kmpc_distribute_static_fini(ptr @[[GLOB2]], i32 [[TMP41]])
// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
// CHECK3: omp.precond.end:
// CHECK3-NEXT: ret void
//
//
// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined
-// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR3]] {
+// CHECK3-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[DOTPREVIOUS_LB_:%.*]], i32 noundef [[DOTPREVIOUS_UB_:%.*]], i32 noundef [[N:%.*]], ptr noundef nonnull align 4 dereferenceable(4000) [[A:%.*]], ptr noundef [[V:%.*]]) #[[ATTR2]] {
// CHECK3-NEXT: entry:
+// CHECK3-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8
// CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 4
// CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4
@@ -3728,11 +3156,6 @@ int bar(int n){
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4
// CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4
-// CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4
// CHECK3-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR]], align 4
// CHECK3-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR]], align 4
// CHECK3-NEXT: store i32 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR]], align 4
@@ -3748,59 +3171,57 @@ int bar(int n){
// CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1
// CHECK3-NEXT: store i32 [[SUB2]], ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[I]], align 4
-// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_]], align 4
-// CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]]
-// CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// CHECK3: omp.precond.then:
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
-// CHECK3-NEXT: store i32 [[TMP4]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[DOTPREVIOUS_LB__ADDR]], align 4
-// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: store i32 [[TMP5]], ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP6]], ptr [[DOTOMP_UB]], align 4
-// CHECK3-NEXT: store i32 1, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST]], align 4
-// CHECK3-NEXT: [[TMP7:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_init_4(ptr @[[GLOB3]], i32 [[TMP8]], i32 33, ptr [[DOTOMP_IS_LAST]], ptr [[DOTOMP_LB]], ptr [[DOTOMP_UB]], ptr [[DOTOMP_STRIDE]], i32 1, i32 1)
-// CHECK3-NEXT: [[TMP9:%.*]] = load i32, ptr [[DOTOMP_LB]], align 4
-// CHECK3-NEXT: store i32 [[TMP9]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// CHECK3: omp.inner.for.cond:
-// CHECK3-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTPREVIOUS_UB__ADDR]], align 4
-// CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]]
-// CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// CHECK3: omp.inner.for.body:
-// CHECK3-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP12]], 1
-// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// CHECK3-NEXT: store i32 [[ADD]], ptr [[I3]], align 4
-// CHECK3-NEXT: [[TMP13:%.*]] = load ptr, ptr [[V_ADDR]], align 4
-// CHECK3-NEXT: [[TMP14:%.*]] = load i32, ptr [[I3]], align 4
-// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP13]], i32 [[TMP14]]
-// CHECK3-NEXT: [[TMP15:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// CHECK3-NEXT: [[TMP16:%.*]] = load i32, ptr [[I3]], align 4
-// CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [1000 x i32], ptr [[TMP0]], i32 0, i32 [[TMP16]]
-// CHECK3-NEXT: store i32 [[TMP15]], ptr [[ARRAYIDX5]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_1]], align 4
+// CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP3]], 1
+// CHECK3-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// CHECK3: omp_loop.preheader:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 0
+// CHECK3-NEXT: store ptr [[DOTOMP_IV]], ptr [[GEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 1
+// CHECK3-NEXT: store ptr [[I]], ptr [[GEP_I]], align 4
+// CHECK3-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 2
+// CHECK3-NEXT: store ptr [[V_ADDR]], ptr [[GEP_V_ADDR]], align 4
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[STRUCTARG]], i32 0, i32 3
+// CHECK3-NEXT: store ptr [[TMP0]], ptr [[GEP_]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = call i32 @omp_get_num_threads()
+// CHECK3-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr @[[GLOB2]], ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG]], i32 [[ADD]], i32 [[TMP4]], i32 0, i32 0, i8 0)
+// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// CHECK3: omp_loop.exit:
+// CHECK3-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1]])
+// CHECK3-NEXT: call void @__kmpc_barrier(ptr @[[GLOB3]], i32 [[OMP_GLOBAL_THREAD_NUM]])
+// CHECK3-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// CHECK3: omp_loop.after:
+// CHECK3-NEXT: ret void
+//
+//
+// CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l53_omp_outlined_omp_outlined..omp_par
+// CHECK3-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3]] {
+// CHECK3-NEXT: omp_loop.body:
+// CHECK3-NEXT: [[GEP__OMP_IV:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// CHECK3-NEXT: [[LOADGEP__OMP_IV:%.*]] = load ptr, ptr [[GEP__OMP_IV]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_I:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// CHECK3-NEXT: [[LOADGEP_I:%.*]] = load ptr, ptr [[GEP_I]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_V_ADDR:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// CHECK3-NEXT: [[LOADGEP_V_ADDR:%.*]] = load ptr, ptr [[GEP_V_ADDR]], align 4, !align [[META10]]
+// CHECK3-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// CHECK3-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 4, !align [[META10]]
+// CHECK3-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV]], align 4
+// CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 0, [[MUL]]
+// CHECK3-NEXT: store i32 [[ADD3]], ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[TMP3:%.*]] = load ptr, ptr [[LOADGEP_V_ADDR]], align 4
+// CHECK3-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i32 [[TMP4]]
+// CHECK3-NEXT: [[TMP5:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// CHECK3-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_I]], align 4
+// CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [1000 x i32], ptr [[LOADGEP_]], i32 0, i32 [[TMP6]]
+// CHECK3-NEXT: store i32 [[TMP5]], ptr [[ARRAYIDX4]], align 4
// CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// CHECK3: omp.body.continue:
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// CHECK3: omp.inner.for.inc:
-// CHECK3-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: [[TMP18:%.*]] = load i32, ptr [[DOTOMP_STRIDE]], align 4
-// CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP17]], [[TMP18]]
-// CHECK3-NEXT: store i32 [[ADD6]], ptr [[DOTOMP_IV]], align 4
-// CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]]
-// CHECK3: omp.inner.for.end:
-// CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// CHECK3: omp.loop.exit:
-// CHECK3-NEXT: [[TMP19:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR]], align 4
-// CHECK3-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 4
-// CHECK3-NEXT: call void @__kmpc_for_static_fini(ptr @[[GLOB3]], i32 [[TMP20]])
-// CHECK3-NEXT: br label [[OMP_PRECOND_END]]
-// CHECK3: omp.precond.end:
+// CHECK3-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// CHECK3: omp_loop.body.cont:
+// CHECK3-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// CHECK3: omp.prelatch.exitStub:
// CHECK3-NEXT: ret void
//
diff --git a/clang/test/OpenMP/target_loop_promotion.cpp b/clang/test/OpenMP/target_loop_promotion.cpp
new file mode 100644
index 00000000000000..0a3dccdcf34a6e
--- /dev/null
+++ b/clang/test/OpenMP/target_loop_promotion.cpp
@@ -0,0 +1,444 @@
+// REQUIRES: amdgpu-registered-target
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux-gnu \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-host.bc
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux-gnu \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa \
+// RUN: -fopenmp-assume-teams-oversubscription \
+// RUN: -fopenmp-assume-threads-oversubscription \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=HOST
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux-gnu \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -o - | FileCheck %s \
+// RUN: --check-prefix=HOST-NOFLAGS --implicit-check-not=omp.tripcount
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
+// RUN: -fopenmp-host-ir-file-path %t-host.bc \
+// RUN: -fopenmp-assume-teams-oversubscription \
+// RUN: -fopenmp-assume-threads-oversubscription \
+// RUN: -emit-llvm %s -o - | FileCheck %s \
+// RUN: --check-prefixes=CHECK,NOLOOP
+
+// RUN: %clang_cc1 -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
+// RUN: -fopenmp-host-ir-file-path %t-host.bc \
+// RUN: -fopenmp-assume-teams-oversubscription \
+// RUN: -fopenmp-assume-threads-oversubscription \
+// RUN: -emit-pch %s -o %t.pch
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
+// RUN: -fopenmp-host-ir-file-path %t-host.bc \
+// RUN: -fopenmp-assume-teams-oversubscription \
+// RUN: -fopenmp-assume-threads-oversubscription \
+// RUN: -include-pch %t.pch -emit-llvm %s -o - | FileCheck %s \
+// RUN: --check-prefixes=CHECK,NOLOOP
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
+// RUN: -fopenmp-host-ir-file-path %t-host.bc \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,STRIDED
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
+// RUN: -fopenmp-host-ir-file-path %t-host.bc \
+// RUN: -fopenmp-assume-teams-oversubscription \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,STRIDED
+
+// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
+// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
+// RUN: -fopenmp-host-ir-file-path %t-host.bc \
+// RUN: -fopenmp-assume-threads-oversubscription \
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,STRIDED
+
+// expected-no-diagnostics
+
+#ifndef HEADER
+#define HEADER
+
+int foo(int i);
+
+void promotable_no_loop(int *array, int n, int c) {
+#pragma omp target teams distribute parallel for
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for simd
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for nowait
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for
+ for (int i = 0; i < n; ++i)
+ array[i] = i + 1;
+
+ {
+ int tmp;
+#pragma omp target teams distribute parallel for private(tmp)
+ for (int i = 0; i < 1024; ++i) {
+ tmp = i + 1;
+ array[i] = tmp;
+ }
+ }
+
+ {
+ auto set = [&array](int i) { array[i] = i + 1; };
+#pragma omp target teams distribute parallel for
+ for (int i = 0; i < 1024; ++i)
+ set(i);
+ }
+
+ {
+ int i;
+#pragma omp target teams distribute parallel for lastprivate(i)
+ for (i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+ }
+
+ {
+ int last = 0;
+#pragma omp target teams distribute parallel for lastprivate(last)
+ for (int i = 0; i < 1024; ++i) {
+ array[i] = i + 1;
+ last = i;
+ }
+ }
+
+ {
+ int last = 0;
+#pragma omp target teams distribute parallel for lastprivate(last) nowait
+ for (int i = 0; i < 1024; ++i) {
+ array[i] = i + 1;
+ last = i;
+ }
+ }
+
+ {
+ int i;
+#pragma omp target teams distribute parallel for simd linear(i)
+ for (i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+ }
+
+#pragma omp target teams loop
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target
+ {
+#pragma omp teams loop
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+ }
+
+#pragma omp target teams
+ {
+#pragma omp distribute parallel for
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+ }
+
+#pragma omp target
+ {
+#pragma omp teams
+ {
+#pragma omp distribute parallel for
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+ }
+ }
+
+#pragma omp target teams distribute parallel for schedule(static, 1)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for schedule(auto)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for if(parallel : 1)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for if(1)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for if(target : c)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+}
+
+void promotable_strided(int *array) {
+#pragma omp target teams distribute parallel for num_teams(3)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams num_teams(3)
+ {
+#pragma omp distribute parallel for
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+ }
+}
+
+void non_promotable(int *array, int c) {
+#pragma omp target teams distribute parallel for collapse(2)
+ for (int i = 0; i < 32; ++i)
+ for (int j = 0; j < 32; ++j)
+ array[i * 32 + j] = i + j;
+
+#pragma omp target teams distribute parallel for schedule(static)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for schedule(guided)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for dist_schedule(static)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for
+ for (int i = 0; i < 1024; ++i) {
+ array[i] = i + 1;
+#pragma omp cancel for
+ }
+
+#pragma omp target
+ {
+#pragma omp teams loop
+ for (int i = 0; i < 1024; ++i)
+ array[i] = foo(i);
+ }
+
+#pragma omp target teams distribute parallel for if(parallel : c)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams distribute parallel for if(c)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+
+#pragma omp target teams
+ {
+#pragma omp distribute parallel for if(parallel : c)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+ }
+
+#pragma omp target teams loop if(c)
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + 1;
+}
+
+#pragma omp declare target
+static int offset = 1;
+#pragma omp end declare target
+
+void promotable_after_reduction(int *array) {
+ int sum = 0;
+#pragma omp target teams distribute parallel for reduction(+ : sum)
+ for (int i = 0; i < 1024; ++i)
+ sum += array[i];
+
+#pragma omp target teams distribute parallel for
+ for (int i = 0; i < 1024; ++i)
+ array[i] = i + offset;
+}
+
+#endif
+
+// NOLOOP-COUNT-19: promotable_no_loop{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 6
+// NOLOOP-COUNT-2: promotable_strided{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+// NOLOOP-COUNT-10: non_promotable{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
+// NOLOOP: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
+// NOLOOP: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 6
+
+// STRIDED-COUNT-19: promotable_no_loop{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+// STRIDED-COUNT-2: promotable_strided{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+// STRIDED-COUNT-10: non_promotable{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
+// STRIDED: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
+// STRIDED: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+
+// reduction before a promoted kernel
+// CHECK: @llvm.compiler.used = {{.*}}$ref
+// CHECK-NOT: @llvm.compiler.used.
+
+// empty range reports a zero trip count
+// HOST-LABEL: define {{.*}}@_Z18promotable_no_loopPiii(
+// HOST: %.omp.tripcount = alloca i64
+// HOST: store i64 0, ptr %.omp.tripcount
+// HOST: br i1 {{.*}}, label %omp.tripcount.then, label %omp.tripcount.end
+// HOST: omp.tripcount.then:
+// HOST: store i64 {{.*}}, ptr %.omp.tripcount
+// HOST: omp.tripcount.end:
+// HOST: load i64, ptr %.omp.tripcount
+
+// HOST-NOFLAGS-LABEL: define {{.*}}@_Z18promotable_no_loopPiii(
+
+// no clause
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l64_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l64_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l64_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// simd
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l68_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: store i32 1024, ptr %i
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l68_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l68_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// nowait
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l72_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l72_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l72_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.exit:
+// CHECK-NEXT: br label %omp_loop.after
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// runtime trip count
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l76_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: br label %omp.precond.end
+// CHECK: [[LAST:%.*]] = load i32, ptr %.capture_expr.1.ascast
+// CHECK-NEXT: [[TC:%.*]] = add nsw i32 [[LAST]], 1
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l76_{{.*}}, i32 [[TC]], i32 %{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l76_{{.*}}, i32 [[TC]], i32 %{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// private
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l82_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// CHECK: store ptr %tmp1.ascast, ptr addrspace(5) %gep_tmp1.ascast
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l82_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l82_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+// CHECK: store i32 {{.*}}, ptr %loadgep_tmp1.ascast
+
+// lambda
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l91_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// CHECK: [[SET:%.*]] = load ptr, ptr %set.addr.ascast
+// CHECK-NEXT: [[FIELD:%.*]] = getelementptr inbounds nuw %class.anon, ptr [[SET]], i32 0, i32 0
+// CHECK-NEXT: store ptr %array.addr.ascast, ptr [[FIELD]]
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l91_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l91_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// lastprivate loop counter
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l98_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: store i32 1024, ptr %i
+// CHECK-NEXT: @__kmpc_free_shared(ptr %i{{.*}})
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l98_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l98_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: @__kmpc_barrier
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// lastprivate scalar
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l105_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: @__kmpc_free_shared(ptr %last{{.*}})
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l105_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l105_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: @__kmpc_barrier
+// CHECK: store {{.*}}, ptr %last.
+// CHECK-NEXT: %.omp.lastprivate.done
+
+// lastprivate scalar, nowait
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l114_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: @__kmpc_free_shared(ptr %last{{.*}})
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l114_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l114_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: @__kmpc_barrier
+// CHECK: store {{.*}}, ptr %last.
+// CHECK-NEXT: %.omp.lastprivate.done
+
+// simd linear loop counter
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l123_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: store i32 1024, ptr %i
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l123_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l123_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// target teams loop
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l128_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l128_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l128_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// target + teams loop
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l132_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l132_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l132_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// target teams + distribute parallel for
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l139_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l139_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l139_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// target + teams + distribute parallel for
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l146_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l146_{{.*}}, i32 0, i32 0, i8 1)
+// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l146_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// num_teams(3)
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_strided{{.*}}_l178_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// CHECK: @__kmpc_distribute_for_static_loop_4u({{.*}}_l178_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
+
+// num_teams(3)
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_strided{{.*}}_l182_{{.*}})
+// CHECK: omp.loop.exit:
+// CHECK-NEXT: ret void
+// CHECK: @__kmpc_distribute_for_static_loop_4u({{.*}}_l182_{{.*}}, i32 0, i32 0, i8 0)
+// CHECK: omp_loop.after:
+// CHECK-NEXT: ret void
diff --git a/clang/test/OpenMP/target_no_loop.cpp b/clang/test/OpenMP/target_no_loop.cpp
deleted file mode 100644
index 1001547a47baf1..00000000000000
--- a/clang/test/OpenMP/target_no_loop.cpp
+++ /dev/null
@@ -1,356 +0,0 @@
-// REQUIRES: amdgpu-registered-target
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux-gnu \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm-bc %s -o %t-host.bc
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux-gnu \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa \
-// RUN: -fopenmp-assume-teams-oversubscription \
-// RUN: -fopenmp-assume-threads-oversubscription \
-// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefix=HOST
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-linux-gnu \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -emit-llvm %s -o - | FileCheck %s \
-// RUN: --check-prefix=HOST-NOFLAGS --implicit-check-not=omp.tripcount
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
-// RUN: -fopenmp-host-ir-file-path %t-host.bc \
-// RUN: -fopenmp-assume-teams-oversubscription \
-// RUN: -fopenmp-assume-threads-oversubscription \
-// RUN: -emit-llvm %s -o - | FileCheck %s \
-// RUN: --check-prefixes=NOLOOP
-
-// RUN: %clang_cc1 -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
-// RUN: -fopenmp-host-ir-file-path %t-host.bc \
-// RUN: -fopenmp-assume-teams-oversubscription \
-// RUN: -fopenmp-assume-threads-oversubscription \
-// RUN: -emit-pch %s -o %t.pch
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
-// RUN: -fopenmp-host-ir-file-path %t-host.bc \
-// RUN: -fopenmp-assume-teams-oversubscription \
-// RUN: -fopenmp-assume-threads-oversubscription \
-// RUN: -include-pch %t.pch -emit-llvm %s -o - | FileCheck %s \
-// RUN: --check-prefixes=NOLOOP
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
-// RUN: -fopenmp-host-ir-file-path %t-host.bc \
-// RUN: -emit-llvm %s -o - | FileCheck %s \
-// RUN: --check-prefix=SPMD --implicit-check-not=__kmpc_distribute_for_static_loop_4u
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
-// RUN: -fopenmp-host-ir-file-path %t-host.bc \
-// RUN: -fopenmp-assume-teams-oversubscription \
-// RUN: -emit-llvm %s -o - | FileCheck %s \
-// RUN: --check-prefix=SPMD --implicit-check-not=__kmpc_distribute_for_static_loop_4u
-
-// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
-// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
-// RUN: -fopenmp-host-ir-file-path %t-host.bc \
-// RUN: -fopenmp-assume-threads-oversubscription \
-// RUN: -emit-llvm %s -o - | FileCheck %s \
-// RUN: --check-prefix=SPMD --implicit-check-not=__kmpc_distribute_for_static_loop_4u
-
-// expected-no-diagnostics
-
-#ifndef HEADER
-#define HEADER
-
-int foo(int i);
-
-void promotable_no_loop(int *array, int n) {
-#pragma omp target teams distribute parallel for
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for simd
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for nowait
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for
- for (int i = 0; i < n; ++i)
- array[i] = i + 1;
-
- {
- int tmp;
-#pragma omp target teams distribute parallel for private(tmp)
- for (int i = 0; i < 1024; ++i) {
- tmp = i + 1;
- array[i] = tmp;
- }
- }
-
- {
- auto set = [&array](int i) { array[i] = i + 1; };
-#pragma omp target teams distribute parallel for
- for (int i = 0; i < 1024; ++i)
- set(i);
- }
-
-#pragma omp target teams distribute parallel for if(1)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
- {
- int i;
-#pragma omp target teams distribute parallel for lastprivate(i)
- for (i = 0; i < 1024; ++i)
- array[i] = i + 1;
- }
-
- {
- int last = 0;
-#pragma omp target teams distribute parallel for lastprivate(last)
- for (int i = 0; i < 1024; ++i) {
- array[i] = i + 1;
- last = i;
- }
- }
-
- {
- int last = 0;
-#pragma omp target teams distribute parallel for lastprivate(last) nowait
- for (int i = 0; i < 1024; ++i) {
- array[i] = i + 1;
- last = i;
- }
- }
-
- {
- int i;
-#pragma omp target teams distribute parallel for simd linear(i)
- for (i = 0; i < 1024; ++i)
- array[i] = i + 1;
- }
-
-#pragma omp target teams loop
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target
- {
-#pragma omp teams loop
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
- }
-
-#pragma omp target teams
- {
-#pragma omp distribute parallel for
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
- }
-
-#pragma omp target
- {
-#pragma omp teams
- {
-#pragma omp distribute parallel for
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
- }
- }
-
-#pragma omp target teams distribute parallel for schedule(static, 1)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for schedule(auto)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-}
-
-void non_promotable(int *array, int n) {
-#pragma omp target teams distribute parallel for collapse(2)
- for (int i = 0; i < 32; ++i)
- for (int j = 0; j < 32; ++j)
- array[i * 32 + j] = i + j;
-
-#pragma omp target teams distribute parallel for schedule(static)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for schedule(guided)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for dist_schedule(static)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for
- for (int i = 0; i < 1024; ++i) {
- array[i] = i + 1;
-#pragma omp cancel for
- }
-
-#pragma omp target teams distribute parallel for if(parallel: n > 0)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target teams distribute parallel for if(n > 0)
- for (int i = 0; i < 1024; ++i)
- array[i] = i + 1;
-
-#pragma omp target
- {
-#pragma omp teams loop
- for (int i = 0; i < 1024; ++i)
- array[i] = foo(i);
- }
-}
-
-#pragma omp declare target
-static int offset = 1;
-#pragma omp end declare target
-
-void promotable_after_reduction(int *array) {
- int sum = 0;
-#pragma omp target teams distribute parallel for reduction(+ : sum)
- for (int i = 0; i < 1024; ++i)
- sum += array[i];
-
-#pragma omp target teams distribute parallel for
- for (int i = 0; i < 1024; ++i)
- array[i] = i + offset;
-}
-
-#endif
-
-// NOLOOP-COUNT-17: promotable_no_loop{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 6
-// NOLOOP-COUNT-8: non_promotable{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
-// NOLOOP: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
-// NOLOOP: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 6
-
-// SPMD-COUNT-17: promotable_no_loop{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
-// SPMD-COUNT-8: non_promotable{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
-// SPMD-COUNT-2: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
-
-// reduction before a promoted kernel
-// NOLOOP: @llvm.compiler.used = {{.*}}$ref
-// NOLOOP-NOT: @llvm.compiler.used.
-
-// empty range reports a zero trip count
-// HOST-LABEL: define {{.*}}@_Z18promotable_no_loopPii(
-// HOST: %.omp.tripcount = alloca i64
-// HOST: store i64 0, ptr %.omp.tripcount
-// HOST: br i1 {{.*}}, label %omp.tripcount.then, label %omp.tripcount.end
-// HOST: omp.tripcount.then:
-// HOST: store i64 {{.*}}, ptr %.omp.tripcount
-// HOST: omp.tripcount.end:
-// HOST: load i64, ptr %.omp.tripcount
-
-// HOST-NOFLAGS-LABEL: define {{.*}}@_Z18promotable_no_loopPii(
-
-// no clause
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l67_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: ret void
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l67_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-
-// simd
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l71_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: store i32 1024, ptr %i
-// NOLOOP-NEXT: ret void
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l71_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-
-// nowait
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l75_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: ret void
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l75_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: omp_loop.exit:
-// NOLOOP-NEXT: br label %omp_loop.after
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-
-// runtime trip count
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l79_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: br label %omp.precond.end
-// NOLOOP: [[LAST:%.*]] = load i32, ptr %.capture_expr.1.ascast
-// NOLOOP-NEXT: [[TC:%.*]] = add nsw i32 [[LAST]], 1
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l79_{{.*}}, i32 [[TC]], i32 %{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-
-// private
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l85_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: ret void
-// NOLOOP: store ptr %tmp1.ascast, ptr addrspace(5) %gep_tmp1.ascast
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l85_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-// NOLOOP: store i32 {{.*}}, ptr %loadgep_tmp1.ascast
-
-// lambda
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l94_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: ret void
-// NOLOOP: [[SET:%.*]] = load ptr, ptr %set.addr.ascast
-// NOLOOP-NEXT: [[FIELD:%.*]] = getelementptr inbounds nuw %class.anon, ptr [[SET]], i32 0, i32 0
-// NOLOOP-NEXT: store ptr %array.addr.ascast, ptr [[FIELD]]
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l94_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-
-// lastprivate loop counter
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l105_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: store i32 1024, ptr %i
-// NOLOOP-NEXT: @__kmpc_free_shared(ptr %i{{.*}})
-// NOLOOP-NEXT: ret void
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l105_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: @__kmpc_barrier
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-
-// lastprivate scalar
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l112_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: @__kmpc_free_shared(ptr %last{{.*}})
-// NOLOOP-NEXT: ret void
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l112_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: @__kmpc_barrier
-// NOLOOP: store {{.*}}, ptr %last.
-// NOLOOP-NEXT: %.omp.lastprivate.done
-
-// lastprivate scalar, nowait
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l121_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: @__kmpc_free_shared(ptr %last{{.*}})
-// NOLOOP-NEXT: ret void
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l121_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: @__kmpc_barrier
-// NOLOOP: store {{.*}}, ptr %last.
-// NOLOOP-NEXT: %.omp.lastprivate.done
-
-// simd linear loop counter
-// NOLOOP-LABEL: @__kmpc_parallel_60({{.*}}promotable_no_loop{{.*}}_l130_{{.*}})
-// NOLOOP: omp.loop.exit:
-// NOLOOP-NEXT: store i32 1024, ptr %i
-// NOLOOP-NEXT: ret void
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l130_{{.*}}, i32 0, i32 0, i8 1)
-// NOLOOP: omp_loop.after:
-// NOLOOP-NEXT: ret void
-
-// target teams loop
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}promotable_no_loop{{.*}}_l135_{{.*}})
-
-// target + teams loop
-// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}promotable_no_loop{{.*}}_l139_{{.*}})
diff --git a/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
index a16e3942526c56..bcbf81e918fab2 100644
--- a/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
+++ b/clang/test/OpenMP/target_teams_generic_loop_codegen_as_parallel_for.cpp
@@ -111,7 +111,7 @@ int main()
// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
// IR-GPU-NEXT: store i32 [[TMP5]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4
// IR-GPU-NEXT: [[TMP8:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
-// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined(ptr [[TMP8]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2:[0-9]+]]
+// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined(ptr [[TMP8]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR4:[0-9]+]]
// IR-GPU-NEXT: call void @__kmpc_target_deinit()
// IR-GPU-NEXT: ret void
// IR-GPU: worker.exit:
@@ -187,105 +187,47 @@ int main()
// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// IR-GPU-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// IR-GPU-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
-// IR-GPU-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// IR-GPU: cond.true:
-// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END:%.*]]
-// IR-GPU: cond.false:
-// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END]]
-// IR-GPU: cond.end:
-// IR-GPU-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
-// IR-GPU-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// IR-GPU: omp.inner.for.cond:
-// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
-// IR-GPU-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
-// IR-GPU-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// IR-GPU: omp.inner.for.body:
-// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP21]], ptr addrspace(5) [[N_CASTED]], align 4
-// IR-GPU-NEXT: [[TMP22:%.*]] = load i64, ptr addrspace(5) [[N_CASTED]], align 8
-// IR-GPU-NEXT: [[TMP23:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
-// IR-GPU-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP18]] to ptr
+// IR-GPU-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
+// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: store i32 [[TMP12]], ptr addrspace(5) [[N_CASTED]], align 4
+// IR-GPU-NEXT: [[TMP13:%.*]] = load i64, ptr addrspace(5) [[N_CASTED]], align 8
+// IR-GPU-NEXT: [[TMP14:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
+// IR-GPU-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP9]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP15]], ptr [[TMP14]], align 8
+// IR-GPU-NEXT: [[TMP16:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
+// IR-GPU-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP11]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
+// IR-GPU-NEXT: [[TMP18:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
+// IR-GPU-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP13]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8
+// IR-GPU-NEXT: [[TMP20:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
+// IR-GPU-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP0]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
+// IR-GPU-NEXT: [[TMP22:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4
+// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP22]], align 8
+// IR-GPU-NEXT: [[TMP23:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5
+// IR-GPU-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP2]] to ptr
// IR-GPU-NEXT: store ptr [[TMP24]], ptr [[TMP23]], align 8
-// IR-GPU-NEXT: [[TMP25:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
-// IR-GPU-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP20]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8
-// IR-GPU-NEXT: [[TMP27:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
-// IR-GPU-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP22]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8
-// IR-GPU-NEXT: [[TMP29:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
-// IR-GPU-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP0]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP30]], ptr [[TMP29]], align 8
-// IR-GPU-NEXT: [[TMP31:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4
-// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP31]], align 8
-// IR-GPU-NEXT: [[TMP32:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5
-// IR-GPU-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP2]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP33]], ptr [[TMP32]], align 8
-// IR-GPU-NEXT: [[TMP34:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6
-// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP34]], align 8
-// IR-GPU-NEXT: [[TMP35:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP36:%.*]] = load i32, ptr [[TMP35]], align 4
-// IR-GPU-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP36]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 7, i32 0)
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// IR-GPU: omp.inner.for.inc:
-// IR-GPU-NEXT: [[TMP37:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP38:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP37]], [[TMP38]]
-// IR-GPU-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP39:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP40:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP39]], [[TMP40]]
-// IR-GPU-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP41]], [[TMP42]]
-// IR-GPU-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], [[TMP44]]
-// IR-GPU-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
-// IR-GPU: cond.true12:
-// IR-GPU-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END14:%.*]]
-// IR-GPU: cond.false13:
-// IR-GPU-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END14]]
-// IR-GPU: cond.end14:
-// IR-GPU-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP45]], [[COND_TRUE12]] ], [ [[TMP46]], [[COND_FALSE13]] ]
-// IR-GPU-NEXT: store i32 [[COND15]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP47]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]]
-// IR-GPU: omp.inner.for.end:
+// IR-GPU-NEXT: [[TMP25:%.*]] = getelementptr inbounds [7 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6
+// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP25]], align 8
+// IR-GPU-NEXT: [[TMP26:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// IR-GPU-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP26]], align 4
+// IR-GPU-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP27]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 7, i32 0)
// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// IR-GPU: omp.loop.exit:
-// IR-GPU-NEXT: [[TMP48:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP49:%.*]] = load i32, ptr [[TMP48]], align 4
-// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP49]])
// IR-GPU-NEXT: br label [[OMP_PRECOND_END]]
// IR-GPU: omp.precond.end:
// IR-GPU-NEXT: ret void
//
//
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined
-// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR3:[0-9]+]] {
+// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2:[0-9]+]] {
// IR-GPU-NEXT: entry:
+// IR-GPU-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr }, align 8, addrspace(5)
+// IR-GPU-NEXT: [[STRUCTARG_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[STRUCTARG]] to ptr
// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5)
@@ -300,11 +242,6 @@ int main()
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[J6:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTPREVIOUS_LB__ADDR]] to ptr
@@ -319,11 +256,6 @@ int main()
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr
// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
-// IR-GPU-NEXT: [[J6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J6]] to ptr
// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store i64 [[DOTPREVIOUS_LB_]], ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
@@ -344,64 +276,59 @@ int main()
// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
-// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]]
-// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// IR-GPU: omp.precond.then:
-// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32
-// IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
-// IR-GPU-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
-// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// IR-GPU: omp.inner.for.cond:
-// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
-// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[CMP8:%.*]] = icmp ule i64 [[CONV7]], [[TMP14]]
-// IR-GPU-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// IR-GPU: omp.inner.for.body:
-// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
-// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// IR-GPU-NEXT: store i32 [[ADD]], ptr [[J6_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[J6_ASCAST]], align 4
-// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP16]] to i64
-// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]]
-// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[J6_ASCAST]], align 4
-// IR-GPU-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP18]] to i64
-// IR-GPU-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM9]]
-// IR-GPU-NEXT: store i32 [[TMP17]], ptr [[ARRAYIDX10]], align 4
+// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
+// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
+// IR-GPU-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// IR-GPU: omp_loop.preheader:
+// IR-GPU-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 0
+// IR-GPU-NEXT: store ptr [[DOTOMP_IV_ASCAST]], ptr addrspace(5) [[GEP__OMP_IV_ASCAST]], align 8
+// IR-GPU-NEXT: [[GEP_J_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 1
+// IR-GPU-NEXT: store ptr [[J_ASCAST]], ptr addrspace(5) [[GEP_J_ASCAST]], align 8
+// IR-GPU-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 2
+// IR-GPU-NEXT: store ptr [[TMP3]], ptr addrspace(5) [[GEP_]], align 8
+// IR-GPU-NEXT: [[GEP_8:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 3
+// IR-GPU-NEXT: store ptr [[TMP1]], ptr addrspace(5) [[GEP_8]], align 8
+// IR-GPU-NEXT: [[TMP7:%.*]] = call i32 @omp_get_num_threads()
+// IR-GPU-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr addrspacecast (ptr addrspace(1) @[[GLOB2:[0-9]+]] to ptr), ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG_ASCAST]], i32 [[ADD]], i32 [[TMP7]], i32 0, i32 0, i8 0)
+// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// IR-GPU: omp_loop.exit:
+// IR-GPU-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr))
+// IR-GPU-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB3:[0-9]+]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]])
+// IR-GPU-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// IR-GPU: omp_loop.after:
+// IR-GPU-NEXT: ret void
+//
+//
+// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_omp_outlined_omp_outlined..omp_par
+// IR-GPU-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3:[0-9]+]] {
+// IR-GPU-NEXT: omp_loop.body:
+// IR-GPU-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// IR-GPU-NEXT: [[LOADGEP__OMP_IV_ASCAST:%.*]] = load ptr, ptr [[GEP__OMP_IV_ASCAST]], align 8, !align [[META8]]
+// IR-GPU-NEXT: [[GEP_J_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// IR-GPU-NEXT: [[LOADGEP_J_ASCAST:%.*]] = load ptr, ptr [[GEP_J_ASCAST]], align 8, !align [[META8]]
+// IR-GPU-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// IR-GPU-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META8]]
+// IR-GPU-NEXT: [[GEP_1:%.*]] = getelementptr { ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// IR-GPU-NEXT: [[LOADGEP_2:%.*]] = load ptr, ptr [[GEP_1]], align 8, !align [[META8]]
+// IR-GPU-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// IR-GPU-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// IR-GPU-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]]
+// IR-GPU-NEXT: store i32 [[ADD5]], ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP3]] to i64
+// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_]], i64 [[IDXPROM]]
+// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP5]] to i64
+// IR-GPU-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_2]], i64 [[IDXPROM6]]
+// IR-GPU-NEXT: store i32 [[TMP4]], ptr [[ARRAYIDX7]], align 4
// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// IR-GPU: omp.body.continue:
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// IR-GPU: omp.inner.for.inc:
-// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP20:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD11:%.*]] = add nsw i32 [[TMP19]], [[TMP20]]
-// IR-GPU-NEXT: store i32 [[ADD11]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]]
-// IR-GPU: omp.inner.for.end:
-// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// IR-GPU: omp.loop.exit:
-// IR-GPU-NEXT: [[TMP21:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[TMP21]], align 4
-// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP22]])
-// IR-GPU-NEXT: br label [[OMP_PRECOND_END]]
-// IR-GPU: omp.precond.end:
+// IR-GPU-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// IR-GPU: omp_loop.body.cont:
+// IR-GPU-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// IR-GPU: omp.prelatch.exitStub:
// IR-GPU-NEXT: ret void
//
//
@@ -445,7 +372,7 @@ int main()
// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
// IR-GPU-NEXT: store i32 [[TMP5]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4
// IR-GPU-NEXT: [[TMP8:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
-// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined(ptr [[TMP8]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2]]
+// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined(ptr [[TMP8]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR4]]
// IR-GPU-NEXT: call void @__kmpc_target_deinit()
// IR-GPU-NEXT: ret void
// IR-GPU: worker.exit:
@@ -545,7 +472,7 @@ int main()
// IR-GPU-NEXT: [[CONV13:%.*]] = zext i32 [[NVPTX_NUM_THREADS]] to i64
// IR-GPU-NEXT: [[TMP11:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 4
-// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP12]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 [[CONV13]])
+// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB4:[0-9]+]] to ptr), i32 [[TMP12]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 [[CONV13]])
// IR-GPU-NEXT: [[TMP13:%.*]] = load i64, ptr [[DOTOMP_COMB_UB_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTCAPTURE_EXPR_5_ASCAST]], align 8
// IR-GPU-NEXT: [[CMP14:%.*]] = icmp sgt i64 [[TMP13]], [[TMP14]]
@@ -631,14 +558,14 @@ int main()
// IR-GPU: omp.loop.exit:
// IR-GPU-NEXT: [[TMP49:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP50:%.*]] = load i32, ptr [[TMP49]], align 4
-// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP50]])
+// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB4]] to ptr), i32 [[TMP50]])
// IR-GPU-NEXT: br label [[OMP_PRECOND_END]]
// IR-GPU: omp.precond.end:
// IR-GPU-NEXT: ret void
//
//
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l46_omp_outlined_omp_outlined
-// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR3]] {
+// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] {
// IR-GPU-NEXT: entry:
// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
@@ -735,7 +662,7 @@ int main()
// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// IR-GPU-NEXT: [[TMP13:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 4
-// IR-GPU-NEXT: call void @__kmpc_for_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP14]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 1)
+// IR-GPU-NEXT: call void @__kmpc_for_static_init_8(ptr addrspacecast (ptr addrspace(1) @[[GLOB5:[0-9]+]] to ptr), i32 [[TMP14]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i64 1, i64 1)
// IR-GPU-NEXT: [[TMP15:%.*]] = load i64, ptr [[DOTOMP_LB_ASCAST]], align 8
// IR-GPU-NEXT: store i64 [[TMP15]], ptr [[DOTOMP_IV_ASCAST]], align 8
// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
@@ -801,14 +728,14 @@ int main()
// IR-GPU: omp.loop.exit:
// IR-GPU-NEXT: [[TMP31:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: [[TMP32:%.*]] = load i32, ptr [[TMP31]], align 4
-// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP32]])
+// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB5]] to ptr), i32 [[TMP32]])
// IR-GPU-NEXT: br label [[OMP_PRECOND_END]]
// IR-GPU: omp.precond.end:
// IR-GPU-NEXT: ret void
//
//
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55
-// IR-GPU-SAME: (i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR5:[0-9]+]] {
+// IR-GPU-SAME: (i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]], ptr noalias noundef [[DYN_PTR:%.*]]) #[[ATTR7:[0-9]+]] {
// IR-GPU-NEXT: entry:
// IR-GPU-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
// IR-GPU-NEXT: [[NT_ADDR:%.*]] = alloca i64, align 8, addrspace(5)
@@ -854,7 +781,7 @@ int main()
// IR-GPU-NEXT: store i32 0, ptr [[DOTZERO_ADDR_ASCAST]], align 4
// IR-GPU-NEXT: store i32 [[TMP5]], ptr addrspace(5) [[DOTTHREADID_TEMP_]], align 4
// IR-GPU-NEXT: [[TMP10:%.*]] = addrspacecast ptr addrspace(5) [[DOTTHREADID_TEMP_]] to ptr
-// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined(ptr [[TMP10]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR2]]
+// IR-GPU-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined(ptr [[TMP10]], ptr [[DOTZERO_ADDR_ASCAST]], i64 [[TMP7]], i64 [[TMP9]], i64 [[TMP0]], ptr [[TMP1]], i64 [[TMP2]], ptr [[TMP3]]) #[[ATTR4]]
// IR-GPU-NEXT: call void @__kmpc_target_deinit()
// IR-GPU-NEXT: ret void
// IR-GPU: worker.exit:
@@ -934,111 +861,53 @@ int main()
// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
// IR-GPU-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @__kmpc_get_hardware_num_threads_in_block()
-// IR-GPU-NEXT: [[TMP8:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
-// IR-GPU-NEXT: call void @__kmpc_distribute_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP9]], i32 91, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_COMB_LB_ASCAST]], ptr [[DOTOMP_COMB_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 [[NVPTX_NUM_THREADS]])
+// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
+// IR-GPU-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP10]], [[TMP11]]
-// IR-GPU-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]]
-// IR-GPU: cond.true:
-// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END:%.*]]
-// IR-GPU: cond.false:
-// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END]]
-// IR-GPU: cond.end:
-// IR-GPU-NEXT: [[COND:%.*]] = phi i32 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ]
-// IR-GPU-NEXT: store i32 [[COND]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP14]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// IR-GPU: omp.inner.for.cond:
-// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP16]], 1
-// IR-GPU-NEXT: [[CMP7:%.*]] = icmp slt i32 [[TMP15]], [[ADD]]
-// IR-GPU-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// IR-GPU: omp.inner.for.body:
-// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP18:%.*]] = zext i32 [[TMP17]] to i64
-// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP20:%.*]] = zext i32 [[TMP19]] to i64
-// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP21]], ptr addrspace(5) [[N_CASTED]], align 4
-// IR-GPU-NEXT: [[TMP22:%.*]] = load i64, ptr addrspace(5) [[N_CASTED]], align 8
-// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP23]], ptr addrspace(5) [[NT_CASTED]], align 4
-// IR-GPU-NEXT: [[TMP24:%.*]] = load i64, ptr addrspace(5) [[NT_CASTED]], align 8
-// IR-GPU-NEXT: [[TMP25:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
-// IR-GPU-NEXT: [[TMP26:%.*]] = inttoptr i64 [[TMP18]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP26]], ptr [[TMP25]], align 8
-// IR-GPU-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
-// IR-GPU-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP20]] to ptr
+// IR-GPU-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
+// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: store i32 [[TMP12]], ptr addrspace(5) [[N_CASTED]], align 4
+// IR-GPU-NEXT: [[TMP13:%.*]] = load i64, ptr addrspace(5) [[N_CASTED]], align 8
+// IR-GPU-NEXT: [[TMP14:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: store i32 [[TMP14]], ptr addrspace(5) [[NT_CASTED]], align 4
+// IR-GPU-NEXT: [[TMP15:%.*]] = load i64, ptr addrspace(5) [[NT_CASTED]], align 8
+// IR-GPU-NEXT: [[TMP16:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 0
+// IR-GPU-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP9]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP17]], ptr [[TMP16]], align 8
+// IR-GPU-NEXT: [[TMP18:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 1
+// IR-GPU-NEXT: [[TMP19:%.*]] = inttoptr i64 [[TMP11]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP19]], ptr [[TMP18]], align 8
+// IR-GPU-NEXT: [[TMP20:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
+// IR-GPU-NEXT: [[TMP21:%.*]] = inttoptr i64 [[TMP13]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP21]], ptr [[TMP20]], align 8
+// IR-GPU-NEXT: [[TMP22:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
+// IR-GPU-NEXT: [[TMP23:%.*]] = inttoptr i64 [[TMP15]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP23]], ptr [[TMP22]], align 8
+// IR-GPU-NEXT: [[TMP24:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4
+// IR-GPU-NEXT: [[TMP25:%.*]] = inttoptr i64 [[TMP0]] to ptr
+// IR-GPU-NEXT: store ptr [[TMP25]], ptr [[TMP24]], align 8
+// IR-GPU-NEXT: [[TMP26:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5
+// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP26]], align 8
+// IR-GPU-NEXT: [[TMP27:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6
+// IR-GPU-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP2]] to ptr
// IR-GPU-NEXT: store ptr [[TMP28]], ptr [[TMP27]], align 8
-// IR-GPU-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 2
-// IR-GPU-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP22]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP30]], ptr [[TMP29]], align 8
-// IR-GPU-NEXT: [[TMP31:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 3
-// IR-GPU-NEXT: [[TMP32:%.*]] = inttoptr i64 [[TMP24]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP32]], ptr [[TMP31]], align 8
-// IR-GPU-NEXT: [[TMP33:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 4
-// IR-GPU-NEXT: [[TMP34:%.*]] = inttoptr i64 [[TMP0]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP34]], ptr [[TMP33]], align 8
-// IR-GPU-NEXT: [[TMP35:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 5
-// IR-GPU-NEXT: store ptr [[TMP1]], ptr [[TMP35]], align 8
-// IR-GPU-NEXT: [[TMP36:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 6
-// IR-GPU-NEXT: [[TMP37:%.*]] = inttoptr i64 [[TMP2]] to ptr
-// IR-GPU-NEXT: store ptr [[TMP37]], ptr [[TMP36]], align 8
-// IR-GPU-NEXT: [[TMP38:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 7
-// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP38]], align 8
-// IR-GPU-NEXT: [[TMP39:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP40:%.*]] = load i32, ptr [[TMP39]], align 4
-// IR-GPU-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP40]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 8, i32 0)
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// IR-GPU: omp.inner.for.inc:
-// IR-GPU-NEXT: [[TMP41:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP42:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP41]], [[TMP42]]
-// IR-GPU-NEXT: store i32 [[ADD8]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP43:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP44:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP43]], [[TMP44]]
-// IR-GPU-NEXT: store i32 [[ADD9]], ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP45:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP46:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP45]], [[TMP46]]
-// IR-GPU-NEXT: store i32 [[ADD10]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP47:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP48:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP47]], [[TMP48]]
-// IR-GPU-NEXT: br i1 [[CMP11]], label [[COND_TRUE12:%.*]], label [[COND_FALSE13:%.*]]
-// IR-GPU: cond.true12:
-// IR-GPU-NEXT: [[TMP49:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END14:%.*]]
-// IR-GPU: cond.false13:
-// IR-GPU-NEXT: [[TMP50:%.*]] = load i32, ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[COND_END14]]
-// IR-GPU: cond.end14:
-// IR-GPU-NEXT: [[COND15:%.*]] = phi i32 [ [[TMP49]], [[COND_TRUE12]] ], [ [[TMP50]], [[COND_FALSE13]] ]
-// IR-GPU-NEXT: store i32 [[COND15]], ptr [[DOTOMP_COMB_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP51:%.*]] = load i32, ptr [[DOTOMP_COMB_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP51]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]]
-// IR-GPU: omp.inner.for.end:
+// IR-GPU-NEXT: [[TMP29:%.*]] = getelementptr inbounds [8 x ptr], ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 0, i64 7
+// IR-GPU-NEXT: store ptr [[TMP3]], ptr [[TMP29]], align 8
+// IR-GPU-NEXT: [[TMP30:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
+// IR-GPU-NEXT: [[TMP31:%.*]] = load i32, ptr [[TMP30]], align 4
+// IR-GPU-NEXT: call void @__kmpc_parallel_60(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr), i32 [[TMP31]], i32 1, i32 -1, i32 -1, ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined, ptr null, ptr [[CAPTURED_VARS_ADDRS_ASCAST]], i64 8, i32 0)
// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
// IR-GPU: omp.loop.exit:
-// IR-GPU-NEXT: [[TMP52:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP53:%.*]] = load i32, ptr [[TMP52]], align 4
-// IR-GPU-NEXT: call void @__kmpc_distribute_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), i32 [[TMP53]])
// IR-GPU-NEXT: br label [[OMP_PRECOND_END]]
// IR-GPU: omp.precond.end:
// IR-GPU-NEXT: ret void
//
//
// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined
-// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR3]] {
+// IR-GPU-SAME: (ptr noalias noundef [[DOTGLOBAL_TID_:%.*]], ptr noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[DOTPREVIOUS_LB_:%.*]], i64 noundef [[DOTPREVIOUS_UB_:%.*]], i64 noundef [[N:%.*]], i64 noundef [[NT:%.*]], i64 noundef [[VLA:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[A:%.*]], i64 noundef [[VLA1:%.*]], ptr noundef nonnull align 4 dereferenceable(4) [[B:%.*]]) #[[ATTR2]] {
// IR-GPU-NEXT: entry:
+// IR-GPU-NEXT: [[STRUCTARG:%.*]] = alloca { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, align 8, addrspace(5)
+// IR-GPU-NEXT: [[STRUCTARG_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[STRUCTARG]] to ptr
// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca ptr, align 8, addrspace(5)
// IR-GPU-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8, addrspace(5)
@@ -1054,11 +923,6 @@ int main()
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-NEXT: [[I:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4, addrspace(5)
-// IR-GPU-NEXT: [[I6:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-NEXT: [[J:%.*]] = alloca i32, align 4, addrspace(5)
// IR-GPU-NEXT: [[DOTGLOBAL_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTGLOBAL_TID__ADDR]] to ptr
// IR-GPU-NEXT: [[DOTBOUND_TID__ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTBOUND_TID__ADDR]] to ptr
@@ -1075,11 +939,6 @@ int main()
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR__ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_]] to ptr
// IR-GPU-NEXT: [[DOTCAPTURE_EXPR_3_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTCAPTURE_EXPR_3]] to ptr
// IR-GPU-NEXT: [[I_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_LB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_LB]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_UB_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_UB]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_STRIDE_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_STRIDE]] to ptr
-// IR-GPU-NEXT: [[DOTOMP_IS_LAST_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[DOTOMP_IS_LAST]] to ptr
-// IR-GPU-NEXT: [[I6_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[I6]] to ptr
// IR-GPU-NEXT: [[J_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[J]] to ptr
// IR-GPU-NEXT: store ptr [[DOTGLOBAL_TID_]], ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
// IR-GPU-NEXT: store ptr [[DOTBOUND_TID_]], ptr [[DOTBOUND_TID__ADDR_ASCAST]], align 8
@@ -1102,91 +961,98 @@ int main()
// IR-GPU-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1
// IR-GPU-NEXT: [[SUB4:%.*]] = sub nsw i32 [[DIV]], 1
// IR-GPU-NEXT: store i32 [[SUB4]], ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 0, ptr [[I_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR__ASCAST]], align 4
-// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP6]]
-// IR-GPU-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]]
-// IR-GPU: omp.precond.then:
-// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_LB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP7]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP8:%.*]] = load i64, ptr [[DOTPREVIOUS_LB__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[CONV:%.*]] = trunc i64 [[TMP8]] to i32
-// IR-GPU-NEXT: [[TMP9:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[CONV5:%.*]] = trunc i64 [[TMP9]] to i32
-// IR-GPU-NEXT: store i32 [[CONV]], ptr [[DOTOMP_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[CONV5]], ptr [[DOTOMP_UB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 1, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 0, ptr [[DOTOMP_IS_LAST_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP10:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4
-// IR-GPU-NEXT: call void @__kmpc_for_static_init_4(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP11]], i32 33, ptr [[DOTOMP_IS_LAST_ASCAST]], ptr [[DOTOMP_LB_ASCAST]], ptr [[DOTOMP_UB_ASCAST]], ptr [[DOTOMP_STRIDE_ASCAST]], i32 1, i32 1)
-// IR-GPU-NEXT: [[TMP12:%.*]] = load i32, ptr [[DOTOMP_LB_ASCAST]], align 4
-// IR-GPU-NEXT: store i32 [[TMP12]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND:%.*]]
-// IR-GPU: omp.inner.for.cond:
-// IR-GPU-NEXT: [[TMP13:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[CONV7:%.*]] = sext i32 [[TMP13]] to i64
-// IR-GPU-NEXT: [[TMP14:%.*]] = load i64, ptr [[DOTPREVIOUS_UB__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[CMP8:%.*]] = icmp ule i64 [[CONV7]], [[TMP14]]
-// IR-GPU-NEXT: br i1 [[CMP8]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]]
-// IR-GPU: omp.inner.for.body:
-// IR-GPU-NEXT: [[TMP15:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP15]], 1
-// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]]
-// IR-GPU-NEXT: store i32 [[ADD]], ptr [[I6_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP16:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4
-// IR-GPU-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP16]], 0
+// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[DOTCAPTURE_EXPR_3_ASCAST]], align 4
+// IR-GPU-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
+// IR-GPU-NEXT: br label [[OMP_LOOP_PREHEADER:%.*]]
+// IR-GPU: omp_loop.preheader:
+// IR-GPU-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 0
+// IR-GPU-NEXT: store ptr [[DOTOMP_IV_ASCAST]], ptr addrspace(5) [[GEP__OMP_IV_ASCAST]], align 8
+// IR-GPU-NEXT: [[GEP_I_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 1
+// IR-GPU-NEXT: store ptr [[I_ASCAST]], ptr addrspace(5) [[GEP_I_ASCAST]], align 8
+// IR-GPU-NEXT: [[GEP_NT_ADDR_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 2
+// IR-GPU-NEXT: store ptr [[NT_ADDR_ASCAST]], ptr addrspace(5) [[GEP_NT_ADDR_ASCAST]], align 8
+// IR-GPU-NEXT: [[GEP_J_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 3
+// IR-GPU-NEXT: store ptr [[J_ASCAST]], ptr addrspace(5) [[GEP_J_ASCAST]], align 8
+// IR-GPU-NEXT: [[GEP_N_ADDR_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 4
+// IR-GPU-NEXT: store ptr [[N_ADDR_ASCAST]], ptr addrspace(5) [[GEP_N_ADDR_ASCAST]], align 8
+// IR-GPU-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 5
+// IR-GPU-NEXT: store ptr [[TMP3]], ptr addrspace(5) [[GEP_]], align 8
+// IR-GPU-NEXT: [[GEP_10:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr addrspace(5) [[STRUCTARG]], i32 0, i32 6
+// IR-GPU-NEXT: store ptr [[TMP1]], ptr addrspace(5) [[GEP_10]], align 8
+// IR-GPU-NEXT: [[TMP7:%.*]] = call i32 @omp_get_num_threads()
+// IR-GPU-NEXT: call void @__kmpc_distribute_for_static_loop_4u(ptr addrspacecast (ptr addrspace(1) @[[GLOB2]] to ptr), ptr @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined..omp_par, ptr [[STRUCTARG_ASCAST]], i32 [[ADD]], i32 [[TMP7]], i32 0, i32 0, i8 0)
+// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
+// IR-GPU: omp_loop.exit:
+// IR-GPU-NEXT: [[OMP_GLOBAL_THREAD_NUM:%.*]] = call i32 @__kmpc_global_thread_num(ptr addrspacecast (ptr addrspace(1) @[[GLOB1]] to ptr))
+// IR-GPU-NEXT: call void @__kmpc_barrier(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[OMP_GLOBAL_THREAD_NUM]])
+// IR-GPU-NEXT: br label [[OMP_LOOP_AFTER:%.*]]
+// IR-GPU: omp_loop.after:
+// IR-GPU-NEXT: ret void
+//
+//
+// IR-GPU-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l55_omp_outlined_omp_outlined..omp_par
+// IR-GPU-SAME: (i32 [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR3]] {
+// IR-GPU-NEXT: omp_loop.body:
+// IR-GPU-NEXT: [[GEP__OMP_IV_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 0
+// IR-GPU-NEXT: [[LOADGEP__OMP_IV_ASCAST:%.*]] = load ptr, ptr [[GEP__OMP_IV_ASCAST]], align 8, !align [[META8]]
+// IR-GPU-NEXT: [[GEP_I_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 1
+// IR-GPU-NEXT: [[LOADGEP_I_ASCAST:%.*]] = load ptr, ptr [[GEP_I_ASCAST]], align 8, !align [[META8]]
+// IR-GPU-NEXT: [[GEP_NT_ADDR_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 2
+// IR-GPU-NEXT: [[LOADGEP_NT_ADDR_ASCAST:%.*]] = load ptr, ptr [[GEP_NT_ADDR_ASCAST]], align 8, !align [[META9:![0-9]+]]
+// IR-GPU-NEXT: [[GEP_J_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 3
+// IR-GPU-NEXT: [[LOADGEP_J_ASCAST:%.*]] = load ptr, ptr [[GEP_J_ASCAST]], align 8, !align [[META8]]
+// IR-GPU-NEXT: [[GEP_N_ADDR_ASCAST:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 4
+// IR-GPU-NEXT: [[LOADGEP_N_ADDR_ASCAST:%.*]] = load ptr, ptr [[GEP_N_ADDR_ASCAST]], align 8, !align [[META9]]
+// IR-GPU-NEXT: [[GEP_:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 5
+// IR-GPU-NEXT: [[LOADGEP_:%.*]] = load ptr, ptr [[GEP_]], align 8, !align [[META8]]
+// IR-GPU-NEXT: [[GEP_1:%.*]] = getelementptr { ptr, ptr, ptr, ptr, ptr, ptr, ptr }, ptr [[TMP1]], i32 0, i32 6
+// IR-GPU-NEXT: [[LOADGEP_2:%.*]] = load ptr, ptr [[GEP_1]], align 8, !align [[META8]]
+// IR-GPU-NEXT: store i32 [[TMP0]], ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// IR-GPU-NEXT: [[TMP2:%.*]] = load i32, ptr [[LOADGEP__OMP_IV_ASCAST]], align 4
+// IR-GPU-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP2]], 1
+// IR-GPU-NEXT: [[ADD5:%.*]] = add nsw i32 0, [[MUL]]
+// IR-GPU-NEXT: store i32 [[ADD5]], ptr [[LOADGEP_I_ASCAST]], align 4
+// IR-GPU-NEXT: [[TMP3:%.*]] = load i32, ptr [[LOADGEP_NT_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0
// IR-GPU-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]]
// IR-GPU: if.then:
-// IR-GPU-NEXT: [[CALL:%.*]] = call noundef i32 @_Z17omp_get_num_teamsv() #[[ATTR7:[0-9]+]]
-// IR-GPU-NEXT: store i32 [[CALL]], ptr [[NT_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: [[CALL:%.*]] = call noundef i32 @_Z17omp_get_num_teamsv() #[[ATTR9:[0-9]+]]
+// IR-GPU-NEXT: store i32 [[CALL]], ptr [[LOADGEP_NT_ADDR_ASCAST]], align 4
// IR-GPU-NEXT: br label [[IF_END]]
// IR-GPU: if.end:
-// IR-GPU-NEXT: store i32 0, ptr [[J_ASCAST]], align 4
+// IR-GPU-NEXT: store i32 0, ptr [[LOADGEP_J_ASCAST]], align 4
// IR-GPU-NEXT: br label [[FOR_COND:%.*]]
// IR-GPU: for.cond:
-// IR-GPU-NEXT: [[TMP17:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP18:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
-// IR-GPU-NEXT: [[CMP9:%.*]] = icmp slt i32 [[TMP17]], [[TMP18]]
-// IR-GPU-NEXT: br i1 [[CMP9]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
-// IR-GPU: for.body:
-// IR-GPU-NEXT: [[TMP19:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64
-// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[TMP3]], i64 [[IDXPROM]]
-// IR-GPU-NEXT: [[TMP20:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
-// IR-GPU-NEXT: [[TMP21:%.*]] = load i32, ptr [[N_ADDR_ASCAST]], align 4
-// IR-GPU-NEXT: [[MUL10:%.*]] = mul nsw i32 [[TMP20]], [[TMP21]]
-// IR-GPU-NEXT: [[TMP22:%.*]] = load i32, ptr [[NT_ADDR_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD11:%.*]] = add nsw i32 [[MUL10]], [[TMP22]]
-// IR-GPU-NEXT: [[TMP23:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// IR-GPU-NEXT: [[IDXPROM12:%.*]] = sext i32 [[TMP23]] to i64
-// IR-GPU-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[IDXPROM12]]
-// IR-GPU-NEXT: store i32 [[ADD11]], ptr [[ARRAYIDX13]], align 4
-// IR-GPU-NEXT: br label [[FOR_INC:%.*]]
-// IR-GPU: for.inc:
-// IR-GPU-NEXT: [[TMP24:%.*]] = load i32, ptr [[J_ASCAST]], align 4
-// IR-GPU-NEXT: [[INC:%.*]] = add nsw i32 [[TMP24]], 1
-// IR-GPU-NEXT: store i32 [[INC]], ptr [[J_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]]
+// IR-GPU-NEXT: [[TMP4:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: [[TMP5:%.*]] = load i32, ptr [[LOADGEP_N_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP4]], [[TMP5]]
+// IR-GPU-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]]
// IR-GPU: for.end:
// IR-GPU-NEXT: br label [[OMP_BODY_CONTINUE:%.*]]
// IR-GPU: omp.body.continue:
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_INC:%.*]]
-// IR-GPU: omp.inner.for.inc:
-// IR-GPU-NEXT: [[TMP25:%.*]] = load i32, ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: [[TMP26:%.*]] = load i32, ptr [[DOTOMP_STRIDE_ASCAST]], align 4
-// IR-GPU-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP25]], [[TMP26]]
-// IR-GPU-NEXT: store i32 [[ADD14]], ptr [[DOTOMP_IV_ASCAST]], align 4
-// IR-GPU-NEXT: br label [[OMP_INNER_FOR_COND]]
-// IR-GPU: omp.inner.for.end:
-// IR-GPU-NEXT: br label [[OMP_LOOP_EXIT:%.*]]
-// IR-GPU: omp.loop.exit:
-// IR-GPU-NEXT: [[TMP27:%.*]] = load ptr, ptr [[DOTGLOBAL_TID__ADDR_ASCAST]], align 8
-// IR-GPU-NEXT: [[TMP28:%.*]] = load i32, ptr [[TMP27]], align 4
-// IR-GPU-NEXT: call void @__kmpc_for_static_fini(ptr addrspacecast (ptr addrspace(1) @[[GLOB3]] to ptr), i32 [[TMP28]])
-// IR-GPU-NEXT: br label [[OMP_PRECOND_END]]
-// IR-GPU: omp.precond.end:
+// IR-GPU-NEXT: br label [[OMP_LOOP_BODY_CONT:%.*]]
+// IR-GPU: omp_loop.body.cont:
+// IR-GPU-NEXT: br label [[OMP_PRELATCH_EXITSTUB:%.*]]
+// IR-GPU: for.body:
+// IR-GPU-NEXT: [[TMP6:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP6]] to i64
+// IR-GPU-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_]], i64 [[IDXPROM]]
+// IR-GPU-NEXT: [[TMP7:%.*]] = load i32, ptr [[ARRAYIDX]], align 4
+// IR-GPU-NEXT: [[TMP8:%.*]] = load i32, ptr [[LOADGEP_N_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: [[MUL6:%.*]] = mul nsw i32 [[TMP7]], [[TMP8]]
+// IR-GPU-NEXT: [[TMP9:%.*]] = load i32, ptr [[LOADGEP_NT_ADDR_ASCAST]], align 4
+// IR-GPU-NEXT: [[ADD7:%.*]] = add nsw i32 [[MUL6]], [[TMP9]]
+// IR-GPU-NEXT: [[TMP10:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP10]] to i64
+// IR-GPU-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds i32, ptr [[LOADGEP_2]], i64 [[IDXPROM8]]
+// IR-GPU-NEXT: store i32 [[ADD7]], ptr [[ARRAYIDX9]], align 4
+// IR-GPU-NEXT: br label [[FOR_INC:%.*]]
+// IR-GPU: for.inc:
+// IR-GPU-NEXT: [[TMP11:%.*]] = load i32, ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: [[INC:%.*]] = add nsw i32 [[TMP11]], 1
+// IR-GPU-NEXT: store i32 [[INC]], ptr [[LOADGEP_J_ASCAST]], align 4
+// IR-GPU-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]]
+// IR-GPU: omp.prelatch.exitStub:
// IR-GPU-NEXT: ret void
//
//
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
index c41b4d1e9844ce..78d7ea7e6d0fc1 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
+++ b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
@@ -22,9 +22,10 @@ enum OMPTgtExecModeFlags : unsigned char {
OMP_TGT_EXEC_MODE_BARE = 0,
OMP_TGT_EXEC_MODE_GENERIC = 1 << 0,
OMP_TGT_EXEC_MODE_SPMD = 1 << 1,
- OMP_TGT_EXEC_MODE_GENERIC_SPMD =
- OMP_TGT_EXEC_MODE_GENERIC | OMP_TGT_EXEC_MODE_SPMD,
- OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD
+ OMP_TGT_EXEC_MODE_GENERIC_SPMD = OMP_TGT_EXEC_MODE_GENERIC |
+ OMP_TGT_EXEC_MODE_SPMD,
+ OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD,
+ OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP = 1 << 3 | OMP_TGT_EXEC_MODE_SPMD
};
} // end namespace omp
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
index 83ce9be8dea57b..8cc933c1a222f8 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
+++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def
@@ -483,17 +483,17 @@ __OMP_RTL(__kmpc_kernel_prepare_parallel, false, Void, VoidPtr)
__OMP_RTL(__kmpc_parallel_60, false, Void, IdentPtr, Int32, Int32, Int32, Int32,
FuncPtrTy, FuncPtrTy, VoidPtrPtr, SizeTy, Int32)
__OMP_RTL(__kmpc_for_static_loop_4, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int8)
-__OMP_RTL(__kmpc_for_static_loop_4u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int8)
+__OMP_RTL(__kmpc_for_static_loop_4u, false, Void, IdentPtr, FuncPtrTy, VoidPtr, Int32, Int32, Int32, Int8)
__OMP_RTL(__kmpc_for_static_loop_8, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int64, Int8)
-__OMP_RTL(__kmpc_for_static_loop_8u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int64, Int8)
+__OMP_RTL(__kmpc_for_static_loop_8u, false, Void, IdentPtr, FuncPtrTy, VoidPtr, Int64, Int64, Int64, Int8)
__OMP_RTL(__kmpc_distribute_static_loop_4, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int8)
-__OMP_RTL(__kmpc_distribute_static_loop_4u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int8)
+__OMP_RTL(__kmpc_distribute_static_loop_4u, false, Void, IdentPtr, FuncPtrTy, VoidPtr, Int32, Int32, Int8)
__OMP_RTL(__kmpc_distribute_static_loop_8, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int8)
-__OMP_RTL(__kmpc_distribute_static_loop_8u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int8)
+__OMP_RTL(__kmpc_distribute_static_loop_8u, false, Void, IdentPtr, FuncPtrTy, VoidPtr, Int64, Int64, Int8)
__OMP_RTL(__kmpc_distribute_for_static_loop_4, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int32, Int8)
-__OMP_RTL(__kmpc_distribute_for_static_loop_4u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int32, Int32, Int32, Int32, Int8)
+__OMP_RTL(__kmpc_distribute_for_static_loop_4u, false, Void, IdentPtr, FuncPtrTy, VoidPtr, Int32, Int32, Int32, Int32, Int8)
__OMP_RTL(__kmpc_distribute_for_static_loop_8, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int64, Int64, Int8)
-__OMP_RTL(__kmpc_distribute_for_static_loop_8u, false, Void, IdentPtr, VoidPtr, VoidPtr, Int64, Int64, Int64, Int64, Int8)
+__OMP_RTL(__kmpc_distribute_for_static_loop_8u, false, Void, IdentPtr, FuncPtrTy, VoidPtr, Int64, Int64, Int64, Int64, Int8)
__OMP_RTL(__kmpc_kernel_parallel, false, Int1, VoidPtrPtr)
__OMP_RTL(__kmpc_kernel_end_parallel, false, Void, )
__OMP_RTL(__kmpc_serialized_parallel, false, Void, IdentPtr, Int32)
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 9497d93f217073..33289147b8fde0 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -6543,12 +6543,14 @@ static void createTargetLoopWorkshareCall(OpenMPIRBuilder *OMPBuilder,
Type *TripCountTy = TripCount->getType();
Module &M = OMPBuilder->M;
IRBuilder<> &Builder = OMPBuilder->Builder;
+ Builder.restoreIP(std::prev(InsertBlock->end()));
FunctionCallee RTLFn =
getKmpcForStaticLoopForType(TripCountTy, OMPBuilder, LoopType);
SmallVector<Value *, 8> RealArgs;
RealArgs.push_back(Ident);
RealArgs.push_back(&LoopBodyFn);
- RealArgs.push_back(LoopBodyArg);
+ RealArgs.push_back(Builder.CreatePointerBitCastOrAddrSpaceCast(
+ LoopBodyArg, RTLFn.getFunctionType()->getParamType(2)));
RealArgs.push_back(TripCount);
if (LoopType == WorksharingLoopType::DistributeStaticLoop) {
RealArgs.push_back(ConstantInt::get(TripCountTy, 0));
@@ -8626,7 +8628,8 @@ Constant *OpenMPIRBuilder::emitKernelEnvironment(
Constant *IsSPMDVal = ConstantInt::getSigned(Int8, Attrs.ExecFlags);
Constant *UseGenericStateMachineVal = ConstantInt::getSigned(
Int8, Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD &&
- Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP);
+ Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP &&
+ Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP);
Constant *MayUseNestedParallelismVal = ConstantInt::getSigned(Int8, true);
Constant *DebugIndentionLevelVal = ConstantInt::getSigned(Int16, 0);
diff --git a/offload/include/device.h b/offload/include/device.h
index 39d3a2b40bb4ec..d0a71077edeb2f 100644
--- a/offload/include/device.h
+++ b/offload/include/device.h
@@ -66,6 +66,9 @@ struct KernelLaunchInfoTy {
bool isNoLoopMode() const {
return Mode == llvm::omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP;
}
+ bool isStridedLoopMode() const {
+ return Mode == llvm::omp::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP;
+ }
static const char *getExecutionModeName(llvm::omp::OMPTgtExecModeFlags Mode) {
switch (Mode) {
@@ -79,6 +82,8 @@ struct KernelLaunchInfoTy {
return "Generic-SPMD";
case llvm::omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP:
return "SPMD-No-Loop";
+ case llvm::omp::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP:
+ return "SPMD-Strided-Loop";
}
return "Unknown";
}
diff --git a/offload/libompaccsupport/device.cpp b/offload/libompaccsupport/device.cpp
index 2cf9f8c1fec884..bec23ef85ecc52 100644
--- a/offload/libompaccsupport/device.cpp
+++ b/offload/libompaccsupport/device.cpp
@@ -775,7 +775,7 @@ static uint32_t getEffectiveNumBlocks(
uint64_t DefaultNumBlocks = Props.DefaultNumBlocks;
uint64_t TripCountNumBlocks = std::numeric_limits<uint64_t>::max();
if (LoopTripCount > 0) {
- if (KernelEnv.isSPMDMode()) {
+ if (KernelEnv.isSPMDMode() || KernelEnv.isStridedLoopMode()) {
// We have a combined construct, i.e. `target teams distribute
// parallel for [simd]`. We launch so many blocks so that each thread
// will execute one iteration of the loop; rounded up to the nearest
diff --git a/offload/plugins-nextgen/common/include/PluginInterface.h b/offload/plugins-nextgen/common/include/PluginInterface.h
index a387e246be4b2d..c92400ee814075 100644
--- a/offload/plugins-nextgen/common/include/PluginInterface.h
+++ b/offload/plugins-nextgen/common/include/PluginInterface.h
@@ -447,6 +447,7 @@ struct GenericKernelTy {
case OMP_TGT_EXEC_MODE_GENERIC:
case OMP_TGT_EXEC_MODE_GENERIC_SPMD:
case OMP_TGT_EXEC_MODE_SPMD_NO_LOOP:
+ case OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP:
return true;
}
return false;
diff --git a/offload/test/offloading/gpupgo/pgo_atomic_teams.c b/offload/test/offloading/gpupgo/pgo_atomic_teams.c
index b3b72db080392b..756045f0e066c7 100644
--- a/offload/test/offloading/gpupgo/pgo_atomic_teams.c
+++ b/offload/test/offloading/gpupgo/pgo_atomic_teams.c
@@ -39,63 +39,27 @@ int main() {
}
// clang-format off
-// LLVM-PGO-LABEL: __omp_offloading_{{[_0-9a-zA-Z]*}}_main_{{[_0-9a-zA-Z]*}}:
-// LLVM-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// LLVM-PGO: Counters: 2
-// LLVM-PGO: Block counts: [0, {{.*}}]
-
-// LLVM-PGO-LABEL: __omp_offloading_{{[_0-9a-zA-Z]*}}_main_{{[_0-9a-zA-Z]*}}_omp_outlined:
-// LLVM-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// LLVM-PGO: Counters: 4
-// LLVM-PGO: Block counts: [{{.*}}, 0, {{.*}}, 0]
-
-// LLVM-PGO-LABEL: __omp_offloading_{{[_0-9a-zA-Z]*}}_main_{{[_0-9a-zA-Z]*}}_omp_outlined_omp_outlined:
-// LLVM-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// LLVM-PGO: Counters: 4
-// LLVM-PGO: Block counts: [30, 15, 10, {{.*}}]
+// LLVM-PGO-DAG: {{(\[| )}}30{{(,|\])}}
+// LLVM-PGO-DAG: {{(\[| )}}15{{(,|\])}}
+// LLVM-PGO-DAG: {{(\[| )}}10{{(,|\])}}
// LLVM-PGO-LABEL: test1:
-// LLVM-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// LLVM-PGO: Counters: 1
// LLVM-PGO: Block counts: [15]
// LLVM-PGO-LABEL: test2:
-// LLVM-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// LLVM-PGO: Counters: 1
// LLVM-PGO: Block counts: [10]
// LLVM-PGO-LABEL: Instrumentation level:
// LLVM-PGO-SAME: IR
-// CLANG-PGO-LABEL: __omp_offloading_{{[_0-9a-zA-Z]*}}_main_{{[_0-9a-zA-Z]*}}:
-// CLANG-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// CLANG-PGO: Counters: 1
-// CLANG-PGO: Function count: {{.*}}
-// CLANG-PGO: Block counts: []
-
-// CLANG-PGO-LABEL: __omp_offloading_{{[_0-9a-zA-Z]*}}_main_{{[_0-9a-zA-Z]*}}_omp_outlined:
-// CLANG-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// CLANG-PGO: Counters: 1
-// CLANG-PGO: Function count: {{.*}}
-// CLANG-PGO: Block counts: []
-
-// CLANG-PGO-LABEL: __omp_offloading_{{[_0-9a-zA-Z]*}}_main_{{[_0-9a-zA-Z]*}}_omp_outlined_omp_outlined:
-// CLANG-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// CLANG-PGO: Counters: 4
-// CLANG-PGO: Function count: 30
-// CLANG-PGO: Block counts: [{{.*}}, 15, 10]
+// CLANG-PGO-DAG: {{(\[| )}}15{{(,|\])}}
+// CLANG-PGO-DAG: {{(\[| )}}10{{(,|\])}}
// CLANG-PGO-LABEL: test1:
-// CLANG-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// CLANG-PGO: Counters: 1
// CLANG-PGO: Function count: 15
-// CLANG-PGO: Block counts: []
// CLANG-PGO-LABEL: test2:
-// CLANG-PGO: Hash: {{0[xX][0-9a-fA-F]+}}
-// CLANG-PGO: Counters: 1
// CLANG-PGO: Function count: 10
-// CLANG-PGO: Block counts: []
// CLANG-PGO-LABEL: Instrumentation level:
// CLANG-PGO-SAME: Front-end
diff --git a/offload/test/offloading/small_trip_count.c b/offload/test/offloading/small_trip_count.c
index e9ec8b7103d66b..526cd17e0a4103 100644
--- a/offload/test/offloading/small_trip_count.c
+++ b/offload/test/offloading/small_trip_count.c
@@ -12,26 +12,26 @@
__attribute__((optnone)) void optnone() {}
int main() {
- // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD-Strided-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD-Strided-Loop mode
#pragma omp target teams distribute parallel for simd
for (int i = 0; i < N; ++i) {
optnone();
}
- // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD-Strided-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD-Strided-Loop mode
#pragma omp target teams distribute parallel for simd
for (int i = 0; i < N - 1; ++i) {
optnone();
}
- // DEFAULT: Launching kernel {{.+_main_.+}} with [5,1,1] blocks and [32,1,1] threads in SPMD mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [17,1,1] blocks and [8,1,1] threads in SPMD mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [5,1,1] blocks and [32,1,1] threads in SPMD-Strided-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [17,1,1] blocks and [8,1,1] threads in SPMD-Strided-Loop mode
#pragma omp target teams distribute parallel for simd
for (int i = 0; i < N + 1; ++i) {
optnone();
}
- // DEFAULT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD-Strided-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD-Strided-Loop mode
#pragma omp target teams distribute parallel for simd thread_limit(4)
for (int i = 0; i < N; ++i) {
optnone();
diff --git a/offload/test/offloading/small_trip_count_thread_limit.cpp b/offload/test/offloading/small_trip_count_thread_limit.cpp
index fbd7fe9175d705..795fc3c090c141 100644
--- a/offload/test/offloading/small_trip_count_thread_limit.cpp
+++ b/offload/test/offloading/small_trip_count_thread_limit.cpp
@@ -25,4 +25,4 @@ int main(int argc, char *argv[]) {
return 0;
}
-// CHECK: Launching kernel {{.*}} with [4,1,1] blocks and [256,1,1] threads in SPMD mode
+// CHECK: Launching kernel {{.*}} with [4,1,1] blocks and [256,1,1] threads in SPMD-Strided-Loop mode
diff --git a/offload/test/offloading/target-no-loop.c b/offload/test/offloading/target-no-loop.c
index a3149025044c31..c352b672c40fb3 100644
--- a/offload/test/offloading/target-no-loop.c
+++ b/offload/test/offloading/target-no-loop.c
@@ -30,7 +30,7 @@ int main(void) {
array[i] = i + 1;
errors += check_errors(array);
- // SPMD kernel (num_teams clause blocks promotion to no-loop)
+ // Strided-loop kernel (num_teams clause blocks promotion to no-loop)
for (int i = 0; i < 1024; ++i)
array[i] = 1;
#pragma omp target teams distribute parallel for num_teams(3)
@@ -114,13 +114,26 @@ int main(void) {
++errors;
#endif
+ // Strided-loop kernel with a lastprivate variable
+ for (int i = 0; i < 1024; ++i)
+ array[i] = 1;
+ int strided_last = -1;
+#pragma omp target teams distribute parallel for num_teams(3) lastprivate(strided_last) map(tofrom : strided_last)
+ for (int i = 0; i < 1024; ++i) {
+ array[i] = i + 1;
+ strided_last = i;
+ }
+ errors += check_errors(array);
+ if (strided_last != 1023)
+ ++errors;
+
printf("number of errors: %d\n", errors);
return 0;
}
// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode
// CHECK: info: #Args: 2 Teams x Thrds: 64x 16
-// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD mode
+// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-Strided-Loop mode
// CHECK: info: #Args: 2 Teams x Thrds: 3x 16 {{.*}}
// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode
// CHECK: info: #Args: 2 Teams x Thrds: 64x 16 {{.*}}
@@ -136,4 +149,6 @@ int main(void) {
// CHECK: info: #Args: 3 Teams x Thrds: 64x 16 {{.*}}
// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode
// CHECK: info: #Args: 3 Teams x Thrds: 64x 16 {{.*}}
+// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-Strided-Loop mode
+// CHECK: info: #Args: 3 Teams x Thrds: 3x 16 {{.*}}
// CHECK: number of errors: 0
diff --git a/openmp/device/src/Kernel.cpp b/openmp/device/src/Kernel.cpp
index 2f40e44496c5ed..7774041aabd6fc 100644
--- a/openmp/device/src/Kernel.cpp
+++ b/openmp/device/src/Kernel.cpp
@@ -29,9 +29,10 @@ enum OMPTgtExecModeFlags : unsigned char {
OMP_TGT_EXEC_MODE_BARE = 0,
OMP_TGT_EXEC_MODE_GENERIC = 1 << 0,
OMP_TGT_EXEC_MODE_SPMD = 1 << 1,
- OMP_TGT_EXEC_MODE_GENERIC_SPMD =
- OMP_TGT_EXEC_MODE_GENERIC | OMP_TGT_EXEC_MODE_SPMD,
- OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD
+ OMP_TGT_EXEC_MODE_GENERIC_SPMD = OMP_TGT_EXEC_MODE_GENERIC |
+ OMP_TGT_EXEC_MODE_SPMD,
+ OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD,
+ OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP = 1 << 3 | OMP_TGT_EXEC_MODE_SPMD
};
static void
>From a207c14e1f668661fc04c240d54d6ee7ff71a393 Mon Sep 17 00:00:00 2001
From: Nicole Aschenbrenner <nicole.aschenbrenner at amd.com>
Date: Tue, 20 Oct 2026 09:20:29 -0500
Subject: [PATCH 2/2] [NFC] Change strided loop name
Changes strided loop to be named grid-stride loop instead for less
ambiguity as stride describes the jump distance in general.
---
clang/lib/CodeGen/CGOpenMPRuntime.h | 4 +-
clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp | 10 ++--
clang/lib/CodeGen/CGOpenMPRuntimeGPU.h | 14 ++---
clang/lib/CodeGen/CGStmtOpenMP.cpp | 11 ++--
clang/test/OpenMP/target_loop_promotion.cpp | 52 +++++++++----------
.../llvm/Frontend/OpenMP/OMPDeviceConstants.h | 2 +-
llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 7 +--
offload/include/device.h | 8 +--
offload/libompaccsupport/device.cpp | 2 +-
.../common/include/PluginInterface.h | 2 +-
offload/test/offloading/small_trip_count.c | 16 +++---
.../small_trip_count_thread_limit.cpp | 2 +-
offload/test/offloading/target-no-loop.c | 16 +++---
openmp/device/src/Kernel.cpp | 2 +-
14 files changed, 75 insertions(+), 73 deletions(-)
diff --git a/clang/lib/CodeGen/CGOpenMPRuntime.h b/clang/lib/CodeGen/CGOpenMPRuntime.h
index d931e75e9da37f..156d60b4d1dc1a 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntime.h
+++ b/clang/lib/CodeGen/CGOpenMPRuntime.h
@@ -677,8 +677,8 @@ class CGOpenMPRuntime {
}
/// Check whether \a S is the loop the target kernel being emitted was
- /// promoted for, to complete the promotion to a strided-loop SPMD kernel.
- virtual bool canPromoteToStridedLoop(const OMPLoopDirective &S) const {
+ /// promoted for, to complete the promotion to a grid-stride loop SPMD kernel.
+ virtual bool canPromoteToGridStrideLoop(const OMPLoopDirective &S) const {
return false;
}
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
index 7cc383b76af0b5..86b7c3bb823427 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.cpp
@@ -731,7 +731,7 @@ static bool isPromotableLoopSchedule(ASTContext &Ctx,
void CGOpenMPRuntimeGPU::checkAndSetPromotableLoopDirective(
const OMPExecutableDirective &D) {
NoLoopDirective = nullptr;
- StridedLoopDirective = nullptr;
+ GridStrideLoopDirective = nullptr;
ASTContext &Ctx = CGM.getContext();
const LangOptions &LangOpts = Ctx.getLangOpts();
@@ -783,7 +783,7 @@ void CGOpenMPRuntimeGPU::checkAndSetPromotableLoopDirective(
if (OneIterationPerThread)
NoLoopDirective = LD;
else
- StridedLoopDirective = LD;
+ GridStrideLoopDirective = LD;
};
if (const auto *TTLD = dyn_cast<OMPTargetTeamsGenericLoopDirective>(LD))
@@ -872,9 +872,9 @@ void CGOpenMPRuntimeGPU::emitKernelInit(const OMPExecutableDirective &D,
if (NoLoopDirective)
Attrs.ExecFlags =
llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP;
- else if (StridedLoopDirective)
- Attrs.ExecFlags =
- llvm::omp::OMPTgtExecModeFlags::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP;
+ else if (GridStrideLoopDirective)
+ Attrs.ExecFlags = llvm::omp::OMPTgtExecModeFlags::
+ OMP_TGT_EXEC_MODE_SPMD_GRID_STRIDE_LOOP;
}
computeMinAndMaxThreadsAndTeams(D, CGF, Attrs);
diff --git a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
index 93b95e5908a25b..396bbbe50fe909 100644
--- a/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
+++ b/clang/lib/CodeGen/CGOpenMPRuntimeGPU.h
@@ -64,7 +64,7 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime {
void emitBareKernelEnvironment(const OMPExecutableDirective &D,
CodeGenFunction &CGF);
- /// Set NoLoopDirective or StridedLoopDirective to the loop the SPMD target
+ /// Set NoLoopDirective or GridStrideLoopDirective to the loop the SPMD target
/// directive \a D can be promoted for, resetting both first.
void checkAndSetPromotableLoopDirective(const OMPExecutableDirective &D);
@@ -158,9 +158,9 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime {
}
/// Check whether \a S is the loop the target kernel being emitted was
- /// promoted for, to complete the promotion to a strided-loop SPMD kernel.
- bool canPromoteToStridedLoop(const OMPLoopDirective &S) const override {
- return &S == StridedLoopDirective;
+ /// promoted for, to complete the promotion to a grid-stride loop SPMD kernel.
+ bool canPromoteToGridStrideLoop(const OMPLoopDirective &S) const override {
+ return &S == GridStrideLoopDirective;
}
/// Get call to __kmpc_alloc_shared
@@ -399,9 +399,9 @@ class CGOpenMPRuntimeGPU : public CGOpenMPRuntime {
/// by the kernel prologue and read back while the region's body is emitted.
const OMPLoopDirective *NoLoopDirective = nullptr;
- /// The loop the target region being emitted was promoted to strided-loop
- /// for, set and read like NoLoopDirective.
- const OMPLoopDirective *StridedLoopDirective = nullptr;
+ /// The loop the target region being emitted was promoted to a grid-stride
+ /// loop for, set and read like NoLoopDirective.
+ const OMPLoopDirective *GridStrideLoopDirective = nullptr;
/// Map between an outlined function and its wrapper.
llvm::DenseMap<llvm::Function *, llvm::Function *> WrapperFunctionsMap;
diff --git a/clang/lib/CodeGen/CGStmtOpenMP.cpp b/clang/lib/CodeGen/CGStmtOpenMP.cpp
index 29981c95b475ca..002bfce4964914 100644
--- a/clang/lib/CodeGen/CGStmtOpenMP.cpp
+++ b/clang/lib/CodeGen/CGStmtOpenMP.cpp
@@ -3987,7 +3987,7 @@ emitInnerParallelForWhenCombined(CodeGenFunction &CGF,
CGOpenMPRuntime &RT = CGF.CGM.getOpenMPRuntime();
bool NoLoop = RT.canPromoteToNoLoop(S);
- if (NoLoop || RT.canPromoteToStridedLoop(S)) {
+ if (NoLoop || RT.canPromoteToGridStrideLoop(S)) {
// Prepare the loop variables and their privatization.
emitLoopIterationspaceVars(CGF, S);
OMPLoopScope PreInitScope(CGF, S);
@@ -6638,9 +6638,9 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S,
EmitOMPReductionClauseInit(S, LoopScope);
// Defer lastprivate init to the parallel region for no-loop or
- // strided-loop
+ // grid-stride loop
const bool IsPromotedLoopKernel =
- RT.canPromoteToNoLoop(S) || RT.canPromoteToStridedLoop(S);
+ RT.canPromoteToNoLoop(S) || RT.canPromoteToGridStrideLoop(S);
if (!IsPromotedLoopKernel)
HasLastprivateClause = EmitOMPLastprivateClauseInit(S, LoopScope);
@@ -6671,7 +6671,8 @@ void CodeGenFunction::EmitOMPDistributeLoop(const OMPLoopDirective &S,
// omit the outer distribute loop and let the inner worksharing loop
// schedule the flattened team/thread iteration space, necessary for
- // GPU fused schedule and loop-grid optimization (no-loop & strided-loop).
+ // GPU fused schedule and loop-grid optimization (no-loop & grid-stride
+ // loop).
if (canEmitGPUFusedDistSchedule(CGM, S, S.getDirectiveKind()) ||
IsPromotedLoopKernel) {
JumpDest LoopExit =
@@ -9113,7 +9114,7 @@ emitTeamsGenericLoopAsDistributeParallelFor(CodeGenFunction &CGF,
void CodeGenFunction::EmitOMPTeamsGenericLoopDirective(
const OMPTeamsGenericLoopDirective &S) {
if (CGM.getOpenMPRuntime().canPromoteToNoLoop(S) ||
- CGM.getOpenMPRuntime().canPromoteToStridedLoop(S)) {
+ CGM.getOpenMPRuntime().canPromoteToGridStrideLoop(S)) {
emitTeamsGenericLoopAsDistributeParallelFor(*this, S);
return;
}
diff --git a/clang/test/OpenMP/target_loop_promotion.cpp b/clang/test/OpenMP/target_loop_promotion.cpp
index 0a3dccdcf34a6e..02f5cdd01dfa75 100644
--- a/clang/test/OpenMP/target_loop_promotion.cpp
+++ b/clang/test/OpenMP/target_loop_promotion.cpp
@@ -39,19 +39,19 @@
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
// RUN: -fopenmp-host-ir-file-path %t-host.bc \
-// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,STRIDED
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,GRIDSTRIDE
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
// RUN: -fopenmp-host-ir-file-path %t-host.bc \
// RUN: -fopenmp-assume-teams-oversubscription \
-// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,STRIDED
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,GRIDSTRIDE
// RUN: %clang_cc1 -verify -fopenmp -x c++ -triple amdgcn-amd-amdhsa \
// RUN: -fopenmp-targets=amdgcn-amd-amdhsa -fopenmp-is-target-device \
// RUN: -fopenmp-host-ir-file-path %t-host.bc \
// RUN: -fopenmp-assume-threads-oversubscription \
-// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,STRIDED
+// RUN: -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,GRIDSTRIDE
// expected-no-diagnostics
@@ -174,7 +174,7 @@ void promotable_no_loop(int *array, int n, int c) {
array[i] = i + 1;
}
-void promotable_strided(int *array) {
+void promotable_grid_stride(int *array) {
#pragma omp target teams distribute parallel for num_teams(3)
for (int i = 0; i < 1024; ++i)
array[i] = i + 1;
@@ -256,16 +256,16 @@ void promotable_after_reduction(int *array) {
#endif
// NOLOOP-COUNT-19: promotable_no_loop{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 6
-// NOLOOP-COUNT-2: promotable_strided{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+// NOLOOP-COUNT-2: promotable_grid_stride{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
// NOLOOP-COUNT-10: non_promotable{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
// NOLOOP: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
// NOLOOP: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 6
-// STRIDED-COUNT-19: promotable_no_loop{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
-// STRIDED-COUNT-2: promotable_strided{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
-// STRIDED-COUNT-10: non_promotable{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
-// STRIDED: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
-// STRIDED: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+// GRIDSTRIDE-COUNT-19: promotable_no_loop{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+// GRIDSTRIDE-COUNT-2: promotable_grid_stride{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
+// GRIDSTRIDE-COUNT-10: non_promotable{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
+// GRIDSTRIDE: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 2
+// GRIDSTRIDE: promotable_after_reduction{{.*}}_kernel_environment {{.*}} i8 0, i8 1, i8 10
// reduction before a promoted kernel
// CHECK: @llvm.compiler.used = {{.*}}$ref
@@ -288,7 +288,7 @@ void promotable_after_reduction(int *array) {
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l64_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l64_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l64_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -298,7 +298,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: store i32 1024, ptr %i
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l68_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l68_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l68_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -307,7 +307,7 @@ void promotable_after_reduction(int *array) {
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l72_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l72_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l72_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.exit:
// CHECK-NEXT: br label %omp_loop.after
// CHECK: omp_loop.after:
@@ -320,7 +320,7 @@ void promotable_after_reduction(int *array) {
// CHECK: [[LAST:%.*]] = load i32, ptr %.capture_expr.1.ascast
// CHECK-NEXT: [[TC:%.*]] = add nsw i32 [[LAST]], 1
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l76_{{.*}}, i32 [[TC]], i32 %{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l76_{{.*}}, i32 [[TC]], i32 %{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l76_{{.*}}, i32 [[TC]], i32 %{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -330,7 +330,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: ret void
// CHECK: store ptr %tmp1.ascast, ptr addrspace(5) %gep_tmp1.ascast
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l82_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l82_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l82_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
// CHECK: store i32 {{.*}}, ptr %loadgep_tmp1.ascast
@@ -343,7 +343,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: [[FIELD:%.*]] = getelementptr inbounds nuw %class.anon, ptr [[SET]], i32 0, i32 0
// CHECK-NEXT: store ptr %array.addr.ascast, ptr [[FIELD]]
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l91_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l91_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l91_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -354,7 +354,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: @__kmpc_free_shared(ptr %i{{.*}})
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l98_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l98_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l98_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: @__kmpc_barrier
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -365,7 +365,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: @__kmpc_free_shared(ptr %last{{.*}})
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l105_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l105_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l105_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: @__kmpc_barrier
// CHECK: store {{.*}}, ptr %last.
// CHECK-NEXT: %.omp.lastprivate.done
@@ -376,7 +376,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: @__kmpc_free_shared(ptr %last{{.*}})
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l114_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l114_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l114_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: @__kmpc_barrier
// CHECK: store {{.*}}, ptr %last.
// CHECK-NEXT: %.omp.lastprivate.done
@@ -387,7 +387,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: store i32 1024, ptr %i
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l123_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l123_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l123_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -396,7 +396,7 @@ void promotable_after_reduction(int *array) {
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l128_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l128_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l128_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -405,7 +405,7 @@ void promotable_after_reduction(int *array) {
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l132_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l132_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l132_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -414,7 +414,7 @@ void promotable_after_reduction(int *array) {
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l139_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l139_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l139_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
@@ -423,12 +423,12 @@ void promotable_after_reduction(int *array) {
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// NOLOOP: @__kmpc_distribute_for_static_loop_4u({{.*}}_l146_{{.*}}, i32 0, i32 0, i8 1)
-// STRIDED: @__kmpc_distribute_for_static_loop_4u({{.*}}_l146_{{.*}}, i32 0, i32 0, i8 0)
+// GRIDSTRIDE: @__kmpc_distribute_for_static_loop_4u({{.*}}_l146_{{.*}}, i32 0, i32 0, i8 0)
// CHECK: omp_loop.after:
// CHECK-NEXT: ret void
// num_teams(3)
-// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_strided{{.*}}_l178_{{.*}})
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_grid_stride{{.*}}_l178_{{.*}})
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// CHECK: @__kmpc_distribute_for_static_loop_4u({{.*}}_l178_{{.*}}, i32 0, i32 0, i8 0)
@@ -436,7 +436,7 @@ void promotable_after_reduction(int *array) {
// CHECK-NEXT: ret void
// num_teams(3)
-// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_strided{{.*}}_l182_{{.*}})
+// CHECK-LABEL: @__kmpc_parallel_60({{.*}}promotable_grid_stride{{.*}}_l182_{{.*}})
// CHECK: omp.loop.exit:
// CHECK-NEXT: ret void
// CHECK: @__kmpc_distribute_for_static_loop_4u({{.*}}_l182_{{.*}}, i32 0, i32 0, i8 0)
diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
index 78d7ea7e6d0fc1..aea8da426fa030 100644
--- a/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
+++ b/llvm/include/llvm/Frontend/OpenMP/OMPDeviceConstants.h
@@ -25,7 +25,7 @@ enum OMPTgtExecModeFlags : unsigned char {
OMP_TGT_EXEC_MODE_GENERIC_SPMD = OMP_TGT_EXEC_MODE_GENERIC |
OMP_TGT_EXEC_MODE_SPMD,
OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD,
- OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP = 1 << 3 | OMP_TGT_EXEC_MODE_SPMD
+ OMP_TGT_EXEC_MODE_SPMD_GRID_STRIDE_LOOP = 1 << 3 | OMP_TGT_EXEC_MODE_SPMD
};
} // end namespace omp
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 33289147b8fde0..c7fff915eb0e1e 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -8627,9 +8627,10 @@ Constant *OpenMPIRBuilder::emitKernelEnvironment(
Constant *Ident = getOrCreateIdent(SrcLocStr, SrcLocStrSize);
Constant *IsSPMDVal = ConstantInt::getSigned(Int8, Attrs.ExecFlags);
Constant *UseGenericStateMachineVal = ConstantInt::getSigned(
- Int8, Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD &&
- Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP &&
- Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP);
+ Int8,
+ Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD &&
+ Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP &&
+ Attrs.ExecFlags != omp::OMP_TGT_EXEC_MODE_SPMD_GRID_STRIDE_LOOP);
Constant *MayUseNestedParallelismVal = ConstantInt::getSigned(Int8, true);
Constant *DebugIndentionLevelVal = ConstantInt::getSigned(Int16, 0);
diff --git a/offload/include/device.h b/offload/include/device.h
index d0a71077edeb2f..9184a291aa2d67 100644
--- a/offload/include/device.h
+++ b/offload/include/device.h
@@ -66,8 +66,8 @@ struct KernelLaunchInfoTy {
bool isNoLoopMode() const {
return Mode == llvm::omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP;
}
- bool isStridedLoopMode() const {
- return Mode == llvm::omp::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP;
+ bool isGridStrideLoopMode() const {
+ return Mode == llvm::omp::OMP_TGT_EXEC_MODE_SPMD_GRID_STRIDE_LOOP;
}
static const char *getExecutionModeName(llvm::omp::OMPTgtExecModeFlags Mode) {
@@ -82,8 +82,8 @@ struct KernelLaunchInfoTy {
return "Generic-SPMD";
case llvm::omp::OMP_TGT_EXEC_MODE_SPMD_NO_LOOP:
return "SPMD-No-Loop";
- case llvm::omp::OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP:
- return "SPMD-Strided-Loop";
+ case llvm::omp::OMP_TGT_EXEC_MODE_SPMD_GRID_STRIDE_LOOP:
+ return "SPMD-Grid-Stride-Loop";
}
return "Unknown";
}
diff --git a/offload/libompaccsupport/device.cpp b/offload/libompaccsupport/device.cpp
index bec23ef85ecc52..66c82d318769dd 100644
--- a/offload/libompaccsupport/device.cpp
+++ b/offload/libompaccsupport/device.cpp
@@ -775,7 +775,7 @@ static uint32_t getEffectiveNumBlocks(
uint64_t DefaultNumBlocks = Props.DefaultNumBlocks;
uint64_t TripCountNumBlocks = std::numeric_limits<uint64_t>::max();
if (LoopTripCount > 0) {
- if (KernelEnv.isSPMDMode() || KernelEnv.isStridedLoopMode()) {
+ if (KernelEnv.isSPMDMode() || KernelEnv.isGridStrideLoopMode()) {
// We have a combined construct, i.e. `target teams distribute
// parallel for [simd]`. We launch so many blocks so that each thread
// will execute one iteration of the loop; rounded up to the nearest
diff --git a/offload/plugins-nextgen/common/include/PluginInterface.h b/offload/plugins-nextgen/common/include/PluginInterface.h
index c92400ee814075..b3db42c89e31bf 100644
--- a/offload/plugins-nextgen/common/include/PluginInterface.h
+++ b/offload/plugins-nextgen/common/include/PluginInterface.h
@@ -447,7 +447,7 @@ struct GenericKernelTy {
case OMP_TGT_EXEC_MODE_GENERIC:
case OMP_TGT_EXEC_MODE_GENERIC_SPMD:
case OMP_TGT_EXEC_MODE_SPMD_NO_LOOP:
- case OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP:
+ case OMP_TGT_EXEC_MODE_SPMD_GRID_STRIDE_LOOP:
return true;
}
return false;
diff --git a/offload/test/offloading/small_trip_count.c b/offload/test/offloading/small_trip_count.c
index 526cd17e0a4103..1e51c9d21676d5 100644
--- a/offload/test/offloading/small_trip_count.c
+++ b/offload/test/offloading/small_trip_count.c
@@ -12,26 +12,26 @@
__attribute__((optnone)) void optnone() {}
int main() {
- // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD-Strided-Loop mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD-Strided-Loop mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD-Grid-Stride-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD-Grid-Stride-Loop mode
#pragma omp target teams distribute parallel for simd
for (int i = 0; i < N; ++i) {
optnone();
}
- // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD-Strided-Loop mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD-Strided-Loop mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [4,1,1] blocks and [32,1,1] threads in SPMD-Grid-Stride-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [16,1,1] blocks and [8,1,1] threads in SPMD-Grid-Stride-Loop mode
#pragma omp target teams distribute parallel for simd
for (int i = 0; i < N - 1; ++i) {
optnone();
}
- // DEFAULT: Launching kernel {{.+_main_.+}} with [5,1,1] blocks and [32,1,1] threads in SPMD-Strided-Loop mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [17,1,1] blocks and [8,1,1] threads in SPMD-Strided-Loop mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [5,1,1] blocks and [32,1,1] threads in SPMD-Grid-Stride-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [17,1,1] blocks and [8,1,1] threads in SPMD-Grid-Stride-Loop mode
#pragma omp target teams distribute parallel for simd
for (int i = 0; i < N + 1; ++i) {
optnone();
}
- // DEFAULT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD-Strided-Loop mode
- // EIGHT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD-Strided-Loop mode
+ // DEFAULT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD-Grid-Stride-Loop mode
+ // EIGHT: Launching kernel {{.+_main_.+}} with [32,1,1] blocks and [4,1,1] threads in SPMD-Grid-Stride-Loop mode
#pragma omp target teams distribute parallel for simd thread_limit(4)
for (int i = 0; i < N; ++i) {
optnone();
diff --git a/offload/test/offloading/small_trip_count_thread_limit.cpp b/offload/test/offloading/small_trip_count_thread_limit.cpp
index 795fc3c090c141..8f75fac3838ff3 100644
--- a/offload/test/offloading/small_trip_count_thread_limit.cpp
+++ b/offload/test/offloading/small_trip_count_thread_limit.cpp
@@ -25,4 +25,4 @@ int main(int argc, char *argv[]) {
return 0;
}
-// CHECK: Launching kernel {{.*}} with [4,1,1] blocks and [256,1,1] threads in SPMD-Strided-Loop mode
+// CHECK: Launching kernel {{.*}} with [4,1,1] blocks and [256,1,1] threads in SPMD-Grid-Stride-Loop mode
diff --git a/offload/test/offloading/target-no-loop.c b/offload/test/offloading/target-no-loop.c
index c352b672c40fb3..0fa2dbb163cd3e 100644
--- a/offload/test/offloading/target-no-loop.c
+++ b/offload/test/offloading/target-no-loop.c
@@ -30,7 +30,7 @@ int main(void) {
array[i] = i + 1;
errors += check_errors(array);
- // Strided-loop kernel (num_teams clause blocks promotion to no-loop)
+ // Grid-stride loop kernel (num_teams clause blocks promotion to no-loop)
for (int i = 0; i < 1024; ++i)
array[i] = 1;
#pragma omp target teams distribute parallel for num_teams(3)
@@ -114,17 +114,17 @@ int main(void) {
++errors;
#endif
- // Strided-loop kernel with a lastprivate variable
+ // Grid-stride loop kernel with a lastprivate variable
for (int i = 0; i < 1024; ++i)
array[i] = 1;
- int strided_last = -1;
-#pragma omp target teams distribute parallel for num_teams(3) lastprivate(strided_last) map(tofrom : strided_last)
+ int grid_stride_last = -1;
+#pragma omp target teams distribute parallel for num_teams(3) lastprivate(grid_stride_last) map(tofrom : grid_stride_last)
for (int i = 0; i < 1024; ++i) {
array[i] = i + 1;
- strided_last = i;
+ grid_stride_last = i;
}
errors += check_errors(array);
- if (strided_last != 1023)
+ if (grid_stride_last != 1023)
++errors;
printf("number of errors: %d\n", errors);
@@ -133,7 +133,7 @@ int main(void) {
// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode
// CHECK: info: #Args: 2 Teams x Thrds: 64x 16
-// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-Strided-Loop mode
+// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-Grid-Stride-Loop mode
// CHECK: info: #Args: 2 Teams x Thrds: 3x 16 {{.*}}
// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode
// CHECK: info: #Args: 2 Teams x Thrds: 64x 16 {{.*}}
@@ -149,6 +149,6 @@ int main(void) {
// CHECK: info: #Args: 3 Teams x Thrds: 64x 16 {{.*}}
// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-No-Loop mode
// CHECK: info: #Args: 3 Teams x Thrds: 64x 16 {{.*}}
-// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-Strided-Loop mode
+// CHECK: omptarget device {{[0-9]+}} info: Launching kernel {{.*}} SPMD-Grid-Stride-Loop mode
// CHECK: info: #Args: 3 Teams x Thrds: 3x 16 {{.*}}
// CHECK: number of errors: 0
diff --git a/openmp/device/src/Kernel.cpp b/openmp/device/src/Kernel.cpp
index 7774041aabd6fc..3d4bcadec983b1 100644
--- a/openmp/device/src/Kernel.cpp
+++ b/openmp/device/src/Kernel.cpp
@@ -32,7 +32,7 @@ enum OMPTgtExecModeFlags : unsigned char {
OMP_TGT_EXEC_MODE_GENERIC_SPMD = OMP_TGT_EXEC_MODE_GENERIC |
OMP_TGT_EXEC_MODE_SPMD,
OMP_TGT_EXEC_MODE_SPMD_NO_LOOP = 1 << 2 | OMP_TGT_EXEC_MODE_SPMD,
- OMP_TGT_EXEC_MODE_SPMD_STRIDED_LOOP = 1 << 3 | OMP_TGT_EXEC_MODE_SPMD
+ OMP_TGT_EXEC_MODE_SPMD_GRID_STRIDE_LOOP = 1 << 3 | OMP_TGT_EXEC_MODE_SPMD
};
static void
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