[llvm-branch-commits] [llvm] [AArch64][llvm] Combine SVE AND-NOT operations into BIC for _x forms (PR #232526)

[Jonathan Thackray via llvm-branch-commits]

================
@@ -25381,6 +25394,26 @@ static SDValue lowerPredCounterWhile(Intrinsic::ID IID, SDNode *N,
                      DAG.getTargetConstant(ElementSizeInBits, DL, MVT::i64));
 }
 
+static SDValue performSVEAndNotIntrinsicCombine(SDNode *N, SelectionDAG &DAG) {
+  SDValue Pg = N->getOperand(1);
+
+  // Fold matching predicates before lowering AND_U discards its predicate.
+  // NOT's inactive lanes cannot affect AND_U's active lanes.
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jthackray wrote:

So we could replace the additional code in `performSVEAndCombine()` with this pattern:
```
  +  multiclass SVEAndNotPats<ValueType VT, ValueType PT> {
  +    def : Pat<(and VT:$a,
  +                (VT (int_aarch64_sve_not (VT (undef)), (PT srcvalue), VT:$b))),
  +              (BIC_ZZZ $a, $b)>;
  +    def : Pat<(and VT:$a,
  +                (VT (int_aarch64_sve_not (VT srcvalue), (PT (SVEAllActive)), VT:$b))),
  +              (BIC_ZZZ $a, $b)>;
  +  }
  +  defm : SVEAndNotPats<nxv16i8, nxv16i1>;
  +  defm : SVEAndNotPats<nxv8i16, nxv8i1>;
  +  defm : SVEAndNotPats<nxv4i32, nxv4i1>;
  +  defm : SVEAndNotPats<nxv2i64, nxv2i1>;
```
but the pattern to replace code in `performSVEAndNotIntrinsicCombine()` is longer/more complicated than the C++ code.

https://github.com/llvm/llvm-project/pull/232526