[llvm-branch-commits] [llvm] release/23.x: [VPlan] Split legalizeAndOptimizeIVs in 2 phases. (#217765) (PR #233472)
Nikita Popov via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Oct 19 08:59:02 PDT 2026
https://github.com/nikic created https://github.com/llvm/llvm-project/pull/233472
cherry picked from commit 932f5d22df7775f7cb65befd62053c0e93448959
cherry picked from commit a3ac001f673a87a014ecd6bf7ca11cc8b1cb576d
>From e00a8d7350fcdd87d9d18d213fca8a3a675443e2 Mon Sep 17 00:00:00 2001
From: Florian Hahn <flo at fhahn.com>
Date: Thu, 20 Aug 2026 21:55:41 +0100
Subject: [PATCH] [VPlan] Split legalizeAndOptimizeIVs in 2 phases. (#217765)
Split the transform into 2 phases:
1. narrow all users of all IVs
2. replace wide IVs if all users are scalar.
Together with removing the old, wide recipes, this allows us to catch
slightly more cases.
PR: https://github.com/llvm/llvm-project/pull/217765
(cherry picked from commit 932f5d22df7775f7cb65befd62053c0e93448959)
(cherry picked from commit a3ac001f673a87a014ecd6bf7ca11cc8b1cb576d)
---
.../Transforms/Vectorize/VPlanTransforms.cpp | 27 +--
.../vector-call-linear-args-no-wide-iv.ll | 66 +++++++
.../VPlan/vplan-narrow-iv-users.ll | 167 ++++++++++++++++++
3 files changed, 249 insertions(+), 11 deletions(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args-no-wide-iv.ll
create mode 100644 llvm/test/Transforms/LoopVectorize/VPlan/vplan-narrow-iv-users.ll
diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
index 48ba81dacefc7..3f71fff088ee2 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp
@@ -880,16 +880,17 @@ scalarizeVPWidenPointerInduction(VPWidenPointerInductionRecipe *PtrIV,
static void legalizeAndOptimizeInductions(VPlan &Plan) {
VPBasicBlock *HeaderVPBB = Plan.getVectorLoopRegion()->getEntryBasicBlock();
bool HasOnlyVectorVFs = !Plan.hasScalarVFOnly();
- VPBuilder Builder(HeaderVPBB, HeaderVPBB->getFirstNonPhi());
- for (VPRecipeBase &Phi : HeaderVPBB->phis()) {
- auto *PhiR = dyn_cast<VPWidenInductionRecipe>(&Phi);
- if (!PhiR)
- continue;
- // Try to narrow wide and replicating recipes to uniform recipes, based on
- // VPlan analysis.
- // TODO: Apply to all recipes in the future, to replace legacy uniformity
- // analysis.
+ SmallVector<VPWidenInductionRecipe *> WideIVs;
+ for (VPRecipeBase &Phi : HeaderVPBB->phis())
+ if (auto *PhiR = dyn_cast<VPWidenInductionRecipe>(&Phi))
+ WideIVs.push_back(PhiR);
+
+ // Try to narrow wide and replicating recipes to uniform recipes, based on
+ // VPlan analysis.
+ // TODO: Apply to all recipes in the future, to replace legacy uniformity
+ // analysis.
+ for (VPWidenInductionRecipe *PhiR : WideIVs) {
auto Users = collectUsersRecursively(PhiR);
for (VPUser *U : reverse(Users)) {
auto *Def = dyn_cast<VPRecipeWithIRFlags>(U);
@@ -915,11 +916,15 @@ static void legalizeAndOptimizeInductions(VPlan &Plan) {
Def->getUnderlyingInstr());
Clone->insertAfter(Def);
Def->replaceAllUsesWith(Clone);
+ Def->eraseFromParent();
}
+ }
+ VPBuilder Builder(HeaderVPBB, HeaderVPBB->getFirstNonPhi());
+ for (VPWidenInductionRecipe *PhiR : WideIVs) {
// Replace wide pointer inductions which have only their scalars used by
// PtrAdd(IndStart, ScalarIVSteps (0, Step)).
- if (auto *PtrIV = dyn_cast<VPWidenPointerInductionRecipe>(&Phi)) {
+ if (auto *PtrIV = dyn_cast<VPWidenPointerInductionRecipe>(PhiR)) {
if (!Plan.hasScalarVFOnly() &&
!PtrIV->onlyScalarsGenerated(Plan.hasScalableVF()))
continue;
@@ -931,7 +936,7 @@ static void legalizeAndOptimizeInductions(VPlan &Plan) {
// Replace widened induction with scalar steps for users that only use
// scalars.
- auto *WideIV = cast<VPWidenIntOrFpInductionRecipe>(&Phi);
+ auto *WideIV = cast<VPWidenIntOrFpInductionRecipe>(PhiR);
if (HasOnlyVectorVFs && none_of(WideIV->users(), [WideIV](VPUser *U) {
return U->usesScalars(WideIV);
}))
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args-no-wide-iv.ll b/llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args-no-wide-iv.ll
new file mode 100644
index 0000000000000..9488a5b36a1b1
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/vector-call-linear-args-no-wide-iv.ll
@@ -0,0 +1,66 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 6
+; RUN: opt -passes=loop-vectorize -mattr=+sve -force-vector-interleave=1 -S %s | FileCheck %s
+
+target triple = "aarch64-unknown-linux-gnu"
+
+; The vector variant of @bar takes %trebled as linear argument.
+define void @narrow_linear_call_arg(ptr noalias %a, i64 %n) {
+; CHECK-LABEL: define void @narrow_linear_call_arg(
+; CHECK-SAME: ptr noalias [[A:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-NEXT: [[VECTOR_PH:.*:]]
+; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK: [[VECTOR_BODY]]:
+; CHECK-NEXT: br label %[[LOOP:.*]]
+; CHECK: [[LOOP]]:
+; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_BODY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_BODY]] ], [ [[VEC_IND_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[TMP0:%.*]] = mul <4 x i32> [[VEC_IND]], splat (i32 3)
+; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i32> [[TMP0]], i64 0
+; CHECK-NEXT: [[TMP2:%.*]] = call i32 @bar(i32 [[TMP1]]) #[[ATTR1:[0-9]+]]
+; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP0]], i64 1
+; CHECK-NEXT: [[TMP4:%.*]] = call i32 @bar(i32 [[TMP3]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP0]], i64 2
+; CHECK-NEXT: [[TMP6:%.*]] = call i32 @bar(i32 [[TMP5]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i32> [[TMP0]], i64 3
+; CHECK-NEXT: [[TMP8:%.*]] = call i32 @bar(i32 [[TMP7]]) #[[ATTR1]]
+; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> poison, i32 [[TMP2]], i32 0
+; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP4]], i32 1
+; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP6]], i32 2
+; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP8]], i32 3
+; CHECK-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]]
+; CHECK-NEXT: store <4 x i32> [[TMP12]], ptr [[GEP_A]], align 4
+; CHECK-NEXT: [[IV_NEXT]] = add nuw i64 [[IV]], 4
+; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
+; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1000
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK: [[EXIT]]:
+; CHECK-NEXT: br label %[[EXIT1:.*]]
+; CHECK: [[EXIT1]]:
+; CHECK-NEXT: ret void
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %iv.trunc = trunc i64 %iv to i32
+ %trebled = mul i32 %iv.trunc, 3
+ %data = call i32 @bar(i32 %trebled) #0
+ %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv
+ store i32 %data, ptr %gep.a
+ %iv.next = add nuw nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1000
+ br i1 %ec, label %exit, label %loop, !llvm.loop !0
+
+exit:
+ ret void
+}
+
+declare i32 @bar(i32)
+declare <vscale x 4 x i32> @vec_bar_linear3_nomask_sve(i32)
+
+attributes #0 = { nounwind "vector-function-abi-variant"="_ZGVsNxl3_bar(vec_bar_linear3_nomask_sve)" }
+
+!0 = distinct !{!0, !1, !2}
+!1 = !{!"llvm.loop.vectorize.width", i32 4}
+!2 = !{!"llvm.loop.vectorize.scalable.enable"}
diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/vplan-narrow-iv-users.ll b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-narrow-iv-users.ll
new file mode 100644
index 0000000000000..cf00783561a0e
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/VPlan/vplan-narrow-iv-users.ll
@@ -0,0 +1,167 @@
+; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "middle.block:" --version 6
+; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -disable-output -vplan-print-after=legalizeAndOptimizeInductions %s 2>&1 | FileCheck %s
+
+define void @narrow_iv_user_chain(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: VPlan for loop in 'narrow_iv_user_chain'
+; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: Live-in ir<1000> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP3]]> * ir<1>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: CLONE ir<%and> = and vp<[[VP5]]>, ir<-4>
+; CHECK-NEXT: CLONE ir<%gep.ld> = getelementptr inbounds ir<%A>, ir<%and>
+; CHECK-NEXT: CLONE ir<%ld> = load ir<%gep.ld>
+; CHECK-NEXT: CLONE ir<%calc> = add nsw ir<%ld>, ir<42>
+; CHECK-NEXT: CLONE ir<%gep.st> = getelementptr inbounds ir<%B>, ir<%and>
+; CHECK-NEXT: REPLICATE store ir<%calc>, ir<%gep.st>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %and = and i64 %iv, -4
+ %gep.ld = getelementptr inbounds i64, ptr %A, i64 %and
+ %ld = load i64, ptr %gep.ld, align 8
+ %calc = add nsw i64 %ld, 42
+ %gep.st = getelementptr inbounds i64, ptr %B, i64 %and
+ store i64 %calc, ptr %gep.st, align 8
+ %iv.next = add nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1000
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+; Same as above, but with a chain of 2 narrowable users.
+define void @narrow_iv_user_chain_multiple_levels(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: VPlan for loop in 'narrow_iv_user_chain_multiple_levels'
+; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: Live-in ir<1000> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP3]]> * ir<1>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: CLONE ir<%and> = and vp<[[VP5]]>, ir<-4>
+; CHECK-NEXT: CLONE ir<%gep.ld> = getelementptr inbounds ir<%A>, ir<%and>
+; CHECK-NEXT: CLONE ir<%ld> = load ir<%gep.ld>
+; CHECK-NEXT: CLONE ir<%calc> = add nsw ir<%ld>, ir<42>
+; CHECK-NEXT: CLONE ir<%calc2> = mul nsw ir<%calc>, ir<3>
+; CHECK-NEXT: CLONE ir<%gep.st> = getelementptr inbounds ir<%B>, ir<%and>
+; CHECK-NEXT: REPLICATE store ir<%calc2>, ir<%gep.st>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %and = and i64 %iv, -4
+ %gep.ld = getelementptr inbounds i64, ptr %A, i64 %and
+ %ld = load i64, ptr %gep.ld, align 8
+ %calc = add nsw i64 %ld, 42
+ %calc2 = mul nsw i64 %calc, 3
+ %gep.st = getelementptr inbounds i64, ptr %B, i64 %and
+ store i64 %calc2, ptr %gep.st, align 8
+ %iv.next = add nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1000
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
+
+define void @no_narrowing_if_all_lanes_used(ptr noalias %A, ptr noalias %B) {
+; CHECK-LABEL: VPlan for loop in 'no_narrowing_if_all_lanes_used'
+; CHECK: VPlan 'Initial VPlan for VF={4},UF>=1' {
+; CHECK-NEXT: Live-in vp<[[VP0:%[0-9]+]]> = VF
+; CHECK-NEXT: Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
+; CHECK-NEXT: Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
+; CHECK-NEXT: Live-in ir<1000> = original trip-count
+; CHECK-EMPTY:
+; CHECK-NEXT: ir-bb<entry>:
+; CHECK-NEXT: Successor(s): scalar.ph, vector.ph
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.ph:
+; CHECK-NEXT: Successor(s): vector loop
+; CHECK-EMPTY:
+; CHECK-NEXT: <x1> vector loop: {
+; CHECK-NEXT: vp<[[VP3:%[0-9]+]]> = CANONICAL-IV
+; CHECK-EMPTY:
+; CHECK-NEXT: vector.body:
+; CHECK-NEXT: ir<%iv> = WIDEN-INDUCTION nsw ir<0>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<0> + vp<[[VP3]]> * ir<1>
+; CHECK-NEXT: vp<[[VP5:%[0-9]+]]> = SCALAR-STEPS vp<[[VP4]]>, ir<1>, vp<[[VP0]]>
+; CHECK-NEXT: CLONE ir<%gep.ld> = getelementptr inbounds ir<%A>, vp<[[VP5]]>
+; CHECK-NEXT: vp<[[VP6:%[0-9]+]]> = vector-pointer inbounds ir<%gep.ld>, ir<1>
+; CHECK-NEXT: WIDEN ir<%ld> = load vp<[[VP6]]>
+; CHECK-NEXT: WIDEN ir<%calc> = add nsw ir<%ld>, ir<42>
+; CHECK-NEXT: CLONE ir<%gep.st> = getelementptr inbounds ir<%B>, vp<[[VP5]]>
+; CHECK-NEXT: vp<[[VP7:%[0-9]+]]> = vector-pointer inbounds ir<%gep.st>, ir<1>
+; CHECK-NEXT: WIDEN store vp<[[VP7]]>, ir<%calc>
+; CHECK-NEXT: EMIT vp<%index.next> = add nuw vp<[[VP3]]>, vp<[[VP1]]>
+; CHECK-NEXT: EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
+; CHECK-NEXT: No successors
+; CHECK-NEXT: }
+; CHECK-NEXT: Successor(s): middle.block
+; CHECK-EMPTY:
+; CHECK-NEXT: middle.block:
+;
+entry:
+ br label %loop
+
+loop:
+ %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+ %gep.ld = getelementptr inbounds i64, ptr %A, i64 %iv
+ %ld = load i64, ptr %gep.ld, align 8
+ %calc = add nsw i64 %ld, 42
+ %gep.st = getelementptr inbounds i64, ptr %B, i64 %iv
+ store i64 %calc, ptr %gep.st, align 8
+ %iv.next = add nsw i64 %iv, 1
+ %ec = icmp eq i64 %iv.next, 1000
+ br i1 %ec, label %exit, label %loop
+
+exit:
+ ret void
+}
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