[llvm-branch-commits] [llvm] [AMDGPU] Extract SIAtomicAddrSpace and fence MMRA parsing from SIMemoryLegalizer (PR #231854)

[Fabian Ritter via llvm-branch-commits]

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@@ -478,4 +480,67 @@ bool isClobberedInFunction(const LoadInst *Load, MemorySSA *MSSA,
   return false;
 }
 
+SIAtomicAddrSpace toSIAtomicAddrSpace(unsigned AS) {
+  if (AS == AMDGPUAS::FLAT_ADDRESS)
+    return SIAtomicAddrSpace::FLAT;
+  if (AS == AMDGPUAS::GLOBAL_ADDRESS)
+    return SIAtomicAddrSpace::GLOBAL;
+  if (AS == AMDGPUAS::LOCAL_ADDRESS)
+    return SIAtomicAddrSpace::LDS;
+  if (AS == AMDGPUAS::PRIVATE_ADDRESS)
+    return SIAtomicAddrSpace::SCRATCH;
+  if (AS == AMDGPUAS::REGION_ADDRESS)
+    return SIAtomicAddrSpace::GDS;
+  if (AS == AMDGPUAS::BUFFER_FAT_POINTER || AS == AMDGPUAS::BUFFER_RESOURCE ||
+      AS == AMDGPUAS::BUFFER_STRIDED_POINTER)
+    return SIAtomicAddrSpace::GLOBAL;
+
+  // Constant addrspaces map to OTHER because there is no point in atomic
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ritter-x2a wrote:

So, your point is that the lowering of volatile loads from the constant AS so far (which did not include waits directly after the load instruction) was wrong and that this PR in its current form (which adds those waits) fixes this?

I still don't think it's possible to observe if these waits are present or not with a program that doesn't break the compiler's memory model (because the value of memory that is accessed via a constant-AS pointer must be changed during kernel execution for that).
But I'm fine with conservatively adding the waits, since users probably often use `volatile` for situations that break the compiler's memory model.

https://github.com/llvm/llvm-project/pull/231854