[llvm-branch-commits] [llvm] release/23.x: [X86] Fix constant vector i64 signed div/rem on 32-bit targets (#229244) (PR #233358)
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Mon Oct 19 00:29:53 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-x86
Author: llvmbot
<details>
<summary>Changes</summary>
Backport e3e894a951586e653dd7910cad39804cb30ce9fd
Requested by: @<!-- -->nikic
---
Patch is 79.50 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/233358.diff
2 Files Affected:
- (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+10-5)
- (added) llvm/test/CodeGen/X86/vector-i64-div-rem-32bit.ll (+1593)
``````````diff
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 6e367a94cd9bc..e4d4da09ce9b7 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -1754,9 +1754,12 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
if (HasInt256) {
setOperationAction(ISD::MULHU, MVT::v4i64, Custom);
// Custom so the combiner keeps full products as [SU]MUL_LOHI, not
- // MULH[SU].
- setOperationAction(ISD::UMUL_LOHI, MVT::v4i64, Custom);
- setOperationAction(ISD::SMUL_LOHI, MVT::v4i64, Custom);
+ // MULH[SU]. The custom lowering unrolls to scalar i64 [SU]MUL_LOHI,
+ // which is only legalizable when i64 is a legal type.
+ if (Subtarget.is64Bit()) {
+ setOperationAction(ISD::UMUL_LOHI, MVT::v4i64, Custom);
+ setOperationAction(ISD::SMUL_LOHI, MVT::v4i64, Custom);
+ }
setOperationAction(ISD::VSELECT, MVT::v32i8, Legal);
// Custom legalize 2x32 to get a little better code.
@@ -2029,8 +2032,10 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
setOperationAction(ISD::MUL, MVT::v64i8, Custom);
setOperationAction(ISD::MULHU, MVT::v8i64, Custom);
- setOperationAction(ISD::UMUL_LOHI, MVT::v8i64, Custom);
- setOperationAction(ISD::SMUL_LOHI, MVT::v8i64, Custom);
+ if (Subtarget.is64Bit()) {
+ setOperationAction(ISD::UMUL_LOHI, MVT::v8i64, Custom);
+ setOperationAction(ISD::SMUL_LOHI, MVT::v8i64, Custom);
+ }
setOperationAction(ISD::MULHU, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v16i32, Custom);
setOperationAction(ISD::MULHS, MVT::v32i16, HasBWI ? Legal : Custom);
diff --git a/llvm/test/CodeGen/X86/vector-i64-div-rem-32bit.ll b/llvm/test/CodeGen/X86/vector-i64-div-rem-32bit.ll
new file mode 100644
index 0000000000000..b54d5809f7aba
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vector-i64-div-rem-32bit.ll
@@ -0,0 +1,1593 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefix=AVX2
+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx512f,-avx512dq | FileCheck %s --check-prefix=AVX512F
+; RUN: llc < %s -mtriple=i686-unknown-linux-gnu -mattr=+avx512f,+avx512dq,+avx512vl | FileCheck %s --check-prefix=AVX512DQ
+
+; Constant signed division/remainder must not unroll vector MUL_LOHI into
+; scalar i64 MUL_LOHI on 32-bit targets, where i64 is an illegal type.
+
+define <4 x i64> @sdiv_v4i64(<4 x i64> %a) nounwind {
+; AVX2-LABEL: sdiv_v4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: pushl %ebp
+; AVX2-NEXT: pushl %ebx
+; AVX2-NEXT: pushl %edi
+; AVX2-NEXT: pushl %esi
+; AVX2-NEXT: subl $76, %esp
+; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) # 32-byte Spill
+; AVX2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, %esi
+; AVX2-NEXT: movl %edx, %edi
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, %ebx
+; AVX2-NEXT: movl %edx, %ebp
+; AVX2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovd %eax, %xmm0
+; AVX2-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $2, %ebx, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $3, %ebp, %xmm0, %xmm0
+; AVX2-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vmovd %esi, %xmm0
+; AVX2-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
+; AVX2-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: vmovdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0
+; AVX2-NEXT: vinserti128 $1, {{[-0-9]+}}(%e{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; AVX2-NEXT: addl $76, %esp
+; AVX2-NEXT: popl %esi
+; AVX2-NEXT: popl %edi
+; AVX2-NEXT: popl %ebx
+; AVX2-NEXT: popl %ebp
+; AVX2-NEXT: retl
+;
+; AVX512F-LABEL: sdiv_v4i64:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: pushl %ebp
+; AVX512F-NEXT: pushl %ebx
+; AVX512F-NEXT: pushl %edi
+; AVX512F-NEXT: pushl %esi
+; AVX512F-NEXT: subl $76, %esp
+; AVX512F-NEXT: vmovups %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) # 32-byte Spill
+; AVX512F-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vmovss %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: calll __divdi3
+; AVX512F-NEXT: movl %eax, %esi
+; AVX512F-NEXT: movl %edx, %edi
+; AVX512F-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX512F-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX512F-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: calll __divdi3
+; AVX512F-NEXT: movl %eax, %ebx
+; AVX512F-NEXT: movl %edx, %ebp
+; AVX512F-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX512F-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vmovss %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: calll __divdi3
+; AVX512F-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX512F-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vmovd %eax, %xmm0
+; AVX512F-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $2, %ebx, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $3, %ebp, %xmm0, %xmm0
+; AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX512F-NEXT: vmovd %esi, %xmm0
+; AVX512F-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
+; AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: calll __divdi3
+; AVX512F-NEXT: vmovdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX512F-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0
+; AVX512F-NEXT: vinserti128 $1, {{[-0-9]+}}(%e{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; AVX512F-NEXT: addl $76, %esp
+; AVX512F-NEXT: popl %esi
+; AVX512F-NEXT: popl %edi
+; AVX512F-NEXT: popl %ebx
+; AVX512F-NEXT: popl %ebp
+; AVX512F-NEXT: retl
+;
+; AVX512DQ-LABEL: sdiv_v4i64:
+; AVX512DQ: # %bb.0:
+; AVX512DQ-NEXT: vpsraq $32, %ymm0, %ymm1
+; AVX512DQ-NEXT: vpbroadcastq {{.*#+}} ymm2 = [277094665,0,277094665,0,277094665,0,277094665,0]
+; AVX512DQ-NEXT: vpmuldq %ymm2, %ymm1, %ymm3
+; AVX512DQ-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX512DQ-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512DQ-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512DQ-NEXT: vpsraq $32, %ymm2, %ymm3
+; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm4 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7]
+; AVX512DQ-NEXT: vpbroadcastq {{.*#+}} ymm5 = [2216757314,4294967295,2216757314,4294967295,2216757314,4294967295,2216757314,4294967295]
+; AVX512DQ-NEXT: vpmullq %ymm5, %ymm4, %ymm4
+; AVX512DQ-NEXT: vpaddq %ymm2, %ymm4, %ymm2
+; AVX512DQ-NEXT: vpsraq $32, %ymm2, %ymm2
+; AVX512DQ-NEXT: vpmuldq %ymm5, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpaddq %ymm0, %ymm1, %ymm0
+; AVX512DQ-NEXT: vpaddq %ymm2, %ymm0, %ymm0
+; AVX512DQ-NEXT: vpsrlq $63, %ymm0, %ymm1
+; AVX512DQ-NEXT: vpsraq $5, %ymm0, %ymm0
+; AVX512DQ-NEXT: vpaddq %ymm1, %ymm0, %ymm0
+; AVX512DQ-NEXT: retl
+ %r = sdiv <4 x i64> %a, splat (i64 62)
+ ret <4 x i64> %r
+}
+
+define <4 x i64> @srem_v4i64(<4 x i64> %a) nounwind {
+; AVX2-LABEL: srem_v4i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: pushl %ebp
+; AVX2-NEXT: pushl %ebx
+; AVX2-NEXT: pushl %edi
+; AVX2-NEXT: pushl %esi
+; AVX2-NEXT: subl $76, %esp
+; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) # 32-byte Spill
+; AVX2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __moddi3
+; AVX2-NEXT: movl %eax, %esi
+; AVX2-NEXT: movl %edx, %edi
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __moddi3
+; AVX2-NEXT: movl %eax, %ebx
+; AVX2-NEXT: movl %edx, %ebp
+; AVX2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: calll __moddi3
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovd %eax, %xmm0
+; AVX2-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $2, %ebx, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $3, %ebp, %xmm0, %xmm0
+; AVX2-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vmovd %esi, %xmm0
+; AVX2-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
+; AVX2-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __moddi3
+; AVX2-NEXT: vmovdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0
+; AVX2-NEXT: vinserti128 $1, {{[-0-9]+}}(%e{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; AVX2-NEXT: addl $76, %esp
+; AVX2-NEXT: popl %esi
+; AVX2-NEXT: popl %edi
+; AVX2-NEXT: popl %ebx
+; AVX2-NEXT: popl %ebp
+; AVX2-NEXT: retl
+;
+; AVX512F-LABEL: srem_v4i64:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: pushl %ebp
+; AVX512F-NEXT: pushl %ebx
+; AVX512F-NEXT: pushl %edi
+; AVX512F-NEXT: pushl %esi
+; AVX512F-NEXT: subl $76, %esp
+; AVX512F-NEXT: vmovups %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) # 32-byte Spill
+; AVX512F-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vmovss %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: calll __moddi3
+; AVX512F-NEXT: movl %eax, %esi
+; AVX512F-NEXT: movl %edx, %edi
+; AVX512F-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX512F-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX512F-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX512F-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: calll __moddi3
+; AVX512F-NEXT: movl %eax, %ebx
+; AVX512F-NEXT: movl %edx, %ebp
+; AVX512F-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX512F-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vmovss %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: calll __moddi3
+; AVX512F-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX512F-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX512F-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX512F-NEXT: vmovd %eax, %xmm0
+; AVX512F-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $2, %ebx, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $3, %ebp, %xmm0, %xmm0
+; AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX512F-NEXT: vmovd %esi, %xmm0
+; AVX512F-NEXT: vpinsrd $1, %edi, %xmm0, %xmm0
+; AVX512F-NEXT: vmovdqa %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX512F-NEXT: vzeroupper
+; AVX512F-NEXT: calll __moddi3
+; AVX512F-NEXT: vmovdqa {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX512F-NEXT: vpinsrd $2, %eax, %xmm0, %xmm0
+; AVX512F-NEXT: vpinsrd $3, %edx, %xmm0, %xmm0
+; AVX512F-NEXT: vinserti128 $1, {{[-0-9]+}}(%e{{[sb]}}p), %ymm0, %ymm0 # 16-byte Folded Reload
+; AVX512F-NEXT: addl $76, %esp
+; AVX512F-NEXT: popl %esi
+; AVX512F-NEXT: popl %edi
+; AVX512F-NEXT: popl %ebx
+; AVX512F-NEXT: popl %ebp
+; AVX512F-NEXT: retl
+;
+; AVX512DQ-LABEL: srem_v4i64:
+; AVX512DQ: # %bb.0:
+; AVX512DQ-NEXT: vpsraq $32, %ymm0, %ymm1
+; AVX512DQ-NEXT: vpbroadcastq {{.*#+}} ymm2 = [277094665,0,277094665,0,277094665,0,277094665,0]
+; AVX512DQ-NEXT: vpmuldq %ymm2, %ymm1, %ymm3
+; AVX512DQ-NEXT: vpmuludq %ymm2, %ymm0, %ymm2
+; AVX512DQ-NEXT: vpsrlq $32, %ymm2, %ymm2
+; AVX512DQ-NEXT: vpaddq %ymm2, %ymm3, %ymm2
+; AVX512DQ-NEXT: vpsraq $32, %ymm2, %ymm3
+; AVX512DQ-NEXT: vpxor %xmm4, %xmm4, %xmm4
+; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm2 = ymm2[0],ymm4[1],ymm2[2],ymm4[3],ymm2[4],ymm4[5],ymm2[6],ymm4[7]
+; AVX512DQ-NEXT: vpblendd {{.*#+}} ymm4 = ymm0[0],ymm4[1],ymm0[2],ymm4[3],ymm0[4],ymm4[5],ymm0[6],ymm4[7]
+; AVX512DQ-NEXT: vpbroadcastq {{.*#+}} ymm5 = [2216757314,4294967295,2216757314,4294967295,2216757314,4294967295,2216757314,4294967295]
+; AVX512DQ-NEXT: vpmullq %ymm5, %ymm4, %ymm4
+; AVX512DQ-NEXT: vpaddq %ymm2, %ymm4, %ymm2
+; AVX512DQ-NEXT: vpsraq $32, %ymm2, %ymm2
+; AVX512DQ-NEXT: vpmuldq %ymm5, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpaddq %ymm3, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpaddq %ymm0, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpsrlq $63, %ymm1, %ymm2
+; AVX512DQ-NEXT: vpsraq $5, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpaddq %ymm2, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpmullq {{\.?LCPI[0-9]+_[0-9]+}}{1to4}, %ymm1, %ymm1
+; AVX512DQ-NEXT: vpsubq %ymm1, %ymm0, %ymm0
+; AVX512DQ-NEXT: retl
+ %r = srem <4 x i64> %a, splat (i64 62)
+ ret <4 x i64> %r
+}
+
+define <8 x i64> @sdiv_v8i64(<8 x i64> %a) nounwind {
+; AVX2-LABEL: sdiv_v8i64:
+; AVX2: # %bb.0:
+; AVX2-NEXT: pushl %ebp
+; AVX2-NEXT: pushl %ebx
+; AVX2-NEXT: pushl %edi
+; AVX2-NEXT: pushl %esi
+; AVX2-NEXT: subl $156, %esp
+; AVX2-NEXT: vmovups %ymm0, {{[-0-9]+}}(%e{{[sb]}}p) # 32-byte Spill
+; AVX2-NEXT: vmovups %ymm1, {{[-0-9]+}}(%e{{[sb]}}p) # 32-byte Spill
+; AVX2-NEXT: vextractps $1, %xmm1, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm1, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, %esi
+; AVX2-NEXT: movl %edx, %edi
+; AVX2-NEXT: vmovups {{[-0-9]+}}(%e{{[sb]}}p), %ymm0 # 32-byte Reload
+; AVX2-NEXT: vextractf128 $1, %ymm0, %xmm0
+; AVX2-NEXT: vmovaps %xmm0, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vextractps $3, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vextractps $2, %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vzeroupper
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: movl %eax, %ebx
+; AVX2-NEXT: movl %edx, %ebp
+; AVX2-NEXT: vmovaps {{[-0-9]+}}(%e{{[sb]}}p), %xmm0 # 16-byte Reload
+; AVX2-NEXT: vextractps $1, %xmm0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: vmovss %xmm0, (%esp)
+; AVX2-NEXT: movl $0, {{[0-9]+}}(%esp)
+; AVX2-NEXT: movl $62, {{[0-9]+}}(%esp)
+; AVX2-NEXT: calll __divdi3
+; AVX2-NEXT: vmovd %eax, %xmm0
+; AVX2-NEXT: vpinsrd $1, %edx, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $2, %ebx, %xmm0, %xmm0
+; AVX2-NEXT: vpinsrd $3, %ebp, %xmm0, %xmm0
+; AVX2-NEXT: vmovd %esi, %xmm1
+; AVX2-NEXT: vpinsrd $1, %edi, %xmm1, %xmm1
+; AVX2-NEXT: vpinsrd $2, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload
+; AVX2-NEXT: vpinsrd $3, {{[-0-9]+}}(%e{{[sb]}}p), %xmm1, %xmm1 # 4-byte Folded Reload
+; AVX2-NEXT: vmovd {{[-0-9]+}}(%e{{[sb]}}p), %xmm2 # 4-byte Folded Reload
+; AVX2-NEXT: # xmm2 = mem[0],zero,zero,zero
+; AVX2-NEXT: vpinsrd $1, {{[-0-9]+}}(%e{{[sb]}}p), %xmm2, %xmm2 # 4-byte Folded Reload
+; AVX2-NEXT: vpinsrd $2, {{[-0-9]+}}(%e{{[sb]}}p), %xmm2, %xmm2 # 4-byte Folded Reload
+; AVX2-NEXT: vpinsrd $3, {{[-0-9]+}}(%e{{[sb]}}p), %xmm2, %xmm2 # 4-byte Folded Reload
+; AVX2-NEXT: vmovdqa %xmm2, {{[-0-9]+}}(%e{{[sb]}}p) # 16-byte Spill
+; AVX2-NEXT: vmovups...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/233358
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