[llvm-branch-commits] [llvm] [SLP] Let targets choose the default for -slp-vectorize-once-used (PR #232877)

[Jay Foad via llvm-branch-commits]

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@@ -5,15 +5,16 @@ define i32 @select_bit(ptr addrspace(1) %p, i32 %g, i32 %acc) {
 ; CHECK-LABEL: define i32 @select_bit(
 ; CHECK-SAME: ptr addrspace(1) [[P:%.*]], i32 [[G:%.*]], i32 [[ACC:%.*]]) #[[ATTR0:[0-9]+]] {
 ; CHECK-NEXT:  [[ENTRY:.*:]]
-; CHECK-NEXT:    [[TMP0:%.*]] = insertelement <2 x i32> poison, i32 [[G]], i64 0
-; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <2 x i32> [[TMP0]], <2 x i32> poison, <2 x i32> zeroinitializer
-; CHECK-NEXT:    [[TMP2:%.*]] = and <2 x i32> [[TMP1]], <i32 1, i32 2>
-; CHECK-NEXT:    [[TMP3:%.*]] = load <2 x i32>, ptr addrspace(1) [[P]], align 4
-; CHECK-NEXT:    [[TMP4:%.*]] = icmp eq <2 x i32> [[TMP2]], zeroinitializer
-; CHECK-NEXT:    [[TMP5:%.*]] = select <2 x i1> [[TMP4]], <2 x i32> zeroinitializer, <2 x i32> [[TMP3]]
-; CHECK-NEXT:    [[TMP6:%.*]] = extractelement <2 x i32> [[TMP5]], i64 0
+; CHECK-NEXT:    [[P1:%.*]] = getelementptr inbounds i8, ptr addrspace(1) [[P]], i64 4
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jayfoad wrote:

Can you explain why this non-vectorized version is better for AMDGPU? Maybe there is a way to get equally good codegen from the vectorized version?

https://github.com/llvm/llvm-project/pull/232877