[llvm-branch-commits] [llvm] release/23.x: [Mips] Fix O32 lowering on 64-bit CPUs (#224937) (PR #233237)
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Sun Oct 18 06:54:42 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-mips
Author: llvmbot
<details>
<summary>Changes</summary>
Backport 52500486a0b723a1d9528e3098901702da837c3d
Requested by: @<!-- -->alexrp
---
Patch is 31.01 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/233237.diff
19 Files Affected:
- (modified) llvm/lib/Target/Mips/MipsSEFrameLowering.cpp (+8-20)
- (modified) llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp (+1-1)
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+6-6)
- (modified) llvm/lib/Target/Mips/MipsSubtarget.cpp (+5)
- (modified) llvm/test/CodeGen/Mips/cconv/arguments-float.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/cconv/arguments-struct.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll (+4-4)
- (modified) llvm/test/CodeGen/Mips/cconv/arguments.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll (+4-4)
- (modified) llvm/test/CodeGen/Mips/cconv/callee-saved.ll (+8-8)
- (modified) llvm/test/CodeGen/Mips/cconv/memory-layout.ll (+2-2)
- (added) llvm/test/CodeGen/Mips/cconv/o32-fp64-gpr-moves.ll (+63)
- (added) llvm/test/CodeGen/Mips/cconv/o32-mips64.ll (+124)
- (modified) llvm/test/CodeGen/Mips/cconv/reserved-space.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/cconv/return-float.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/cconv/return-hard-float.ll (+4-4)
- (modified) llvm/test/CodeGen/Mips/cconv/return-struct.ll (+4-4)
- (modified) llvm/test/CodeGen/Mips/cconv/return.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/cconv/stack-alignment.ll (+2-2)
``````````diff
diff --git a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
index 937e33bd840e60..2aeee5b4e97c93 100644
--- a/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsSEFrameLowering.cpp
@@ -277,17 +277,17 @@ bool ExpandPseudo::expandCopyACC(MachineBasicBlock &MBB, Iter I,
}
/// This method expands the same instruction that MipsSEInstrInfo::
-/// expandBuildPairF64 does, for the case when ABI is fpxx and mthc1 is not
-/// available and the case where the ABI is FP64A. It is implemented here
+/// expandBuildPairF64 does, for FPXX/FP64 when mthc1 is not available and
+/// for FP64A. It is implemented here
/// because frame indexes are eliminated before MipsSEInstrInfo::
/// expandBuildPairF64 is called.
bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I,
bool FP64) const {
- // For fpxx and when mthc1 is not available, use:
+ // For FPXX/FP64 when mthc1 is not available, use:
// spill + reload via ldc1
//
- // The case where dmtc1 is available doesn't need to be handled here
+ // The case where 64-bit GPRs can be used doesn't need to be handled here
// because it never creates a BuildPairF64 node.
//
// The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
@@ -306,12 +306,6 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
Register LoReg = I->getOperand(1).getReg();
Register HiReg = I->getOperand(2).getReg();
- // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
- // the cases where mthc1 is not available). 64-bit architectures and
- // MIPS32r2 or later can use FGR64 though.
- assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
- !Subtarget.isFP64bit());
-
const TargetRegisterClass *RC = &Mips::GPR32RegClass;
const TargetRegisterClass *RC2 =
FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
@@ -331,8 +325,8 @@ bool ExpandPseudo::expandBuildPairF64(MachineBasicBlock &MBB,
}
/// This method expands the same instruction that MipsSEInstrInfo::
-/// expandExtractElementF64 does, for the case when ABI is fpxx and mfhc1 is not
-/// available and the case where the ABI is FP64A. It is implemented here
+/// expandExtractElementF64 does, for FPXX/FP64 when mfhc1 is not available and
+/// for FP64A. It is implemented here
/// because frame indexes are eliminated before MipsSEInstrInfo::
/// expandExtractElementF64 is called.
bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
@@ -347,10 +341,10 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
return true;
}
- // For fpxx and when mfhc1 is not available, use:
+ // For FPXX/FP64 when mfhc1 is not available, use:
// spill + reload via ldc1
//
- // The case where dmfc1 is available doesn't need to be handled here
+ // The case where 64-bit GPRs can be used doesn't need to be handled here
// because it never creates a ExtractElementF64 node.
//
// The FP64A ABI (fp64 with nooddspreg) must also use a spill/reload sequence
@@ -370,12 +364,6 @@ bool ExpandPseudo::expandExtractElementF64(MachineBasicBlock &MBB,
unsigned N = Op2.getImm();
int64_t Offset = 4 * (Subtarget.isLittle() ? N : (1 - N));
- // It should be impossible to have FGR64 on MIPS-II or MIPS32r1 (which are
- // the cases where mfhc1 is not available). 64-bit architectures and
- // MIPS32r2 or later can use FGR64 though.
- assert(Subtarget.isGP64bit() || Subtarget.hasMTHC1() ||
- !Subtarget.isFP64bit());
-
const TargetRegisterClass *RC =
FP64 ? &Mips::FGR64RegClass : &Mips::AFGR64RegClass;
const TargetRegisterClass *RC2 = &Mips::GPR32RegClass;
diff --git a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
index 8c60824a42a265..cb87be1d68ff98 100644
--- a/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
+++ b/llvm/lib/Target/Mips/MipsSEISelDAGToDAG.cpp
@@ -163,7 +163,7 @@ void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
break;
case Mips::BuildPairF64_64:
case Mips::ExtractElementF64_64:
- if (!Subtarget->useOddSPReg()) {
+ if (!Subtarget->useOddSPReg() || !Subtarget->hasMTHC1()) {
MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
break;
}
diff --git a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
index 6c59975a1b501c..a11588c5bfd53c 100644
--- a/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
+++ b/llvm/lib/Target/Mips/MipsSEInstrInfo.cpp
@@ -853,9 +853,9 @@ void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
Register SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
- // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
+ // FPXX/FP64 without MFHC1 should have been handled with a spill/reload
// in MipsSEFrameLowering.cpp.
- assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
+ assert(!((Subtarget.isABI_FPXX() || FP64) && !Subtarget.hasMTHC1()));
// FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
// in MipsSEFrameLowering.cpp.
@@ -896,7 +896,7 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
// mtc1 Lo, $fp
// mthc1 Hi, $fp
//
- // Otherwise, for O32 FPXX ABI:
+ // Otherwise, for FPXX/FP64:
// spill + reload via ldc1
// This case is handled by the frame lowering code.
//
@@ -904,12 +904,12 @@ void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
// mtc1 Lo, $fp
// mtc1 Hi, $fp + 1
//
- // The case where dmtc1 is available doesn't need to be handled here
+ // The case where 64-bit GPRs can be used doesn't need to be handled here
// because it never creates a BuildPairF64 node.
- // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
+ // FPXX/FP64 without MTHC1 should have been handled with a spill/reload
// in MipsSEFrameLowering.cpp.
- assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
+ assert(!((Subtarget.isABI_FPXX() || FP64) && !Subtarget.hasMTHC1()));
// FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
// in MipsSEFrameLowering.cpp.
diff --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 14d507848f2f6b..3726a8e04166c9 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -253,6 +253,11 @@ MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
// Parse features string.
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
+
+ // O32 uses 32-bit GPRs even when the selected CPU supports a 64-bit ISA.
+ if (isABI_O32())
+ IsGP64bit = false;
+
if (InMips16Mode && !IsSoftFloat)
InMips16HardFloat = true;
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
index 3a39a29de02fe2..c639b3edc79cb3 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-float.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=mips -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
; RUN: llc -mtriple=mipsel -relocation-model=static -mattr=+soft-float < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
-; RUN-TODO: llc -mtriple=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
-; RUN-TODO: llc -mtriple=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64 -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el -relocation-model=static -mattr=+soft-float -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
; RUN: llc -mtriple=mips64 -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
; RUN: llc -mtriple=mips64el -relocation-model=static -mattr=+soft-float -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-struct.ll b/llvm/test/CodeGen/Mips/cconv/arguments-struct.ll
index 371459f5f85b0c..6496e2de227ba3 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-struct.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-struct.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=mips-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32-BE %s
; RUN: llc -mtriple=mipsel-unknown-linux-gnu -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32-LE %s
-; RUN-TODO: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-BE %s
-; RUN-TODO: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-LE %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-BE %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32-LE %s
; RUN: llc -mtriple=mips64-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW-BE %s
; RUN: llc -mtriple=mips64el-unknown-linux-gnu -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW-LE %s
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
index 1f97b376c290be..b87d27489bd0f3 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments-varargs.ll
@@ -3,10 +3,10 @@
; RUN: llc -mtriple=mipsel-linux -relocation-model=static < %s \
; RUN: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64 -relocation-model=static -target-abi o32 < %s \
-; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64el -relocation-model=static -target-abi o32 < %s \
-; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64 -relocation-model=static -target-abi o32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el -relocation-model=static -target-abi o32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
; RUN: llc -mtriple=mips64-linux -relocation-model=static -target-abi n32 < %s \
; RUN: | FileCheck --check-prefixes=ALL,NEW,N32,NEW-BE %s
diff --git a/llvm/test/CodeGen/Mips/cconv/arguments.ll b/llvm/test/CodeGen/Mips/cconv/arguments.ll
index 75403ec8a4657f..4621f8e66e49e8 100644
--- a/llvm/test/CodeGen/Mips/cconv/arguments.ll
+++ b/llvm/test/CodeGen/Mips/cconv/arguments.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=mips -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
; RUN: llc -mtriple=mipsel -relocation-model=static < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
-; RUN-TODO: llc -mtriple=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
-; RUN-TODO: llc -mtriple=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64 -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el -relocation-model=static -target-abi o32 < %s | FileCheck --check-prefixes=ALL,SYM32,O32 %s
; RUN: llc -mtriple=mips64 -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
; RUN: llc -mtriple=mips64el -relocation-model=static -target-abi n32 < %s | FileCheck --check-prefixes=ALL,SYM32,NEW %s
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
index 14d781dc57df8e..07899b6b76a8e2 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved-float.ll
@@ -3,10 +3,10 @@
; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
-; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64 -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el -target-abi o32 < %s | FileCheck --check-prefixes=ALL,ALL-INV,O32-INV %s
; RUN: llc -mtriple=mips64 -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
; RUN: llc -mtriple=mips64el -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
diff --git a/llvm/test/CodeGen/Mips/cconv/callee-saved.ll b/llvm/test/CodeGen/Mips/cconv/callee-saved.ll
index 93808fbcad03d1..c0223ae0c8c270 100644
--- a/llvm/test/CodeGen/Mips/cconv/callee-saved.ll
+++ b/llvm/test/CodeGen/Mips/cconv/callee-saved.ll
@@ -3,14 +3,14 @@
; RUN: llc -mtriple=mips < %s | FileCheck --check-prefixes=ALL,O32-INV %s
; RUN: llc -mtriple=mipsel < %s | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s \
-; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s \
-; RUN-TODO: | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64 -target-abi o32 < %s \
-; RUN-TODO: | FileCheck --check-prefixes=ALL,O32-INV %s
-; RUN-TODO: llc -mtriple=mips64el -target-abi o32 < %s \
-; RUN-TODO: | FileCheck --check-prefixes=ALL,O32-INV %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64 -target-abi o32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el -target-abi o32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64 -target-abi o32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32-INV %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el -target-abi o32 < %s \
+; RUN: | FileCheck --check-prefixes=ALL,O32-INV %s
; RUN: llc -mtriple=mips64 -target-abi n32 < %s \
; RUN: | FileCheck --check-prefixes=ALL,N32 %s
diff --git a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
index c95fe09de20e70..ceaaa832e67473 100644
--- a/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
+++ b/llvm/test/CodeGen/Mips/cconv/memory-layout.ll
@@ -1,8 +1,8 @@
; RUN: llc -mtriple=mips-elf < %s | FileCheck --check-prefixes=ALL,O32 %s
; RUN: llc -mtriple=mipsel-elf < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
-; RUN-TODO: llc -mtriple=mips64el-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
+; RUN: llc -verify-machineinstrs -mtriple=mips64el-elf -target-abi o32 < %s | FileCheck --check-prefixes=ALL,O32 %s
; RUN: llc -mtriple=mips64-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
; RUN: llc -mtriple=mips64el-elf -target-abi n32 < %s | FileCheck --check-prefixes=ALL,N32 %s
diff --git a/llvm/test/CodeGen/Mips/cconv/o32-fp64-gpr-moves.ll b/llvm/test/CodeGen/Mips/cconv/o32-fp64-gpr-moves.ll
new file mode 100644
index 00000000000000..b6d7dde52852e3
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/cconv/o32-fp64-gpr-moves.ll
@@ -0,0 +1,63 @@
+; RUN: llc -mtriple=mips64 -mcpu=mips3 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64el -mcpu=mips3 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64 -mcpu=mips4 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64el -mcpu=mips4 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64el -mcpu=mips64r6 -target-abi=o32 -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=o32 -mattr=+nooddspreg -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=o32 -mattr=+nooddspreg -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -target-abi=o32 -mattr=+nooddspreg -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=o32 -mattr=+nooddspreg -verify-machineinstrs -filetype=obj %s -o /dev/null
+; RUN: llc -mtriple=mips64 -mcpu=mips64 -target-abi=o32 -verify-machineinstrs < %s | FileCheck %s --check-prefix=SPILL
+; RUN: llc -mtriple=mips64el -mcpu=mips64 -target-abi=o32 -verify-machineinstrs < %s | FileCheck %s --check-prefix=SPILL
+; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -target-abi=o32 -verify-machineinstrs < %s | FileCheck %s --check-prefix=DIRECT-BE
+; RUN: llc -mtriple=mips64el -mcpu=mips64r2 -target-abi=o32 -verify-machineinstrs < %s | FileCheck %s --check-prefix=DIRECT-LE
+
+; An integer argument before a double makes O32 pass that double in two
+; 32-bit GPRs. Check both directions of the transfer with 64-bit FPRs.
+; Before revision 2, MTHC1/MFHC1 are unavailable: the upper half of an FPR
+; cannot be accessed by applying MTC1/MFC1 to its sub_hi register.
+define double @from_gprs(i32 %pad, double %value) {
+; SPILL-LABEL: from_gprs:
+; SPILL: addiu $sp, $sp, -8
+; SPILL: sw $6, 0($sp)
+; SPILL-NEXT: sw $7, 4($sp)
+; SPILL-NEXT: ldc1 $f0, 0($sp)
+; SPILL: addiu $sp, $sp, 8
+;
+; DIRECT-BE-LABEL: from_gprs:
+; DIRECT-BE: mtc1 $7, $f0
+; DIRECT-BE-NEXT: mthc1 $6, $f0
+;
+; DIRECT-LE-LABEL: from_gprs:
+; DIRECT-LE: mtc1 $6, $f0
+; DIRECT-LE-NEXT: mthc1 $7, $f0
+ ret double %value
+}
+
+declare void @consume(i32, double)
+
+define void @to_gprs(double %value) {
+; SPILL-LABEL: to_gprs:
+; SPILL: sdc1 $f12, 16($sp)
+; SPILL-NEXT: lw $6, 16($sp)
+; SPILL-NEXT: sdc1 $f12, 16($sp)
+; SPILL-NEXT: lw $7, 20($sp)
+; SPILL: jal consume
+;
+; DIRECT-BE-LABEL: to_gprs:
+; DIRECT-BE-DAG: mfhc1 $6, $f12
+; DIRECT-BE-DAG: mfc1 $7, $f12
+; DIRECT-BE: jal consume
+;
+; DIRECT-LE-LABEL: to_gprs:
+; DIRECT-LE-DAG: mfc1 $6, $f12
+; DIRECT-LE-DAG: mfhc1 $7, $f12
+; DIRECT-LE: jal consume
+ call void @consume(i32 1, double %value)
+ ret void
+}
diff --git a/llvm/test/CodeGen/Mips/cconv/o32-mips64.ll b/llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
new file mode 100644
index 00000000000000..be4b0f914cc2e7
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/cconv/o32-mips64.ll
@@ -0,0 +1,124 @@
+; RUN: llc -mtriple=mips64 -target-abi=o32 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=BE,HARD
+; RUN: llc -mtriple=mips64el -target-abi=o32 -...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/233237
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