[llvm-branch-commits] [llvm] beb6b7d - [X86] Don't treat vectors with elements wider than 64 bits as immediate-shiftable (#228840)

[via llvm-branch-commits]

Author: Doha Nam
Date: 2026-10-14T08:06:40Z
New Revision: beb6b7dfae46ce96a30742181b1acc83b9f72639

URL: https://github.com/llvm/llvm-project/commit/beb6b7dfae46ce96a30742181b1acc83b9f72639
DIFF: https://github.com/llvm/llvm-project/commit/beb6b7dfae46ce96a30742181b1acc83b9f72639.diff

LOG: [X86] Don't treat vectors with elements wider than 64 bits as immediate-shiftable (#228840)

supportedVectorShiftWithImm accepted any simple 128/256/512-bit vector with
elements of at least 16 bits, including v1i128 and v2i128. X86 has no vector
shifts for such elements, but combineAdd's ADD(x,x) -> X86ISD::VSHLI(x,1)
fold (#161843) relies on this predicate and runs before type legalization.

Reject elements wider than 64 bits.

Fixes #228829.

Co-Authored-By: Claude Opus 5.5 <noreply at anthropic.com>
(cherry picked from commit 7cfe81b25c02118add29d8d89379543510a8418d)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp
    llvm/test/CodeGen/X86/combine-add.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8b48e9c8b0eca7..6e367a94cd9bc5 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -30879,7 +30879,7 @@ static bool supportedVectorShiftWithImm(EVT VT, const X86Subtarget &Subtarget,
   if (!(VT.is128BitVector() || VT.is256BitVector() || VT.is512BitVector()))
     return false;
 
-  if (VT.getScalarSizeInBits() < 16)
+  if (VT.getScalarSizeInBits() < 16 || VT.getScalarSizeInBits() > 64)
     return false;
 
   if (VT.is512BitVector() && Subtarget.useAVX512Regs() &&

diff  --git a/llvm/test/CodeGen/X86/combine-add.ll b/llvm/test/CodeGen/X86/combine-add.ll
index c9455d5c4db4bd..8e9c4b019b31eb 100644
--- a/llvm/test/CodeGen/X86/combine-add.ll
+++ b/llvm/test/CodeGen/X86/combine-add.ll
@@ -640,3 +640,34 @@ define i32 @add_adc_multi_use(i32 %0, i32 %1, i32 %2) nounwind {
   %10 = add i32 %9, %6
   ret i32 %10
 }
+
+; Don't fold add(x,x) -> X86ISD::VSHLI(x,1) for elements wider than 64 bits.
+; PR228829
+define <1 x i128> @combine_vec_add_self_v1i128(<1 x i128> %a) {
+; CHECK-LABEL: combine_vec_add_self_v1i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rsi, %rdx
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    addq %rdi, %rax
+; CHECK-NEXT:    adcq %rsi, %rdx
+; CHECK-NEXT:    retq
+  %s = add <1 x i128> %a, %a
+  ret <1 x i128> %s
+}
+
+define <2 x i128> @combine_vec_add_self_v2i128(<2 x i128> %a) {
+; CHECK-LABEL: combine_vec_add_self_v2i128:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    addq %rsi, %rsi
+; CHECK-NEXT:    adcq %rdx, %rdx
+; CHECK-NEXT:    addq %rcx, %rcx
+; CHECK-NEXT:    adcq %r8, %r8
+; CHECK-NEXT:    movq %r8, 24(%rdi)
+; CHECK-NEXT:    movq %rcx, 16(%rdi)
+; CHECK-NEXT:    movq %rdx, 8(%rdi)
+; CHECK-NEXT:    movq %rsi, (%rdi)
+; CHECK-NEXT:    retq
+  %s = add <2 x i128> %a, %a
+  ret <2 x i128> %s
+}