[llvm-branch-commits] [llvm] [RISCV][P-ext] Use concat_vectors with 0 in widenPackedVectorWithZeros. (PR #232940)
Craig Topper via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Sat Oct 17 10:47:08 PDT 2026
https://github.com/topperc updated https://github.com/llvm/llvm-project/pull/232940
>From 0b50885d85d0d98eef4f9c05d3c1de31e5b56da1 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Fri, 16 Oct 2026 14:06:48 -0700
Subject: [PATCH 1/2] [RISCV][P-ext] Use concat_vectors with 0 in
widenPackedVectorWithZeros.
This will be legalized and combined to a vector_shuffle. That
shuffle can then be matched to a pack with x0 after #232892.
This changes the zext.w to a pack, but that's not obviously worse.
If we need to canonicalize we can add a DAG combine later.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 ++++-----
llvm/test/CodeGen/RISCV/rvp-simd-32.ll | 16 ++++++++--------
2 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6670e481140267..76c59ec147fbab 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -16933,13 +16933,12 @@ static SDValue customLegalizeToWOpWithSExt(SDNode *N, SelectionDAG &DAG) {
return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, NewRes);
}
-// Zero-extend a 32-bit packed vector to the 64-bit packed type WideVT,
-// clearing the upper lanes.
+// Widen a 32-bit packed vector to the 64-bit packed type WideVT by
+// concatenating it with zeros, clearing the upper lanes.
static SDValue widenPackedVectorWithZeros(SelectionDAG &DAG, const SDLoc &DL,
SDValue V, MVT WideVT) {
- SDValue Wide =
- DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, DAG.getBitcast(MVT::i32, V));
- return DAG.getBitcast(WideVT, Wide);
+ SDValue Zero = DAG.getConstant(0, DL, V.getValueType());
+ return DAG.getNode(ISD::CONCAT_VECTORS, DL, WideVT, V, Zero);
}
void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 15e4cb5c2fd0fc..4c9279872cdcff 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -2937,7 +2937,7 @@ define i32 @test_predsum_i8x4_i32(<4 x i8> %a, i32 %b) {
;
; RV64-LABEL: test_predsum_i8x4_i32:
; RV64: # %bb.0:
-; RV64-NEXT: zext.w a0, a0
+; RV64-NEXT: pack a0, a0, zero
; RV64-NEXT: predsum.bs a0, a0, a1
; RV64-NEXT: ret
%res = call i32 @llvm.riscv.predsum.i32.v4i8(<4 x i8> %a, i32 %b)
@@ -2952,7 +2952,7 @@ define i32 @test_predsumu_u8x4_u32(<4 x i8> %a, i32 %b) {
;
; RV64-LABEL: test_predsumu_u8x4_u32:
; RV64: # %bb.0:
-; RV64-NEXT: zext.w a0, a0
+; RV64-NEXT: pack a0, a0, zero
; RV64-NEXT: predsumu.bs a0, a0, a1
; RV64-NEXT: ret
%res = call i32 @llvm.riscv.predsumu.i32.v4i8(<4 x i8> %a, i32 %b)
@@ -2967,7 +2967,7 @@ define i32 @test_predsum_i16x2_i32(<2 x i16> %a, i32 %b) {
;
; RV64-LABEL: test_predsum_i16x2_i32:
; RV64: # %bb.0:
-; RV64-NEXT: zext.w a0, a0
+; RV64-NEXT: pack a0, a0, zero
; RV64-NEXT: predsum.hs a0, a0, a1
; RV64-NEXT: ret
%res = call i32 @llvm.riscv.predsum.i32.v2i16(<2 x i16> %a, i32 %b)
@@ -2982,7 +2982,7 @@ define i32 @test_predsumu_u16x2_u32(<2 x i16> %a, i32 %b) {
;
; RV64-LABEL: test_predsumu_u16x2_u32:
; RV64: # %bb.0:
-; RV64-NEXT: zext.w a0, a0
+; RV64-NEXT: pack a0, a0, zero
; RV64-NEXT: predsumu.hs a0, a0, a1
; RV64-NEXT: ret
%res = call i32 @llvm.riscv.predsumu.i32.v2i16(<2 x i16> %a, i32 %b)
@@ -3255,8 +3255,8 @@ define i32 @test_pabdsumu_u8x4_u32(<4 x i8> %a, <4 x i8> %b) {
;
; RV64-LABEL: test_pabdsumu_u8x4_u32:
; RV64: # %bb.0:
-; RV64-NEXT: zext.w a1, a1
-; RV64-NEXT: zext.w a0, a0
+; RV64-NEXT: pack a1, a1, zero
+; RV64-NEXT: pack a0, a0, zero
; RV64-NEXT: pabdsumu.b a0, a0, a1
; RV64-NEXT: ret
%res = call i32 @llvm.riscv.pabdsumu.i32.v4i8(<4 x i8> %a, <4 x i8> %b)
@@ -3271,8 +3271,8 @@ define i32 @test_pabdsumau_u8x4_u32(i32 %rd, <4 x i8> %a, <4 x i8> %b) {
;
; RV64-LABEL: test_pabdsumau_u8x4_u32:
; RV64: # %bb.0:
-; RV64-NEXT: zext.w a2, a2
-; RV64-NEXT: zext.w a1, a1
+; RV64-NEXT: pack a2, a2, zero
+; RV64-NEXT: pack a1, a1, zero
; RV64-NEXT: pabdsumau.b a0, a1, a2
; RV64-NEXT: ret
%res = call i32 @llvm.riscv.pabdsumau.i32.v4i8(i32 %rd, <4 x i8> %a, <4 x i8> %b)
>From edd70e7135fe0be78475c20c8198715722e5fc85 Mon Sep 17 00:00:00 2001
From: Craig Topper <craig.topper at sifive.com>
Date: Sat, 17 Oct 2026 10:32:28 -0700
Subject: [PATCH 2/2] fixup! update cross-project test
---
.../intrinsic-header-tests/riscv_packed_simd.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
index f137e905deee70..ece5e257abba91 100644
--- a/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
+++ b/cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c
@@ -2283,7 +2283,7 @@ uint16x4_t test_pabdu_u16x4(uint16x4_t a, uint16x4_t b) {
// CHECK-LABEL: test_predsum_i8x4_i32:
// RV32: predsum.bs
-// RV64: zext.w
+// RV64: pack{{[[:space:]]}}
// RV64: predsum.bs
int32_t test_predsum_i8x4_i32(int8x4_t a, int32_t b) {
return __riscv_predsum_i8x4_i32(a, b);
@@ -2291,7 +2291,7 @@ int32_t test_predsum_i8x4_i32(int8x4_t a, int32_t b) {
// CHECK-LABEL: test_predsumu_u8x4_u32:
// RV32: predsumu.bs
-// RV64: zext.w
+// RV64: pack{{[[:space:]]}}
// RV64: predsumu.bs
uint32_t test_predsumu_u8x4_u32(uint8x4_t a, uint32_t b) {
return __riscv_predsumu_u8x4_u32(a, b);
@@ -2299,7 +2299,7 @@ uint32_t test_predsumu_u8x4_u32(uint8x4_t a, uint32_t b) {
// CHECK-LABEL: test_predsum_i16x2_i32:
// RV32: predsum.hs
-// RV64: zext.w
+// RV64: pack{{[[:space:]]}}
// RV64: predsum.hs
int32_t test_predsum_i16x2_i32(int16x2_t a, int32_t b) {
return __riscv_predsum_i16x2_i32(a, b);
@@ -2307,7 +2307,7 @@ int32_t test_predsum_i16x2_i32(int16x2_t a, int32_t b) {
// CHECK-LABEL: test_predsumu_u16x2_u32:
// RV32: predsumu.hs
-// RV64: zext.w
+// RV64: pack{{[[:space:]]}}
// RV64: predsumu.hs
uint32_t test_predsumu_u16x2_u32(uint16x2_t a, uint32_t b) {
return __riscv_predsumu_u16x2_u32(a, b);
@@ -3470,7 +3470,7 @@ uint32x2_t test_prev_u32x2(uint32x2_t a) { return __riscv_prev_u32x2(a); }
// CHECK-LABEL: test_pabdsumu_u8x4_u32:
// RV32: pabdsumu.b
-// RV64: zext.w
+// RV64: pack{{[[:space:]]}}
// RV64: pabdsumu.b
uint32_t test_pabdsumu_u8x4_u32(uint8x4_t a, uint8x4_t b) {
return __riscv_pabdsumu_u8x4_u32(a, b);
@@ -3478,7 +3478,7 @@ uint32_t test_pabdsumu_u8x4_u32(uint8x4_t a, uint8x4_t b) {
// CHECK-LABEL: test_pabdsumau_u8x4_u32:
// RV32: pabdsumau.b
-// RV64: zext.w
+// RV64: pack{{[[:space:]]}}
// RV64: pabdsumau.b
uint32_t test_pabdsumau_u8x4_u32(uint32_t rd, uint8x4_t a, uint8x4_t b) {
return __riscv_pabdsumau_u8x4_u32(rd, a, b);
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