[llvm-branch-commits] [llvm] PowerPC: Move subtarget features to PPCFeatures.td (PR #233059)
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Sat Oct 17 03:01:42 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-powerpc
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
Move the subtarget features, predicates and processor feature lists out
of PPC.td, so they can be used without parsing the instruction and
register definitions.
Co-authored-by: Claude Opus 5.5 <noreply@<!-- -->anthropic.com>
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Patch is 62.97 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/233059.diff
2 Files Affected:
- (modified) llvm/lib/Target/PowerPC/PPC.td (+1-566)
- (added) llvm/lib/Target/PowerPC/PPCFeatures.td (+574)
``````````diff
diff --git a/llvm/lib/Target/PowerPC/PPC.td b/llvm/lib/Target/PowerPC/PPC.td
index 0d691766202e6..fdb84e14655d9 100644
--- a/llvm/lib/Target/PowerPC/PPC.td
+++ b/llvm/lib/Target/PowerPC/PPC.td
@@ -14,572 +14,7 @@
//
include "llvm/Target/Target.td"
-//===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
-//
-
-//===----------------------------------------------------------------------===//
-// CPU Directives //
-//===----------------------------------------------------------------------===//
-
-// These are only used for profitability decisions, so ignore during inlining.
-class Directive<string enum_name>
- : SubtargetFeature<"", "CPUDirective", enum_name, "", [], InlineIgnore>;
-
-def Directive440 : Directive<"PPC::DIR_440">;
-def Directive601 : Directive<"PPC::DIR_601">;
-def Directive602 : Directive<"PPC::DIR_602">;
-def Directive603 : Directive<"PPC::DIR_603">;
-def Directive604 : Directive<"PPC::DIR_603">;
-def Directive620 : Directive<"PPC::DIR_603">;
-def Directive7400: Directive<"PPC::DIR_7400">;
-def Directive750 : Directive<"PPC::DIR_750">;
-def Directive970 : Directive<"PPC::DIR_970">;
-def Directive32 : Directive<"PPC::DIR_32">;
-def Directive64 : Directive<"PPC::DIR_64">;
-def DirectiveA2 : Directive<"PPC::DIR_A2">;
-def DirectiveE500 : Directive<"PPC::DIR_E500">;
-def DirectiveE500mc : Directive<"PPC::DIR_E500mc">;
-def DirectiveE5500 : Directive<"PPC::DIR_E5500">;
-def DirectivePwr3: Directive<"PPC::DIR_PWR3">;
-def DirectivePwr4: Directive<"PPC::DIR_PWR4">;
-def DirectivePwr5: Directive<"PPC::DIR_PWR5">;
-def DirectivePwr5x : Directive<"PPC::DIR_PWR5X">;
-def DirectivePwr6: Directive<"PPC::DIR_PWR6">;
-def DirectivePwr6x : Directive<"PPC::DIR_PWR6X">;
-def DirectivePwr7: Directive<"PPC::DIR_PWR7">;
-def DirectivePwr8: Directive<"PPC::DIR_PWR8">;
-def DirectivePwr9: Directive<"PPC::DIR_PWR9">;
-def DirectivePwr10: Directive<"PPC::DIR_PWR10">;
-def DirectivePwr11: Directive<"PPC::DIR_PWR11">;
-def DirectivePwrFuture : Directive<"PPC::DIR_PWR_FUTURE">;
-
-// Specifies that the selected CPU supports 64-bit instructions, regardless of
-// whether we are in 32-bit or 64-bit mode.
-def Feature64BitSupport : SubtargetFeature<"64bit-support", "Has64BitSupport", "true",
- "Supports 64-bit instructions">;
-// 64-bit is enabled.
-def Feature64Bit : SubtargetFeature<"64bit", "IsPPC64", "true",
- "Enable 64-bit mode",
- [Feature64BitSupport],
- InlineMustMatch>;
-
-def AIXOS: SubtargetFeature<"aix", "IsAIX", "true", "AIX OS">;
-def FeatureModernAIXAs
- : SubtargetFeature<"modern-aix-as", "HasModernAIXAs", "true",
- "AIX system assembler is modern enough to support new mnes">;
-def FeatureHardFloat : SubtargetFeature<"hard-float", "HasHardFloat", "true",
- "Enable floating-point instructions">;
-
-// Specifies that we are in 64-bit mode or that we should use 64-bit registers
-// in 32-bit mode when possible. Requires Feature64Bit to be enabled.
-def Feature64BitRegs : SubtargetFeature<"64bitregs","Use64BitRegs", "true",
- "Enable 64-bit registers usage for ppc32 [beta]">;
-
-// Specify if we should store and manipulate i1 values in the individual
-// condition register bits.
-def FeatureCRBits : SubtargetFeature<"crbits", "UseCRBits", "true",
- "Use condition-register bits individually">;
-def FeatureFPU : SubtargetFeature<"fpu","HasFPU","true",
- "Enable classic FPU instructions",
- [FeatureHardFloat]>;
-def FeatureAltivec : SubtargetFeature<"altivec","HasAltivec", "true",
- "Enable Altivec instructions",
- [FeatureFPU]>;
-def FeatureSPE : SubtargetFeature<"spe","HasSPE", "true",
- "Enable SPE instructions",
- [FeatureHardFloat]>;
-def FeatureEFPU2 : SubtargetFeature<"efpu2", "HasEFPU2", "true",
- "Enable Embedded Floating-Point APU 2 instructions",
- [FeatureSPE]>;
-def FeatureMFOCRF : SubtargetFeature<"mfocrf","HasMFOCRF", "true",
- "Enable the MFOCRF instruction">;
-def FeatureFSqrt : SubtargetFeature<"fsqrt","HasFSQRT", "true",
- "Enable the fsqrt instruction",
- [FeatureFPU]>;
-def FeatureFCPSGN : SubtargetFeature<"fcpsgn", "HasFCPSGN", "true",
- "Enable the fcpsgn instruction",
- [FeatureFPU]>;
-def FeatureFRE : SubtargetFeature<"fre", "HasFRE", "true",
- "Enable the fre instruction",
- [FeatureFPU]>;
-def FeatureFRES : SubtargetFeature<"fres", "HasFRES", "true",
- "Enable the fres instruction",
- [FeatureFPU]>;
-def FeatureFRSQRTE : SubtargetFeature<"frsqrte", "HasFRSQRTE", "true",
- "Enable the frsqrte instruction",
- [FeatureFPU]>;
-def FeatureFRSQRTES : SubtargetFeature<"frsqrtes", "HasFRSQRTES", "true",
- "Enable the frsqrtes instruction",
- [FeatureFPU]>;
-def FeatureRecipPrec : SubtargetFeature<"recipprec", "HasRecipPrec", "true",
- "Assume higher precision reciprocal estimates">;
-def FeatureSTFIWX : SubtargetFeature<"stfiwx","HasSTFIWX", "true",
- "Enable the stfiwx instruction",
- [FeatureFPU]>;
-def FeatureLFIWAX : SubtargetFeature<"lfiwax","HasLFIWAX", "true",
- "Enable the lfiwax instruction",
- [FeatureFPU]>;
-def FeatureFPRND : SubtargetFeature<"fprnd", "HasFPRND", "true",
- "Enable the fri[mnpz] instructions",
- [FeatureFPU]>;
-def FeatureFPCVT : SubtargetFeature<"fpcvt", "HasFPCVT", "true",
- "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
- [FeatureFPU]>;
-def FeatureISEL : SubtargetFeature<"isel","HasISEL", "true",
- "Enable the isel instruction">;
-def FeatureBPERMD : SubtargetFeature<"bpermd", "HasBPERMD", "true",
- "Enable the bpermd instruction">;
-def FeatureExtDiv : SubtargetFeature<"extdiv", "HasExtDiv", "true",
- "Enable extended divide instructions">;
-def FeatureLDBRX : SubtargetFeature<"ldbrx","HasLDBRX", "true",
- "Enable the ldbrx instruction">;
-def FeatureCMPB : SubtargetFeature<"cmpb", "HasCMPB", "true",
- "Enable the cmpb instruction">;
-def FeatureICBT : SubtargetFeature<"icbt","HasICBT", "true",
- "Enable icbt instruction">;
-def FeatureBookE : SubtargetFeature<"booke", "IsBookE", "true",
- "Enable Book E instructions",
- [FeatureICBT]>;
-def FeatureMSYNC : SubtargetFeature<"msync", "HasOnlyMSYNC", "true",
- "Has only the msync instruction instead of sync",
- [FeatureBookE]>;
-def FeatureE500 : SubtargetFeature<"e500", "IsE500", "true",
- "Enable E500/E500mc instructions">;
-def FeatureSecurePlt : SubtargetFeature<"secure-plt","IsSecurePlt", "true",
- "Enable secure plt mode">;
-def FeaturePPC4xx : SubtargetFeature<"ppc4xx", "IsPPC4xx", "true",
- "Enable PPC 4xx instructions">;
-def FeaturePPC6xx : SubtargetFeature<"ppc6xx", "IsPPC6xx", "true",
- "Enable PPC 6xx instructions">;
-def FeatureVSX : SubtargetFeature<"vsx","HasVSX", "true",
- "Enable VSX instructions",
- [FeatureAltivec]>;
-def FeatureTwoConstNR :
- SubtargetFeature<"two-const-nr", "NeedsTwoConstNR", "true",
- "Requires two constant Newton-Raphson computation">;
-def FeatureP8Altivec : SubtargetFeature<"power8-altivec", "HasP8Altivec", "true",
- "Enable POWER8 Altivec instructions",
- [FeatureAltivec]>;
-def FeatureP8Crypto : SubtargetFeature<"crypto", "HasP8Crypto", "true",
- "Enable POWER8 Crypto instructions",
- [FeatureP8Altivec]>;
-def FeatureP8Vector : SubtargetFeature<"power8-vector", "HasP8Vector", "true",
- "Enable POWER8 vector instructions",
- [FeatureVSX, FeatureP8Altivec]>;
-def FeatureDirectMove :
- SubtargetFeature<"direct-move", "HasDirectMove", "true",
- "Enable Power8 direct move instructions",
- [FeatureVSX]>;
-def FeaturePartwordAtomic : SubtargetFeature<"partword-atomics",
- "HasPartwordAtomics", "true",
- "Enable l[bh]arx and st[bh]cx.">;
-def FeatureQuadwordAtomic : SubtargetFeature<"quadword-atomics",
- "HasQuadwordAtomics", "true",
- "Enable lqarx and stqcx.">;
-def FeatureInvariantFunctionDescriptors :
- SubtargetFeature<"invariant-function-descriptors",
- "HasInvariantFunctionDescriptors", "true",
- "Assume function descriptors are invariant",
- [], InlineInverse>;
-def FeatureLongCall : SubtargetFeature<"longcall", "UseLongCalls", "true",
- "Always use indirect calls">;
-def FeatureHTM : SubtargetFeature<"htm", "HasHTM", "true",
- "Enable Hardware Transactional Memory instructions">;
-def FeatureMFTB : SubtargetFeature<"", "IsFeatureMFTB", "true",
- "Implement mftb using the mfspr instruction">;
-def FeatureFusion : SubtargetFeature<"fusion", "HasFusion", "true",
- "Target supports instruction fusion">;
-def FeatureAddiLoadFusion : SubtargetFeature<"fuse-addi-load",
- "HasAddiLoadFusion", "true",
- "Power8 Addi-Load fusion",
- [FeatureFusion]>;
-def FeatureAddisLoadFusion : SubtargetFeature<"fuse-addis-load",
- "HasAddisLoadFusion", "true",
- "Power8 Addis-Load fusion",
- [FeatureFusion]>;
-def FeatureStoreFusion : SubtargetFeature<"fuse-store", "HasStoreFusion", "true",
- "Target supports store clustering",
- [FeatureFusion]>;
-def FeatureArithAddFusion :
- SubtargetFeature<"fuse-arith-add", "HasArithAddFusion", "true",
- "Target supports Arithmetic Operations with Add fusion",
- [FeatureFusion]>;
-def FeatureAddLogicalFusion :
- SubtargetFeature<"fuse-add-logical", "HasAddLogicalFusion", "true",
- "Target supports Add with Logical Operations fusion",
- [FeatureFusion]>;
-def FeatureLogicalAddFusion :
- SubtargetFeature<"fuse-logical-add", "HasLogicalAddFusion", "true",
- "Target supports Logical with Add Operations fusion",
- [FeatureFusion]>;
-def FeatureLogicalFusion :
- SubtargetFeature<"fuse-logical", "HasLogicalFusion", "true",
- "Target supports Logical Operations fusion",
- [FeatureFusion]>;
-def FeatureSha3Fusion :
- SubtargetFeature<"fuse-sha3", "HasSha3Fusion", "true",
- "Target supports SHA3 assist fusion",
- [FeatureFusion]>;
-def FeatureCompareFusion:
- SubtargetFeature<"fuse-cmp", "HasCompareFusion", "true",
- "Target supports Comparison Operations fusion",
- [FeatureFusion]>;
-def FeatureWideImmFusion:
- SubtargetFeature<"fuse-wideimm", "HasWideImmFusion", "true",
- "Target supports Wide-Immediate fusion",
- [FeatureFusion]>;
-def FeatureZeroMoveFusion:
- SubtargetFeature<"fuse-zeromove", "HasZeroMoveFusion", "true",
- "Target supports move to SPR with branch fusion",
- [FeatureFusion]>;
-def FeatureBack2BackFusion:
- SubtargetFeature<"fuse-back2back", "HasBack2BackFusion", "true",
- "Target supports general back to back fusion",
- [FeatureFusion]>;
-def FeatureUnalignedFloats :
- SubtargetFeature<"allow-unaligned-fp-access", "AllowsUnalignedFPAccess",
- "true", "CPU does not trap on unaligned FP access">;
-def FeaturePPCPreRASched:
- SubtargetFeature<"ppc-prera-sched", "UsePPCPreRASchedStrategy", "true",
- "Use PowerPC pre-RA scheduling strategy",
- [], InlineIgnore>;
-def FeaturePPCPostRASched:
- SubtargetFeature<"ppc-postra-sched", "UsePPCPostRASchedStrategy", "true",
- "Use PowerPC post-RA scheduling strategy",
- [], InlineIgnore>;
-def FeatureFloat128 :
- SubtargetFeature<"float128", "HasFloat128", "true",
- "Enable the __float128 data type for IEEE-754R Binary128.",
- [FeatureVSX]>;
-def FeaturePOPCNTD : SubtargetFeature<"popcntd","HasPOPCNTD",
- "POPCNTD_Fast",
- "Enable the popcnt[dw] instructions">;
-// Note that for the a2 processor models we should not use popcnt[dw] by
-// default. These processors do support the instructions, but they're
-// microcoded, and the software emulation is about twice as fast.
-def FeatureSlowPOPCNTD : SubtargetFeature<"slow-popcntd","HasPOPCNTD",
- "POPCNTD_Slow",
- "Has slow popcnt[dw] instructions",
- [], InlineIgnore>;
-
-def DeprecatedDST : SubtargetFeature<"", "IsDeprecatedDST", "true",
- "Treat vector data stream cache control instructions as deprecated">;
-
-def FeatureISA2_06 : SubtargetFeature<"isa-v206-instructions", "IsISA2_06",
- "true",
- "Enable instructions in ISA 2.06.">;
-def FeatureISA2_07 : SubtargetFeature<"isa-v207-instructions", "IsISA2_07",
- "true",
- "Enable instructions in ISA 2.07.">;
-def FeatureISA3_0 : SubtargetFeature<"isa-v30-instructions", "IsISA3_0",
- "true",
- "Enable instructions in ISA 3.0.",
- [FeatureISA2_07]>;
-def FeatureISA3_1 : SubtargetFeature<"isa-v31-instructions", "IsISA3_1",
- "true",
- "Enable instructions in ISA 3.1.",
- [FeatureISA3_0]>;
-def FeatureISAFuture : SubtargetFeature<"isa-future-instructions",
- "IsISAFuture", "true",
- "Enable instructions for Future ISA.",
- [FeatureISA3_1]>;
-def FeatureP9Altivec : SubtargetFeature<"power9-altivec", "HasP9Altivec", "true",
- "Enable POWER9 Altivec instructions",
- [FeatureISA3_0, FeatureP8Altivec]>;
-def FeatureP9Vector : SubtargetFeature<"power9-vector", "HasP9Vector", "true",
- "Enable POWER9 vector instructions",
- [FeatureISA3_0, FeatureP8Vector,
- FeatureP9Altivec]>;
-def FeatureP10Vector : SubtargetFeature<"power10-vector", "HasP10Vector",
- "true",
- "Enable POWER10 vector instructions",
- [FeatureISA3_1, FeatureP9Vector]>;
-def FeatureFutureVector : SubtargetFeature<"future-vector", "HasFutureVector",
- "true",
- "Enable Future vector instructions",
- [FeatureISAFuture, FeatureP10Vector]>;
-// A separate feature for this even though it is equivalent to P9Vector
-// because this is a feature of the implementation rather than the architecture
-// and may go away with future CPU's.
-def FeatureVectorsUseTwoUnits : SubtargetFeature<"vectors-use-two-units",
- "VectorsUseTwoUnits",
- "true",
- "Vectors use two units",
- [], InlineIgnore>;
-def FeaturePrefixInstrs : SubtargetFeature<"prefix-instrs", "HasPrefixInstrs",
- "true",
- "Enable prefixed instructions",
- [FeatureISA3_1]>;
-def FeaturePCRelativeMemops :
- SubtargetFeature<"pcrelative-memops", "HasPCRelativeMemops", "true",
- "Enable PC relative Memory Ops",
- [FeatureISA3_0, FeaturePrefixInstrs]>;
-def FeaturePairedVectorMemops:
- SubtargetFeature<"paired-vector-memops", "PairedVectorMemops", "true",
- "32Byte load and store instructions",
- [FeatureISA3_0, FeatureVSX]>;
-def FeatureMMA : SubtargetFeature<"mma", "HasMMA", "true",
- "Enable MMA instructions",
- [FeatureP8Vector, FeatureP9Altivec,
- FeaturePairedVectorMemops]>;
-def FeatureROPProtect :
- SubtargetFeature<"rop-protect", "HasROPProtect", "true",
- "Add ROP protect">;
-
-def FeaturePrivileged :
- SubtargetFeature<"privileged", "HasPrivileged", "true",
- "Add privileged instructions">;
-
-// Specifies that local-exec TLS accesses in any function with this target
-// attribute should use the optimized TOC-free sequence (where the offset is an
-// immediate off of R13 for which the linker might add fix-up code if the
-// immediate is too large).
-// Clearly, this isn't really a feature of the subtarget, but is used as a
-// convenient way to affect code generation for individual functions.
-def FeatureAIXLocalExecTLS :
- SubtargetFeature<"aix-small-local-exec-tls", "HasAIXSmallLocalExecTLS", "true",
- "Produce a TOC-free local-exec TLS sequence for this function "
- "for 64-bit AIX">;
-
-// Specifies that local-dynamic TLS accesses in any function with this target
-// attribute should use the optimized sequence (where the offset is an immediate
-// off the module-handle for which the linker might add fix-up code for if the
-// immediate is too large).
-def FeatureAIXLocalDynamicTLS :
- SubtargetFeature<"aix-small-local-dynamic-tls", "HasAIXSmallLocalDynamicTLS",
- "true", "Produce a faster local-dynamic TLS sequence for this "
...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/233059
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