[llvm-branch-commits] [llvm] TableGen: Return early from addComposite for known compositions (PR #232815)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/232815

>From ff5a2582db008807d11bfa427bcb112978496f20 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 16 Oct 2026 05:08:45 -0700
Subject: [PATCH] TableGen: Return early from addComposite for known
 compositions

computeComposites calls addComposite for each pair of sub-registers of
every register with a distinct sub-register structure, so most calls
repeat a composition that is already known. Each call still did three
std::map lookups per hardware mode to update the sub-register ranges.
If the composition already exists and its result has an offset in every
mode, the rest of the function has no effect, so return early. Cache
whether the result has an offset in every mode, since offsets are never
cleared once set.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    916               540            169
  After     797 (-13.0%)      489 (-9.5%)    153 (-9.4%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/utils/TableGen/Common/CodeGenRegisters.h | 22 ++++++++++++++++++-
 1 file changed, 21 insertions(+), 1 deletion(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 38f7461482993..439d05aca1398 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -110,12 +110,18 @@ class CodeGenSubRegIndex {
                                    const CodeGenHwModes &CGH) {
     assert(A && B);
     std::pair<CompMap::iterator, bool> Ins = Composed.try_emplace(A, B);
+    unsigned NumModes = CGH.getNumModeIds();
+
+    // An earlier identical call already added the ranges for every mode, so
+    // there is nothing left to do once B has an offset in all of them.
+    if (!Ins.second && Ins.first->second == B &&
+        B->hasOffsetInAllModes(NumModes))
+      return nullptr;
 
     // Synthetic subreg indices that aren't contiguous (for instance ARM
     // register tuples) don't have a bit range, so it's OK to let
     // B->Offset == -1. For the other cases, accumulate the offset and set
     // the size here. Only do so if there is no offset yet though.
-    unsigned NumModes = CGH.getNumModeIds();
     // Skip default mode.
     for (unsigned M = 0; M < NumModes; ++M) {
       // Handle DefaultMode last.
@@ -165,6 +171,20 @@ class CodeGenSubRegIndex {
   }
 
 private:
+  // Return true if Range has an offset in all NumModes modes. Offsets are
+  // never cleared once set, so cache a true result.
+  bool hasOffsetInAllModes(unsigned NumModes) {
+    if (OffsetInAllModes)
+      return true;
+
+    OffsetInAllModes =
+        Range.size() == NumModes && all_of(Range, [](const auto &P) {
+          return P.second.Offset != (uint32_t)-1;
+        });
+    return OffsetInAllModes;
+  }
+
+  bool OffsetInAllModes = false;
   CompMap Composed;
 };