[llvm-branch-commits] [llvm] TableGen: Skip classes without matching super-register classes in RegisterBankEmitter (PR #232817)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/232817

>From a2af6eea2f5aa4e9839838670e4c0809a055d149 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 16 Oct 2026 05:34:41 -0700
Subject: [PATCH] TableGen: Skip classes without matching super-register
 classes in RegisterBankEmitter

visitRegisterBankClasses checks every sub-register index for every pair
of register classes. Skip the per-index loop if RC is not in any of the
class's super-register class sets.

AMDGPU tablegen run for AMDGPUGenRegisterBank.inc:

            Gigacycles     CPU seconds
  Before    51.7           16.0
  After     48.4 (-6.4%)   14.9 (-6.9%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 6 ++++++
 llvm/utils/TableGen/Common/CodeGenRegisters.h   | 3 +++
 llvm/utils/TableGen/RegisterBankEmitter.cpp     | 3 +++
 3 files changed, 12 insertions(+)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 117a4de93923ac..52b70259aa8d79 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1174,6 +1174,12 @@ bool CodeGenRegisterClass::hasSuperRegClass(
   return FindI != SuperRegClasses.end() && FindI->second.contains(RC);
 }
 
+bool CodeGenRegisterClass::hasSuperRegClass(
+    const CodeGenRegisterClass *RC) const {
+  return any_of(SuperRegClasses,
+                [RC](const auto &Entry) { return Entry.second.contains(RC); });
+}
+
 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
                                               BitVector &Out) const {
   auto FindI = SuperRegClasses.find(SubIdx);
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.h b/llvm/utils/TableGen/Common/CodeGenRegisters.h
index 439d05aca13981..333bc4aa073147 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.h
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.h
@@ -494,6 +494,9 @@ class CodeGenRegisterClass {
   bool hasSuperRegClass(const CodeGenSubRegIndex *SubIdx,
                         const CodeGenRegisterClass *RC) const;
 
+  /// Checks if RC is a super-register class of this class for any SubIdx.
+  bool hasSuperRegClass(const CodeGenRegisterClass *RC) const;
+
   // getSuperRegClasses - Returns a bit vector of all register classes
   // containing only SubIdx super-registers of this class.
   void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
diff --git a/llvm/utils/TableGen/RegisterBankEmitter.cpp b/llvm/utils/TableGen/RegisterBankEmitter.cpp
index c53aca44440575..a0a33815509fe8 100644
--- a/llvm/utils/TableGen/RegisterBankEmitter.cpp
+++ b/llvm/utils/TableGen/RegisterBankEmitter.cpp
@@ -205,6 +205,9 @@ static void visitRegisterBankClasses(
     // More precisely, PossibleSubclass is a subreg-class iff Reg:SubIdx is in
     // PossibleSubclass for all registers Reg from RC using any
     // subregister-index SubReg
+    if (!PossibleSubclass.hasSuperRegClass(RC))
+      continue;
+
     for (const auto &SubIdx : RegisterClassHierarchy.getSubRegIndices()) {
       if (PossibleSubclass.hasSuperRegClass(&SubIdx, RC)) {
         std::string TmpKind2 = (Twine(TmpKind) + " " + RC->getName() +