[llvm-branch-commits] [llvm] TableGen: Insert super-register class sets in one step (PR #232816)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/232816

>From 60a5f1822bdb51f73edaf2b26eec2e7f10e5b842 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 16 Oct 2026 05:24:35 -0700
Subject: [PATCH] TableGen: Insert super-register class sets in one step

extendSuperRegClasses added each super-register class to the composed
index's set with a separate addSuperRegClass call, which looks up the
set in the DenseMap every time. Look up the set once and insert the
whole range.

AMDGPU tablegen runs that build the register bank:

            Gigainstructions  Gigacycles     CPU seconds
  Before    797               489            153
  After     755 (-5.2%)       477 (-2.4%)    149 (-2.5%)

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/utils/TableGen/Common/CodeGenRegisters.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 6a868d7925a14..117a4de93923a 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1215,8 +1215,7 @@ void CodeGenRegisterClass::extendSuperRegClasses(CodeGenSubRegIndex *SubIdx) {
       if (!ComposedSubIdx)
         continue;
 
-      for (CodeGenRegisterClass *SuperRC : Pair.second)
-        addSuperRegClass(ComposedSubIdx, SuperRC);
+      SuperRegClasses[ComposedSubIdx].insert_range(Pair.second);
     }
   }
 }