[llvm-branch-commits] [llvm] [RISCV][P-ext] Call tryWidenMaskForShuffle at the end of P extension shuffle lowering. (PR #232892)
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Fri Oct 16 11:48:53 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-risc-v
Author: Craig Topper (topperc)
<details>
<summary>Changes</summary>
If the shuffle mask has contiguous elements we can try shuffling them using a large element type.
---
Full diff: https://github.com/llvm/llvm-project/pull/232892.diff
3 Files Affected:
- (modified) llvm/lib/Target/RISCV/RISCVISelLowering.cpp (+4-1)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-32.ll (-8)
- (modified) llvm/test/CodeGen/RISCV/rvp-simd-64.ll (+24-48)
``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index cd86cfa76fc81..d26dafb6ba308 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -6746,7 +6746,10 @@ SDValue RISCVTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
return V;
if (SDValue V = lowerVECTOR_SHUFFLEAsPPair(SVN, DAG, Subtarget.is64Bit()))
return V;
- return SDValue();
+
+ // As a last resort, widen the elements so the shuffle can be matched on a
+ // wider type, e.g. v4i16 <0,1,6,7> -> v2i32 <0,3>.
+ return tryWidenMaskForShuffle(Op, DAG);
}
if (VT.getVectorElementType() == MVT::i1) {
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
index 2cb3fac1ce2ae..15e4cb5c2fd0f 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-32.ll
@@ -3338,10 +3338,6 @@ define <4 x i8> @test_pnclipp_v4i8(<2 x i16> %a, <2 x i16> %b) {
;
; RV64-LABEL: test_pnclipp_v4i8:
; RV64: # %bb.0:
-; RV64-NEXT: srli a2, a1, 16
-; RV64-NEXT: srli a3, a0, 16
-; RV64-NEXT: ppaire.h a1, a1, a2
-; RV64-NEXT: ppaire.h a0, a0, a3
; RV64-NEXT: pack a0, a0, a1
; RV64-NEXT: pnclipp.b a0, a0, a0
; RV64-NEXT: ret
@@ -3357,10 +3353,6 @@ define <4 x i8> @test_pnclipup_v4i8(<2 x i16> %a, <2 x i16> %b) {
;
; RV64-LABEL: test_pnclipup_v4i8:
; RV64: # %bb.0:
-; RV64-NEXT: srli a2, a1, 16
-; RV64-NEXT: srli a3, a0, 16
-; RV64-NEXT: ppaire.h a1, a1, a2
-; RV64-NEXT: ppaire.h a0, a0, a3
; RV64-NEXT: pack a0, a0, a1
; RV64-NEXT: pnclipup.b a0, a0, a0
; RV64-NEXT: ret
diff --git a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
index ee26f6ab53dd0..650603bde85c4 100644
--- a/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
+++ b/llvm/test/CodeGen/RISCV/rvp-simd-64.ll
@@ -2830,35 +2830,23 @@ define <8 x i8> @test_pmulhsu_b(<8 x i8> %a, <8 x i8> %b) {
;
; RV64-LABEL: test_pmulhsu_b:
; RV64: # %bb.0:
-; RV64-NEXT: srli a2, a0, 56
-; RV64-NEXT: srli a3, a0, 48
-; RV64-NEXT: srli a4, a0, 40
-; RV64-NEXT: srli a5, a0, 32
-; RV64-NEXT: ppaire.b a2, a3, a2
-; RV64-NEXT: ppaire.b a3, a5, a4
-; RV64-NEXT: ppaire.h a2, a3, a2
-; RV64-NEXT: pwcvtu.wb a2, a2
-; RV64-NEXT: srli a3, a1, 56
-; RV64-NEXT: srli a4, a1, 48
-; RV64-NEXT: psext.h.b a2, a2
-; RV64-NEXT: ppaire.b a3, a4, a3
-; RV64-NEXT: srli a4, a1, 40
-; RV64-NEXT: srli a5, a1, 32
+; RV64-NEXT: pwcvtu.wb a2, a0
+; RV64-NEXT: ppairoe.w a0, a0, a0
+; RV64-NEXT: ppairoe.w a3, a1, a1
; RV64-NEXT: pwcvtu.wb a0, a0
-; RV64-NEXT: ppaire.b a4, a5, a4
+; RV64-NEXT: psext.h.b a2, a2
; RV64-NEXT: psext.h.b a0, a0
-; RV64-NEXT: ppaire.h a3, a4, a3
-; RV64-NEXT: pwcvtu.wb a3, a3
; RV64-NEXT: pwcvtu.wb a1, a1
-; RV64-NEXT: pmul.w.h11 a4, a2, a3
-; RV64-NEXT: pmul.w.h00 a2, a2, a3
-; RV64-NEXT: pmul.w.h11 a3, a0, a1
-; RV64-NEXT: pmul.w.h00 a0, a0, a1
-; RV64-NEXT: ppaire.h a1, a2, a4
-; RV64-NEXT: ppaire.h a0, a0, a3
+; RV64-NEXT: pwcvtu.wb a3, a3
+; RV64-NEXT: pmul.w.h11 a4, a0, a3
+; RV64-NEXT: pmul.w.h00 a0, a0, a3
+; RV64-NEXT: pmul.w.h11 a3, a2, a1
+; RV64-NEXT: pmul.w.h00 a1, a2, a1
+; RV64-NEXT: ppaire.h a0, a0, a4
+; RV64-NEXT: ppaire.h a1, a1, a3
; RV64-NEXT: psrli.h a1, a1, 8
; RV64-NEXT: psrli.h a0, a0, 8
-; RV64-NEXT: unzip8p a0, a0, a1
+; RV64-NEXT: unzip8p a0, a1, a0
; RV64-NEXT: ret
%a_ext = sext <8 x i8> %a to <8 x i16>
%b_ext = zext <8 x i8> %b to <8 x i16>
@@ -2879,35 +2867,23 @@ define <8 x i8> @test_pmulhsu_b_commuted(<8 x i8> %a, <8 x i8> %b) {
;
; RV64-LABEL: test_pmulhsu_b_commuted:
; RV64: # %bb.0:
-; RV64-NEXT: srli a2, a0, 56
-; RV64-NEXT: srli a3, a0, 48
-; RV64-NEXT: srli a4, a0, 40
-; RV64-NEXT: srli a5, a0, 32
-; RV64-NEXT: ppaire.b a2, a3, a2
-; RV64-NEXT: ppaire.b a3, a5, a4
-; RV64-NEXT: srli a4, a1, 56
-; RV64-NEXT: srli a5, a1, 48
-; RV64-NEXT: ppaire.h a2, a3, a2
-; RV64-NEXT: ppaire.b a3, a5, a4
-; RV64-NEXT: srli a4, a1, 40
-; RV64-NEXT: srli a5, a1, 32
-; RV64-NEXT: pwcvtu.wb a2, a2
-; RV64-NEXT: ppaire.b a4, a5, a4
+; RV64-NEXT: pwcvtu.wb a2, a0
+; RV64-NEXT: ppairoe.w a0, a0, a0
+; RV64-NEXT: ppairoe.w a3, a1, a1
; RV64-NEXT: pwcvtu.wb a0, a0
-; RV64-NEXT: ppaire.h a3, a4, a3
-; RV64-NEXT: pwcvtu.wb a3, a3
; RV64-NEXT: pwcvtu.wb a1, a1
-; RV64-NEXT: psext.h.b a3, a3
+; RV64-NEXT: pwcvtu.wb a3, a3
; RV64-NEXT: psext.h.b a1, a1
-; RV64-NEXT: pmul.w.h11 a4, a2, a3
-; RV64-NEXT: pmul.w.h00 a2, a2, a3
-; RV64-NEXT: pmul.w.h11 a3, a0, a1
-; RV64-NEXT: pmul.w.h00 a0, a0, a1
-; RV64-NEXT: ppaire.h a1, a2, a4
-; RV64-NEXT: ppaire.h a0, a0, a3
+; RV64-NEXT: psext.h.b a3, a3
+; RV64-NEXT: pmul.w.h11 a4, a0, a3
+; RV64-NEXT: pmul.w.h00 a0, a0, a3
+; RV64-NEXT: pmul.w.h11 a3, a2, a1
+; RV64-NEXT: pmul.w.h00 a1, a2, a1
+; RV64-NEXT: ppaire.h a0, a0, a4
+; RV64-NEXT: ppaire.h a1, a1, a3
; RV64-NEXT: psrli.h a1, a1, 8
; RV64-NEXT: psrli.h a0, a0, 8
-; RV64-NEXT: unzip8p a0, a0, a1
+; RV64-NEXT: unzip8p a0, a1, a0
; RV64-NEXT: ret
%a_ext = zext <8 x i8> %a to <8 x i16>
%b_ext = sext <8 x i8> %b to <8 x i16>
``````````
</details>
https://github.com/llvm/llvm-project/pull/232892
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