[llvm-branch-commits] [llvm] DAG: Don't export arguments for FastISel if it won't be used (PR #232309)
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llvm-branch-commits at lists.llvm.org
Thu Oct 15 05:57:59 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-selectiondag
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
LowerArguments decided whether to export arguments to virtual
registers based on TM.Options.EnableFastISel. That option is set at
-O0 even for targets that have no FastISel implementation. This is
unnecessary without fast isel, so stop doing that.
The unneeded CopyToReg was an extra use of every argument, which
blocked some combines. The dead copies also survived to register
allocation. These copies were an edge case that regallocfast would
introduce dead flags on.
Co-authored-by: Claude Opus 5.5 <noreply@<!-- -->anthropic.com>
---
Patch is 771.76 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/232309.diff
42 Files Affected:
- (modified) llvm/include/llvm/CodeGen/SelectionDAGISel.h (+3-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp (+2-2)
- (modified) llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp (+2-2)
- (modified) llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll (+336-352)
- (modified) llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll (-2)
- (modified) llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll (+216-232)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll (+60-60)
- (modified) llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll (+36-36)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll (+85-134)
- (modified) llvm/test/CodeGen/AMDGPU/wwm-reserved.ll (+40-40)
- (modified) llvm/test/CodeGen/ARM/strict-fp-int-promote.ll (+10-4)
- (modified) llvm/test/CodeGen/Mips/atomic.ll (+2-4)
- (modified) llvm/test/CodeGen/NVPTX/address-folder.ll (+4-4)
- (modified) llvm/test/CodeGen/NVPTX/bfe.ll (+24-44)
- (modified) llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll (+26-42)
- (modified) llvm/test/CodeGen/NVPTX/combine-wide.ll (+228-431)
- (modified) llvm/test/CodeGen/NVPTX/f16-instructions.ll (+42-37)
- (modified) llvm/test/CodeGen/NVPTX/f16x2-instructions.ll (+522-621)
- (modified) llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll (+38-43)
- (modified) llvm/test/CodeGen/NVPTX/f32x2-instructions.ll (+309-438)
- (modified) llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/i128-array.ll (+5-7)
- (modified) llvm/test/CodeGen/NVPTX/i128-ld-st.ll (+4-4)
- (modified) llvm/test/CodeGen/NVPTX/i128-param.ll (+2-2)
- (modified) llvm/test/CodeGen/NVPTX/i128-retval.ll (+1-1)
- (modified) llvm/test/CodeGen/NVPTX/i16x2-instructions.ll (+132-217)
- (modified) llvm/test/CodeGen/NVPTX/i32x2-instructions.ll (+303-418)
- (modified) llvm/test/CodeGen/NVPTX/i8x2-instructions.ll (+7-17)
- (modified) llvm/test/CodeGen/NVPTX/i8x4-instructions.ll (+725-1475)
- (modified) llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll (+1-2)
- (modified) llvm/test/CodeGen/NVPTX/mulwide.ll (+29-81)
- (modified) llvm/test/CodeGen/NVPTX/param-load-store.ll (+20-27)
- (modified) llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll (+746-932)
- (modified) llvm/test/CodeGen/NVPTX/vaargs.ll (+36-34)
- (modified) llvm/test/CodeGen/PowerPC/ppcsoftops.ll (+1-4)
- (modified) llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll (-2)
- (modified) llvm/test/CodeGen/SPARC/fp16-promote.ll (+8-19)
- (modified) llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll (-1)
- (modified) llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll (-2)
- (modified) llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll (-2)
- (modified) llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll (-1)
- (modified) llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll (-2)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 7659de75c4c125..75e5927057d1d8 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -548,8 +548,9 @@ class LLVM_ABI SelectionDAGISel {
void CodeGenAndEmitDAG();
/// Generate instructions for lowering the incoming arguments of the
- /// given function.
- void LowerArguments(const Function &F);
+ /// given function. \p FastISel is true if fast-isel may select other
+ /// instructions in the function.
+ void LowerArguments(const Function &F, bool FastISel);
void ComputeLiveOutVRegInfo();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index d9c14e0f185413..fb7718580b218d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -12170,7 +12170,7 @@ static void tryToElideArgumentCopy(
}
}
-void SelectionDAGISel::LowerArguments(const Function &F) {
+void SelectionDAGISel::LowerArguments(const Function &F, bool FastISel) {
SelectionDAG &DAG = SDB->DAG;
SDLoc dl = SDB->getCurSDLoc();
const DataLayout &DL = DAG.getDataLayout();
@@ -12506,7 +12506,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
continue;
}
}
- if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) {
+ if (!isOnlyUsedInEntryBlock(&Arg, FastISel)) {
FuncInfo->InitializeRegForValue(&Arg);
SDB->CopyToExportRegsIfNeeded(&Arg);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index ba7ecdc165b1da..84958ac50ab4fd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1674,7 +1674,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
CurDAG->setFunctionLoweringInfo(FuncInfo.get());
if (!FastIS) {
- LowerArguments(Fn);
+ LowerArguments(Fn, /*FastISel=*/false);
} else {
// See if fast isel can lower the arguments.
FastIS->startNewBlock();
@@ -1691,7 +1691,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
reportFastISelFailure(*MF, *ORE, R, EnableFastISelAbort > 1);
// Use SelectionDAG argument lowering
- LowerArguments(Fn);
+ LowerArguments(Fn, /*FastISel=*/true);
CurDAG->setRoot(SDB->getControlRoot());
SDB->clear();
CodeGenAndEmitDAG();
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index aabed8e2814c0d..2f99cce38db205 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -3664,35 +3664,34 @@ define i32 @extract_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr4 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v4, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v4, s5, 1
+; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v5, s5, 1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB22_1: ; =>This Inner Loop Header: Depth=1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -3705,25 +3704,25 @@ define i32 @extract_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v4, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v4, s7, 3
+; GCN-O0-NEXT: v_writelane_b32 v5, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v5, s7, 3
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB22_1
; GCN-O0-NEXT: ; %bb.2:
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3745,13 +3744,12 @@ define i32 @extract_dyn_inreg_i32_3(<3 x i32> inreg %arg, i32 inreg %idx) {
; GCN-O0-LABEL: extract_dyn_inreg_i32_3:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: s_mov_b32 m0, s19
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3776,35 +3774,34 @@ define float @extract_dyn_float_3(<3 x float> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr4 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v4, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v4, s5, 1
+; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v5, s5, 1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB24_1: ; =>This Inner Loop Header: Depth=1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -3817,25 +3814,25 @@ define float @extract_dyn_float_3(<3 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v4, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v4, s7, 3
+; GCN-O0-NEXT: v_writelane_b32 v5, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v5, s7, 3
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB24_1
; GCN-O0-NEXT: ; %bb.2:
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3861,13 +3858,12 @@ define float @extract_dyn_inreg_float_3(<3 x float> inreg %arg, i32 inreg %idx)
; GCN-O0-LABEL: extract_dyn_inreg_float_3:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: s_mov_b32 m0, s19
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3898,41 +3894,40 @@ define i32 @extract_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s20
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v6
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v5
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr6 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v6, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v6, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: ; implicit-def: $vgpr9 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v9, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v9, s5, 1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB26_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v6, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v6, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v9, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v9, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -3947,25 +3942,25 @@ define i32 @extract_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v6, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v6, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: v_writelane_b32 v9, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v9, s7, 3
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB26_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v6, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v6, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v9, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v9, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3991,17 +3986,16 @@ define i32 @extract_dyn_inreg_i32_5(<5 x i32> inreg %arg, i32 inreg %idx) {
; GCN-O0-LABEL: extract_dyn_inreg_i32_5:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/232309
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