[llvm-branch-commits] [llvm] DAG: Don't export arguments for FastISel if it won't be used (PR #232309)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Thu Oct 15 05:56:49 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/232309
LowerArguments decided whether to export arguments to virtual
registers based on TM.Options.EnableFastISel. That option is set at
-O0 even for targets that have no FastISel implementation. This is
unnecessary without fast isel, so stop doing that.
The unneeded CopyToReg was an extra use of every argument, which
blocked some combines. The dead copies also survived to register
allocation. These copies were an edge case that regallocfast would
introduce dead flags on.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
>From 87ea512f07423227933350c72ea4f23eb8a36724 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 15 Oct 2026 14:19:12 +0200
Subject: [PATCH] DAG: Don't export arguments for FastISel if it won't be used
LowerArguments decided whether to export arguments to virtual
registers based on TM.Options.EnableFastISel. That option is set at
-O0 even for targets that have no FastISel implementation. This is
unnecessary without fast isel, so stop doing that.
The unneeded CopyToReg was an extra use of every argument, which
blocked some combines. The dead copies also survived to register
allocation. These copies were an edge case that regallocfast would
introduce dead flags on.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
llvm/include/llvm/CodeGen/SelectionDAGISel.h | 5 +-
.../SelectionDAG/SelectionDAGBuilder.cpp | 4 +-
.../CodeGen/SelectionDAG/SelectionDAGISel.cpp | 4 +-
.../CodeGen/AMDGPU/extract_vector_dynelt.ll | 688 +++---
.../CodeGen/AMDGPU/i128-add-carry-chain.ll | 2 -
.../CodeGen/AMDGPU/insert_vector_dynelt.ll | 448 ++--
.../AMDGPU/memory-legalizer-buffer-atomics.ll | 120 +-
...legalizer-single-wave-workgroup-lds-dma.ll | 72 +-
.../test/CodeGen/AMDGPU/wwm-reserved-spill.ll | 219 +-
llvm/test/CodeGen/AMDGPU/wwm-reserved.ll | 80 +-
.../test/CodeGen/ARM/strict-fp-int-promote.ll | 14 +-
llvm/test/CodeGen/Mips/atomic.ll | 6 +-
llvm/test/CodeGen/NVPTX/address-folder.ll | 8 +-
llvm/test/CodeGen/NVPTX/bfe.ll | 68 +-
.../CodeGen/NVPTX/cache-hint-transforms.ll | 68 +-
llvm/test/CodeGen/NVPTX/combine-wide.ll | 659 ++---
llvm/test/CodeGen/NVPTX/f16-instructions.ll | 79 +-
llvm/test/CodeGen/NVPTX/f16x2-instructions.ll | 1143 ++++-----
.../test/CodeGen/NVPTX/f32x2-convert-i32x2.ll | 81 +-
llvm/test/CodeGen/NVPTX/f32x2-instructions.ll | 747 +++---
.../NVPTX/gvn-scalar-pre-reg-pressure.ll | 4 +-
llvm/test/CodeGen/NVPTX/i128-array.ll | 12 +-
llvm/test/CodeGen/NVPTX/i128-ld-st.ll | 8 +-
llvm/test/CodeGen/NVPTX/i128-param.ll | 4 +-
llvm/test/CodeGen/NVPTX/i128-retval.ll | 2 +-
llvm/test/CodeGen/NVPTX/i16x2-instructions.ll | 349 +--
llvm/test/CodeGen/NVPTX/i32x2-instructions.ll | 721 +++---
llvm/test/CodeGen/NVPTX/i8x2-instructions.ll | 24 +-
llvm/test/CodeGen/NVPTX/i8x4-instructions.ll | 2200 ++++++-----------
llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll | 3 +-
llvm/test/CodeGen/NVPTX/mulwide.ll | 110 +-
llvm/test/CodeGen/NVPTX/param-load-store.ll | 47 +-
.../CodeGen/NVPTX/reduction-intrinsics.ll | 1678 ++++++-------
llvm/test/CodeGen/NVPTX/vaargs.ll | 70 +-
llvm/test/CodeGen/PowerPC/ppcsoftops.ll | 5 +-
.../CodeGen/RISCV/rvv/vsetvli-insert-O0.ll | 2 -
llvm/test/CodeGen/SPARC/fp16-promote.ll | 27 +-
llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll | 1 -
llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll | 2 -
llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll | 2 -
llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll | 1 -
llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll | 2 -
42 files changed, 4007 insertions(+), 5782 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/SelectionDAGISel.h b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
index 7659de75c4c125..75e5927057d1d8 100644
--- a/llvm/include/llvm/CodeGen/SelectionDAGISel.h
+++ b/llvm/include/llvm/CodeGen/SelectionDAGISel.h
@@ -548,8 +548,9 @@ class LLVM_ABI SelectionDAGISel {
void CodeGenAndEmitDAG();
/// Generate instructions for lowering the incoming arguments of the
- /// given function.
- void LowerArguments(const Function &F);
+ /// given function. \p FastISel is true if fast-isel may select other
+ /// instructions in the function.
+ void LowerArguments(const Function &F, bool FastISel);
void ComputeLiveOutVRegInfo();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index d9c14e0f185413..fb7718580b218d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -12170,7 +12170,7 @@ static void tryToElideArgumentCopy(
}
}
-void SelectionDAGISel::LowerArguments(const Function &F) {
+void SelectionDAGISel::LowerArguments(const Function &F, bool FastISel) {
SelectionDAG &DAG = SDB->DAG;
SDLoc dl = SDB->getCurSDLoc();
const DataLayout &DL = DAG.getDataLayout();
@@ -12506,7 +12506,7 @@ void SelectionDAGISel::LowerArguments(const Function &F) {
continue;
}
}
- if (!isOnlyUsedInEntryBlock(&Arg, TM.Options.EnableFastISel)) {
+ if (!isOnlyUsedInEntryBlock(&Arg, FastISel)) {
FuncInfo->InitializeRegForValue(&Arg);
SDB->CopyToExportRegsIfNeeded(&Arg);
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index ba7ecdc165b1da..84958ac50ab4fd 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -1674,7 +1674,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
CurDAG->setFunctionLoweringInfo(FuncInfo.get());
if (!FastIS) {
- LowerArguments(Fn);
+ LowerArguments(Fn, /*FastISel=*/false);
} else {
// See if fast isel can lower the arguments.
FastIS->startNewBlock();
@@ -1691,7 +1691,7 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
reportFastISelFailure(*MF, *ORE, R, EnableFastISelAbort > 1);
// Use SelectionDAG argument lowering
- LowerArguments(Fn);
+ LowerArguments(Fn, /*FastISel=*/true);
CurDAG->setRoot(SDB->getControlRoot());
SDB->clear();
CodeGenAndEmitDAG();
diff --git a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
index aabed8e2814c0d..2f99cce38db205 100644
--- a/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/extract_vector_dynelt.ll
@@ -3664,35 +3664,34 @@ define i32 @extract_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr4 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v4, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v4, s5, 1
+; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v5, s5, 1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB22_1: ; =>This Inner Loop Header: Depth=1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -3705,25 +3704,25 @@ define i32 @extract_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v4, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v4, s7, 3
+; GCN-O0-NEXT: v_writelane_b32 v5, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v5, s7, 3
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB22_1
; GCN-O0-NEXT: ; %bb.2:
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3745,13 +3744,12 @@ define i32 @extract_dyn_inreg_i32_3(<3 x i32> inreg %arg, i32 inreg %idx) {
; GCN-O0-LABEL: extract_dyn_inreg_i32_3:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: s_mov_b32 m0, s19
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3776,35 +3774,34 @@ define float @extract_dyn_float_3(<3 x float> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr4 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v4, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v4, s5, 1
+; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v5, s5, 1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB24_1: ; =>This Inner Loop Header: Depth=1
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -3817,25 +3814,25 @@ define float @extract_dyn_float_3(<3 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v4, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v4, s7, 3
+; GCN-O0-NEXT: v_writelane_b32 v5, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v5, s7, 3
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB24_1
; GCN-O0-NEXT: ; %bb.2:
; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v4, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v4, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v5, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v5, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3861,13 +3858,12 @@ define float @extract_dyn_inreg_float_3(<3 x float> inreg %arg, i32 inreg %idx)
; GCN-O0-LABEL: extract_dyn_inreg_float_3:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: s_mov_b32 m0, s19
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3898,41 +3894,40 @@ define i32 @extract_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s20
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v6
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v5
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr6 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v6, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v6, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: ; implicit-def: $vgpr9 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v9, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v9, s5, 1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB26_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v6, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v6, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v9, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v9, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -3947,25 +3942,25 @@ define i32 @extract_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v6, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v6, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: v_writelane_b32 v9, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v9, s7, 3
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB26_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v6, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v6, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v9, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v9, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -3991,17 +3986,16 @@ define i32 @extract_dyn_inreg_i32_5(<5 x i32> inreg %arg, i32 inreg %idx) {
; GCN-O0-LABEL: extract_dyn_inreg_i32_5:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s20
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v6
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v5
; GCN-O0-NEXT: s_mov_b32 m0, s21
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4032,41 +4026,40 @@ define float @extract_dyn_float_5(<5 x float> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s20
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v6
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v5
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr6 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v6, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v6, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: ; implicit-def: $vgpr9 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v9, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v9, s5, 1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB28_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v6, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v6, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v9, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v9, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -4081,25 +4074,25 @@ define float @extract_dyn_float_5(<5 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v6, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v6, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: v_writelane_b32 v9, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v9, s7, 3
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB28_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v6, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v6, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v9, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v9, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4133,17 +4126,16 @@ define float @extract_dyn_inreg_float_5(<5 x float> inreg %arg, i32 inreg %idx)
; GCN-O0-LABEL: extract_dyn_inreg_float_5:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s20
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v6
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v5
; GCN-O0-NEXT: s_mov_b32 m0, s21
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4177,22 +4169,21 @@ define i32 @extract_dyn_i32_6(<6 x i32> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0: ; %entry
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s21
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v6
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -4200,21 +4191,21 @@ define i32 @extract_dyn_i32_6(<6 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v7, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v7, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: ; implicit-def: $vgpr11 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v11, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v11, s5, 1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB30_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v7, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v7, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v11, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v11, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -4230,25 +4221,25 @@ define i32 @extract_dyn_i32_6(<6 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v7, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v7, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: v_writelane_b32 v11, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v11, s7, 3
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB30_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v7, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v7, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v11, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v11, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4277,19 +4268,18 @@ define i32 @extract_dyn_inreg_i32_6(<6 x i32> inreg %arg, i32 inreg %idx) {
; GCN-O0-LABEL: extract_dyn_inreg_i32_6:
; GCN-O0: ; %bb.0: ; %entry
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s21
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v6
; GCN-O0-NEXT: s_mov_b32 m0, s22
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4324,22 +4314,21 @@ define float @extract_dyn_float_6(<6 x float> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0: ; %entry
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s21
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v6
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -4347,21 +4336,21 @@ define float @extract_dyn_float_6(<6 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr7 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v7, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v7, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: ; implicit-def: $vgpr11 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v11, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v11, s5, 1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB32_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v7, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v7, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v11, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v11, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -4377,25 +4366,25 @@ define float @extract_dyn_float_6(<6 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v7, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v7, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: v_writelane_b32 v11, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v11, s7, 3
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB32_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
-; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v7, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v7, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v11, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v11, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4434,19 +4423,18 @@ define float @extract_dyn_inreg_float_6(<6 x float> inreg %arg, i32 inreg %idx)
; GCN-O0-LABEL: extract_dyn_inreg_float_6:
; GCN-O0: ; %bb.0: ; %entry
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s21
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v6
; GCN-O0-NEXT: s_mov_b32 m0, s22
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4484,24 +4472,23 @@ define i32 @extract_dyn_i32_7(<7 x i32> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s10
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v12, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s22
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v12
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v7
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -4510,21 +4497,21 @@ define i32 @extract_dyn_i32_7(<7 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr8 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v8, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v8, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: ; implicit-def: $vgpr13 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v13, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v13, s5, 1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB34_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v8, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v8, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v13, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v13, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -4541,25 +4528,25 @@ define i32 @extract_dyn_i32_7(<7 x i32> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v8, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v8, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: v_writelane_b32 v13, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v13, s7, 3
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB34_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v8, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v8, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v13, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v13, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4589,21 +4576,20 @@ define i32 @extract_dyn_inreg_i32_7(<7 x i32> inreg %arg, i32 inreg %idx) {
; GCN-O0-LABEL: extract_dyn_inreg_i32_7:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s10
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v12, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s22
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v12
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v7
; GCN-O0-NEXT: s_mov_b32 m0, s23
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4640,24 +4626,23 @@ define float @extract_dyn_float_7(<7 x float> inreg %arg, i32 %idx) {
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s10
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v12, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s22
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v12
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v7
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -4666,21 +4651,21 @@ define float @extract_dyn_float_7(<7 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
-; GCN-O0-NEXT: ; implicit-def: $vgpr8 : SGPR spill to VGPR lane
-; GCN-O0-NEXT: v_writelane_b32 v8, s4, 0
-; GCN-O0-NEXT: v_writelane_b32 v8, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: ; implicit-def: $vgpr13 : SGPR spill to VGPR lane
+; GCN-O0-NEXT: v_writelane_b32 v13, s4, 0
+; GCN-O0-NEXT: v_writelane_b32 v13, s5, 1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: ; implicit-def: $vgpr0
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB36_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v8, 2
-; GCN-O0-NEXT: v_readlane_b32 s5, v8, 3
+; GCN-O0-NEXT: v_readlane_b32 s4, v13, 2
+; GCN-O0-NEXT: v_readlane_b32 s5, v13, 3
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload
; GCN-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Reload
@@ -4697,25 +4682,25 @@ define float @extract_dyn_float_7(<7 x float> inreg %arg, i32 %idx) {
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
-; GCN-O0-NEXT: v_writelane_b32 v8, s6, 2
-; GCN-O0-NEXT: v_writelane_b32 v8, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: v_writelane_b32 v13, s6, 2
+; GCN-O0-NEXT: v_writelane_b32 v13, s7, 3
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB36_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
-; GCN-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
+; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
-; GCN-O0-NEXT: v_readlane_b32 s4, v8, 0
-; GCN-O0-NEXT: v_readlane_b32 s5, v8, 1
+; GCN-O0-NEXT: v_readlane_b32 s4, v13, 0
+; GCN-O0-NEXT: v_readlane_b32 s5, v13, 1
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: ; %bb.3:
; GCN-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1
-; GCN-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
@@ -4757,21 +4742,20 @@ define float @extract_dyn_inreg_float_7(<7 x float> inreg %arg, i32 inreg %idx)
; GCN-O0-LABEL: extract_dyn_inreg_float_7:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s10
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v12, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s22
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v12
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v7
; GCN-O0-NEXT: s_mov_b32 m0, s23
; GCN-O0-NEXT: v_movrels_b32_e32 v0, v0
; GCN-O0-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll b/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
index ea8477acbd629f..4e09da26e9f7cf 100644
--- a/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
+++ b/llvm/test/CodeGen/AMDGPU/i128-add-carry-chain.ll
@@ -18,7 +18,6 @@ define i128 @i128_add_uniform_carry_to_divergent(i128 %x) #0 {
; GFX9-NEXT: v_writelane_b32 v42, s34, 0
; GFX9-NEXT: v_writelane_b32 v42, s30, 1
; GFX9-NEXT: v_writelane_b32 v42, s31, 2
-; GFX9-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX9-NEXT: s_mov_b32 s34, 32
; GFX9-NEXT: v_lshlrev_b64 v[40:41], s34, v[0:1]
; GFX9-NEXT: s_getpc_b64 s[16:17]
@@ -68,7 +67,6 @@ define i128 @i128_add_uniform_carry_to_divergent(i128 %x) #0 {
; GFX12-NEXT: v_writelane_b32 v42, s34, 0
; GFX12-NEXT: v_writelane_b32 v42, s30, 1
; GFX12-NEXT: v_writelane_b32 v42, s31, 2
-; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
; GFX12-NEXT: s_mov_b32 s34, 32
; GFX12-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX12-NEXT: v_lshlrev_b64_e64 v[40:41], s34, v[0:1]
diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
index f690522f266c3a..77347ff9495684 100644
--- a/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
+++ b/llvm/test/CodeGen/AMDGPU/insert_vector_dynelt.ll
@@ -8827,13 +8827,12 @@ define <3 x i32> @insert_dyn_i32_3(<3 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
@@ -8926,13 +8925,12 @@ define <3 x i32> @insert_dyn_inreg_i32_3(<3 x i32> inreg %arg, i32 inreg %idx, i
; GCN-O0-LABEL: insert_dyn_inreg_i32_3:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s18
+; GCN-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v5
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v1
; GCN-O0-NEXT: s_mov_b32 m0, s19
; GCN-O0-NEXT: v_movreld_b32_e32 v2, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v2
@@ -8968,13 +8966,12 @@ define <3 x float> @insert_dyn_float_3(<3 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:16 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v3
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr5 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v5, s4, 0
@@ -9067,13 +9064,12 @@ define <3 x float> @insert_dyn_inreg_float_3(<3 x float> inreg %arg, i32 inreg %
; GCN-O0-LABEL: insert_dyn_inreg_float_3:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s6
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s18
+; GCN-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v5
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v1
; GCN-O0-NEXT: s_mov_b32 m0, s19
; GCN-O0-NEXT: v_movreld_b32_e32 v2, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v2
@@ -9115,24 +9111,23 @@ define <5 x i32> @insert_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s20
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v6
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v5
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr9 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v9, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v9, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -9140,9 +9135,9 @@ define <5 x i32> @insert_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB28_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v9, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v9, 3
@@ -9172,15 +9167,15 @@ define <5 x i32> @insert_dyn_i32_5(<5 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v9, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v9, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB28_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v9, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v9, 1
@@ -9240,17 +9235,16 @@ define <5 x i32> @insert_dyn_inreg_i32_5(<5 x i32> inreg %arg, i32 inreg %idx, i
; GCN-O0-LABEL: insert_dyn_inreg_i32_5:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v7, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v8, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s20
+; GCN-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v3
+; GCN-O0-NEXT: v_mov_b32_e32 v7, v2
+; GCN-O0-NEXT: v_mov_b32_e32 v8, v1
; GCN-O0-NEXT: s_mov_b32 m0, s21
; GCN-O0-NEXT: v_movreld_b32_e32 v4, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v4
@@ -9294,24 +9288,23 @@ define <5 x float> @insert_dyn_float_5(<5 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s20
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v6
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v5
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr9 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v9, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v9, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -9319,9 +9312,9 @@ define <5 x float> @insert_dyn_float_5(<5 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:20 ; 4-byte Folded Spill
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB30_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v9, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v9, 3
@@ -9351,15 +9344,15 @@ define <5 x float> @insert_dyn_float_5(<5 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v9, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v9, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB30_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v9, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v9, 1
@@ -9419,17 +9412,16 @@ define <5 x float> @insert_dyn_inreg_float_5(<5 x float> inreg %arg, i32 inreg %
; GCN-O0-LABEL: insert_dyn_inreg_float_5:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v7, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v8, s8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s20
+; GCN-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5_vgpr6_vgpr7_vgpr8 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v3
+; GCN-O0-NEXT: v_mov_b32_e32 v7, v2
+; GCN-O0-NEXT: v_mov_b32_e32 v8, v1
; GCN-O0-NEXT: s_mov_b32 m0, s21
; GCN-O0-NEXT: v_movreld_b32_e32 v4, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v4
@@ -9476,26 +9468,25 @@ define <6 x i32> @insert_dyn_i32_6(<6 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s21
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v6
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr11 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v11, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v11, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -9504,9 +9495,9 @@ define <6 x i32> @insert_dyn_i32_6(<6 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB32_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v11, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v11, 3
@@ -9539,15 +9530,15 @@ define <6 x i32> @insert_dyn_i32_6(<6 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v11, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v11, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB32_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v11, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v11, 1
@@ -9614,19 +9605,18 @@ define <6 x i32> @insert_dyn_inreg_i32_6(<6 x i32> inreg %arg, i32 inreg %idx, i
; GCN-O0-LABEL: insert_dyn_inreg_i32_6:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v10, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v9, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v8, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v7, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s4
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s21
+; GCN-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v7, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v8, v3
+; GCN-O0-NEXT: v_mov_b32_e32 v9, v2
+; GCN-O0-NEXT: v_mov_b32_e32 v10, v1
; GCN-O0-NEXT: s_mov_b32 m0, s22
; GCN-O0-NEXT: v_movreld_b32_e32 v5, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v5
@@ -9674,26 +9664,25 @@ define <6 x float> @insert_dyn_float_6(<6 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s21
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v7
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v6
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr11 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v11, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v11, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -9702,9 +9691,9 @@ define <6 x float> @insert_dyn_float_6(<6 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB34_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v11, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v11, 3
@@ -9737,15 +9726,15 @@ define <6 x float> @insert_dyn_float_6(<6 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v11, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v11, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB34_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[12:13], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[12:13]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v11, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v11, 1
@@ -9812,19 +9801,18 @@ define <6 x float> @insert_dyn_inreg_float_6(<6 x float> inreg %arg, i32 inreg %
; GCN-O0-LABEL: insert_dyn_inreg_float_6:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: v_mov_b32_e32 v10, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v9, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v8, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v7, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s4
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s21
+; GCN-O0-NEXT: ; kill: def $vgpr5 killed $vgpr5 def $vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v7, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v8, v3
+; GCN-O0-NEXT: v_mov_b32_e32 v9, v2
+; GCN-O0-NEXT: v_mov_b32_e32 v10, v1
; GCN-O0-NEXT: s_mov_b32 m0, s22
; GCN-O0-NEXT: v_movreld_b32_e32 v5, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v5
@@ -9875,28 +9863,27 @@ define <7 x i32> @insert_dyn_i32_7(<7 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s10
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v12, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s22
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v12
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v7
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr13 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v13, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v13, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -9906,9 +9893,9 @@ define <7 x i32> @insert_dyn_i32_7(<7 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB36_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v13, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v13, 3
@@ -9944,15 +9931,15 @@ define <7 x i32> @insert_dyn_i32_7(<7 x i32> inreg %arg, i32 %idx, i32 %val) {
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v13, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v13, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB36_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v13, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v13, 1
@@ -10026,21 +10013,20 @@ define <7 x i32> @insert_dyn_inreg_i32_7(<7 x i32> inreg %arg, i32 inreg %idx, i
; GCN-O0-LABEL: insert_dyn_inreg_i32_7:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v12, s10
-; GCN-O0-NEXT: v_mov_b32_e32 v11, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v10, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v9, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v8, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v7, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s4
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v13, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s22
+; GCN-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v7, v13
+; GCN-O0-NEXT: v_mov_b32_e32 v8, v5
+; GCN-O0-NEXT: v_mov_b32_e32 v9, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v10, v3
+; GCN-O0-NEXT: v_mov_b32_e32 v11, v2
+; GCN-O0-NEXT: v_mov_b32_e32 v12, v1
; GCN-O0-NEXT: s_mov_b32 m0, s23
; GCN-O0-NEXT: v_movreld_b32_e32 v6, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v6
@@ -10092,28 +10078,27 @@ define <7 x float> @insert_dyn_float_7(<7 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: s_mov_b64 exec, s[4:5]
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v0, s4
-; GCN-O0-NEXT: v_mov_b32_e32 v1, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v2, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v3, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v4, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v5, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s10
+; GCN-O0-NEXT: v_mov_b32_e32 v0, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v12, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v11, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v10, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v9, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v8, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v7, s22
+; GCN-O0-NEXT: ; kill: def $vgpr0 killed $vgpr0 def $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v1, v12
+; GCN-O0-NEXT: v_mov_b32_e32 v2, v11
+; GCN-O0-NEXT: v_mov_b32_e32 v3, v10
+; GCN-O0-NEXT: v_mov_b32_e32 v4, v9
+; GCN-O0-NEXT: v_mov_b32_e32 v5, v8
+; GCN-O0-NEXT: v_mov_b32_e32 v6, v7
; GCN-O0-NEXT: s_mov_b64 s[4:5], exec
; GCN-O0-NEXT: ; implicit-def: $vgpr13 : SGPR spill to VGPR lane
; GCN-O0-NEXT: v_writelane_b32 v13, s4, 0
; GCN-O0-NEXT: v_writelane_b32 v13, s5, 1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GCN-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
@@ -10123,9 +10108,9 @@ define <7 x float> @insert_dyn_float_7(<7 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
; GCN-O0-NEXT: ; implicit-def: $sgpr4_sgpr5
; GCN-O0-NEXT: .LBB38_1: ; =>This Inner Loop Header: Depth=1
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v13, 2
; GCN-O0-NEXT: v_readlane_b32 s5, v13, 3
@@ -10161,15 +10146,15 @@ define <7 x float> @insert_dyn_float_7(<7 x float> inreg %arg, i32 %idx, float %
; GCN-O0-NEXT: s_mov_b64 s[6:7], s[4:5]
; GCN-O0-NEXT: v_writelane_b32 v13, s6, 2
; GCN-O0-NEXT: v_writelane_b32 v13, s7, 3
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 ; 4-byte Folded Spill
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_xor_b64 exec, exec, s[4:5]
; GCN-O0-NEXT: s_cbranch_execnz .LBB38_1
; GCN-O0-NEXT: ; %bb.2:
-; GCN-O0-NEXT: s_or_saveexec_b64 s[14:15], -1
+; GCN-O0-NEXT: s_or_saveexec_b64 s[10:11], -1
; GCN-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 ; 4-byte Folded Reload
-; GCN-O0-NEXT: s_mov_b64 exec, s[14:15]
+; GCN-O0-NEXT: s_mov_b64 exec, s[10:11]
; GCN-O0-NEXT: s_waitcnt vmcnt(0)
; GCN-O0-NEXT: v_readlane_b32 s4, v13, 0
; GCN-O0-NEXT: v_readlane_b32 s5, v13, 1
@@ -10243,21 +10228,20 @@ define <7 x float> @insert_dyn_inreg_float_7(<7 x float> inreg %arg, i32 inreg %
; GCN-O0-LABEL: insert_dyn_inreg_float_7:
; GCN-O0: ; %bb.0:
; GCN-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GCN-O0-NEXT: s_mov_b32 s4, s16
-; GCN-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10
-; GCN-O0-NEXT: s_mov_b32 s5, s17
-; GCN-O0-NEXT: s_mov_b32 s6, s18
-; GCN-O0-NEXT: s_mov_b32 s7, s19
-; GCN-O0-NEXT: s_mov_b32 s8, s20
-; GCN-O0-NEXT: s_mov_b32 s9, s21
-; GCN-O0-NEXT: s_mov_b32 s10, s22
-; GCN-O0-NEXT: v_mov_b32_e32 v12, s10
-; GCN-O0-NEXT: v_mov_b32_e32 v11, s9
-; GCN-O0-NEXT: v_mov_b32_e32 v10, s8
-; GCN-O0-NEXT: v_mov_b32_e32 v9, s7
-; GCN-O0-NEXT: v_mov_b32_e32 v8, s6
-; GCN-O0-NEXT: v_mov_b32_e32 v7, s5
-; GCN-O0-NEXT: v_mov_b32_e32 v6, s4
+; GCN-O0-NEXT: v_mov_b32_e32 v6, s16
+; GCN-O0-NEXT: v_mov_b32_e32 v13, s17
+; GCN-O0-NEXT: v_mov_b32_e32 v5, s18
+; GCN-O0-NEXT: v_mov_b32_e32 v4, s19
+; GCN-O0-NEXT: v_mov_b32_e32 v3, s20
+; GCN-O0-NEXT: v_mov_b32_e32 v2, s21
+; GCN-O0-NEXT: v_mov_b32_e32 v1, s22
+; GCN-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12 killed $exec
+; GCN-O0-NEXT: v_mov_b32_e32 v7, v13
+; GCN-O0-NEXT: v_mov_b32_e32 v8, v5
+; GCN-O0-NEXT: v_mov_b32_e32 v9, v4
+; GCN-O0-NEXT: v_mov_b32_e32 v10, v3
+; GCN-O0-NEXT: v_mov_b32_e32 v11, v2
+; GCN-O0-NEXT: v_mov_b32_e32 v12, v1
; GCN-O0-NEXT: s_mov_b32 m0, s23
; GCN-O0-NEXT: v_movreld_b32_e32 v6, v0
; GCN-O0-NEXT: v_mov_b32_e32 v0, v6
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
index 1cf8ef7a918f48..c9f40c3ad9192d 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-buffer-atomics.ll
@@ -7,19 +7,19 @@ define void @buffer_fat_ptr_agent_atomic_add_noret_i32(ptr addrspace(7) inreg %p
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s6, s2
-; GFX1250-NEXT: s_mov_b32 s4, s0
+; GFX1250-NEXT: s_mov_b32 s2, s1
; GFX1250-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX1250-NEXT: s_mov_b32 s7, s3
-; GFX1250-NEXT: s_mov_b32 s8, s7
-; GFX1250-NEXT: s_mov_b32 s9, s6
-; GFX1250-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX1250-NEXT: s_mov_b32 s5, s1
-; GFX1250-NEXT: s_mov_b32 s10, s5
-; GFX1250-NEXT: s_mov_b32 s0, s4
+; GFX1250-NEXT: s_mov_b32 s4, s7
+; GFX1250-NEXT: s_mov_b32 s5, s6
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX1250-NEXT: s_mov_b32 s1, s2
+; GFX1250-NEXT: s_mov_b32 s6, s1
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX1250-NEXT: s_mov_b32 s1, s10
-; GFX1250-NEXT: s_mov_b32 s2, s9
-; GFX1250-NEXT: s_mov_b32 s3, s8
+; GFX1250-NEXT: s_mov_b32 s1, s6
+; GFX1250-NEXT: s_mov_b32 s2, s5
+; GFX1250-NEXT: s_mov_b32 s3, s4
; GFX1250-NEXT: v_mov_b32_e32 v1, s16
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: buffer_atomic_add_u32 v0, v1, s[0:3], null offen
@@ -34,19 +34,19 @@ define i32 @buffer_fat_ptr_agent_atomic_add_ret_i32(ptr addrspace(7) inreg %ptr,
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s6, s2
-; GFX1250-NEXT: s_mov_b32 s4, s0
+; GFX1250-NEXT: s_mov_b32 s2, s1
; GFX1250-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX1250-NEXT: s_mov_b32 s7, s3
-; GFX1250-NEXT: s_mov_b32 s8, s7
-; GFX1250-NEXT: s_mov_b32 s9, s6
-; GFX1250-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX1250-NEXT: s_mov_b32 s5, s1
-; GFX1250-NEXT: s_mov_b32 s10, s5
-; GFX1250-NEXT: s_mov_b32 s0, s4
+; GFX1250-NEXT: s_mov_b32 s4, s7
+; GFX1250-NEXT: s_mov_b32 s5, s6
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX1250-NEXT: s_mov_b32 s1, s2
+; GFX1250-NEXT: s_mov_b32 s6, s1
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX1250-NEXT: s_mov_b32 s1, s10
-; GFX1250-NEXT: s_mov_b32 s2, s9
-; GFX1250-NEXT: s_mov_b32 s3, s8
+; GFX1250-NEXT: s_mov_b32 s1, s6
+; GFX1250-NEXT: s_mov_b32 s2, s5
+; GFX1250-NEXT: s_mov_b32 s3, s4
; GFX1250-NEXT: v_mov_b32_e32 v1, s16
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: buffer_atomic_add_u32 v0, v1, s[0:3], null offen th:TH_ATOMIC_RETURN
@@ -313,19 +313,19 @@ define void @buffer_fat_ptr_store_i32(ptr addrspace(7) inreg %ptr, i32 %val) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s6, s2
-; GFX1250-NEXT: s_mov_b32 s4, s0
+; GFX1250-NEXT: s_mov_b32 s2, s1
; GFX1250-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX1250-NEXT: s_mov_b32 s7, s3
-; GFX1250-NEXT: s_mov_b32 s8, s7
-; GFX1250-NEXT: s_mov_b32 s9, s6
-; GFX1250-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX1250-NEXT: s_mov_b32 s5, s1
-; GFX1250-NEXT: s_mov_b32 s10, s5
-; GFX1250-NEXT: s_mov_b32 s0, s4
+; GFX1250-NEXT: s_mov_b32 s4, s7
+; GFX1250-NEXT: s_mov_b32 s5, s6
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX1250-NEXT: s_mov_b32 s1, s2
+; GFX1250-NEXT: s_mov_b32 s6, s1
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX1250-NEXT: s_mov_b32 s1, s10
-; GFX1250-NEXT: s_mov_b32 s2, s9
-; GFX1250-NEXT: s_mov_b32 s3, s8
+; GFX1250-NEXT: s_mov_b32 s1, s6
+; GFX1250-NEXT: s_mov_b32 s2, s5
+; GFX1250-NEXT: s_mov_b32 s3, s4
; GFX1250-NEXT: v_mov_b32_e32 v1, s16
; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen
; GFX1250-NEXT: s_set_pc_i64 s[30:31]
@@ -339,19 +339,19 @@ define void @buffer_fat_ptr_store_i32_volatile(ptr addrspace(7) inreg %ptr, i32
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s6, s2
-; GFX1250-NEXT: s_mov_b32 s4, s0
+; GFX1250-NEXT: s_mov_b32 s2, s1
; GFX1250-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX1250-NEXT: s_mov_b32 s7, s3
-; GFX1250-NEXT: s_mov_b32 s8, s7
-; GFX1250-NEXT: s_mov_b32 s9, s6
-; GFX1250-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX1250-NEXT: s_mov_b32 s5, s1
-; GFX1250-NEXT: s_mov_b32 s10, s5
-; GFX1250-NEXT: s_mov_b32 s0, s4
+; GFX1250-NEXT: s_mov_b32 s4, s7
+; GFX1250-NEXT: s_mov_b32 s5, s6
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX1250-NEXT: s_mov_b32 s1, s2
+; GFX1250-NEXT: s_mov_b32 s6, s1
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX1250-NEXT: s_mov_b32 s1, s10
-; GFX1250-NEXT: s_mov_b32 s2, s9
-; GFX1250-NEXT: s_mov_b32 s3, s8
+; GFX1250-NEXT: s_mov_b32 s1, s6
+; GFX1250-NEXT: s_mov_b32 s2, s5
+; GFX1250-NEXT: s_mov_b32 s3, s4
; GFX1250-NEXT: v_mov_b32_e32 v1, s16
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: buffer_store_b32 v0, v1, s[0:3], null offen scope:SCOPE_SYS
@@ -367,19 +367,19 @@ define i32 @buffer_fat_ptr_load_i32(ptr addrspace(7) inreg %ptr) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s6, s2
-; GFX1250-NEXT: s_mov_b32 s4, s0
+; GFX1250-NEXT: s_mov_b32 s2, s1
; GFX1250-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX1250-NEXT: s_mov_b32 s7, s3
-; GFX1250-NEXT: s_mov_b32 s8, s7
-; GFX1250-NEXT: s_mov_b32 s9, s6
-; GFX1250-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX1250-NEXT: s_mov_b32 s5, s1
-; GFX1250-NEXT: s_mov_b32 s10, s5
-; GFX1250-NEXT: s_mov_b32 s0, s4
+; GFX1250-NEXT: s_mov_b32 s4, s7
+; GFX1250-NEXT: s_mov_b32 s5, s6
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX1250-NEXT: s_mov_b32 s1, s2
+; GFX1250-NEXT: s_mov_b32 s6, s1
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX1250-NEXT: s_mov_b32 s1, s10
-; GFX1250-NEXT: s_mov_b32 s2, s9
-; GFX1250-NEXT: s_mov_b32 s3, s8
+; GFX1250-NEXT: s_mov_b32 s1, s6
+; GFX1250-NEXT: s_mov_b32 s2, s5
+; GFX1250-NEXT: s_mov_b32 s3, s4
; GFX1250-NEXT: v_mov_b32_e32 v0, s16
; GFX1250-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen
; GFX1250-NEXT: s_wait_loadcnt 0x0
@@ -394,19 +394,19 @@ define i32 @buffer_fat_ptr_load_i32_volatile(ptr addrspace(7) inreg %ptr) {
; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0
; GFX1250-NEXT: s_wait_kmcnt 0x0
; GFX1250-NEXT: s_mov_b32 s6, s2
-; GFX1250-NEXT: s_mov_b32 s4, s0
+; GFX1250-NEXT: s_mov_b32 s2, s1
; GFX1250-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX1250-NEXT: s_mov_b32 s7, s3
-; GFX1250-NEXT: s_mov_b32 s8, s7
-; GFX1250-NEXT: s_mov_b32 s9, s6
-; GFX1250-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX1250-NEXT: s_mov_b32 s5, s1
-; GFX1250-NEXT: s_mov_b32 s10, s5
-; GFX1250-NEXT: s_mov_b32 s0, s4
+; GFX1250-NEXT: s_mov_b32 s4, s7
+; GFX1250-NEXT: s_mov_b32 s5, s6
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX1250-NEXT: s_mov_b32 s1, s2
+; GFX1250-NEXT: s_mov_b32 s6, s1
+; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX1250-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX1250-NEXT: s_mov_b32 s1, s10
-; GFX1250-NEXT: s_mov_b32 s2, s9
-; GFX1250-NEXT: s_mov_b32 s3, s8
+; GFX1250-NEXT: s_mov_b32 s1, s6
+; GFX1250-NEXT: s_mov_b32 s2, s5
+; GFX1250-NEXT: s_mov_b32 s3, s4
; GFX1250-NEXT: v_mov_b32_e32 v0, s16
; GFX1250-NEXT: s_wait_xcnt 0x0
; GFX1250-NEXT: buffer_load_b32 v0, v0, s[0:3], null offen scope:SCOPE_SYS
diff --git a/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll b/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
index e12ae82214287f..b4a78d92c663fc 100644
--- a/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
+++ b/llvm/test/CodeGen/AMDGPU/memory-legalizer-single-wave-workgroup-lds-dma.ll
@@ -124,20 +124,20 @@ define void @lds_dma_wg_fence_release_single32(ptr addrspace(8) inreg %rsrc, ptr
; GFX9-LABEL: lds_dma_wg_fence_release_single32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-NEXT: s_mov_b32 s10, s18
-; GFX9-NEXT: s_mov_b32 s8, s16
-; GFX9-NEXT: ; kill: def $sgpr10 killed $sgpr10 def $sgpr10_sgpr11
-; GFX9-NEXT: s_mov_b32 s11, s19
-; GFX9-NEXT: s_mov_b32 s12, s11
-; GFX9-NEXT: s_mov_b32 s13, s10
-; GFX9-NEXT: ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9
-; GFX9-NEXT: s_mov_b32 s9, s17
-; GFX9-NEXT: s_mov_b32 s14, s9
-; GFX9-NEXT: s_mov_b32 s4, s8
+; GFX9-NEXT: s_mov_b32 s6, s18
+; GFX9-NEXT: s_mov_b32 s4, s16
+; GFX9-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
+; GFX9-NEXT: s_mov_b32 s7, s19
+; GFX9-NEXT: s_mov_b32 s8, s7
+; GFX9-NEXT: s_mov_b32 s9, s6
+; GFX9-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
+; GFX9-NEXT: s_mov_b32 s5, s17
+; GFX9-NEXT: s_mov_b32 s10, s5
+; GFX9-NEXT: ; kill: def $sgpr4 killed $sgpr4 killed $sgpr4_sgpr5
; GFX9-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7
-; GFX9-NEXT: s_mov_b32 s5, s14
-; GFX9-NEXT: s_mov_b32 s6, s13
-; GFX9-NEXT: s_mov_b32 s7, s12
+; GFX9-NEXT: s_mov_b32 s5, s10
+; GFX9-NEXT: s_mov_b32 s6, s9
+; GFX9-NEXT: s_mov_b32 s7, s8
; GFX9-NEXT: s_mov_b32 s8, 0
; GFX9-NEXT: s_mov_b32 m0, s20
; GFX9-NEXT: s_nop 0
@@ -155,19 +155,19 @@ define void @lds_dma_wg_fence_release_single32(ptr addrspace(8) inreg %rsrc, ptr
; GFX942: ; %bb.0:
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX942-NEXT: s_mov_b32 s6, s2
-; GFX942-NEXT: s_mov_b32 s4, s0
+; GFX942-NEXT: s_mov_b32 s2, s1
; GFX942-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX942-NEXT: s_mov_b32 s7, s3
-; GFX942-NEXT: s_mov_b32 s8, s7
-; GFX942-NEXT: s_mov_b32 s9, s6
-; GFX942-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX942-NEXT: s_mov_b32 s5, s1
-; GFX942-NEXT: s_mov_b32 s10, s5
-; GFX942-NEXT: s_mov_b32 s0, s4
+; GFX942-NEXT: s_mov_b32 s4, s7
+; GFX942-NEXT: s_mov_b32 s5, s6
+; GFX942-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX942-NEXT: s_mov_b32 s1, s2
+; GFX942-NEXT: s_mov_b32 s6, s1
+; GFX942-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX942-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX942-NEXT: s_mov_b32 s1, s10
-; GFX942-NEXT: s_mov_b32 s2, s9
-; GFX942-NEXT: s_mov_b32 s3, s8
+; GFX942-NEXT: s_mov_b32 s1, s6
+; GFX942-NEXT: s_mov_b32 s2, s5
+; GFX942-NEXT: s_mov_b32 s3, s4
; GFX942-NEXT: s_mov_b32 s4, 0
; GFX942-NEXT: s_mov_b32 m0, s16
; GFX942-NEXT: s_nop 0
@@ -184,20 +184,20 @@ define void @lds_dma_wg_fence_release_single32(ptr addrspace(8) inreg %rsrc, ptr
; GFX10-LABEL: lds_dma_wg_fence_release_single32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX10-NEXT: s_mov_b32 s10, s18
-; GFX10-NEXT: s_mov_b32 s8, s16
-; GFX10-NEXT: ; kill: def $sgpr10 killed $sgpr10 def $sgpr10_sgpr11
-; GFX10-NEXT: s_mov_b32 s11, s19
-; GFX10-NEXT: s_mov_b32 s12, s11
-; GFX10-NEXT: s_mov_b32 s13, s10
-; GFX10-NEXT: ; kill: def $sgpr8 killed $sgpr8 def $sgpr8_sgpr9
-; GFX10-NEXT: s_mov_b32 s9, s17
-; GFX10-NEXT: s_mov_b32 s14, s9
-; GFX10-NEXT: s_mov_b32 s4, s8
+; GFX10-NEXT: s_mov_b32 s6, s18
+; GFX10-NEXT: s_mov_b32 s4, s16
+; GFX10-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
+; GFX10-NEXT: s_mov_b32 s7, s19
+; GFX10-NEXT: s_mov_b32 s8, s7
+; GFX10-NEXT: s_mov_b32 s9, s6
+; GFX10-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
+; GFX10-NEXT: s_mov_b32 s5, s17
+; GFX10-NEXT: s_mov_b32 s10, s5
+; GFX10-NEXT: ; kill: def $sgpr4 killed $sgpr4 killed $sgpr4_sgpr5
; GFX10-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5_sgpr6_sgpr7
-; GFX10-NEXT: s_mov_b32 s5, s14
-; GFX10-NEXT: s_mov_b32 s6, s13
-; GFX10-NEXT: s_mov_b32 s7, s12
+; GFX10-NEXT: s_mov_b32 s5, s10
+; GFX10-NEXT: s_mov_b32 s6, s9
+; GFX10-NEXT: s_mov_b32 s7, s8
; GFX10-NEXT: s_mov_b32 s8, 0
; GFX10-NEXT: s_mov_b32 m0, s20
; GFX10-NEXT: buffer_load_dword off, s[4:7], s8 lds
diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
index 7fb97edf097d8f..d7ef3ba6cc7a44 100644
--- a/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved-spill.ll
@@ -11,20 +11,20 @@ define amdgpu_gfx void @strict_wwm_no_cfg(ptr addrspace(8) inreg %tmp14) #1 {
; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:4 ; 4-byte Folded Spill
; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:8 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 exec, s[34:35]
-; GFX9-O0-NEXT: s_mov_b32 s40, s6
-; GFX9-O0-NEXT: s_mov_b32 s34, s4
-; GFX9-O0-NEXT: ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41
-; GFX9-O0-NEXT: s_mov_b32 s41, s7
-; GFX9-O0-NEXT: s_mov_b32 s42, s41
-; GFX9-O0-NEXT: s_mov_b32 s43, s40
-; GFX9-O0-NEXT: ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35
-; GFX9-O0-NEXT: s_mov_b32 s35, s5
-; GFX9-O0-NEXT: s_mov_b32 s44, s35
-; GFX9-O0-NEXT: s_mov_b32 s36, s34
+; GFX9-O0-NEXT: s_mov_b32 s38, s6
+; GFX9-O0-NEXT: s_mov_b32 s36, s4
+; GFX9-O0-NEXT: ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39
+; GFX9-O0-NEXT: s_mov_b32 s39, s7
+; GFX9-O0-NEXT: s_mov_b32 s34, s39
+; GFX9-O0-NEXT: s_mov_b32 s35, s38
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37
+; GFX9-O0-NEXT: s_mov_b32 s37, s5
+; GFX9-O0-NEXT: s_mov_b32 s40, s37
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 killed $sgpr36_sgpr37
; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37_sgpr38_sgpr39
-; GFX9-O0-NEXT: s_mov_b32 s37, s44
-; GFX9-O0-NEXT: s_mov_b32 s38, s43
-; GFX9-O0-NEXT: s_mov_b32 s39, s42
+; GFX9-O0-NEXT: s_mov_b32 s37, s40
+; GFX9-O0-NEXT: s_mov_b32 s38, s35
+; GFX9-O0-NEXT: s_mov_b32 s39, s34
; GFX9-O0-NEXT: s_mov_b32 s34, 0
; GFX9-O0-NEXT: buffer_load_dwordx2 v[5:6], off, s[36:39], s34
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
@@ -353,20 +353,20 @@ define amdgpu_gfx void @strict_wwm_call(ptr addrspace(8) inreg %tmp14, i32 inreg
; GFX9-O0-NEXT: s_add_i32 s32, s32, 0x400
; GFX9-O0-NEXT: v_writelane_b32 v3, s30, 0
; GFX9-O0-NEXT: v_writelane_b32 v3, s31, 1
-; GFX9-O0-NEXT: s_mov_b32 s40, s6
-; GFX9-O0-NEXT: s_mov_b32 s34, s4
-; GFX9-O0-NEXT: ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41
-; GFX9-O0-NEXT: s_mov_b32 s41, s7
-; GFX9-O0-NEXT: s_mov_b32 s42, s41
-; GFX9-O0-NEXT: s_mov_b32 s43, s40
-; GFX9-O0-NEXT: ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35
-; GFX9-O0-NEXT: s_mov_b32 s35, s5
-; GFX9-O0-NEXT: s_mov_b32 s44, s35
-; GFX9-O0-NEXT: s_mov_b32 s36, s34
+; GFX9-O0-NEXT: s_mov_b32 s38, s6
+; GFX9-O0-NEXT: s_mov_b32 s36, s4
+; GFX9-O0-NEXT: ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39
+; GFX9-O0-NEXT: s_mov_b32 s39, s7
+; GFX9-O0-NEXT: s_mov_b32 s34, s39
+; GFX9-O0-NEXT: s_mov_b32 s35, s38
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37
+; GFX9-O0-NEXT: s_mov_b32 s37, s5
+; GFX9-O0-NEXT: s_mov_b32 s40, s37
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 killed $sgpr36_sgpr37
; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37_sgpr38_sgpr39
-; GFX9-O0-NEXT: s_mov_b32 s37, s44
-; GFX9-O0-NEXT: s_mov_b32 s38, s43
-; GFX9-O0-NEXT: s_mov_b32 s39, s42
+; GFX9-O0-NEXT: s_mov_b32 s37, s40
+; GFX9-O0-NEXT: s_mov_b32 s38, s35
+; GFX9-O0-NEXT: s_mov_b32 s39, s34
; GFX9-O0-NEXT: s_mov_b32 s34, 0
; GFX9-O0-NEXT: ; implicit-def: $sgpr40_sgpr41
; GFX9-O0-NEXT: v_mov_b32_e32 v0, s8
@@ -525,7 +525,7 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i
; GFX9-O0-LABEL: strict_wwm_call_i64:
; GFX9-O0: ; %bb.0:
; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX9-O0-NEXT: s_mov_b32 s46, s33
+; GFX9-O0-NEXT: s_mov_b32 s44, s33
; GFX9-O0-NEXT: s_mov_b32 s33, s32
; GFX9-O0-NEXT: s_xor_saveexec_b64 s[34:35], -1
; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s33 ; 4-byte Folded Spill
@@ -553,20 +553,20 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i
; GFX9-O0-NEXT: ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39
; GFX9-O0-NEXT: s_mov_b32 s39, s7
; GFX9-O0-NEXT: s_mov_b32 s35, s39
-; GFX9-O0-NEXT: s_mov_b32 s44, s38
+; GFX9-O0-NEXT: s_mov_b32 s40, s38
; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37
; GFX9-O0-NEXT: s_mov_b32 s37, s5
-; GFX9-O0-NEXT: s_mov_b32 s45, s37
-; GFX9-O0-NEXT: s_mov_b32 s40, s36
-; GFX9-O0-NEXT: ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41_sgpr42_sgpr43
-; GFX9-O0-NEXT: s_mov_b32 s41, s45
-; GFX9-O0-NEXT: s_mov_b32 s42, s44
-; GFX9-O0-NEXT: s_mov_b32 s43, s35
+; GFX9-O0-NEXT: s_mov_b32 s41, s37
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 killed $sgpr36_sgpr37
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37_sgpr38_sgpr39
+; GFX9-O0-NEXT: s_mov_b32 s37, s41
+; GFX9-O0-NEXT: s_mov_b32 s38, s40
+; GFX9-O0-NEXT: s_mov_b32 s39, s35
; GFX9-O0-NEXT: ; implicit-def: $vgpr11 : SGPR spill to VGPR lane
-; GFX9-O0-NEXT: v_writelane_b32 v11, s40, 0
-; GFX9-O0-NEXT: v_writelane_b32 v11, s41, 1
-; GFX9-O0-NEXT: v_writelane_b32 v11, s42, 2
-; GFX9-O0-NEXT: v_writelane_b32 v11, s43, 3
+; GFX9-O0-NEXT: v_writelane_b32 v11, s36, 0
+; GFX9-O0-NEXT: v_writelane_b32 v11, s37, 1
+; GFX9-O0-NEXT: v_writelane_b32 v11, s38, 2
+; GFX9-O0-NEXT: v_writelane_b32 v11, s39, 3
; GFX9-O0-NEXT: ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35
; GFX9-O0-NEXT: s_mov_b32 s35, s9
; GFX9-O0-NEXT: s_mov_b32 s38, s35
@@ -638,7 +638,7 @@ define amdgpu_gfx void @strict_wwm_call_i64(ptr addrspace(8) inreg %tmp14, i64 i
; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s33 offset:40 ; 4-byte Folded Reload
; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s33 offset:44 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_mov_b64 exec, s[34:35]
-; GFX9-O0-NEXT: s_mov_b32 s33, s46
+; GFX9-O0-NEXT: s_mov_b32 s33, s44
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-O0-NEXT: s_setpc_b64 s[30:31]
;
@@ -718,20 +718,20 @@ define amdgpu_gfx void @strict_wwm_amdgpu_cs_main(ptr addrspace(8) inreg %desc,
; GFX9-O0-NEXT: s_nop 0
; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:12 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 exec, s[34:35]
-; GFX9-O0-NEXT: s_mov_b32 s40, s6
-; GFX9-O0-NEXT: s_mov_b32 s34, s4
-; GFX9-O0-NEXT: ; kill: def $sgpr40 killed $sgpr40 def $sgpr40_sgpr41
-; GFX9-O0-NEXT: s_mov_b32 s41, s7
-; GFX9-O0-NEXT: s_mov_b32 s42, s41
-; GFX9-O0-NEXT: s_mov_b32 s43, s40
-; GFX9-O0-NEXT: ; kill: def $sgpr34 killed $sgpr34 def $sgpr34_sgpr35
-; GFX9-O0-NEXT: s_mov_b32 s35, s5
-; GFX9-O0-NEXT: s_mov_b32 s44, s35
-; GFX9-O0-NEXT: s_mov_b32 s36, s34
+; GFX9-O0-NEXT: s_mov_b32 s38, s6
+; GFX9-O0-NEXT: s_mov_b32 s36, s4
+; GFX9-O0-NEXT: ; kill: def $sgpr38 killed $sgpr38 def $sgpr38_sgpr39
+; GFX9-O0-NEXT: s_mov_b32 s39, s7
+; GFX9-O0-NEXT: s_mov_b32 s34, s39
+; GFX9-O0-NEXT: s_mov_b32 s35, s38
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37
+; GFX9-O0-NEXT: s_mov_b32 s37, s5
+; GFX9-O0-NEXT: s_mov_b32 s40, s37
+; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 killed $sgpr36_sgpr37
; GFX9-O0-NEXT: ; kill: def $sgpr36 killed $sgpr36 def $sgpr36_sgpr37_sgpr38_sgpr39
-; GFX9-O0-NEXT: s_mov_b32 s37, s44
-; GFX9-O0-NEXT: s_mov_b32 s38, s43
-; GFX9-O0-NEXT: s_mov_b32 s39, s42
+; GFX9-O0-NEXT: s_mov_b32 s37, s40
+; GFX9-O0-NEXT: s_mov_b32 s38, s35
+; GFX9-O0-NEXT: s_mov_b32 s39, s34
; GFX9-O0-NEXT: s_mov_b32 s34, 5
; GFX9-O0-NEXT: v_lshlrev_b32_e64 v0, s34, v0
; GFX9-O0-NEXT: s_mov_b32 s34, 0
@@ -894,86 +894,31 @@ define amdgpu_gfx <32 x i32> @strict_wwm_callee_saves(<32 x i32> inreg %keep, pt
; GFX9-O0: ; %bb.0:
; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-O0-NEXT: s_xor_saveexec_b64 s[34:35], -1
-; GFX9-O0-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: buffer_store_dword v32, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: buffer_store_dword v33, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_nop 0
-; GFX9-O0-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: buffer_store_dword v34, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
; GFX9-O0-NEXT: s_mov_b64 exec, s[34:35]
-; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:20
-; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:16
-; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_load_dword v35, off, s[0:3], s32 offset:12
-; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: buffer_store_dword v35, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_load_dword v36, off, s[0:3], s32 offset:8
-; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: buffer_store_dword v36, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_load_dword v37, off, s[0:3], s32 offset:4
-; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: buffer_store_dword v37, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: buffer_load_dword v38, off, s[0:3], s32
-; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
-; GFX9-O0-NEXT: buffer_store_dword v38, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill
-; GFX9-O0-NEXT: v_mov_b32_e32 v0, s4
-; GFX9-O0-NEXT: v_mov_b32_e32 v1, s5
-; GFX9-O0-NEXT: v_mov_b32_e32 v2, s6
-; GFX9-O0-NEXT: v_mov_b32_e32 v3, s7
-; GFX9-O0-NEXT: v_mov_b32_e32 v4, s8
-; GFX9-O0-NEXT: v_mov_b32_e32 v5, s9
-; GFX9-O0-NEXT: v_mov_b32_e32 v6, s10
-; GFX9-O0-NEXT: v_mov_b32_e32 v7, s11
-; GFX9-O0-NEXT: v_mov_b32_e32 v8, s12
-; GFX9-O0-NEXT: v_mov_b32_e32 v9, s13
-; GFX9-O0-NEXT: v_mov_b32_e32 v10, s14
-; GFX9-O0-NEXT: v_mov_b32_e32 v11, s15
-; GFX9-O0-NEXT: v_mov_b32_e32 v12, s16
-; GFX9-O0-NEXT: v_mov_b32_e32 v13, s17
-; GFX9-O0-NEXT: v_mov_b32_e32 v14, s18
-; GFX9-O0-NEXT: v_mov_b32_e32 v15, s19
-; GFX9-O0-NEXT: v_mov_b32_e32 v16, s20
-; GFX9-O0-NEXT: v_mov_b32_e32 v17, s21
-; GFX9-O0-NEXT: v_mov_b32_e32 v18, s22
-; GFX9-O0-NEXT: v_mov_b32_e32 v19, s23
-; GFX9-O0-NEXT: v_mov_b32_e32 v20, s24
-; GFX9-O0-NEXT: v_mov_b32_e32 v21, s25
-; GFX9-O0-NEXT: v_mov_b32_e32 v22, s26
-; GFX9-O0-NEXT: v_mov_b32_e32 v23, s27
-; GFX9-O0-NEXT: v_mov_b32_e32 v24, s28
-; GFX9-O0-NEXT: v_mov_b32_e32 v25, s29
-; GFX9-O0-NEXT: v_mov_b32_e32 v26, v38
-; GFX9-O0-NEXT: v_mov_b32_e32 v27, v37
-; GFX9-O0-NEXT: v_mov_b32_e32 v28, v36
-; GFX9-O0-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:28 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: v_mov_b32_e32 v8, v7
+; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: s_nop 0
+; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:32 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: v_mov_b32_e32 v9, v6
+; GFX9-O0-NEXT: v_mov_b32_e32 v6, v5
+; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: v_mov_b32_e32 v11, v4
+; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: v_mov_b32_e32 v8, v3
+; GFX9-O0-NEXT: v_mov_b32_e32 v3, v2
+; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: s_nop 0
+; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:24 ; 4-byte Folded Spill
+; GFX9-O0-NEXT: v_mov_b32_e32 v10, v1
+; GFX9-O0-NEXT: v_mov_b32_e32 v1, v0
; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:24 ; 4-byte Folded Reload
; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec
; GFX9-O0-NEXT: s_waitcnt vmcnt(4)
@@ -987,6 +932,12 @@ define amdgpu_gfx <32 x i32> @strict_wwm_callee_saves(<32 x i32> inreg %keep, pt
; GFX9-O0-NEXT: ; kill: def $vgpr10 killed $vgpr10 def $vgpr10_vgpr11 killed $exec
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-O0-NEXT: v_mov_b32_e32 v11, v0
+; GFX9-O0-NEXT: buffer_load_dword v31, off, s[0:3], s32 offset:20
+; GFX9-O0-NEXT: buffer_load_dword v30, off, s[0:3], s32 offset:16
+; GFX9-O0-NEXT: buffer_load_dword v29, off, s[0:3], s32 offset:12
+; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:8
+; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:4
+; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32
; GFX9-O0-NEXT: v_mov_b32_e32 v0, v11
; GFX9-O0-NEXT: s_or_saveexec_b64 s[34:35], -1
; GFX9-O0-NEXT: s_mov_b64 s[38:39], 0
@@ -1120,10 +1071,10 @@ define amdgpu_gfx <32 x i32> @strict_wwm_callee_saves(<32 x i32> inreg %keep, pt
; GFX9-O0-NEXT: v_mov_b32_e32 v24, s28
; GFX9-O0-NEXT: v_mov_b32_e32 v25, s29
; GFX9-O0-NEXT: s_xor_saveexec_b64 s[34:35], -1
-; GFX9-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload
-; GFX9-O0-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload
+; GFX9-O0-NEXT: buffer_load_dword v34, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload
; GFX9-O0-NEXT: s_mov_b64 exec, s[34:35]
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
; GFX9-O0-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
index ad895ad4190dd6..ddf9fe4d83977b 100644
--- a/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
+++ b/llvm/test/CodeGen/AMDGPU/wwm-reserved.ll
@@ -8,19 +8,19 @@ define amdgpu_cs void @no_cfg(ptr addrspace(8) inreg %tmp14) {
; GFX9-O0-LABEL: no_cfg:
; GFX9-O0: ; %bb.0:
; GFX9-O0-NEXT: s_mov_b32 s6, s2
-; GFX9-O0-NEXT: s_mov_b32 s4, s0
+; GFX9-O0-NEXT: s_mov_b32 s2, s1
; GFX9-O0-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX9-O0-NEXT: s_mov_b32 s7, s3
-; GFX9-O0-NEXT: s_mov_b32 s8, s7
-; GFX9-O0-NEXT: s_mov_b32 s9, s6
-; GFX9-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX9-O0-NEXT: s_mov_b32 s5, s1
-; GFX9-O0-NEXT: s_mov_b32 s10, s5
-; GFX9-O0-NEXT: s_mov_b32 s0, s4
+; GFX9-O0-NEXT: s_mov_b32 s4, s7
+; GFX9-O0-NEXT: s_mov_b32 s5, s6
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX9-O0-NEXT: s_mov_b32 s1, s2
+; GFX9-O0-NEXT: s_mov_b32 s6, s1
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX9-O0-NEXT: s_mov_b32 s1, s10
-; GFX9-O0-NEXT: s_mov_b32 s2, s9
-; GFX9-O0-NEXT: s_mov_b32 s3, s8
+; GFX9-O0-NEXT: s_mov_b32 s1, s6
+; GFX9-O0-NEXT: s_mov_b32 s2, s5
+; GFX9-O0-NEXT: s_mov_b32 s3, s4
; GFX9-O0-NEXT: s_mov_b32 s4, 0
; GFX9-O0-NEXT: buffer_load_dwordx2 v[5:6], off, s[0:3], s4
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
@@ -727,19 +727,19 @@ define amdgpu_cs void @_amdgpu_cs_main(ptr addrspace(8) inreg %desc, i32 %index)
; GFX9-O0-LABEL: _amdgpu_cs_main:
; GFX9-O0: ; %bb.0:
; GFX9-O0-NEXT: s_mov_b32 s6, s2
-; GFX9-O0-NEXT: s_mov_b32 s4, s0
+; GFX9-O0-NEXT: s_mov_b32 s2, s1
; GFX9-O0-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX9-O0-NEXT: s_mov_b32 s7, s3
-; GFX9-O0-NEXT: s_mov_b32 s8, s7
-; GFX9-O0-NEXT: s_mov_b32 s9, s6
-; GFX9-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX9-O0-NEXT: s_mov_b32 s5, s1
-; GFX9-O0-NEXT: s_mov_b32 s10, s5
-; GFX9-O0-NEXT: s_mov_b32 s0, s4
+; GFX9-O0-NEXT: s_mov_b32 s4, s7
+; GFX9-O0-NEXT: s_mov_b32 s5, s6
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX9-O0-NEXT: s_mov_b32 s1, s2
+; GFX9-O0-NEXT: s_mov_b32 s6, s1
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX9-O0-NEXT: s_mov_b32 s1, s10
-; GFX9-O0-NEXT: s_mov_b32 s2, s9
-; GFX9-O0-NEXT: s_mov_b32 s3, s8
+; GFX9-O0-NEXT: s_mov_b32 s1, s6
+; GFX9-O0-NEXT: s_mov_b32 s2, s5
+; GFX9-O0-NEXT: s_mov_b32 s3, s4
; GFX9-O0-NEXT: s_mov_b32 s4, 5
; GFX9-O0-NEXT: v_lshlrev_b32_e64 v0, s4, v0
; GFX9-O0-NEXT: s_mov_b32 s4, 0
@@ -871,19 +871,19 @@ define amdgpu_cs void @strict_wwm_no_cfg(ptr addrspace(8) inreg %tmp14) {
; GFX9-O0-LABEL: strict_wwm_no_cfg:
; GFX9-O0: ; %bb.0:
; GFX9-O0-NEXT: s_mov_b32 s6, s2
-; GFX9-O0-NEXT: s_mov_b32 s4, s0
+; GFX9-O0-NEXT: s_mov_b32 s2, s1
; GFX9-O0-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX9-O0-NEXT: s_mov_b32 s7, s3
-; GFX9-O0-NEXT: s_mov_b32 s8, s7
-; GFX9-O0-NEXT: s_mov_b32 s9, s6
-; GFX9-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX9-O0-NEXT: s_mov_b32 s5, s1
-; GFX9-O0-NEXT: s_mov_b32 s10, s5
-; GFX9-O0-NEXT: s_mov_b32 s0, s4
+; GFX9-O0-NEXT: s_mov_b32 s4, s7
+; GFX9-O0-NEXT: s_mov_b32 s5, s6
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX9-O0-NEXT: s_mov_b32 s1, s2
+; GFX9-O0-NEXT: s_mov_b32 s6, s1
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX9-O0-NEXT: s_mov_b32 s1, s10
-; GFX9-O0-NEXT: s_mov_b32 s2, s9
-; GFX9-O0-NEXT: s_mov_b32 s3, s8
+; GFX9-O0-NEXT: s_mov_b32 s1, s6
+; GFX9-O0-NEXT: s_mov_b32 s2, s5
+; GFX9-O0-NEXT: s_mov_b32 s3, s4
; GFX9-O0-NEXT: s_mov_b32 s4, 0
; GFX9-O0-NEXT: buffer_load_dwordx2 v[5:6], off, s[0:3], s4
; GFX9-O0-NEXT: s_waitcnt vmcnt(0)
@@ -1590,19 +1590,19 @@ define amdgpu_cs void @strict_wwm_amdgpu_cs_main(ptr addrspace(8) inreg %desc, i
; GFX9-O0-LABEL: strict_wwm_amdgpu_cs_main:
; GFX9-O0: ; %bb.0:
; GFX9-O0-NEXT: s_mov_b32 s6, s2
-; GFX9-O0-NEXT: s_mov_b32 s4, s0
+; GFX9-O0-NEXT: s_mov_b32 s2, s1
; GFX9-O0-NEXT: ; kill: def $sgpr6 killed $sgpr6 def $sgpr6_sgpr7
; GFX9-O0-NEXT: s_mov_b32 s7, s3
-; GFX9-O0-NEXT: s_mov_b32 s8, s7
-; GFX9-O0-NEXT: s_mov_b32 s9, s6
-; GFX9-O0-NEXT: ; kill: def $sgpr4 killed $sgpr4 def $sgpr4_sgpr5
-; GFX9-O0-NEXT: s_mov_b32 s5, s1
-; GFX9-O0-NEXT: s_mov_b32 s10, s5
-; GFX9-O0-NEXT: s_mov_b32 s0, s4
+; GFX9-O0-NEXT: s_mov_b32 s4, s7
+; GFX9-O0-NEXT: s_mov_b32 s5, s6
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1
+; GFX9-O0-NEXT: s_mov_b32 s1, s2
+; GFX9-O0-NEXT: s_mov_b32 s6, s1
+; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 killed $sgpr0_sgpr1
; GFX9-O0-NEXT: ; kill: def $sgpr0 killed $sgpr0 def $sgpr0_sgpr1_sgpr2_sgpr3
-; GFX9-O0-NEXT: s_mov_b32 s1, s10
-; GFX9-O0-NEXT: s_mov_b32 s2, s9
-; GFX9-O0-NEXT: s_mov_b32 s3, s8
+; GFX9-O0-NEXT: s_mov_b32 s1, s6
+; GFX9-O0-NEXT: s_mov_b32 s2, s5
+; GFX9-O0-NEXT: s_mov_b32 s3, s4
; GFX9-O0-NEXT: s_mov_b32 s4, 5
; GFX9-O0-NEXT: v_lshlrev_b32_e64 v0, s4, v0
; GFX9-O0-NEXT: s_mov_b32 s4, 0
diff --git a/llvm/test/CodeGen/ARM/strict-fp-int-promote.ll b/llvm/test/CodeGen/ARM/strict-fp-int-promote.ll
index b62c823166a43f..4242c60de88d2d 100644
--- a/llvm/test/CodeGen/ARM/strict-fp-int-promote.ll
+++ b/llvm/test/CodeGen/ARM/strict-fp-int-promote.ll
@@ -10,9 +10,11 @@ declare float @llvm.experimental.constrained.uitofp.f32.i16(i16, metadata, metad
define i32 @test(i32 %a, i16 %b) #0 {
; CHECK-LABEL: test:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r1, r0
-; CHECK-NEXT: sxth r0, r2
+; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
+; CHECK-NEXT: sxth r0, r0
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vcvt.f32.s32 s0, s0
; CHECK-NEXT: vmov s2, r0
@@ -21,6 +23,7 @@ define i32 @test(i32 %a, i16 %b) #0 {
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: movweq r0, #1
+; CHECK-NEXT: add sp, sp, #4
; CHECK-NEXT: bx lr
;
; CHECK-O3-LABEL: test:
@@ -46,9 +49,11 @@ entry:
define i32 @test2(i32 %a, i16 %b) #0 {
; CHECK-LABEL: test2:
; CHECK: @ %bb.0: @ %entry
-; CHECK-NEXT: mov r2, r1
+; CHECK-NEXT: sub sp, sp, #4
+; CHECK-NEXT: str r1, [sp] @ 4-byte Spill
; CHECK-NEXT: mov r1, r0
-; CHECK-NEXT: uxth r0, r2
+; CHECK-NEXT: ldr r0, [sp] @ 4-byte Reload
+; CHECK-NEXT: uxth r0, r0
; CHECK-NEXT: vmov s0, r1
; CHECK-NEXT: vcvt.f32.s32 s0, s0
; CHECK-NEXT: vmov s2, r0
@@ -57,6 +62,7 @@ define i32 @test2(i32 %a, i16 %b) #0 {
; CHECK-NEXT: vmrs APSR_nzcv, fpscr
; CHECK-NEXT: mov r0, #0
; CHECK-NEXT: movweq r0, #1
+; CHECK-NEXT: add sp, sp, #4
; CHECK-NEXT: bx lr
;
; CHECK-O3-LABEL: test2:
diff --git a/llvm/test/CodeGen/Mips/atomic.ll b/llvm/test/CodeGen/Mips/atomic.ll
index f83de83b3d037d..678b1950bc97cc 100644
--- a/llvm/test/CodeGen/Mips/atomic.ll
+++ b/llvm/test/CodeGen/Mips/atomic.ll
@@ -1762,8 +1762,7 @@ define i32 @AtomicSwap32(i32 signext %newval) nounwind {
; MIPS64R6O0-NEXT: lui $1, %hi(%neg(%gp_rel(AtomicSwap32)))
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicSwap32)))
-; MIPS64R6O0-NEXT: move $2, $4
-; MIPS64R6O0-NEXT: sw $2, 12($sp)
+; MIPS64R6O0-NEXT: sw $4, 12($sp)
; MIPS64R6O0-NEXT: lw $4, 12($sp)
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB6_1: # %entry
@@ -2095,8 +2094,7 @@ define i32 @AtomicCmpSwap32(i32 signext %oldval, i32 signext %newval) nounwind {
; MIPS64R6O0-NEXT: daddu $1, $1, $25
; MIPS64R6O0-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(AtomicCmpSwap32)))
; MIPS64R6O0-NEXT: # kill: def $a0 killed $a0 killed $a0_64
-; MIPS64R6O0-NEXT: move $2, $5
-; MIPS64R6O0-NEXT: sw $2, 12($sp)
+; MIPS64R6O0-NEXT: sw $5, 12($sp)
; MIPS64R6O0-NEXT: lw $5, 12($sp)
; MIPS64R6O0-NEXT: ld $3, %got_disp(x)($1)
; MIPS64R6O0-NEXT: .LBB7_1: # %entry
diff --git a/llvm/test/CodeGen/NVPTX/address-folder.ll b/llvm/test/CodeGen/NVPTX/address-folder.ll
index 813fd2c4396518..56ee83f29c9119 100644
--- a/llvm/test/CodeGen/NVPTX/address-folder.ll
+++ b/llvm/test/CodeGen/NVPTX/address-folder.ll
@@ -32,17 +32,17 @@ define ptx_kernel void @test_kernel_cross_block(ptr byval([2 x i64]) align 8 %r,
; O0-NEXT: .reg .b64 %rd<7>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd3, [test_kernel_cross_block_param_2];
-; O0-NEXT: ld.param.b64 %rd2, [test_kernel_cross_block_param_1];
+; O0-NEXT: ld.param.b64 %rd2, [test_kernel_cross_block_param_2];
; O0-NEXT: mov.b64 %rd1, test_kernel_cross_block_param_0;
-; O0-NEXT: setp.lt.s64 %p1, %rd2, 1;
+; O0-NEXT: ld.param.b64 %rd3, [test_kernel_cross_block_param_1];
+; O0-NEXT: setp.lt.s64 %p1, %rd3, 1;
; O0-NEXT: @%p1 bra $L__BB0_2;
; O0-NEXT: bra.uni $L__BB0_1;
; O0-NEXT: $L__BB0_1: // %body
; O0-NEXT: ld.param.b64 %rd4, [%rd1];
; O0-NEXT: ld.param.b64 %rd5, [%rd1+8];
; O0-NEXT: mul.lo.s64 %rd6, %rd4, %rd5;
-; O0-NEXT: st.global.b64 [%rd3], %rd6;
+; O0-NEXT: st.global.b64 [%rd2], %rd6;
; O0-NEXT: bra.uni $L__BB0_2;
; O0-NEXT: $L__BB0_2: // %done
; O0-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/bfe.ll b/llvm/test/CodeGen/NVPTX/bfe.ll
index 0b5dab03b1af23..e230d2c5fda9ba 100644
--- a/llvm/test/CodeGen/NVPTX/bfe.ll
+++ b/llvm/test/CodeGen/NVPTX/bfe.ll
@@ -112,31 +112,18 @@ define i32 @bfe_shifted_mask(i32 %x) {
}
define i64 @no_bfe_i64_start_above_32(i64 %a, i64 %b) {
-; CHECK-O3-LABEL: no_bfe_i64_start_above_32(
-; CHECK-O3: {
-; CHECK-O3-NEXT: .reg .b64 %rd<6>;
-; CHECK-O3-EMPTY:
-; CHECK-O3-NEXT: // %bb.0:
-; CHECK-O3-NEXT: ld.param.b64 %rd1, [no_bfe_i64_start_above_32_param_0];
-; CHECK-O3-NEXT: ld.param.b64 %rd2, [no_bfe_i64_start_above_32_param_1];
-; CHECK-O3-NEXT: xor.b64 %rd3, %rd1, %rd2;
-; CHECK-O3-NEXT: shr.u64 %rd4, %rd3, 40;
-; CHECK-O3-NEXT: and.b64 %rd5, %rd4, 255;
-; CHECK-O3-NEXT: st.param.b64 [func_retval0], %rd5;
-; CHECK-O3-NEXT: ret;
-;
-; CHECK-O0-LABEL: no_bfe_i64_start_above_32(
-; CHECK-O0: {
-; CHECK-O0-NEXT: .reg .b64 %rd<6>;
-; CHECK-O0-EMPTY:
-; CHECK-O0-NEXT: // %bb.0:
-; CHECK-O0-NEXT: ld.param.b64 %rd2, [no_bfe_i64_start_above_32_param_1];
-; CHECK-O0-NEXT: ld.param.b64 %rd1, [no_bfe_i64_start_above_32_param_0];
-; CHECK-O0-NEXT: xor.b64 %rd3, %rd1, %rd2;
-; CHECK-O0-NEXT: shr.u64 %rd4, %rd3, 40;
-; CHECK-O0-NEXT: and.b64 %rd5, %rd4, 255;
-; CHECK-O0-NEXT: st.param.b64 [func_retval0], %rd5;
-; CHECK-O0-NEXT: ret;
+; CHECK-LABEL: no_bfe_i64_start_above_32(
+; CHECK: {
+; CHECK-NEXT: .reg .b64 %rd<6>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b64 %rd1, [no_bfe_i64_start_above_32_param_0];
+; CHECK-NEXT: ld.param.b64 %rd2, [no_bfe_i64_start_above_32_param_1];
+; CHECK-NEXT: xor.b64 %rd3, %rd1, %rd2;
+; CHECK-NEXT: shr.u64 %rd4, %rd3, 40;
+; CHECK-NEXT: and.b64 %rd5, %rd4, 255;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd5;
+; CHECK-NEXT: ret;
;
; SM70-LABEL: no_bfe_i64_start_above_32(
; SM70: {
@@ -265,25 +252,15 @@ define i64 @no_bfe_on_64bit_overflow_shr_and_pair(i64 %a) {
}
define i32 @bfe_ashr_signed_32(i32 %x) {
-; CHECK-O3-LABEL: bfe_ashr_signed_32(
-; CHECK-O3: {
-; CHECK-O3-NEXT: .reg .b32 %r<3>;
-; CHECK-O3-EMPTY:
-; CHECK-O3-NEXT: // %bb.0:
-; CHECK-O3-NEXT: ld.param.b16 %r1, [bfe_ashr_signed_32_param_0+2];
-; CHECK-O3-NEXT: bfe.s32 %r2, %r1, 4, 12;
-; CHECK-O3-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-O3-NEXT: ret;
-;
-; CHECK-O0-LABEL: bfe_ashr_signed_32(
-; CHECK-O0: {
-; CHECK-O0-NEXT: .reg .b32 %r<3>;
-; CHECK-O0-EMPTY:
-; CHECK-O0-NEXT: // %bb.0:
-; CHECK-O0-NEXT: ld.param.b32 %r1, [bfe_ashr_signed_32_param_0];
-; CHECK-O0-NEXT: bfe.s32 %r2, %r1, 20, 12;
-; CHECK-O0-NEXT: st.param.b32 [func_retval0], %r2;
-; CHECK-O0-NEXT: ret;
+; CHECK-LABEL: bfe_ashr_signed_32(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %r1, [bfe_ashr_signed_32_param_0+2];
+; CHECK-NEXT: bfe.s32 %r2, %r1, 4, 12;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r2;
+; CHECK-NEXT: ret;
;
; SM70-LABEL: bfe_ashr_signed_32(
; SM70: {
@@ -438,3 +415,6 @@ define i64 @bfe4(i128 %a) {
%shr = ashr exact i64 %and, 17
ret i64 %shr
}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK-O0: {{.*}}
+; CHECK-O3: {{.*}}
diff --git a/llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll b/llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll
index 356992e4a95021..1d9c294087792d 100644
--- a/llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll
+++ b/llvm/test/CodeGen/NVPTX/cache-hint-transforms.ll
@@ -136,19 +136,12 @@ define <16 x i32> @test_legalize_split_load_v16i32(ptr addrspace(1) %p) {
}
define void @test_legalize_split_store_v16i32(ptr addrspace(1) %p, <16 x i32> %v) {
-; O2-LABEL: test_legalize_split_store_v16i32(
-; O2: mov.b64 %rd2, 12345;
-; O2: st.global.L2::cache_hint.v4.b32 [%rd1+48], {%r1, %r2, %r3, %r4}, %rd2;
-; O2: st.global.L2::cache_hint.v4.b32 [%rd1+32], {%r5, %r6, %r7, %r8}, %rd2;
-; O2: st.global.L2::cache_hint.v4.b32 [%rd1+16], {%r9, %r10, %r11, %r12}, %rd2;
-; O2: st.global.L2::cache_hint.v4.b32 [%rd1], {%r13, %r14, %r15, %r16}, %rd2;
-;
-; O0-LABEL: test_legalize_split_store_v16i32(
-; O0: mov.b64 %rd2, 12345;
-; O0: st.global.L2::cache_hint.v4.b32 [%rd1+48], {%r13, %r14, %r15, %r16}, %rd2;
-; O0: st.global.L2::cache_hint.v4.b32 [%rd1+32], {%r9, %r10, %r11, %r12}, %rd2;
-; O0: st.global.L2::cache_hint.v4.b32 [%rd1+16], {%r5, %r6, %r7, %r8}, %rd2;
-; O0: st.global.L2::cache_hint.v4.b32 [%rd1], {%r1, %r2, %r3, %r4}, %rd2;
+; CHECK-LABEL: test_legalize_split_store_v16i32(
+; CHECK: mov.b64 %rd2, 12345;
+; CHECK: st.global.L2::cache_hint.v4.b32 [%rd1+48], {%r1, %r2, %r3, %r4}, %rd2;
+; CHECK: st.global.L2::cache_hint.v4.b32 [%rd1+32], {%r5, %r6, %r7, %r8}, %rd2;
+; CHECK: st.global.L2::cache_hint.v4.b32 [%rd1+16], {%r9, %r10, %r11, %r12}, %rd2;
+; CHECK: st.global.L2::cache_hint.v4.b32 [%rd1], {%r13, %r14, %r15, %r16}, %rd2;
store <16 x i32> %v, ptr addrspace(1) %p, align 16, !mem.cache_hint !12
ret void
}
@@ -163,15 +156,10 @@ define <3 x i64> @test_legalize_scalarize_load_v3i64(ptr addrspace(1) %p) {
}
define void @test_legalize_scalarize_store_v3i64(ptr addrspace(1) %p, <3 x i64> %v) {
-; O2-LABEL: test_legalize_scalarize_store_v3i64(
-; O2: st.global.L1::evict_first.b64 [%rd1+16], %rd2;
-; O2: st.global.L1::evict_first.b64 [%rd1+8], %rd4;
-; O2: st.global.L1::evict_first.b64 [%rd1], %rd3;
-;
-; O0-LABEL: test_legalize_scalarize_store_v3i64(
-; O0: st.global.L1::evict_first.b64 [%rd1+16], %rd4;
-; O0: st.global.L1::evict_first.b64 [%rd1+8], %rd3;
-; O0: st.global.L1::evict_first.b64 [%rd1], %rd2;
+; CHECK-LABEL: test_legalize_scalarize_store_v3i64(
+; CHECK: st.global.L1::evict_first.b64 [%rd1+16], %rd2;
+; CHECK: st.global.L1::evict_first.b64 [%rd1+8], %rd4;
+; CHECK: st.global.L1::evict_first.b64 [%rd1], %rd3;
store <3 x i64> %v, ptr addrspace(1) %p, align 8, !mem.cache_hint !14
ret void
}
@@ -228,21 +216,21 @@ define void @legalize_unaligned_v3i64_store(ptr addrspace(1) %p, <3 x i64> %v) {
; O2: st.global.L1::evict_first.b8 [%rd1+1], %rd25;
;
; O0-LABEL: legalize_unaligned_v3i64_store(
-; O0: st.global.L1::evict_first.b8 [%rd1+23], %rd5;
-; O0: st.global.L1::evict_first.b8 [%rd1+22], %rd6;
-; O0: st.global.L1::evict_first.b8 [%rd1+21], %rd7;
-; O0: st.global.L1::evict_first.b8 [%rd1+20], %rd8;
-; O0: st.global.L1::evict_first.b8 [%rd1+19], %rd9;
-; O0: st.global.L1::evict_first.b8 [%rd1+18], %rd10;
-; O0: st.global.L1::evict_first.b8 [%rd1+16], %rd4;
-; O0: st.global.L1::evict_first.b8 [%rd1+17], %rd11;
+; O0: st.global.L1::evict_first.b8 [%rd1+23], %rd3;
+; O0: st.global.L1::evict_first.b8 [%rd1+22], %rd4;
+; O0: st.global.L1::evict_first.b8 [%rd1+21], %rd5;
+; O0: st.global.L1::evict_first.b8 [%rd1+20], %rd6;
+; O0: st.global.L1::evict_first.b8 [%rd1+19], %rd7;
+; O0: st.global.L1::evict_first.b8 [%rd1+18], %rd8;
+; O0: st.global.L1::evict_first.b8 [%rd1+16], %rd2;
+; O0: st.global.L1::evict_first.b8 [%rd1+17], %rd9;
; O0: st.global.L1::evict_first.b8 [%rd1+15], %rd12;
; O0: st.global.L1::evict_first.b8 [%rd1+14], %rd13;
; O0: st.global.L1::evict_first.b8 [%rd1+13], %rd14;
; O0: st.global.L1::evict_first.b8 [%rd1+12], %rd15;
; O0: st.global.L1::evict_first.b8 [%rd1+11], %rd16;
; O0: st.global.L1::evict_first.b8 [%rd1+10], %rd17;
-; O0: st.global.L1::evict_first.b8 [%rd1+8], %rd3;
+; O0: st.global.L1::evict_first.b8 [%rd1+8], %rd11;
; O0: st.global.L1::evict_first.b8 [%rd1+9], %rd18;
; O0: st.global.L1::evict_first.b8 [%rd1+7], %rd19;
; O0: st.global.L1::evict_first.b8 [%rd1+6], %rd20;
@@ -250,7 +238,7 @@ define void @legalize_unaligned_v3i64_store(ptr addrspace(1) %p, <3 x i64> %v) {
; O0: st.global.L1::evict_first.b8 [%rd1+4], %rd22;
; O0: st.global.L1::evict_first.b8 [%rd1+3], %rd23;
; O0: st.global.L1::evict_first.b8 [%rd1+2], %rd24;
-; O0: st.global.L1::evict_first.b8 [%rd1], %rd2;
+; O0: st.global.L1::evict_first.b8 [%rd1], %rd10;
; O0: st.global.L1::evict_first.b8 [%rd1+1], %rd25;
store <3 x i64> %v, ptr addrspace(1) %p, align 1, !mem.cache_hint !14
ret void
@@ -343,11 +331,8 @@ define <3 x i1> @legalize_scalarize_load_v3i1(ptr addrspace(1) %p) {
}
define void @legalize_scalarize_store_v3i1(ptr addrspace(1) %p, <3 x i1> %v) {
-; O2-LABEL: legalize_scalarize_store_v3i1(
-; O2: st.global.L1::evict_first.b8 [%rd1], %rs10;
-;
-; O0-LABEL: legalize_scalarize_store_v3i1(
-; O0: st.global.L1::evict_first.b8 [%rd1], %rs11;
+; CHECK-LABEL: legalize_scalarize_store_v3i1(
+; CHECK: st.global.L1::evict_first.b8 [%rd1], %rs10;
store <3 x i1> %v, ptr addrspace(1) %p, align 1, !mem.cache_hint !14
ret void
}
@@ -369,10 +354,9 @@ define void @legalize_widen_truncstore_v3i8(ptr addrspace(1) %p, <3 x i32> %v) {
; O2: st.global.L1::evict_first.b8 [%rd1+1], %rs3;
;
; O0-LABEL: legalize_widen_truncstore_v3i8(
-; O0: ld.param.b32 %r3, [legalize_widen_truncstore_v3i8_param_1+8];
-; O0: st.global.L1::evict_first.b8 [%rd1], %rs1;
-; O0: st.global.L1::evict_first.b8 [%rd1+1], %rs2;
-; O0: st.global.L1::evict_first.b8 [%rd1+2], %r3;
+; O0: st.global.L1::evict_first.b8 [%rd1], %rs2;
+; O0: st.global.L1::evict_first.b8 [%rd1+1], %rs3;
+; O0: st.global.L1::evict_first.b8 [%rd1+2], %rs1;
%trunc = trunc <3 x i32> %v to <3 x i8>
store <3 x i8> %trunc, ptr addrspace(1) %p, align 1, !mem.cache_hint !14
ret void
@@ -383,7 +367,7 @@ define i32 @scalarize_extracted_vector_load(ptr addrspace(1) %p, i64 %idx) {
; O2: ld.global.L1::evict_last.b32 %r1, [%rd5];
;
; O0-LABEL: scalarize_extracted_vector_load(
-; O0: mov.b64 %rd2, %rd3;
+; O0: mov.b64 %rd3, %rd2;
; O0: ld.global.L1::evict_last.b32 %r1, [%rd6];
%v = load <4 x i32>, ptr addrspace(1) %p, align 16, !mem.cache_hint !13
%elt = extractelement <4 x i32> %v, i64 %idx
diff --git a/llvm/test/CodeGen/NVPTX/combine-wide.ll b/llvm/test/CodeGen/NVPTX/combine-wide.ll
index 63e0f3789f49fd..9a5ae707a74e23 100644
--- a/llvm/test/CodeGen/NVPTX/combine-wide.ll
+++ b/llvm/test/CodeGen/NVPTX/combine-wide.ll
@@ -39,12 +39,12 @@ define i64 @t1(i32 %a, i32 %b, i64 %c) {
; O0-NEXT: .reg .b64 %rd<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [t1_param_2];
-; O0-NEXT: ld.param.b32 %r2, [t1_param_1];
; O0-NEXT: ld.param.b32 %r1, [t1_param_0];
+; O0-NEXT: ld.param.b32 %r2, [t1_param_1];
; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.s64.s32 %rd2, %r3;
-; O0-NEXT: add.s64 %rd3, %rd1, %rd2;
+; O0-NEXT: cvt.s64.s32 %rd1, %r3;
+; O0-NEXT: ld.param.b64 %rd2, [t1_param_2];
+; O0-NEXT: add.s64 %rd3, %rd2, %rd1;
; O0-NEXT: st.param.b64 [func_retval0], %rd3;
; O0-NEXT: ret;
%mul = mul nsw i32 %a, %b
@@ -87,12 +87,12 @@ define i64 @t2(i32 %a, i32 %b, i64 %c) {
; O0-NEXT: .reg .b64 %rd<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [t2_param_2];
-; O0-NEXT: ld.param.b32 %r2, [t2_param_1];
; O0-NEXT: ld.param.b32 %r1, [t2_param_0];
+; O0-NEXT: ld.param.b32 %r2, [t2_param_1];
; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.s64.s32 %rd2, %r3;
-; O0-NEXT: add.s64 %rd3, %rd2, %rd1;
+; O0-NEXT: cvt.s64.s32 %rd1, %r3;
+; O0-NEXT: ld.param.b64 %rd2, [t2_param_2];
+; O0-NEXT: add.s64 %rd3, %rd1, %rd2;
; O0-NEXT: st.param.b64 [func_retval0], %rd3;
; O0-NEXT: ret;
%mul = mul nsw i32 %a, %b
@@ -133,8 +133,8 @@ define i64 @t3(i32 %a, i32 %b) {
; O0-NEXT: .reg .b64 %rd<3>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t3_param_1];
; O0-NEXT: ld.param.b32 %r1, [t3_param_0];
+; O0-NEXT: ld.param.b32 %r2, [t3_param_1];
; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
; O0-NEXT: cvt.s64.s32 %rd1, %r3;
; O0-NEXT: add.s64 %rd2, %rd1, 1;
@@ -178,9 +178,9 @@ define i64 @t4(i32 %a, i64 %c) {
; O0-NEXT: .reg .b64 %rd<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [t4_param_1];
; O0-NEXT: ld.param.b32 %r1, [t4_param_0];
; O0-NEXT: mul.lo.s32 %r2, %r1, 3;
+; O0-NEXT: ld.param.b64 %rd1, [t4_param_1];
; O0-NEXT: cvt.s64.s32 %rd2, %r2;
; O0-NEXT: add.s64 %rd3, %rd1, %rd2;
; O0-NEXT: st.param.b64 [func_retval0], %rd3;
@@ -267,12 +267,12 @@ define i64 @t5(i32 %a, i32 %b, i64 %c) {
; O0-NEXT: .reg .b64 %rd<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [t5_param_2];
-; O0-NEXT: ld.param.b32 %r2, [t5_param_1];
; O0-NEXT: ld.param.b32 %r1, [t5_param_0];
+; O0-NEXT: ld.param.b32 %r2, [t5_param_1];
; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.u64.u32 %rd2, %r3;
-; O0-NEXT: add.s64 %rd3, %rd1, %rd2;
+; O0-NEXT: cvt.u64.u32 %rd1, %r3;
+; O0-NEXT: ld.param.b64 %rd2, [t5_param_2];
+; O0-NEXT: add.s64 %rd3, %rd2, %rd1;
; O0-NEXT: st.param.b64 [func_retval0], %rd3;
; O0-NEXT: ret;
%mul = mul nuw i32 %a, %b
@@ -315,12 +315,12 @@ define i64 @t6(i32 %a, i32 %b, i64 %c) {
; O0-NEXT: .reg .b64 %rd<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [t6_param_2];
-; O0-NEXT: ld.param.b32 %r2, [t6_param_1];
; O0-NEXT: ld.param.b32 %r1, [t6_param_0];
+; O0-NEXT: ld.param.b32 %r2, [t6_param_1];
; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.u64.u32 %rd2, %r3;
-; O0-NEXT: add.s64 %rd3, %rd2, %rd1;
+; O0-NEXT: cvt.u64.u32 %rd1, %r3;
+; O0-NEXT: ld.param.b64 %rd2, [t6_param_2];
+; O0-NEXT: add.s64 %rd3, %rd1, %rd2;
; O0-NEXT: st.param.b64 [func_retval0], %rd3;
; O0-NEXT: ret;
%mul = mul nuw i32 %a, %b
@@ -330,155 +330,90 @@ define i64 @t6(i32 %a, i32 %b, i64 %c) {
}
define i32 @t7(i16 %a, i16 %b) {
-; O1-LABEL: t7(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b32 %r<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t7_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t7_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.u32.u16 %r1, %rs3;
-; O1-NEXT: st.param.b32 [func_retval0], %r1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t7(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t7_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t7_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.u32.u16 %r1, %rs3;
-; O0-NEXT: st.param.b32 [func_retval0], %r1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t7(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t7_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t7_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%mul = mul i16 %a, %b
%zext = zext i16 %mul to i32
ret i32 %zext
}
define i32 @t8(i16 %a, i16 %b) {
-; O1-LABEL: t8(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b32 %r<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t8_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t8_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.s32.s16 %r1, %rs3;
-; O1-NEXT: st.param.b32 [func_retval0], %r1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t8(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t8_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t8_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.s32.s16 %r1, %rs3;
-; O0-NEXT: st.param.b32 [func_retval0], %r1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t8(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t8_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t8_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.s32.s16 %r1, %rs3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%mul = mul i16 %a, %b
%sext = sext i16 %mul to i32
ret i32 %sext
}
define i64 @t9(i32 %a, i32 %b) {
-; O1-LABEL: t9(
-; O1: {
-; O1-NEXT: .reg .b32 %r<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b32 %r1, [t9_param_0];
-; O1-NEXT: ld.param.b32 %r2, [t9_param_1];
-; O1-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O1-NEXT: cvt.u64.u32 %rd1, %r3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t9(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t9_param_1];
-; O0-NEXT: ld.param.b32 %r1, [t9_param_0];
-; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.u64.u32 %rd1, %r3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t9(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [t9_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [t9_param_1];
+; CHECK-NEXT: mul.lo.s32 %r3, %r1, %r2;
+; CHECK-NEXT: cvt.u64.u32 %rd1, %r3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = mul i32 %a, %b
%zext = zext i32 %mul to i64
ret i64 %zext
}
define i64 @t10(i32 %a, i32 %b) {
-; O1-LABEL: t10(
-; O1: {
-; O1-NEXT: .reg .b32 %r<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b32 %r1, [t10_param_0];
-; O1-NEXT: ld.param.b32 %r2, [t10_param_1];
-; O1-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O1-NEXT: cvt.s64.s32 %rd1, %r3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t10(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t10_param_1];
-; O0-NEXT: ld.param.b32 %r1, [t10_param_0];
-; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.s64.s32 %rd1, %r3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t10(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [t10_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [t10_param_1];
+; CHECK-NEXT: mul.lo.s32 %r3, %r1, %r2;
+; CHECK-NEXT: cvt.s64.s32 %rd1, %r3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = mul i32 %a, %b
%sext = sext i32 %mul to i64
ret i64 %sext
}
define i32 @t11(i16 %a, i16 %b) {
-; O1-LABEL: t11(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b32 %r<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t11_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t11_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.u32.u16 %r1, %rs3;
-; O1-NEXT: st.param.b32 [func_retval0], %r1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t11(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t11_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t11_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.u32.u16 %r1, %rs3;
-; O0-NEXT: st.param.b32 [func_retval0], %r1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t11(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t11_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t11_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%mul = mul nsw i16 %a, %b
%zext = zext i16 %mul to i32
ret i32 %zext
@@ -503,8 +438,8 @@ define i32 @t12(i16 %a, i16 %b) {
; O0-NEXT: .reg .b32 %r<2>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t12_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t12_param_0];
+; O0-NEXT: ld.param.b16 %rs2, [t12_param_1];
; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
; O0-NEXT: cvt.s32.s16 %r1, %rs3;
; O0-NEXT: st.param.b32 [func_retval0], %r1;
@@ -515,31 +450,18 @@ define i32 @t12(i16 %a, i16 %b) {
}
define i64 @t13(i32 %a, i32 %b) {
-; O1-LABEL: t13(
-; O1: {
-; O1-NEXT: .reg .b32 %r<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b32 %r1, [t13_param_0];
-; O1-NEXT: ld.param.b32 %r2, [t13_param_1];
-; O1-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O1-NEXT: cvt.u64.u32 %rd1, %r3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t13(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t13_param_1];
-; O0-NEXT: ld.param.b32 %r1, [t13_param_0];
-; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.u64.u32 %rd1, %r3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t13(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [t13_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [t13_param_1];
+; CHECK-NEXT: mul.lo.s32 %r3, %r1, %r2;
+; CHECK-NEXT: cvt.u64.u32 %rd1, %r3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = mul nsw i32 %a, %b
%zext = zext i32 %mul to i64
ret i64 %zext
@@ -564,8 +486,8 @@ define i64 @t14(i32 %a, i32 %b) {
; O0-NEXT: .reg .b64 %rd<2>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t14_param_1];
; O0-NEXT: ld.param.b32 %r1, [t14_param_0];
+; O0-NEXT: ld.param.b32 %r2, [t14_param_1];
; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
; O0-NEXT: cvt.s64.s32 %rd1, %r3;
; O0-NEXT: st.param.b64 [func_retval0], %rd1;
@@ -594,8 +516,8 @@ define i32 @t15(i16 %a, i16 %b) {
; O0-NEXT: .reg .b32 %r<2>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t15_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t15_param_0];
+; O0-NEXT: ld.param.b16 %rs2, [t15_param_1];
; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
; O0-NEXT: cvt.u32.u16 %r1, %rs3;
; O0-NEXT: st.param.b32 [func_retval0], %r1;
@@ -606,31 +528,18 @@ define i32 @t15(i16 %a, i16 %b) {
}
define i32 @t16(i16 %a, i16 %b) {
-; O1-LABEL: t16(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b32 %r<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t16_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t16_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.s32.s16 %r1, %rs3;
-; O1-NEXT: st.param.b32 [func_retval0], %r1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t16(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t16_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t16_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.s32.s16 %r1, %rs3;
-; O0-NEXT: st.param.b32 [func_retval0], %r1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t16(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t16_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t16_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.s32.s16 %r1, %rs3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%mul = mul nuw i16 %a, %b
%sext = sext i16 %mul to i32
ret i32 %sext
@@ -655,8 +564,8 @@ define i64 @t17(i32 %a, i32 %b) {
; O0-NEXT: .reg .b64 %rd<2>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t17_param_1];
; O0-NEXT: ld.param.b32 %r1, [t17_param_0];
+; O0-NEXT: ld.param.b32 %r2, [t17_param_1];
; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
; O0-NEXT: cvt.u64.u32 %rd1, %r3;
; O0-NEXT: st.param.b64 [func_retval0], %rd1;
@@ -667,62 +576,36 @@ define i64 @t17(i32 %a, i32 %b) {
}
define i64 @t18(i32 %a, i32 %b) {
-; O1-LABEL: t18(
-; O1: {
-; O1-NEXT: .reg .b32 %r<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b32 %r1, [t18_param_0];
-; O1-NEXT: ld.param.b32 %r2, [t18_param_1];
-; O1-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O1-NEXT: cvt.s64.s32 %rd1, %r3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t18(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t18_param_1];
-; O0-NEXT: ld.param.b32 %r1, [t18_param_0];
-; O0-NEXT: mul.lo.s32 %r3, %r1, %r2;
-; O0-NEXT: cvt.s64.s32 %rd1, %r3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t18(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [t18_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [t18_param_1];
+; CHECK-NEXT: mul.lo.s32 %r3, %r1, %r2;
+; CHECK-NEXT: cvt.s64.s32 %rd1, %r3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = mul nuw i32 %a, %b
%sext = sext i32 %mul to i64
ret i64 %sext
}
define i32 @t19(i16 %a, i16 %b) {
-; O1-LABEL: t19(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b32 %r<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t19_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t19_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.u32.u16 %r1, %rs3;
-; O1-NEXT: st.param.b32 [func_retval0], %r1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t19(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t19_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t19_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.u32.u16 %r1, %rs3;
-; O0-NEXT: st.param.b32 [func_retval0], %r1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t19(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t19_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t19_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%mul = mul i16 %a, %b
%zext = zext i16 %mul to i32
ret i32 %zext
@@ -960,31 +843,18 @@ define i64 @t30(i32 %a) {
}
define i64 @t31(i32 %a, i32 %b) {
-; O1-LABEL: t31(
-; O1: {
-; O1-NEXT: .reg .b32 %r<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b32 %r1, [t31_param_0];
-; O1-NEXT: ld.param.b32 %r2, [t31_param_1];
-; O1-NEXT: shl.b32 %r3, %r1, %r2;
-; O1-NEXT: cvt.s64.s32 %rd1, %r3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t31(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [t31_param_1];
-; O0-NEXT: ld.param.b32 %r1, [t31_param_0];
-; O0-NEXT: shl.b32 %r3, %r1, %r2;
-; O0-NEXT: cvt.s64.s32 %rd1, %r3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t31(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [t31_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [t31_param_1];
+; CHECK-NEXT: shl.b32 %r3, %r1, %r2;
+; CHECK-NEXT: cvt.s64.s32 %rd1, %r3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = shl nuw i32 %a, %b
%sext = sext i32 %mul to i64
ret i64 %sext
@@ -1024,12 +894,12 @@ define i32 @t32(i16 %a, i16 %b, i32 %c) {
; O0-NEXT: .reg .b32 %r<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r1, [t32_param_2];
-; O0-NEXT: ld.param.b16 %rs2, [t32_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t32_param_0];
+; O0-NEXT: ld.param.b16 %rs2, [t32_param_1];
; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.s32.s16 %r2, %rs3;
-; O0-NEXT: add.s32 %r3, %r1, %r2;
+; O0-NEXT: cvt.s32.s16 %r1, %rs3;
+; O0-NEXT: ld.param.b32 %r2, [t32_param_2];
+; O0-NEXT: add.s32 %r3, %r2, %r1;
; O0-NEXT: st.param.b32 [func_retval0], %r3;
; O0-NEXT: ret;
%mul = mul nsw i16 %a, %b
@@ -1072,12 +942,12 @@ define i32 @t33(i16 %a, i16 %b, i32 %c) {
; O0-NEXT: .reg .b32 %r<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r1, [t33_param_2];
-; O0-NEXT: ld.param.b16 %rs2, [t33_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t33_param_0];
+; O0-NEXT: ld.param.b16 %rs2, [t33_param_1];
; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.s32.s16 %r2, %rs3;
-; O0-NEXT: add.s32 %r3, %r1, %r2;
+; O0-NEXT: cvt.s32.s16 %r1, %rs3;
+; O0-NEXT: ld.param.b32 %r2, [t33_param_2];
+; O0-NEXT: add.s32 %r3, %r2, %r1;
; O0-NEXT: st.param.b32 [func_retval0], %r3;
; O0-NEXT: ret;
%mul = mul nsw i16 %a, %b
@@ -1118,8 +988,8 @@ define i32 @t34(i16 %a, i16 %b) {
; O0-NEXT: .reg .b32 %r<3>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t34_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t34_param_0];
+; O0-NEXT: ld.param.b16 %rs2, [t34_param_1];
; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
; O0-NEXT: cvt.s32.s16 %r1, %rs3;
; O0-NEXT: add.s32 %r2, %r1, 1;
@@ -1163,9 +1033,9 @@ define i32 @t35(i16 %a, i32 %c) {
; O0-NEXT: .reg .b32 %r<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r1, [t35_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t35_param_0];
; O0-NEXT: mul.lo.s16 %rs2, %rs1, 3;
+; O0-NEXT: ld.param.b32 %r1, [t35_param_1];
; O0-NEXT: cvt.s32.s16 %r2, %rs2;
; O0-NEXT: add.s32 %r3, %r1, %r2;
; O0-NEXT: st.param.b32 [func_retval0], %r3;
@@ -1252,12 +1122,12 @@ define i32 @t37(i16 %a, i16 %b, i32 %c) {
; O0-NEXT: .reg .b32 %r<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r1, [t37_param_2];
-; O0-NEXT: ld.param.b16 %rs2, [t37_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t37_param_0];
+; O0-NEXT: ld.param.b16 %rs2, [t37_param_1];
; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.u32.u16 %r2, %rs3;
-; O0-NEXT: add.s32 %r3, %r1, %r2;
+; O0-NEXT: cvt.u32.u16 %r1, %rs3;
+; O0-NEXT: ld.param.b32 %r2, [t37_param_2];
+; O0-NEXT: add.s32 %r3, %r2, %r1;
; O0-NEXT: st.param.b32 [func_retval0], %r3;
; O0-NEXT: ret;
%mul = mul nuw i16 %a, %b
@@ -1300,12 +1170,12 @@ define i32 @t38(i16 %a, i16 %b, i32 %c) {
; O0-NEXT: .reg .b32 %r<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r1, [t38_param_2];
-; O0-NEXT: ld.param.b16 %rs2, [t38_param_1];
; O0-NEXT: ld.param.b16 %rs1, [t38_param_0];
+; O0-NEXT: ld.param.b16 %rs2, [t38_param_1];
; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.u32.u16 %r2, %rs3;
-; O0-NEXT: add.s32 %r3, %r2, %r1;
+; O0-NEXT: cvt.u32.u16 %r1, %rs3;
+; O0-NEXT: ld.param.b32 %r2, [t38_param_2];
+; O0-NEXT: add.s32 %r3, %r1, %r2;
; O0-NEXT: st.param.b32 [func_retval0], %r3;
; O0-NEXT: ret;
%mul = mul nuw i16 %a, %b
@@ -1315,130 +1185,75 @@ define i32 @t38(i16 %a, i16 %b, i32 %c) {
}
define i64 @t39(i16 %a, i16 %b) {
-; O1-LABEL: t39(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t39_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t39_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.u64.u16 %rd1, %rs3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t39(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t39_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t39_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.u64.u16 %rd1, %rs3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t39(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t39_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t39_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.u64.u16 %rd1, %rs3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = mul i16 %a, %b
%zext = zext i16 %mul to i64
ret i64 %zext
}
define i64 @t40(i16 %a, i16 %b) {
-; O1-LABEL: t40(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t40_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t40_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.u64.u16 %rd1, %rs3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t40(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t40_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t40_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.u64.u16 %rd1, %rs3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t40(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t40_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t40_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.u64.u16 %rd1, %rs3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = mul nuw i16 %a, %b
%zext = zext i16 %mul to i64
ret i64 %zext
}
define i64 @t41(i16 %a, i16 %b) {
-; O1-LABEL: t41(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t41_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t41_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: cvt.s64.s16 %rd1, %rs3;
-; O1-NEXT: st.param.b64 [func_retval0], %rd1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t41(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b16 %rs2, [t41_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t41_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: cvt.s64.s16 %rd1, %rs3;
-; O0-NEXT: st.param.b64 [func_retval0], %rd1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t41(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t41_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t41_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: cvt.s64.s16 %rd1, %rs3;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd1;
+; CHECK-NEXT: ret;
%mul = mul nsw i16 %a, %b
%sext = sext i16 %mul to i64
ret i64 %sext
}
define i32 @t42(i16 %a, i16 %b, ptr %ptr) {
-; O1-LABEL: t42(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b32 %r<2>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t42_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t42_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: ld.param.b64 %rd1, [t42_param_2];
-; O1-NEXT: st.b16 [%rd1], %rs3;
-; O1-NEXT: cvt.u32.u16 %r1, %rs3;
-; O1-NEXT: st.param.b32 [func_retval0], %r1;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t42(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [t42_param_2];
-; O0-NEXT: ld.param.b16 %rs2, [t42_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t42_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: st.b16 [%rd1], %rs3;
-; O0-NEXT: cvt.u32.u16 %r1, %rs3;
-; O0-NEXT: st.param.b32 [func_retval0], %r1;
-; O0-NEXT: ret;
+; CHECK-LABEL: t42(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t42_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t42_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: ld.param.b64 %rd1, [t42_param_2];
+; CHECK-NEXT: st.b16 [%rd1], %rs3;
+; CHECK-NEXT: cvt.u32.u16 %r1, %rs3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
+; CHECK-NEXT: ret;
%mul = mul nuw i16 %a, %b
store i16 %mul, ptr %ptr
%zext = zext i16 %mul to i32
@@ -1446,41 +1261,23 @@ define i32 @t42(i16 %a, i16 %b, ptr %ptr) {
}
define i32 @t43(i16 %a, i16 %b, i32 %c, ptr %ptr) {
-; O1-LABEL: t43(
-; O1: {
-; O1-NEXT: .reg .b16 %rs<4>;
-; O1-NEXT: .reg .b32 %r<4>;
-; O1-NEXT: .reg .b64 %rd<2>;
-; O1-EMPTY:
-; O1-NEXT: // %bb.0:
-; O1-NEXT: ld.param.b16 %rs1, [t43_param_0];
-; O1-NEXT: ld.param.b16 %rs2, [t43_param_1];
-; O1-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O1-NEXT: ld.param.b64 %rd1, [t43_param_3];
-; O1-NEXT: st.b16 [%rd1], %rs3;
-; O1-NEXT: ld.param.b32 %r1, [t43_param_2];
-; O1-NEXT: cvt.u32.u16 %r2, %rs3;
-; O1-NEXT: add.s32 %r3, %r2, %r1;
-; O1-NEXT: st.param.b32 [func_retval0], %r3;
-; O1-NEXT: ret;
-;
-; O0-LABEL: t43(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<4>;
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [t43_param_3];
-; O0-NEXT: ld.param.b32 %r1, [t43_param_2];
-; O0-NEXT: ld.param.b16 %rs2, [t43_param_1];
-; O0-NEXT: ld.param.b16 %rs1, [t43_param_0];
-; O0-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
-; O0-NEXT: st.b16 [%rd1], %rs3;
-; O0-NEXT: cvt.u32.u16 %r2, %rs3;
-; O0-NEXT: add.s32 %r3, %r2, %r1;
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
+; CHECK-LABEL: t43(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b16 %rs1, [t43_param_0];
+; CHECK-NEXT: ld.param.b16 %rs2, [t43_param_1];
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs1, %rs2;
+; CHECK-NEXT: ld.param.b64 %rd1, [t43_param_3];
+; CHECK-NEXT: st.b16 [%rd1], %rs3;
+; CHECK-NEXT: ld.param.b32 %r1, [t43_param_2];
+; CHECK-NEXT: cvt.u32.u16 %r2, %rs3;
+; CHECK-NEXT: add.s32 %r3, %r2, %r1;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%mul = mul nuw i16 %a, %b
store i16 %mul, ptr %ptr
%zext = zext i16 %mul to i32
diff --git a/llvm/test/CodeGen/NVPTX/f16-instructions.ll b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
index 3ba8b897d01471..12523ce4e63ac4 100644
--- a/llvm/test/CodeGen/NVPTX/f16-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16-instructions.ll
@@ -257,9 +257,9 @@ define void @test_halfp0a1(ptr noalias readonly %rrom, ptr %to) {
declare half @test_callee(half %a, half %b) #0
; CHECK-LABEL: test_call(
-; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_call_param_0];
-; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_call_param_1];
+; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_call_param_0];
; CHECK: {
+; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_call_param_1];
; CHECK-DAG: .param .align 2 .b8 param0[2];
; CHECK-DAG: .param .align 2 .b8 param1[2];
; CHECK-DAG: st.param.b16 [param0], [[A]];
@@ -276,9 +276,9 @@ define half @test_call(half %a, half %b) #0 {
}
; CHECK-LABEL: test_call_flipped(
-; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_call_flipped_param_0];
-; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_call_flipped_param_1];
+; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_call_flipped_param_0];
; CHECK: {
+; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_call_flipped_param_1];
; CHECK-DAG: .param .align 2 .b8 param0[2];
; CHECK-DAG: .param .align 2 .b8 param1[2];
; CHECK-DAG: st.param.b16 [param0], [[B]];
@@ -295,9 +295,9 @@ define half @test_call_flipped(half %a, half %b) #0 {
}
; CHECK-LABEL: test_tailcall_flipped(
-; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_tailcall_flipped_param_0];
-; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_tailcall_flipped_param_1];
+; CHECK: ld.param.b16 [[A:%rs[0-9]+]], [test_tailcall_flipped_param_0];
; CHECK: {
+; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_tailcall_flipped_param_1];
; CHECK-DAG: .param .align 2 .b8 param0[2];
; CHECK-DAG: .param .align 2 .b8 param1[2];
; CHECK-DAG: st.param.b16 [param0], [[B]];
@@ -314,10 +314,11 @@ define half @test_tailcall_flipped(half %a, half %b) #0 {
}
; CHECK-LABEL: test_select(
-; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_select_param_0];
-; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_select_param_1];
; CHECK-DAG: setp.ne.b16 [[PRED:%p[0-9]+]], %rs{{.*}}, 0;
-; CHECK-NEXT: selp.b16 [[R:%rs[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-DAG: mov.b64 [[A:%rd[0-9]+]], test_select_param_0;
+; CHECK-DAG: mov.b64 [[B:%rd[0-9]+]], test_select_param_1;
+; CHECK: selp.b64 [[PTR:%rd[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-NEXT: ld.param.b16 [[R:%rs[0-9]+]], {{\[}}[[PTR]]{{\]}};
; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];
; CHECK-NEXT: ret;
define half @test_select(half %a, half %b, i1 zeroext %c) #0 {
@@ -326,15 +327,14 @@ define half @test_select(half %a, half %b, i1 zeroext %c) #0 {
}
; CHECK-LABEL: test_select_cc(
-; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_select_cc_param_0];
-; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_select_cc_param_1];
-; CHECK-DAG: ld.param.b16 [[C:%rs[0-9]+]], [test_select_cc_param_2];
-; CHECK-DAG: ld.param.b16 [[D:%rs[0-9]+]], [test_select_cc_param_3];
-; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%r[0-9]+]], [[D]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%r[0-9]+]], [[C]];
-; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]]
-; CHECK: selp.b16 [[R:%rs[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-DAG: ld.param.b16 {{%rs[0-9]+}}, [test_select_cc_param_2];
+; CHECK-DAG: ld.param.b16 {{%rs[0-9]+}}, [test_select_cc_param_3];
+; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}}
+; CHECK-DAG: mov.b64 [[A:%rd[0-9]+]], test_select_cc_param_0;
+; CHECK-DAG: mov.b64 [[B:%rd[0-9]+]], test_select_cc_param_1;
+; CHECK: selp.b64 [[PTR:%rd[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-NEXT: ld.param.b16 [[R:%rs[0-9]+]], {{\[}}[[PTR]]{{\]}};
; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];
; CHECK-NEXT: ret;
define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {
@@ -344,16 +344,15 @@ define half @test_select_cc(half %a, half %b, half %c, half %d) #0 {
}
; CHECK-LABEL: test_select_cc_f32_f16(
-; CHECK-DAG: ld.param.b32 [[A:%r[0-9]+]], [test_select_cc_f32_f16_param_0];
-; CHECK-DAG: ld.param.b32 [[B:%r[0-9]+]], [test_select_cc_f32_f16_param_1];
-; CHECK-DAG: ld.param.b16 [[C:%rs[0-9]+]], [test_select_cc_f32_f16_param_2];
-; CHECK-DAG: ld.param.b16 [[D:%rs[0-9]+]], [test_select_cc_f32_f16_param_3];
-; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]
-; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], [[C]], [[D]]
-; CHECK-NOF16-DAG: cvt.f32.f16 [[DF:%r[0-9]+]], [[D]];
-; CHECK-NOF16-DAG: cvt.f32.f16 [[CF:%r[0-9]+]], [[C]];
-; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], [[CF]], [[DF]]
-; CHECK-NEXT: selp.f32 [[R:%r[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-DAG: ld.param.b16 {{%rs[0-9]+}}, [test_select_cc_f32_f16_param_2];
+; CHECK-DAG: ld.param.b16 {{%rs[0-9]+}}, [test_select_cc_f32_f16_param_3];
+; CHECK-F16-NOFTZ: setp.neu.f16 [[PRED:%p[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK-F16-FTZ: setp.neu.ftz.f16 [[PRED:%p[0-9]+]], %rs{{[0-9]+}}, %rs{{[0-9]+}}
+; CHECK-NOF16: setp.neu.f32 [[PRED:%p[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}}
+; CHECK-DAG: mov.b64 [[A:%rd[0-9]+]], test_select_cc_f32_f16_param_0;
+; CHECK-DAG: mov.b64 [[B:%rd[0-9]+]], test_select_cc_f32_f16_param_1;
+; CHECK: selp.b64 [[PTR:%rd[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-NEXT: ld.param.b32 [[R:%r[0-9]+]], {{\[}}[[PTR]]{{\]}};
; CHECK-NEXT: st.param.b32 [func_retval0], [[R]];
; CHECK-NEXT: ret;
define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 {
@@ -363,13 +362,14 @@ define float @test_select_cc_f32_f16(float %a, float %b, half %c, half %d) #0 {
}
; CHECK-LABEL: test_select_cc_f16_f32(
-; CHECK-DAG: ld.param.b16 [[A:%rs[0-9]+]], [test_select_cc_f16_f32_param_0];
-; CHECK-DAG: ld.param.b32 [[C:%r[0-9]+]], [test_select_cc_f16_f32_param_2];
-; CHECK-DAG: ld.param.b32 [[D:%r[0-9]+]], [test_select_cc_f16_f32_param_3];
-; CHECK-NOFTZ-DAG: setp.neu.f32 [[PRED:%p[0-9]+]], [[C]], [[D]]
-; CHECK-F16-FTZ-DAG: setp.neu.ftz.f32 [[PRED:%p[0-9]+]], [[C]], [[D]]
-; CHECK-DAG: ld.param.b16 [[B:%rs[0-9]+]], [test_select_cc_f16_f32_param_1];
-; CHECK-NEXT: selp.b16 [[R:%rs[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-DAG: ld.param.b32 {{%r[0-9]+}}, [test_select_cc_f16_f32_param_2];
+; CHECK-DAG: ld.param.b32 {{%r[0-9]+}}, [test_select_cc_f16_f32_param_3];
+; CHECK-NOFTZ: setp.neu.f32 [[PRED:%p[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}}
+; CHECK-F16-FTZ: setp.neu.ftz.f32 [[PRED:%p[0-9]+]], %r{{[0-9]+}}, %r{{[0-9]+}}
+; CHECK-DAG: mov.b64 [[A:%rd[0-9]+]], test_select_cc_f16_f32_param_0;
+; CHECK-DAG: mov.b64 [[B:%rd[0-9]+]], test_select_cc_f16_f32_param_1;
+; CHECK: selp.b64 [[PTR:%rd[0-9]+]], [[A]], [[B]], [[PRED]];
+; CHECK-NEXT: ld.param.b16 [[R:%rs[0-9]+]], {{\[}}[[PTR]]{{\]}};
; CHECK-NEXT: st.param.b16 [func_retval0], [[R]];
; CHECK-NEXT: ret;
define half @test_select_cc_f16_f32(half %a, half %b, float %c, float %d) #0 {
@@ -816,8 +816,7 @@ define double @test_fpext_double(half %a) #0 {
; CHECK-LABEL: test_bitcast_halftoi16(
-; CHECK: ld.param.b16 [[AH:%rs[0-9]+]], [test_bitcast_halftoi16_param_0];
-; CHECK: cvt.u32.u16 [[R:%r[0-9]+]], [[AH]]
+; CHECK: ld.param.b16 [[R:%r[0-9]+]], [test_bitcast_halftoi16_param_0];
; CHECK: st.param.b32 [func_retval0], [[R]];
; CHECK: ret;
define i16 @test_bitcast_halftoi16(half %a) #0 {
@@ -1185,3 +1184,9 @@ define <2 x half> @test_neg_f16x2(<2 x half> noundef %arg) #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
+; CHECK-F16-FTZ: {{.*}}
+; CHECK-F16-NOFTZ: {{.*}}
+; CHECK-NOF16: {{.*}}
+; CHECK-NOFTZ: {{.*}}
diff --git a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
index 1b18838c811676..fd2340a50608eb 100644
--- a/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f16x2-instructions.ll
@@ -45,11 +45,9 @@ define half @test_extract_0(<2 x half> %a) #0 {
; CHECK-LABEL: test_extract_0(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_extract_0_param_0];
-; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {%rs1, tmp}, %r1; }
+; CHECK-NEXT: ld.param.b16 %rs1, [test_extract_0_param_0];
; CHECK-NEXT: st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT: ret;
%e = extractelement <2 x half> %a, i32 0
@@ -60,11 +58,9 @@ define half @test_extract_1(<2 x half> %a) #0 {
; CHECK-LABEL: test_extract_1(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<2>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_extract_1_param_0];
-; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r1; }
+; CHECK-NEXT: ld.param.b16 %rs1, [test_extract_1_param_0+2];
; CHECK-NEXT: st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT: ret;
%e = extractelement <2 x half> %a, i32 1
@@ -74,18 +70,18 @@ define half @test_extract_1(<2 x half> %a) #0 {
define half @test_extract_i(<2 x half> %a, i64 %idx) #0 {
; CHECK-LABEL: test_extract_i(
; CHECK: {
-; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<4>;
-; CHECK-NEXT: .reg .b32 %r<2>;
-; CHECK-NEXT: .reg .b64 %rd<2>;
+; CHECK-NEXT: .reg .b16 %rs<2>;
+; CHECK-NEXT: .reg .b64 %rd<7>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b64 %rd1, [test_extract_i_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_extract_i_param_0];
-; CHECK-NEXT: setp.eq.b64 %p1, %rd1, 0;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
-; CHECK-NEXT: st.param.b16 [func_retval0], %rs3;
+; CHECK-NEXT: mov.b64 %rd2, %rd1;
+; CHECK-NEXT: and.b64 %rd3, %rd2, 1;
+; CHECK-NEXT: shl.b64 %rd4, %rd3, 1;
+; CHECK-NEXT: mov.b64 %rd5, test_extract_i_param_0;
+; CHECK-NEXT: add.s64 %rd6, %rd5, %rd4;
+; CHECK-NEXT: ld.param.b16 %rs1, [%rd6];
+; CHECK-NEXT: st.param.b16 [func_retval0], %rs1;
; CHECK-NEXT: ret;
%e = extractelement <2 x half> %a, i64 %idx
ret half %e
@@ -97,8 +93,8 @@ define <2 x half> @test_fadd(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<4>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fadd_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fadd_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fadd_param_1];
; CHECK-F16-NEXT: add.rn.f16x2 %r3, %r1, %r2;
; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-F16-NEXT: ret;
@@ -106,23 +102,21 @@ define <2 x half> @test_fadd(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16-LABEL: test_fadd(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<10>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fadd_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fadd_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: add.rn.f32 %r5, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r5;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs3;
-; CHECK-NOF16-NEXT: add.rn.f32 %r8, %r7, %r6;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r8;
-; CHECK-NOF16-NEXT: mov.b32 %r9, {%rs6, %rs5};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fadd_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fadd_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: add.rn.f32 %r3, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
+; CHECK-NOF16-NEXT: add.rn.f32 %r6, %r5, %r4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r6;
+; CHECK-NOF16-NEXT: mov.b32 %r7, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NOF16-NEXT: ret;
%r = fadd <2 x half> %a, %b
ret <2 x half> %r
@@ -144,19 +138,18 @@ define <2 x half> @test_fadd_imm_0(<2 x half> %a) #0 {
; CHECK-NOF16-LABEL: test_fadd_imm_0(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<6>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fadd_imm_0_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NOF16-NEXT: add.rn.f32 %r3, %r2, 0f40000000;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NOF16-NEXT: add.rn.f32 %r5, %r4, 0f3F800000;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NOF16-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fadd_imm_0_param_0];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NOF16-NEXT: add.rn.f32 %r2, %r1, 0f40000000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs1;
+; CHECK-NOF16-NEXT: add.rn.f32 %r4, %r3, 0f3F800000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r4;
+; CHECK-NOF16-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NOF16-NEXT: ret;
%r = fadd <2 x half> <half 1.0, half 2.0>, %a
ret <2 x half> %r
@@ -177,19 +170,18 @@ define <2 x half> @test_fadd_imm_1(<2 x half> %a) #0 {
; CHECK-NOF16-LABEL: test_fadd_imm_1(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<6>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fadd_imm_1_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NOF16-NEXT: add.rn.f32 %r3, %r2, 0f40000000;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NOF16-NEXT: add.rn.f32 %r5, %r4, 0f3F800000;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NOF16-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fadd_imm_1_param_0];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NOF16-NEXT: add.rn.f32 %r2, %r1, 0f40000000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs1;
+; CHECK-NOF16-NEXT: add.rn.f32 %r4, %r3, 0f3F800000;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r4;
+; CHECK-NOF16-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NOF16-NEXT: ret;
%r = fadd <2 x half> %a, <half 1.0, half 2.0>
ret <2 x half> %r
@@ -201,8 +193,8 @@ define <2 x half> @test_fsub(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<4>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fsub_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fsub_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fsub_param_1];
; CHECK-F16-NEXT: sub.rn.f16x2 %r3, %r1, %r2;
; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-F16-NEXT: ret;
@@ -210,23 +202,21 @@ define <2 x half> @test_fsub(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16-LABEL: test_fsub(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<10>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fsub_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fsub_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: sub.rn.f32 %r5, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r5;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs3;
-; CHECK-NOF16-NEXT: sub.rn.f32 %r8, %r7, %r6;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r8;
-; CHECK-NOF16-NEXT: mov.b32 %r9, {%rs6, %rs5};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fsub_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fsub_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: sub.rn.f32 %r3, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
+; CHECK-NOF16-NEXT: sub.rn.f32 %r6, %r5, %r4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r6;
+; CHECK-NOF16-NEXT: mov.b32 %r7, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NOF16-NEXT: ret;
%r = fsub <2 x half> %a, %b
ret <2 x half> %r
@@ -247,19 +237,18 @@ define <2 x half> @test_fneg(<2 x half> %a) #0 {
; CHECK-NOF16-LABEL: test_fneg(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<6>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fneg_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NOF16-NEXT: sub.rn.f32 %r3, 0f00000000, %r2;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NOF16-NEXT: sub.rn.f32 %r5, 0f00000000, %r4;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NOF16-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fneg_param_0];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NOF16-NEXT: sub.rn.f32 %r2, 0f00000000, %r1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs3, %r2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs1;
+; CHECK-NOF16-NEXT: sub.rn.f32 %r4, 0f00000000, %r3;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs4, %r4;
+; CHECK-NOF16-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NOF16-NEXT: ret;
%r = fsub <2 x half> <half 0.0, half 0.0>, %a
ret <2 x half> %r
@@ -271,8 +260,8 @@ define <2 x half> @test_fmul(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<4>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fmul_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fmul_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fmul_param_1];
; CHECK-F16-NEXT: mul.rn.f16x2 %r3, %r1, %r2;
; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r3;
; CHECK-F16-NEXT: ret;
@@ -280,23 +269,21 @@ define <2 x half> @test_fmul(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16-LABEL: test_fmul(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<10>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fmul_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fmul_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: mul.rn.f32 %r5, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r5;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs3;
-; CHECK-NOF16-NEXT: mul.rn.f32 %r8, %r7, %r6;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r8;
-; CHECK-NOF16-NEXT: mov.b32 %r9, {%rs6, %rs5};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fmul_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fmul_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: mul.rn.f32 %r3, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
+; CHECK-NOF16-NEXT: mul.rn.f32 %r6, %r5, %r4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r6;
+; CHECK-NOF16-NEXT: mov.b32 %r7, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NOF16-NEXT: ret;
%r = fmul <2 x half> %a, %b
ret <2 x half> %r
@@ -306,23 +293,21 @@ define <2 x half> @test_fdiv(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-LABEL: test_fdiv(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<7>;
-; CHECK-NEXT: .reg .b32 %r<10>;
+; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_fdiv_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_fdiv_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NEXT: div.rn.f32 %r5, %r4, %r3;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %r5;
-; CHECK-NEXT: cvt.f32.f16 %r6, %rs1;
-; CHECK-NEXT: cvt.f32.f16 %r7, %rs3;
-; CHECK-NEXT: div.rn.f32 %r8, %r7, %r6;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %r8;
-; CHECK-NEXT: mov.b32 %r9, {%rs6, %rs5};
-; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fdiv_param_0];
+; CHECK-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fdiv_param_1];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NEXT: div.rn.f32 %r3, %r2, %r1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %r3;
+; CHECK-NEXT: cvt.f32.f16 %r4, %rs3;
+; CHECK-NEXT: cvt.f32.f16 %r5, %rs1;
+; CHECK-NEXT: div.rn.f32 %r6, %r5, %r4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %r6;
+; CHECK-NEXT: mov.b32 %r7, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NEXT: ret;
%r = fdiv <2 x half> %a, %b
ret <2 x half> %r
@@ -339,24 +324,22 @@ define <2 x half> @test_frem(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-LABEL: test_frem(
; CHECK-F16: {
; CHECK-F16-NEXT: .reg .b16 %rs<13>;
-; CHECK-F16-NEXT: .reg .b32 %r<9>;
+; CHECK-F16-NEXT: .reg .b32 %r<7>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_frem_param_1];
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_frem_param_0];
-; CHECK-F16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-F16-NEXT: mov.b32 {%rs3, %rs4}, %r2;
-; CHECK-F16-NEXT: cvt.f32.f16 %r3, %rs3;
-; CHECK-F16-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-F16-NEXT: div.rn.f32 %r5, %r4, %r3;
-; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs5, %r5;
+; CHECK-F16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_frem_param_0];
+; CHECK-F16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_frem_param_1];
+; CHECK-F16-NEXT: cvt.f32.f16 %r1, %rs3;
+; CHECK-F16-NEXT: cvt.f32.f16 %r2, %rs1;
+; CHECK-F16-NEXT: div.rn.f32 %r3, %r2, %r1;
+; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs5, %r3;
; CHECK-F16-NEXT: cvt.rzi.f16.f16 %rs6, %rs5;
; CHECK-F16-NEXT: xor.b16 %rs7, %rs6, -32768;
; CHECK-F16-NEXT: fma.rn.f16 %rs8, %rs7, %rs3, %rs1;
-; CHECK-F16-NEXT: cvt.f32.f16 %r6, %rs4;
-; CHECK-F16-NEXT: cvt.f32.f16 %r7, %rs2;
-; CHECK-F16-NEXT: div.rn.f32 %r8, %r7, %r6;
-; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs9, %r8;
+; CHECK-F16-NEXT: cvt.f32.f16 %r4, %rs4;
+; CHECK-F16-NEXT: cvt.f32.f16 %r5, %rs2;
+; CHECK-F16-NEXT: div.rn.f32 %r6, %r5, %r4;
+; CHECK-F16-NEXT: cvt.rn.f16.f32 %rs9, %r6;
; CHECK-F16-NEXT: cvt.rzi.f16.f16 %rs10, %rs9;
; CHECK-F16-NEXT: xor.b16 %rs11, %rs10, -32768;
; CHECK-F16-NEXT: fma.rn.f16 %rs12, %rs11, %rs4, %rs2;
@@ -366,18 +349,16 @@ define <2 x half> @test_frem(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16-LABEL: test_frem(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<13>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<10>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<8>;
; CHECK-NOF16-NEXT: .reg .b64 %rd<9>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_frem_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_frem_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NOF16-NEXT: div.rn.f32 %r5, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_frem_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_frem_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs1;
+; CHECK-NOF16-NEXT: div.rn.f32 %r3, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r3;
; CHECK-NOF16-NEXT: cvt.rzi.f16.f16 %rs6, %rs5;
; CHECK-NOF16-NEXT: xor.b16 %rs7, %rs6, -32768;
; CHECK-NOF16-NEXT: cvt.f64.f16 %rd1, %rs7;
@@ -385,10 +366,10 @@ define <2 x half> @test_frem(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16-NEXT: cvt.f64.f16 %rd3, %rs3;
; CHECK-NOF16-NEXT: fma.rn.f64 %rd4, %rd1, %rd3, %rd2;
; CHECK-NOF16-NEXT: cvt.rn.f16.f64 %rs8, %rd4;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs4;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs2;
-; CHECK-NOF16-NEXT: div.rn.f32 %r8, %r7, %r6;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs9, %r8;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs2;
+; CHECK-NOF16-NEXT: div.rn.f32 %r6, %r5, %r4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs9, %r6;
; CHECK-NOF16-NEXT: cvt.rzi.f16.f16 %rs10, %rs9;
; CHECK-NOF16-NEXT: xor.b16 %rs11, %rs10, -32768;
; CHECK-NOF16-NEXT: cvt.f64.f16 %rd5, %rs11;
@@ -396,8 +377,8 @@ define <2 x half> @test_frem(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16-NEXT: cvt.f64.f16 %rd7, %rs4;
; CHECK-NOF16-NEXT: fma.rn.f64 %rd8, %rd5, %rd7, %rd6;
; CHECK-NOF16-NEXT: cvt.rn.f16.f64 %rs12, %rd8;
-; CHECK-NOF16-NEXT: mov.b32 %r9, {%rs8, %rs12};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NOF16-NEXT: mov.b32 %r7, {%rs8, %rs12};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NOF16-NEXT: ret;
%r = frem afn <2 x half> %a, %b
ret <2 x half> %r
@@ -410,9 +391,9 @@ define void @test_ldst_v2f16(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v2f16_param_1];
; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v2f16_param_0];
; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v2f16_param_1];
; CHECK-NEXT: st.b32 [%rd2], %r1;
; CHECK-NEXT: ret;
%t1 = load <2 x half>, ptr %a
@@ -432,13 +413,13 @@ define void @test_ldst_v3f16(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v3f16_param_1];
; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v3f16_param_0];
-; CHECK-NEXT: ld.b64 %rd3, [%rd1];
-; CHECK-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r1}, %rd3; }
-; CHECK-NEXT: st.b32 [%rd2], %rd3;
+; CHECK-NEXT: ld.b64 %rd2, [%rd1];
+; CHECK-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r1}, %rd2; }
+; CHECK-NEXT: ld.param.b64 %rd3, [test_ldst_v3f16_param_1];
+; CHECK-NEXT: st.b32 [%rd3], %rd2;
; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {%rs1, tmp}, %r1; }
-; CHECK-NEXT: st.b16 [%rd2+4], %rs1;
+; CHECK-NEXT: st.b16 [%rd3+4], %rs1;
; CHECK-NEXT: ret;
%t1 = load <3 x half>, ptr %a
store <3 x half> %t1, ptr %b, align 16
@@ -452,9 +433,9 @@ define void @test_ldst_v4f16(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v4f16_param_1];
; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v4f16_param_0];
; CHECK-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v4f16_param_1];
; CHECK-NEXT: st.v2.b32 [%rd2], {%r1, %r2};
; CHECK-NEXT: ret;
%t1 = load <4 x half>, ptr %a
@@ -469,9 +450,9 @@ define void @test_ldst_v8f16(ptr %a, ptr %b) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v8f16_param_1];
; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v8f16_param_0];
; CHECK-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v8f16_param_1];
; CHECK-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NEXT: ret;
%t1 = load <8 x half>, ptr %a
@@ -487,12 +468,12 @@ define <2 x half> @test_call(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_call_param_1];
; CHECK-NEXT: ld.param.b32 %r1, [test_call_param_0];
; CHECK-NEXT: { // callseq 0, 0
; CHECK-NEXT: .param .align 4 .b8 param0[4];
; CHECK-NEXT: .param .align 4 .b8 param1[4];
; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: ld.param.b32 %r2, [test_call_param_1];
; CHECK-NEXT: st.param.b32 [param1], %r2;
; CHECK-NEXT: st.param.b32 [param0], %r1;
; CHECK-NEXT: call.uni (retval0), test_callee, (param0, param1);
@@ -510,13 +491,13 @@ define <2 x half> @test_call_flipped(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
; CHECK-NEXT: ld.param.b32 %r1, [test_call_flipped_param_0];
; CHECK-NEXT: { // callseq 1, 0
; CHECK-NEXT: .param .align 4 .b8 param0[4];
; CHECK-NEXT: .param .align 4 .b8 param1[4];
; CHECK-NEXT: .param .align 4 .b8 retval0[4];
; CHECK-NEXT: st.param.b32 [param1], %r1;
+; CHECK-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
; CHECK-NEXT: st.param.b32 [param0], %r2;
; CHECK-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-NEXT: ld.param.b32 %r3, [retval0];
@@ -533,13 +514,13 @@ define <2 x half> @test_tailcall_flipped(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NEXT: .reg .b32 %r<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
; CHECK-NEXT: ld.param.b32 %r1, [test_tailcall_flipped_param_0];
; CHECK-NEXT: { // callseq 2, 0
; CHECK-NEXT: .param .align 4 .b8 param0[4];
; CHECK-NEXT: .param .align 4 .b8 param1[4];
; CHECK-NEXT: .param .align 4 .b8 retval0[4];
; CHECK-NEXT: st.param.b32 [param1], %r1;
+; CHECK-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
; CHECK-NEXT: st.param.b32 [param0], %r2;
; CHECK-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-NEXT: ld.param.b32 %r3, [retval0];
@@ -554,17 +535,20 @@ define <2 x half> @test_select(<2 x half> %a, <2 x half> %b, i1 zeroext %c) #0 {
; CHECK-LABEL: test_select(
; CHECK: {
; CHECK-NEXT: .reg .pred %p<2>;
-; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b16 %rs<4>;
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b8 %rs1, [test_select_param_2];
-; CHECK-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NEXT: ld.param.b32 %r2, [test_select_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_select_param_0];
-; CHECK-NEXT: selp.b32 %r3, %r1, %r2, %p1;
-; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: mov.b16 %rs2, %rs1;
+; CHECK-NEXT: and.b16 %rs3, %rs2, 1;
+; CHECK-NEXT: setp.ne.b16 %p1, %rs3, 0;
+; CHECK-NEXT: mov.b64 %rd1, test_select_param_1;
+; CHECK-NEXT: mov.b64 %rd2, test_select_param_0;
+; CHECK-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
+; CHECK-NEXT: ld.param.b32 %r1, [%rd3];
+; CHECK-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NEXT: ret;
%r = select i1 %c, <2 x half> %a, <2 x half> %b
ret <2 x half> %r
@@ -575,18 +559,16 @@ define <2 x half> @test_select_cc(<2 x half> %a, <2 x half> %b, <2 x half> %c, <
; CHECK-F16: {
; CHECK-F16-NEXT: .reg .pred %p<3>;
; CHECK-F16-NEXT: .reg .b16 %rs<7>;
-; CHECK-F16-NEXT: .reg .b32 %r<5>;
+; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r4, [test_select_cc_param_3];
-; CHECK-F16-NEXT: ld.param.b32 %r3, [test_select_cc_param_2];
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
-; CHECK-F16-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
-; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r3, %r4;
-; CHECK-F16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-F16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-F16-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
-; CHECK-F16-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; CHECK-F16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_select_cc_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r1, [test_select_cc_param_2];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_select_cc_param_3];
+; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r1, %r2;
+; CHECK-F16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_select_cc_param_1];
+; CHECK-F16-NEXT: selp.b16 %rs5, %rs2, %rs4, %p2;
+; CHECK-F16-NEXT: selp.b16 %rs6, %rs1, %rs3, %p1;
; CHECK-F16-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; CHECK-F16-NEXT: ret;
;
@@ -594,25 +576,21 @@ define <2 x half> @test_select_cc(<2 x half> %a, <2 x half> %b, <2 x half> %c, <
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<11>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<9>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r4, [test_select_cc_param_3];
-; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_select_cc_param_2];
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r4;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %r6, %r5;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r8, %rs4;
-; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %r8, %r7;
-; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; CHECK-NOF16-NEXT: selp.b16 %rs9, %rs8, %rs6, %p2;
-; CHECK-NOF16-NEXT: selp.b16 %rs10, %rs7, %rs5, %p1;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_select_cc_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_select_cc_param_3];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs3;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [test_select_cc_param_2];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs5;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs6;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %r4, %r3;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs7, %rs8}, [test_select_cc_param_1];
+; CHECK-NOF16-NEXT: selp.b16 %rs9, %rs2, %rs8, %p2;
+; CHECK-NOF16-NEXT: selp.b16 %rs10, %rs1, %rs7, %p1;
; CHECK-NOF16-NEXT: st.param.v2.b16 [func_retval0], {%rs10, %rs9};
; CHECK-NOF16-NEXT: ret;
%cc = fcmp une <2 x half> %c, %d
@@ -627,13 +605,13 @@ define <2 x float> @test_select_cc_f32_f16(<2 x float> %a, <2 x float> %b,
; CHECK-F16-NEXT: .reg .b32 %r<9>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f32_f16_param_1];
; CHECK-F16-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_f32_f16_param_0];
-; CHECK-F16-NEXT: ld.param.b32 %r6, [test_select_cc_f32_f16_param_3];
-; CHECK-F16-NEXT: ld.param.b32 %r5, [test_select_cc_f32_f16_param_2];
-; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r5, %r6;
-; CHECK-F16-NEXT: selp.f32 %r7, %r2, %r4, %p2;
-; CHECK-F16-NEXT: selp.f32 %r8, %r1, %r3, %p1;
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_select_cc_f32_f16_param_2];
+; CHECK-F16-NEXT: ld.param.b32 %r4, [test_select_cc_f32_f16_param_3];
+; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r3, %r4;
+; CHECK-F16-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_select_cc_f32_f16_param_1];
+; CHECK-F16-NEXT: selp.f32 %r7, %r2, %r6, %p2;
+; CHECK-F16-NEXT: selp.f32 %r8, %r1, %r5, %p1;
; CHECK-F16-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-F16-NEXT: ret;
;
@@ -641,24 +619,22 @@ define <2 x float> @test_select_cc_f32_f16(<2 x float> %a, <2 x float> %b,
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<5>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<13>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<11>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f32_f16_param_1];
; CHECK-NOF16-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_f32_f16_param_0];
-; CHECK-NOF16-NEXT: ld.param.b32 %r6, [test_select_cc_f32_f16_param_3];
-; CHECK-NOF16-NEXT: ld.param.b32 %r5, [test_select_cc_f32_f16_param_2];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r6;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs1;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r5;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r8, %rs3;
-; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %r8, %r7;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r9, %rs2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r10, %rs4;
-; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %r10, %r9;
-; CHECK-NOF16-NEXT: selp.f32 %r11, %r2, %r4, %p2;
-; CHECK-NOF16-NEXT: selp.f32 %r12, %r1, %r3, %p1;
-; CHECK-NOF16-NEXT: st.param.v2.b32 [func_retval0], {%r12, %r11};
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_select_cc_f32_f16_param_3];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs1;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_select_cc_f32_f16_param_2];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs3;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %r4, %r3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs2;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs4;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b32 {%r7, %r8}, [test_select_cc_f32_f16_param_1];
+; CHECK-NOF16-NEXT: selp.f32 %r9, %r2, %r8, %p2;
+; CHECK-NOF16-NEXT: selp.f32 %r10, %r1, %r7, %p1;
+; CHECK-NOF16-NEXT: st.param.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-NOF16-NEXT: ret;
<2 x half> %c, <2 x half> %d) #0 {
%cc = fcmp une <2 x half> %c, %d
@@ -671,19 +647,17 @@ define <2 x half> @test_select_cc_f16_f32(<2 x half> %a, <2 x half> %b,
; CHECK: {
; CHECK-NEXT: .reg .pred %p<3>;
; CHECK-NEXT: .reg .b16 %rs<7>;
-; CHECK-NEXT: .reg .b32 %r<7>;
+; CHECK-NEXT: .reg .b32 %r<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_select_cc_f16_f32_param_3];
-; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f16_f32_param_2];
-; CHECK-NEXT: ld.param.b32 %r2, [test_select_cc_f16_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_select_cc_f16_f32_param_0];
-; CHECK-NEXT: setp.neu.f32 %p1, %r3, %r5;
-; CHECK-NEXT: setp.neu.f32 %p2, %r4, %r6;
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
-; CHECK-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_select_cc_f16_f32_param_0];
+; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_f16_f32_param_2];
+; CHECK-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f16_f32_param_3];
+; CHECK-NEXT: setp.neu.f32 %p1, %r1, %r3;
+; CHECK-NEXT: setp.neu.f32 %p2, %r2, %r4;
+; CHECK-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_select_cc_f16_f32_param_1];
+; CHECK-NEXT: selp.b16 %rs5, %rs2, %rs4, %p2;
+; CHECK-NEXT: selp.b16 %rs6, %rs1, %rs3, %p1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; CHECK-NEXT: ret;
<2 x float> %c, <2 x float> %d) #0 {
@@ -700,8 +674,8 @@ define <2 x i1> @test_fcmp_une(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_une_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_une_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_une_param_1];
; CHECK-F16-NEXT: setp.neu.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -713,19 +687,17 @@ define <2 x i1> @test_fcmp_une(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_une_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_une_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_une_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_une_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.neu.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -743,8 +715,8 @@ define <2 x i1> @test_fcmp_ueq(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ueq_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ueq_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ueq_param_1];
; CHECK-F16-NEXT: setp.equ.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -756,19 +728,17 @@ define <2 x i1> @test_fcmp_ueq(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ueq_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ueq_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.equ.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.equ.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_ueq_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_ueq_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.equ.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.equ.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -786,8 +756,8 @@ define <2 x i1> @test_fcmp_ugt(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ugt_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ugt_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ugt_param_1];
; CHECK-F16-NEXT: setp.gtu.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -799,19 +769,17 @@ define <2 x i1> @test_fcmp_ugt(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ugt_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ugt_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.gtu.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.gtu.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_ugt_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_ugt_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.gtu.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.gtu.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -829,8 +797,8 @@ define <2 x i1> @test_fcmp_uge(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_uge_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_uge_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_uge_param_1];
; CHECK-F16-NEXT: setp.geu.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -842,19 +810,17 @@ define <2 x i1> @test_fcmp_uge(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_uge_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_uge_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.geu.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.geu.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_uge_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_uge_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.geu.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.geu.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -872,8 +838,8 @@ define <2 x i1> @test_fcmp_ult(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ult_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ult_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ult_param_1];
; CHECK-F16-NEXT: setp.ltu.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -885,19 +851,17 @@ define <2 x i1> @test_fcmp_ult(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ult_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ult_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.ltu.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.ltu.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_ult_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_ult_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.ltu.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.ltu.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -915,8 +879,8 @@ define <2 x i1> @test_fcmp_ule(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ule_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ule_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ule_param_1];
; CHECK-F16-NEXT: setp.leu.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -928,19 +892,17 @@ define <2 x i1> @test_fcmp_ule(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ule_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ule_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.leu.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.leu.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_ule_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_ule_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.leu.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.leu.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -959,8 +921,8 @@ define <2 x i1> @test_fcmp_uno(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_uno_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_uno_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_uno_param_1];
; CHECK-F16-NEXT: setp.nan.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -972,19 +934,17 @@ define <2 x i1> @test_fcmp_uno(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_uno_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_uno_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_uno_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_uno_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.nan.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1002,8 +962,8 @@ define <2 x i1> @test_fcmp_one(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_one_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_one_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_one_param_1];
; CHECK-F16-NEXT: setp.ne.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -1015,19 +975,17 @@ define <2 x i1> @test_fcmp_one(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_one_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_one_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.ne.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.ne.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_one_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_one_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.ne.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.ne.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1045,8 +1003,8 @@ define <2 x i1> @test_fcmp_oeq(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_oeq_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_oeq_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_oeq_param_1];
; CHECK-F16-NEXT: setp.eq.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -1058,19 +1016,17 @@ define <2 x i1> @test_fcmp_oeq(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_oeq_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_oeq_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.eq.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_oeq_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_oeq_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.eq.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1088,8 +1044,8 @@ define <2 x i1> @test_fcmp_ogt(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ogt_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ogt_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ogt_param_1];
; CHECK-F16-NEXT: setp.gt.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -1101,19 +1057,17 @@ define <2 x i1> @test_fcmp_ogt(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ogt_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ogt_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.gt.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.gt.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_ogt_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_ogt_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.gt.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.gt.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1131,8 +1085,8 @@ define <2 x i1> @test_fcmp_oge(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_oge_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_oge_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_oge_param_1];
; CHECK-F16-NEXT: setp.ge.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -1144,19 +1098,17 @@ define <2 x i1> @test_fcmp_oge(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_oge_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_oge_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.ge.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.ge.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_oge_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_oge_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.ge.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.ge.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1174,8 +1126,8 @@ define <2 x i1> @test_fcmp_olt(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_olt_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_olt_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_olt_param_1];
; CHECK-F16-NEXT: setp.lt.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -1187,19 +1139,17 @@ define <2 x i1> @test_fcmp_olt(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_olt_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_olt_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.lt.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.lt.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_olt_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_olt_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.lt.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.lt.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1217,8 +1167,8 @@ define <2 x i1> @test_fcmp_ole(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ole_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ole_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ole_param_1];
; CHECK-F16-NEXT: setp.le.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -1230,19 +1180,17 @@ define <2 x i1> @test_fcmp_ole(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ole_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ole_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.le.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.le.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_ole_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_ole_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.le.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.le.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1260,8 +1208,8 @@ define <2 x i1> @test_fcmp_ord(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<3>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ord_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fcmp_ord_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fcmp_ord_param_1];
; CHECK-F16-NEXT: setp.num.f16x2 %p1|%p2, %r1, %r2;
; CHECK-F16-NEXT: selp.b16 %rs1, -1, 0, %p1;
; CHECK-F16-NEXT: st.param.b8 [func_retval0], %rs1;
@@ -1273,19 +1221,17 @@ define <2 x i1> @test_fcmp_ord(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .pred %p<3>;
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fcmp_ord_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fcmp_ord_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NOF16-NEXT: setp.num.f32 %p1, %r4, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
-; CHECK-NOF16-NEXT: setp.num.f32 %p2, %r6, %r5;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fcmp_ord_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fcmp_ord_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NOF16-NEXT: setp.num.f32 %p1, %r2, %r1;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs3;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs1;
+; CHECK-NOF16-NEXT: setp.num.f32 %p2, %r4, %r3;
; CHECK-NOF16-NEXT: selp.b16 %rs5, -1, 0, %p2;
; CHECK-NOF16-NEXT: st.param.b8 [func_retval0], %rs5;
; CHECK-NOF16-NEXT: selp.b16 %rs6, -1, 0, %p1;
@@ -1299,14 +1245,13 @@ define <2 x i32> @test_fptosi_i32(<2 x half> %a) #0 {
; CHECK-LABEL: test_fptosi_i32(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fptosi_i32_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.rzi.s32.f16 %r2, %rs2;
-; CHECK-NEXT: cvt.rzi.s32.f16 %r3, %rs1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptosi_i32_param_0];
+; CHECK-NEXT: cvt.rzi.s32.f16 %r1, %rs2;
+; CHECK-NEXT: cvt.rzi.s32.f16 %r2, %rs1;
+; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NEXT: ret;
%r = fptosi <2 x half> %a to <2 x i32>
ret <2 x i32> %r
@@ -1316,12 +1261,10 @@ define <2 x i64> @test_fptosi_i64(<2 x half> %a) #0 {
; CHECK-LABEL: test_fptosi_i64(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fptosi_i64_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptosi_i64_param_0];
; CHECK-NEXT: cvt.rzi.s64.f16 %rd1, %rs2;
; CHECK-NEXT: cvt.rzi.s64.f16 %rd2, %rs1;
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd2, %rd1};
@@ -1334,14 +1277,13 @@ define <2 x i32> @test_fptoui_2xi32(<2 x half> %a) #0 {
; CHECK-LABEL: test_fptoui_2xi32(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fptoui_2xi32_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.rzi.u32.f16 %r2, %rs2;
-; CHECK-NEXT: cvt.rzi.u32.f16 %r3, %rs1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptoui_2xi32_param_0];
+; CHECK-NEXT: cvt.rzi.u32.f16 %r1, %rs2;
+; CHECK-NEXT: cvt.rzi.u32.f16 %r2, %rs1;
+; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NEXT: ret;
%r = fptoui <2 x half> %a to <2 x i32>
ret <2 x i32> %r
@@ -1351,12 +1293,10 @@ define <2 x i64> @test_fptoui_2xi64(<2 x half> %a) #0 {
; CHECK-LABEL: test_fptoui_2xi64(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fptoui_2xi64_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptoui_2xi64_param_0];
; CHECK-NEXT: cvt.rzi.u64.f16 %rd1, %rs2;
; CHECK-NEXT: cvt.rzi.u64.f16 %rd2, %rs1;
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd2, %rd1};
@@ -1438,35 +1378,34 @@ define <2 x half> @test_uitofp_2xi32_fadd(<2 x i32> %a, <2 x half> %b) #0 {
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
; CHECK-F16-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_uitofp_2xi32_fadd_param_0];
-; CHECK-F16-NEXT: ld.param.b32 %r3, [test_uitofp_2xi32_fadd_param_1];
; CHECK-F16-NEXT: cvt.rn.f16.u32 %rs1, %r2;
; CHECK-F16-NEXT: cvt.rn.f16.u32 %rs2, %r1;
-; CHECK-F16-NEXT: mov.b32 %r4, {%rs2, %rs1};
-; CHECK-F16-NEXT: add.rn.f16x2 %r5, %r3, %r4;
+; CHECK-F16-NEXT: mov.b32 %r3, {%rs2, %rs1};
+; CHECK-F16-NEXT: ld.param.b32 %r4, [test_uitofp_2xi32_fadd_param_1];
+; CHECK-F16-NEXT: add.rn.f16x2 %r5, %r4, %r3;
; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-F16-NEXT: ret;
;
; CHECK-NOF16-LABEL: test_uitofp_2xi32_fadd(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<11>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<10>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_uitofp_2xi32_fadd_param_0];
-; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_uitofp_2xi32_fadd_param_1];
; CHECK-NOF16-NEXT: cvt.rn.f16.u32 %rs1, %r1;
; CHECK-NOF16-NEXT: cvt.rn.f16.u32 %rs2, %r2;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_uitofp_2xi32_fadd_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs4;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs4;
-; CHECK-NOF16-NEXT: add.rn.f32 %r6, %r5, %r4;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r6;
+; CHECK-NOF16-NEXT: add.rn.f32 %r5, %r3, %r4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r5;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r8, %rs3;
-; CHECK-NOF16-NEXT: add.rn.f32 %r9, %r8, %r7;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r9;
-; CHECK-NOF16-NEXT: mov.b32 %r10, {%rs6, %rs5};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-NOF16-NEXT: add.rn.f32 %r8, %r6, %r7;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r8;
+; CHECK-NOF16-NEXT: mov.b32 %r9, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r9;
; CHECK-NOF16-NEXT: ret;
%c = uitofp <2 x i32> %a to <2 x half>
%r = fadd <2 x half> %b, %c
@@ -1481,35 +1420,34 @@ define <2 x half> @test_sitofp_2xi32_fadd(<2 x i32> %a, <2 x half> %b) #0 {
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
; CHECK-F16-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_sitofp_2xi32_fadd_param_0];
-; CHECK-F16-NEXT: ld.param.b32 %r3, [test_sitofp_2xi32_fadd_param_1];
; CHECK-F16-NEXT: cvt.rn.f16.s32 %rs1, %r2;
; CHECK-F16-NEXT: cvt.rn.f16.s32 %rs2, %r1;
-; CHECK-F16-NEXT: mov.b32 %r4, {%rs2, %rs1};
-; CHECK-F16-NEXT: add.rn.f16x2 %r5, %r3, %r4;
+; CHECK-F16-NEXT: mov.b32 %r3, {%rs2, %rs1};
+; CHECK-F16-NEXT: ld.param.b32 %r4, [test_sitofp_2xi32_fadd_param_1];
+; CHECK-F16-NEXT: add.rn.f16x2 %r5, %r4, %r3;
; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-F16-NEXT: ret;
;
; CHECK-NOF16-LABEL: test_sitofp_2xi32_fadd(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<7>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<11>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<10>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
; CHECK-NOF16-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_sitofp_2xi32_fadd_param_0];
-; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_sitofp_2xi32_fadd_param_1];
; CHECK-NOF16-NEXT: cvt.rn.f16.s32 %rs1, %r1;
; CHECK-NOF16-NEXT: cvt.rn.f16.s32 %rs2, %r2;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_sitofp_2xi32_fadd_param_1];
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r3, %rs4;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r4, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r5, %rs4;
-; CHECK-NOF16-NEXT: add.rn.f32 %r6, %r5, %r4;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r6;
+; CHECK-NOF16-NEXT: add.rn.f32 %r5, %r3, %r4;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs5, %r5;
+; CHECK-NOF16-NEXT: cvt.f32.f16 %r6, %rs3;
; CHECK-NOF16-NEXT: cvt.f32.f16 %r7, %rs1;
-; CHECK-NOF16-NEXT: cvt.f32.f16 %r8, %rs3;
-; CHECK-NOF16-NEXT: add.rn.f32 %r9, %r8, %r7;
-; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r9;
-; CHECK-NOF16-NEXT: mov.b32 %r10, {%rs6, %rs5};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r10;
+; CHECK-NOF16-NEXT: add.rn.f32 %r8, %r6, %r7;
+; CHECK-NOF16-NEXT: cvt.rn.f16.f32 %rs6, %r8;
+; CHECK-NOF16-NEXT: mov.b32 %r9, {%rs6, %rs5};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r9;
; CHECK-NOF16-NEXT: ret;
%c = sitofp <2 x i32> %a to <2 x half>
%r = fadd <2 x half> %b, %c
@@ -1555,14 +1493,13 @@ define <2 x float> @test_fpext_2xfloat(<2 x half> %a) #0 {
; CHECK-LABEL: test_fpext_2xfloat(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-NEXT: .reg .b32 %r<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fpext_2xfloat_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NEXT: cvt.f32.f16 %r3, %rs1;
-; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fpext_2xfloat_param_0];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NEXT: cvt.f32.f16 %r2, %rs1;
+; CHECK-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NEXT: ret;
%r = fpext <2 x half> %a to <2 x float>
ret <2 x float> %r
@@ -1572,12 +1509,10 @@ define <2 x double> @test_fpext_2xdouble(<2 x half> %a) #0 {
; CHECK-LABEL: test_fpext_2xdouble(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_fpext_2xdouble_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fpext_2xdouble_param_0];
; CHECK-NEXT: cvt.f64.f16 %rd1, %rs2;
; CHECK-NEXT: cvt.f64.f16 %rd2, %rs1;
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd2, %rd1};
@@ -1667,19 +1602,18 @@ define <2 x half> @test_sqrt(<2 x half> %a) #0 {
; CHECK-LABEL: test_sqrt(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<7>;
+; CHECK-NEXT: .reg .b32 %r<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_sqrt_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NEXT: sqrt.rn.f32 %r3, %r2;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NEXT: sqrt.rn.f32 %r5, %r4;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_sqrt_param_0];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NEXT: sqrt.rn.f32 %r2, %r1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r2;
+; CHECK-NEXT: cvt.f32.f16 %r3, %rs1;
+; CHECK-NEXT: sqrt.rn.f32 %r4, %r3;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r4;
+; CHECK-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.sqrt.f16(<2 x half> %a)
ret <2 x half> %r
@@ -1696,19 +1630,18 @@ define <2 x half> @test_sin(<2 x half> %a) #0 {
; CHECK-LABEL: test_sin(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<7>;
+; CHECK-NEXT: .reg .b32 %r<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_sin_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NEXT: sin.approx.f32 %r3, %r2;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NEXT: sin.approx.f32 %r5, %r4;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_sin_param_0];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NEXT: sin.approx.f32 %r2, %r1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r2;
+; CHECK-NEXT: cvt.f32.f16 %r3, %rs1;
+; CHECK-NEXT: sin.approx.f32 %r4, %r3;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r4;
+; CHECK-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NEXT: ret;
%r = call afn <2 x half> @llvm.sin.f16(<2 x half> %a)
ret <2 x half> %r
@@ -1718,19 +1651,18 @@ define <2 x half> @test_cos(<2 x half> %a) #0 {
; CHECK-LABEL: test_cos(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<7>;
+; CHECK-NEXT: .reg .b32 %r<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_cos_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NEXT: cos.approx.f32 %r3, %r2;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r3;
-; CHECK-NEXT: cvt.f32.f16 %r4, %rs1;
-; CHECK-NEXT: cos.approx.f32 %r5, %r4;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r5;
-; CHECK-NEXT: mov.b32 %r6, {%rs4, %rs3};
-; CHECK-NEXT: st.param.b32 [func_retval0], %r6;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_cos_param_0];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NEXT: cos.approx.f32 %r2, %r1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r2;
+; CHECK-NEXT: cvt.f32.f16 %r3, %rs1;
+; CHECK-NEXT: cos.approx.f32 %r4, %r3;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r4;
+; CHECK-NEXT: mov.b32 %r5, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NEXT: ret;
%r = call afn <2 x half> @llvm.cos.f16(<2 x half> %a)
ret <2 x half> %r
@@ -1785,9 +1717,9 @@ define <2 x half> @test_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
; CHECK-F16-NEXT: .reg .b32 %r<5>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r3, [test_fma_param_2];
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fma_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fma_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fma_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_fma_param_2];
; CHECK-F16-NEXT: fma.rn.f16x2 %r4, %r1, %r2, %r3;
; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-F16-NEXT: ret;
@@ -1795,28 +1727,25 @@ define <2 x half> @test_fma(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0 {
; CHECK-NOF16-LABEL: test_fma(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<9>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<2>;
; CHECK-NOF16-NEXT: .reg .b64 %rd<9>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_fma_param_2];
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fma_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fma_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r3;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd1, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r2;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd2, %rs4;
-; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd3, %rs6;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fma_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fma_param_2];
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd1, %rs4;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [test_fma_param_1];
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd2, %rs6;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd3, %rs2;
; CHECK-NOF16-NEXT: fma.rn.f64 %rd4, %rd3, %rd2, %rd1;
; CHECK-NOF16-NEXT: cvt.rn.f16.f64 %rs7, %rd4;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd6, %rs3;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd7, %rs5;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd5, %rs3;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd6, %rs5;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd7, %rs1;
; CHECK-NOF16-NEXT: fma.rn.f64 %rd8, %rd7, %rd6, %rd5;
; CHECK-NOF16-NEXT: cvt.rn.f16.f64 %rs8, %rd8;
-; CHECK-NOF16-NEXT: mov.b32 %r4, {%rs8, %rs7};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: mov.b32 %r1, {%rs8, %rs7};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NOF16-NEXT: ret;
%r = call <2 x half> @llvm.fma.f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
ret <2 x half> %r
@@ -1840,23 +1769,21 @@ define <2 x half> @test_minnum(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-LABEL: test_minnum(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<7>;
-; CHECK-NEXT: .reg .b32 %r<10>;
+; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_minnum_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_minnum_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NEXT: min.f32 %r5, %r4, %r3;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %r5;
-; CHECK-NEXT: cvt.f32.f16 %r6, %rs1;
-; CHECK-NEXT: cvt.f32.f16 %r7, %rs3;
-; CHECK-NEXT: min.f32 %r8, %r7, %r6;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %r8;
-; CHECK-NEXT: mov.b32 %r9, {%rs6, %rs5};
-; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_minnum_param_0];
+; CHECK-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_minnum_param_1];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NEXT: min.f32 %r3, %r2, %r1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %r3;
+; CHECK-NEXT: cvt.f32.f16 %r4, %rs3;
+; CHECK-NEXT: cvt.f32.f16 %r5, %rs1;
+; CHECK-NEXT: min.f32 %r6, %r5, %r4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %r6;
+; CHECK-NEXT: mov.b32 %r7, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.minnum.f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %r
@@ -1866,23 +1793,21 @@ define <2 x half> @test_maxnum(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-LABEL: test_maxnum(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<7>;
-; CHECK-NEXT: .reg .b32 %r<10>;
+; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_maxnum_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_maxnum_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-NEXT: cvt.f32.f16 %r3, %rs2;
-; CHECK-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r4, %rs4;
-; CHECK-NEXT: max.f32 %r5, %r4, %r3;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %r5;
-; CHECK-NEXT: cvt.f32.f16 %r6, %rs1;
-; CHECK-NEXT: cvt.f32.f16 %r7, %rs3;
-; CHECK-NEXT: max.f32 %r8, %r7, %r6;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %r8;
-; CHECK-NEXT: mov.b32 %r9, {%rs6, %rs5};
-; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_maxnum_param_0];
+; CHECK-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_maxnum_param_1];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs4;
+; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
+; CHECK-NEXT: max.f32 %r3, %r2, %r1;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs5, %r3;
+; CHECK-NEXT: cvt.f32.f16 %r4, %rs3;
+; CHECK-NEXT: cvt.f32.f16 %r5, %rs1;
+; CHECK-NEXT: max.f32 %r6, %r5, %r4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs6, %r6;
+; CHECK-NEXT: mov.b32 %r7, {%rs6, %rs5};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.maxnum.f16(<2 x half> %a, <2 x half> %b)
ret <2 x half> %r
@@ -1894,11 +1819,11 @@ define <2 x half> @test_copysign(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NEXT: .reg .b32 %r<6>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_copysign_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_param_0];
-; CHECK-NEXT: and.b32 %r3, %r2, -2147450880;
-; CHECK-NEXT: and.b32 %r4, %r1, 2147450879;
-; CHECK-NEXT: or.b32 %r5, %r4, %r3;
+; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_param_1];
+; CHECK-NEXT: and.b32 %r2, %r1, -2147450880;
+; CHECK-NEXT: ld.param.b32 %r3, [test_copysign_param_0];
+; CHECK-NEXT: and.b32 %r4, %r3, 2147450879;
+; CHECK-NEXT: or.b32 %r5, %r4, %r2;
; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.copysign.f16(<2 x half> %a, <2 x half> %b)
@@ -1912,14 +1837,14 @@ define <2 x half> @test_copysign_f32(<2 x half> %a, <2 x float> %b) #0 {
; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b32 {%r2, %r3}, [test_copysign_f32_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_f32_param_0];
-; CHECK-NEXT: cvt.rn.f16.f32 %rs1, %r3;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs2, %r2;
-; CHECK-NEXT: mov.b32 %r4, {%rs2, %rs1};
-; CHECK-NEXT: and.b32 %r5, %r4, -2147450880;
-; CHECK-NEXT: and.b32 %r6, %r1, 2147450879;
-; CHECK-NEXT: or.b32 %r7, %r6, %r5;
+; CHECK-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_copysign_f32_param_1];
+; CHECK-NEXT: cvt.rn.f16.f32 %rs1, %r2;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs2, %r1;
+; CHECK-NEXT: mov.b32 %r3, {%rs2, %rs1};
+; CHECK-NEXT: and.b32 %r4, %r3, -2147450880;
+; CHECK-NEXT: ld.param.b32 %r5, [test_copysign_f32_param_0];
+; CHECK-NEXT: and.b32 %r6, %r5, 2147450879;
+; CHECK-NEXT: or.b32 %r7, %r6, %r4;
; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
; CHECK-NEXT: ret;
%tb = fptrunc <2 x float> %b to <2 x half>
@@ -1936,13 +1861,13 @@ define <2 x half> @test_copysign_f64(<2 x half> %a, <2 x double> %b) #0 {
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_copysign_f64_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_f64_param_0];
; CHECK-NEXT: cvt.rn.f16.f64 %rs1, %rd2;
; CHECK-NEXT: cvt.rn.f16.f64 %rs2, %rd1;
-; CHECK-NEXT: mov.b32 %r2, {%rs2, %rs1};
-; CHECK-NEXT: and.b32 %r3, %r2, -2147450880;
-; CHECK-NEXT: and.b32 %r4, %r1, 2147450879;
-; CHECK-NEXT: or.b32 %r5, %r4, %r3;
+; CHECK-NEXT: mov.b32 %r1, {%rs2, %rs1};
+; CHECK-NEXT: and.b32 %r2, %r1, -2147450880;
+; CHECK-NEXT: ld.param.b32 %r3, [test_copysign_f64_param_0];
+; CHECK-NEXT: and.b32 %r4, %r3, 2147450879;
+; CHECK-NEXT: or.b32 %r5, %r4, %r2;
; CHECK-NEXT: st.param.b32 [func_retval0], %r5;
; CHECK-NEXT: ret;
%tb = fptrunc <2 x double> %b to <2 x half>
@@ -1957,11 +1882,11 @@ define <2 x float> @test_copysign_extended(<2 x half> %a, <2 x half> %b) #0 {
; CHECK-NEXT: .reg .b32 %r<8>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r2, [test_copysign_extended_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_extended_param_0];
-; CHECK-NEXT: and.b32 %r3, %r2, -2147450880;
-; CHECK-NEXT: and.b32 %r4, %r1, 2147450879;
-; CHECK-NEXT: or.b32 %r5, %r4, %r3;
+; CHECK-NEXT: ld.param.b32 %r1, [test_copysign_extended_param_1];
+; CHECK-NEXT: and.b32 %r2, %r1, -2147450880;
+; CHECK-NEXT: ld.param.b32 %r3, [test_copysign_extended_param_0];
+; CHECK-NEXT: and.b32 %r4, %r3, 2147450879;
+; CHECK-NEXT: or.b32 %r5, %r4, %r2;
; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r5;
; CHECK-NEXT: cvt.f32.f16 %r6, %rs2;
; CHECK-NEXT: cvt.f32.f16 %r7, %rs1;
@@ -1976,11 +1901,9 @@ define <2 x half> @test_floor(<2 x half> %a) #0 {
; CHECK-LABEL: test_floor(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_floor_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_floor_param_0];
; CHECK-NEXT: cvt.rmi.f16.f16 %rs3, %rs2;
; CHECK-NEXT: cvt.rmi.f16.f16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -1993,11 +1916,9 @@ define <2 x half> @test_ceil(<2 x half> %a) #0 {
; CHECK-LABEL: test_ceil(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_ceil_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_ceil_param_0];
; CHECK-NEXT: cvt.rpi.f16.f16 %rs3, %rs2;
; CHECK-NEXT: cvt.rpi.f16.f16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -2010,11 +1931,9 @@ define <2 x half> @test_trunc(<2 x half> %a) #0 {
; CHECK-LABEL: test_trunc(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_trunc_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_trunc_param_0];
; CHECK-NEXT: cvt.rzi.f16.f16 %rs3, %rs2;
; CHECK-NEXT: cvt.rzi.f16.f16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -2027,11 +1946,9 @@ define <2 x half> @test_rint(<2 x half> %a) #0 {
; CHECK-LABEL: test_rint(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_rint_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_rint_param_0];
; CHECK-NEXT: cvt.rni.f16.f16 %rs3, %rs2;
; CHECK-NEXT: cvt.rni.f16.f16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -2044,11 +1961,9 @@ define <2 x half> @test_nearbyint(<2 x half> %a) #0 {
; CHECK-LABEL: test_nearbyint(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_nearbyint_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_nearbyint_param_0];
; CHECK-NEXT: cvt.rni.f16.f16 %rs3, %rs2;
; CHECK-NEXT: cvt.rni.f16.f16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -2061,11 +1976,9 @@ define <2 x half> @test_roundeven(<2 x half> %a) #0 {
; CHECK-LABEL: test_roundeven(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_roundeven_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_roundeven_param_0];
; CHECK-NEXT: cvt.rni.f16.f16 %rs3, %rs2;
; CHECK-NEXT: cvt.rni.f16.f16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -2080,37 +1993,36 @@ define <2 x half> @test_round(<2 x half> %a) #0 {
; CHECK: {
; CHECK-NEXT: .reg .pred %p<5>;
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<21>;
+; CHECK-NEXT: .reg .b32 %r<20>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_round_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NEXT: cvt.f32.f16 %r2, %rs2;
-; CHECK-NEXT: and.b32 %r3, %r2, -2147483648;
-; CHECK-NEXT: or.b32 %r4, %r3, 1056964608;
-; CHECK-NEXT: add.rn.f32 %r5, %r2, %r4;
-; CHECK-NEXT: cvt.rzi.f32.f32 %r6, %r5;
-; CHECK-NEXT: abs.f32 %r7, %r2;
-; CHECK-NEXT: setp.gt.f32 %p1, %r7, 0f4B000000;
-; CHECK-NEXT: selp.f32 %r8, %r2, %r6, %p1;
-; CHECK-NEXT: cvt.rzi.f32.f32 %r9, %r2;
-; CHECK-NEXT: setp.lt.f32 %p2, %r7, 0f3F000000;
-; CHECK-NEXT: selp.f32 %r10, %r9, %r8, %p2;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r10;
-; CHECK-NEXT: cvt.f32.f16 %r11, %rs1;
-; CHECK-NEXT: and.b32 %r12, %r11, -2147483648;
-; CHECK-NEXT: or.b32 %r13, %r12, 1056964608;
-; CHECK-NEXT: add.rn.f32 %r14, %r11, %r13;
-; CHECK-NEXT: cvt.rzi.f32.f32 %r15, %r14;
-; CHECK-NEXT: abs.f32 %r16, %r11;
-; CHECK-NEXT: setp.gt.f32 %p3, %r16, 0f4B000000;
-; CHECK-NEXT: selp.f32 %r17, %r11, %r15, %p3;
-; CHECK-NEXT: cvt.rzi.f32.f32 %r18, %r11;
-; CHECK-NEXT: setp.lt.f32 %p4, %r16, 0f3F000000;
-; CHECK-NEXT: selp.f32 %r19, %r18, %r17, %p4;
-; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r19;
-; CHECK-NEXT: mov.b32 %r20, {%rs4, %rs3};
-; CHECK-NEXT: st.param.b32 [func_retval0], %r20;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_round_param_0];
+; CHECK-NEXT: cvt.f32.f16 %r1, %rs2;
+; CHECK-NEXT: and.b32 %r2, %r1, -2147483648;
+; CHECK-NEXT: or.b32 %r3, %r2, 1056964608;
+; CHECK-NEXT: add.rn.f32 %r4, %r1, %r3;
+; CHECK-NEXT: cvt.rzi.f32.f32 %r5, %r4;
+; CHECK-NEXT: abs.f32 %r6, %r1;
+; CHECK-NEXT: setp.gt.f32 %p1, %r6, 0f4B000000;
+; CHECK-NEXT: selp.f32 %r7, %r1, %r5, %p1;
+; CHECK-NEXT: cvt.rzi.f32.f32 %r8, %r1;
+; CHECK-NEXT: setp.lt.f32 %p2, %r6, 0f3F000000;
+; CHECK-NEXT: selp.f32 %r9, %r8, %r7, %p2;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs3, %r9;
+; CHECK-NEXT: cvt.f32.f16 %r10, %rs1;
+; CHECK-NEXT: and.b32 %r11, %r10, -2147483648;
+; CHECK-NEXT: or.b32 %r12, %r11, 1056964608;
+; CHECK-NEXT: add.rn.f32 %r13, %r10, %r12;
+; CHECK-NEXT: cvt.rzi.f32.f32 %r14, %r13;
+; CHECK-NEXT: abs.f32 %r15, %r10;
+; CHECK-NEXT: setp.gt.f32 %p3, %r15, 0f4B000000;
+; CHECK-NEXT: selp.f32 %r16, %r10, %r14, %p3;
+; CHECK-NEXT: cvt.rzi.f32.f32 %r17, %r10;
+; CHECK-NEXT: setp.lt.f32 %p4, %r15, 0f3F000000;
+; CHECK-NEXT: selp.f32 %r18, %r17, %r16, %p4;
+; CHECK-NEXT: cvt.rn.f16.f32 %rs4, %r18;
+; CHECK-NEXT: mov.b32 %r19, {%rs4, %rs3};
+; CHECK-NEXT: st.param.b32 [func_retval0], %r19;
; CHECK-NEXT: ret;
%r = call <2 x half> @llvm.round.f16(<2 x half> %a)
ret <2 x half> %r
@@ -2122,9 +2034,9 @@ define <2 x half> @test_fmuladd(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0
; CHECK-F16-NEXT: .reg .b32 %r<5>;
; CHECK-F16-EMPTY:
; CHECK-F16-NEXT: // %bb.0:
-; CHECK-F16-NEXT: ld.param.b32 %r3, [test_fmuladd_param_2];
-; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fmuladd_param_1];
; CHECK-F16-NEXT: ld.param.b32 %r1, [test_fmuladd_param_0];
+; CHECK-F16-NEXT: ld.param.b32 %r2, [test_fmuladd_param_1];
+; CHECK-F16-NEXT: ld.param.b32 %r3, [test_fmuladd_param_2];
; CHECK-F16-NEXT: fma.rn.f16x2 %r4, %r1, %r2, %r3;
; CHECK-F16-NEXT: st.param.b32 [func_retval0], %r4;
; CHECK-F16-NEXT: ret;
@@ -2132,28 +2044,25 @@ define <2 x half> @test_fmuladd(<2 x half> %a, <2 x half> %b, <2 x half> %c) #0
; CHECK-NOF16-LABEL: test_fmuladd(
; CHECK-NOF16: {
; CHECK-NOF16-NEXT: .reg .b16 %rs<9>;
-; CHECK-NOF16-NEXT: .reg .b32 %r<5>;
+; CHECK-NOF16-NEXT: .reg .b32 %r<2>;
; CHECK-NOF16-NEXT: .reg .b64 %rd<9>;
; CHECK-NOF16-EMPTY:
; CHECK-NOF16-NEXT: // %bb.0:
-; CHECK-NOF16-NEXT: ld.param.b32 %r3, [test_fmuladd_param_2];
-; CHECK-NOF16-NEXT: ld.param.b32 %r2, [test_fmuladd_param_1];
-; CHECK-NOF16-NEXT: ld.param.b32 %r1, [test_fmuladd_param_0];
-; CHECK-NOF16-NEXT: mov.b32 {%rs1, %rs2}, %r3;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd1, %rs2;
-; CHECK-NOF16-NEXT: mov.b32 {%rs3, %rs4}, %r2;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd2, %rs4;
-; CHECK-NOF16-NEXT: mov.b32 {%rs5, %rs6}, %r1;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd3, %rs6;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fmuladd_param_0];
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_fmuladd_param_2];
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd1, %rs4;
+; CHECK-NOF16-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [test_fmuladd_param_1];
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd2, %rs6;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd3, %rs2;
; CHECK-NOF16-NEXT: fma.rn.f64 %rd4, %rd3, %rd2, %rd1;
; CHECK-NOF16-NEXT: cvt.rn.f16.f64 %rs7, %rd4;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd5, %rs1;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd6, %rs3;
-; CHECK-NOF16-NEXT: cvt.f64.f16 %rd7, %rs5;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd5, %rs3;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd6, %rs5;
+; CHECK-NOF16-NEXT: cvt.f64.f16 %rd7, %rs1;
; CHECK-NOF16-NEXT: fma.rn.f64 %rd8, %rd7, %rd6, %rd5;
; CHECK-NOF16-NEXT: cvt.rn.f16.f64 %rs8, %rd8;
-; CHECK-NOF16-NEXT: mov.b32 %r4, {%rs8, %rs7};
-; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NOF16-NEXT: mov.b32 %r1, {%rs8, %rs7};
+; CHECK-NOF16-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NOF16-NEXT: ret;
%r = call <2 x half> @llvm.fmuladd.f16(<2 x half> %a, <2 x half> %b, <2 x half> %c)
ret <2 x half> %r
@@ -2163,11 +2072,9 @@ define <2 x half> @test_shufflevector(<2 x half> %a) #0 {
; CHECK-LABEL: test_shufflevector(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_shufflevector_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_shufflevector_param_0];
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs2, %rs1};
; CHECK-NEXT: ret;
%s = shufflevector <2 x half> %a, <2 x half> undef, <2 x i32> <i32 1, i32 0>
@@ -2178,12 +2085,10 @@ define <2 x half> @test_insertelement(<2 x half> %a, half %x) #0 {
; CHECK-LABEL: test_insertelement(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<3>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
; CHECK-NEXT: ld.param.b16 %rs1, [test_insertelement_param_1];
-; CHECK-NEXT: ld.param.b32 %r1, [test_insertelement_param_0];
-; CHECK-NEXT: { .reg .b16 tmp; mov.b32 {%rs2, tmp}, %r1; }
+; CHECK-NEXT: ld.param.b16 %rs2, [test_insertelement_param_0];
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs2, %rs1};
; CHECK-NEXT: ret;
%i = insertelement <2 x half> %a, half %x, i64 1
@@ -2194,11 +2099,9 @@ define <2 x half> @test_sitofp_2xi16_to_2xhalf(<2 x i16> %a) #0 {
; CHECK-LABEL: test_sitofp_2xi16_to_2xhalf(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_sitofp_2xi16_to_2xhalf_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_sitofp_2xi16_to_2xhalf_param_0];
; CHECK-NEXT: cvt.rn.f16.s16 %rs3, %rs2;
; CHECK-NEXT: cvt.rn.f16.s16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -2211,11 +2114,9 @@ define <2 x half> @test_uitofp_2xi16_to_2xhalf(<2 x i16> %a) #0 {
; CHECK-LABEL: test_uitofp_2xi16_to_2xhalf(
; CHECK: {
; CHECK-NEXT: .reg .b16 %rs<5>;
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_uitofp_2xi16_to_2xhalf_param_0];
-; CHECK-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; CHECK-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_uitofp_2xi16_to_2xhalf_param_0];
; CHECK-NEXT: cvt.rn.f16.u16 %rs3, %rs2;
; CHECK-NEXT: cvt.rn.f16.u16 %rs4, %rs1;
; CHECK-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -2231,10 +2132,10 @@ define void @test_store_2xhalf(ptr %p1, ptr %p2, <2 x half> %v) {
; CHECK-NEXT: .reg .b64 %rd<3>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [test_store_2xhalf_param_2];
-; CHECK-NEXT: ld.param.b64 %rd2, [test_store_2xhalf_param_1];
; CHECK-NEXT: ld.param.b64 %rd1, [test_store_2xhalf_param_0];
+; CHECK-NEXT: ld.param.b32 %r1, [test_store_2xhalf_param_2];
; CHECK-NEXT: st.b32 [%rd1], %r1;
+; CHECK-NEXT: ld.param.b64 %rd2, [test_store_2xhalf_param_1];
; CHECK-NEXT: st.b32 [%rd2], 1006648320;
; CHECK-NEXT: ret;
store <2 x half> %v, ptr %p1
diff --git a/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll b/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll
index 8fa9791b68058e..9c25c9c3cd5250 100644
--- a/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll
+++ b/llvm/test/CodeGen/NVPTX/f32x2-convert-i32x2.ll
@@ -26,7 +26,6 @@ define ptx_kernel void @store_i32x2(i32 %0, ptr %p) {
; CHECK-SM90A-NEXT: .reg .b64 %rd<2>;
; CHECK-SM90A-EMPTY:
; CHECK-SM90A-NEXT: // %bb.0:
-; CHECK-SM90A-NEXT: ld.param.b64 %rd1, [store_i32x2_param_1];
; CHECK-SM90A-NEXT: ld.param.b32 %r1, [store_i32x2_param_0];
; CHECK-SM90A-NEXT: { // callseq 0, 0
; CHECK-SM90A-NEXT: .param .b32 param0;
@@ -35,6 +34,7 @@ define ptx_kernel void @store_i32x2(i32 %0, ptr %p) {
; CHECK-SM90A-NEXT: call.uni (retval0), return_i32x2, (param0);
; CHECK-SM90A-NEXT: ld.param.v2.b32 {%r2, %r3}, [retval0];
; CHECK-SM90A-NEXT: } // callseq 0
+; CHECK-SM90A-NEXT: ld.param.b64 %rd1, [store_i32x2_param_1];
; CHECK-SM90A-NEXT: add.rn.f32 %r4, %r3, %r3;
; CHECK-SM90A-NEXT: add.rn.f32 %r5, %r2, %r2;
; CHECK-SM90A-NEXT: st.v2.b32 [%rd1], {%r5, %r4};
@@ -46,17 +46,17 @@ define ptx_kernel void @store_i32x2(i32 %0, ptr %p) {
; CHECK-SM100-NEXT: .reg .b64 %rd<4>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::entry.b64 %rd1, [store_i32x2_param_1];
; CHECK-SM100-NEXT: ld.param::entry.b32 %r1, [store_i32x2_param_0];
; CHECK-SM100-NEXT: { // callseq 0, 0
; CHECK-SM100-NEXT: .param .b32 param0;
; CHECK-SM100-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-SM100-NEXT: st.param::func.b32 [param0], %r1;
; CHECK-SM100-NEXT: call.uni (retval0), return_i32x2, (param0);
-; CHECK-SM100-NEXT: ld.param::func.b64 %rd2, [retval0];
+; CHECK-SM100-NEXT: ld.param::func.b64 %rd1, [retval0];
; CHECK-SM100-NEXT: } // callseq 0
-; CHECK-SM100-NEXT: add.rn.f32x2 %rd3, %rd2, %rd2;
-; CHECK-SM100-NEXT: st.b64 [%rd1], %rd3;
+; CHECK-SM100-NEXT: ld.param::entry.b64 %rd2, [store_i32x2_param_1];
+; CHECK-SM100-NEXT: add.rn.f32x2 %rd3, %rd1, %rd1;
+; CHECK-SM100-NEXT: st.b64 [%rd2], %rd3;
; CHECK-SM100-NEXT: ret;
%v = call <2 x i32> @return_i32x2(i32 %0)
%v.f32x2 = bitcast <2 x i32> %v to <2 x float>
@@ -77,8 +77,8 @@ define ptx_kernel void @inlineasm(ptr %p) {
; CHECK-SM90A-NEXT: ld.param.b64 %rd1, [inlineasm_param_0];
; CHECK-SM90A-NEXT: mov.b32 %r3, 0;
; CHECK-SM90A-NEXT: mov.b32 %r4, %r3;
-; CHECK-SM90A-NEXT: mov.b32 %r2, %r4;
; CHECK-SM90A-NEXT: mov.b32 %r1, %r3;
+; CHECK-SM90A-NEXT: mov.b32 %r2, %r4;
; CHECK-SM90A-NEXT: // begin inline asm
; CHECK-SM90A-NEXT: // nop
; CHECK-SM90A-NEXT: // end inline asm
@@ -96,8 +96,8 @@ define ptx_kernel void @inlineasm(ptr %p) {
; CHECK-SM100-NEXT: ld.param::entry.b64 %rd1, [inlineasm_param_0];
; CHECK-SM100-NEXT: mov.b32 %r3, 0;
; CHECK-SM100-NEXT: mov.b32 %r4, %r3;
-; CHECK-SM100-NEXT: mov.b32 %r2, %r4;
; CHECK-SM100-NEXT: mov.b32 %r1, %r3;
+; CHECK-SM100-NEXT: mov.b32 %r2, %r4;
; CHECK-SM100-NEXT: // begin inline asm
; CHECK-SM100-NEXT: // nop
; CHECK-SM100-NEXT: // end inline asm
@@ -134,16 +134,15 @@ define ptx_kernel void @trunc_v2i32(<2 x i32> %0) {
; CHECK-SM100-LABEL: trunc_v2i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<6>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<3>;
+; CHECK-SM100-NEXT: .reg .b64 %rd<2>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::entry.b64 %rd1, [trunc_v2i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-SM100-NEXT: ld.param::entry.v2.b32 {%r1, %r2}, [trunc_v2i32_param_0];
; CHECK-SM100-NEXT: prmt.b32 %r3, %r1, %r2, 0x3340U;
; CHECK-SM100-NEXT: prmt.b32 %r4, 0, 0, 0x3340U;
; CHECK-SM100-NEXT: prmt.b32 %r5, %r4, %r3, 0x5410U;
-; CHECK-SM100-NEXT: mov.b64 %rd2, 0;
-; CHECK-SM100-NEXT: st.b32 [%rd2], %r5;
+; CHECK-SM100-NEXT: mov.b64 %rd1, 0;
+; CHECK-SM100-NEXT: st.b32 [%rd1], %r5;
; CHECK-SM100-NEXT: ret;
%2 = trunc <2 x i32> %0 to <2 x i8>
%3 = shufflevector <2 x i8> zeroinitializer, <2 x i8> %2, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
@@ -155,18 +154,17 @@ define ptx_kernel void @zextend_to_v2i32(<2 x i8> %0) {
; CHECK-SM90A-LABEL: zextend_to_v2i32(
; CHECK-SM90A: {
; CHECK-SM90A-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM90A-NEXT: .reg .b32 %r<4>;
+; CHECK-SM90A-NEXT: .reg .b32 %r<3>;
; CHECK-SM90A-NEXT: .reg .b64 %rd<5>;
; CHECK-SM90A-EMPTY:
; CHECK-SM90A-NEXT: // %bb.0:
; CHECK-SM90A-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [zextend_to_v2i32_param_0];
-; CHECK-SM90A-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-SM90A-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-SM90A-NEXT: cvt.u32.u16 %r3, %rs2;
+; CHECK-SM90A-NEXT: cvt.u32.u16 %r1, %rs1;
+; CHECK-SM90A-NEXT: cvt.u32.u16 %r2, %rs2;
; CHECK-SM90A-NEXT: mov.b64 %rd1, 12;
-; CHECK-SM90A-NEXT: st.b32 [%rd1], %r3;
+; CHECK-SM90A-NEXT: st.b32 [%rd1], %r2;
; CHECK-SM90A-NEXT: mov.b64 %rd2, 8;
-; CHECK-SM90A-NEXT: st.b32 [%rd2], %r2;
+; CHECK-SM90A-NEXT: st.b32 [%rd2], %r1;
; CHECK-SM90A-NEXT: mov.b64 %rd3, 4;
; CHECK-SM90A-NEXT: st.b32 [%rd3], 0;
; CHECK-SM90A-NEXT: mov.b64 %rd4, 0;
@@ -176,17 +174,16 @@ define ptx_kernel void @zextend_to_v2i32(<2 x i8> %0) {
; CHECK-SM100-LABEL: zextend_to_v2i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM100-NEXT: .reg .b32 %r<5>;
+; CHECK-SM100-NEXT: .reg .b32 %r<4>;
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
; CHECK-SM100-NEXT: ld.param::entry.v2.b8 {%rs1, %rs2}, [zextend_to_v2i32_param_0];
-; CHECK-SM100-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-SM100-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-SM100-NEXT: mov.b64 %rd1, {%r3, %r2};
-; CHECK-SM100-NEXT: mov.b32 %r4, 0;
-; CHECK-SM100-NEXT: mov.b64 %rd2, {%r4, %r4};
+; CHECK-SM100-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r2, %rs1;
+; CHECK-SM100-NEXT: mov.b64 %rd1, {%r2, %r1};
+; CHECK-SM100-NEXT: mov.b32 %r3, 0;
+; CHECK-SM100-NEXT: mov.b64 %rd2, {%r3, %r3};
; CHECK-SM100-NEXT: mov.b64 %rd3, 4;
; CHECK-SM100-NEXT: st.b32 [%rd3], %rd2;
; CHECK-SM100-NEXT: mov.b64 %rd4, 0;
@@ -207,20 +204,19 @@ define ptx_kernel void @sextend_to_v2i32(<2 x i8> %0) {
; CHECK-SM90A-LABEL: sextend_to_v2i32(
; CHECK-SM90A: {
; CHECK-SM90A-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM90A-NEXT: .reg .b32 %r<6>;
+; CHECK-SM90A-NEXT: .reg .b32 %r<5>;
; CHECK-SM90A-NEXT: .reg .b64 %rd<5>;
; CHECK-SM90A-EMPTY:
; CHECK-SM90A-NEXT: // %bb.0:
; CHECK-SM90A-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [sextend_to_v2i32_param_0];
-; CHECK-SM90A-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-SM90A-NEXT: cvt.u32.u16 %r2, %rs1;
-; CHECK-SM90A-NEXT: cvt.s32.s8 %r3, %r2;
-; CHECK-SM90A-NEXT: cvt.u32.u16 %r4, %rs2;
-; CHECK-SM90A-NEXT: cvt.s32.s8 %r5, %r4;
+; CHECK-SM90A-NEXT: cvt.u32.u16 %r1, %rs1;
+; CHECK-SM90A-NEXT: cvt.s32.s8 %r2, %r1;
+; CHECK-SM90A-NEXT: cvt.u32.u16 %r3, %rs2;
+; CHECK-SM90A-NEXT: cvt.s32.s8 %r4, %r3;
; CHECK-SM90A-NEXT: mov.b64 %rd1, 12;
-; CHECK-SM90A-NEXT: st.b32 [%rd1], %r5;
+; CHECK-SM90A-NEXT: st.b32 [%rd1], %r4;
; CHECK-SM90A-NEXT: mov.b64 %rd2, 8;
-; CHECK-SM90A-NEXT: st.b32 [%rd2], %r3;
+; CHECK-SM90A-NEXT: st.b32 [%rd2], %r2;
; CHECK-SM90A-NEXT: mov.b64 %rd3, 4;
; CHECK-SM90A-NEXT: st.b32 [%rd3], 0;
; CHECK-SM90A-NEXT: mov.b64 %rd4, 0;
@@ -230,25 +226,24 @@ define ptx_kernel void @sextend_to_v2i32(<2 x i8> %0) {
; CHECK-SM100-LABEL: sextend_to_v2i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b16 %rs<3>;
-; CHECK-SM100-NEXT: .reg .b32 %r<7>;
+; CHECK-SM100-NEXT: .reg .b32 %r<6>;
; CHECK-SM100-NEXT: .reg .b64 %rd<7>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
; CHECK-SM100-NEXT: ld.param::entry.v2.b8 {%rs1, %rs2}, [sextend_to_v2i32_param_0];
-; CHECK-SM100-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-SM100-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-SM100-NEXT: cvt.s32.s8 %r3, %r2;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r4, %rs1;
-; CHECK-SM100-NEXT: cvt.s32.s8 %r5, %r4;
-; CHECK-SM100-NEXT: mov.b64 %rd1, {%r5, %r3};
-; CHECK-SM100-NEXT: mov.b32 %r6, 0;
-; CHECK-SM100-NEXT: mov.b64 %rd2, {%r6, %r6};
+; CHECK-SM100-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-SM100-NEXT: cvt.s32.s8 %r2, %r1;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r3, %rs1;
+; CHECK-SM100-NEXT: cvt.s32.s8 %r4, %r3;
+; CHECK-SM100-NEXT: mov.b64 %rd1, {%r4, %r2};
+; CHECK-SM100-NEXT: mov.b32 %r5, 0;
+; CHECK-SM100-NEXT: mov.b64 %rd2, {%r5, %r5};
; CHECK-SM100-NEXT: mov.b64 %rd3, 4;
; CHECK-SM100-NEXT: st.b32 [%rd3], %rd2;
; CHECK-SM100-NEXT: mov.b64 %rd4, 0;
; CHECK-SM100-NEXT: st.b32 [%rd4], %rd2;
; CHECK-SM100-NEXT: mov.b64 %rd5, 12;
-; CHECK-SM100-NEXT: st.b32 [%rd5], %r3;
+; CHECK-SM100-NEXT: st.b32 [%rd5], %r2;
; CHECK-SM100-NEXT: mov.b64 %rd6, 8;
; CHECK-SM100-NEXT: st.b32 [%rd6], %rd1;
; CHECK-SM100-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
index 3f5528baf9fa27..030661f5b7d12f 100644
--- a/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/f32x2-instructions.ll
@@ -46,11 +46,9 @@ define float @test_extract_0(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_extract_0(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<2>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_0_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, _}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b32 %r1, [test_extract_0_param_0];
; CHECK-F32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-F32X2-NEXT: ret;
%e = extractelement <2 x float> %a, i32 0
@@ -70,11 +68,9 @@ define float @test_extract_1(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_extract_1(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<2>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_1_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {_, %r1}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b32 %r1, [test_extract_1_param_0+4];
; CHECK-F32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-F32X2-NEXT: ret;
%e = extractelement <2 x float> %a, i32 1
@@ -84,40 +80,34 @@ define float @test_extract_1(<2 x float> %a) #0 {
define float @test_extract_i(<2 x float> %a, i64 %idx) #0 {
; CHECK-NOF32X2-LABEL: test_extract_i(
; CHECK-NOF32X2: {
-; CHECK-NOF32X2-NEXT: .local .align 8 .b8 __local_depot3[8];
-; CHECK-NOF32X2-NEXT: .reg .b64 %SP;
-; CHECK-NOF32X2-NEXT: .reg .b64 %SPL;
-; CHECK-NOF32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOF32X2-NEXT: .reg .b32 %r<2>;
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: mov.b64 %SPL, __local_depot3;
-; CHECK-NOF32X2-NEXT: cvta.local.u64 %SP, %SPL;
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_extract_i_param_0];
-; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_extract_i_param_1];
-; CHECK-NOF32X2-NEXT: mov.b64 %rd1, %rd2;
-; CHECK-NOF32X2-NEXT: st.v2.b32 [%SP], {%r1, %r2};
-; CHECK-NOF32X2-NEXT: and.b64 %rd3, %rd1, 1;
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_extract_i_param_1];
+; CHECK-NOF32X2-NEXT: mov.b64 %rd2, %rd1;
+; CHECK-NOF32X2-NEXT: and.b64 %rd3, %rd2, 1;
; CHECK-NOF32X2-NEXT: shl.b64 %rd4, %rd3, 2;
-; CHECK-NOF32X2-NEXT: add.u64 %rd5, %SP, 0;
-; CHECK-NOF32X2-NEXT: or.b64 %rd6, %rd5, %rd4;
-; CHECK-NOF32X2-NEXT: ld.b32 %r3, [%rd6];
-; CHECK-NOF32X2-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NOF32X2-NEXT: mov.b64 %rd5, test_extract_i_param_0;
+; CHECK-NOF32X2-NEXT: add.s64 %rd6, %rd5, %rd4;
+; CHECK-NOF32X2-NEXT: ld.param.b32 %r1, [%rd6];
+; CHECK-NOF32X2-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NOF32X2-NEXT: ret;
;
; CHECK-F32X2-LABEL: test_extract_i(
; CHECK-F32X2: {
-; CHECK-F32X2-NEXT: .reg .pred %p<2>;
-; CHECK-F32X2-NEXT: .reg .b32 %r<4>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-F32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_extract_i_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_i_param_0];
-; CHECK-F32X2-NEXT: setp.eq.b64 %p1, %rd2, 0;
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: selp.f32 %r3, %r1, %r2, %p1;
-; CHECK-F32X2-NEXT: st.param::func.b32 [func_retval0], %r3;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_i_param_1];
+; CHECK-F32X2-NEXT: mov.b64 %rd2, %rd1;
+; CHECK-F32X2-NEXT: and.b64 %rd3, %rd2, 1;
+; CHECK-F32X2-NEXT: shl.b64 %rd4, %rd3, 2;
+; CHECK-F32X2-NEXT: mov.b64 %rd5, test_extract_i_param_0;
+; CHECK-F32X2-NEXT: add.s64 %rd6, %rd5, %rd4;
+; CHECK-F32X2-NEXT: ld.param::func.b32 %r1, [%rd6];
+; CHECK-F32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-F32X2-NEXT: ret;
%e = extractelement <2 x float> %a, i64 %idx
ret float %e
@@ -129,8 +119,8 @@ define <2 x float> @test_fadd(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fadd_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fadd_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fadd_param_1];
; CHECK-NOF32X2-NEXT: add.rn.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: add.rn.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -141,8 +131,8 @@ define <2 x float> @test_fadd(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fadd_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fadd_param_1];
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd3, %rd1, %rd2;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
@@ -214,8 +204,8 @@ define <4 x float> @test_fadd_v4(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<13>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [test_fadd_v4_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [test_fadd_v4_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [test_fadd_v4_param_1];
; CHECK-NOF32X2-NEXT: add.rn.f32 %r9, %r4, %r8;
; CHECK-NOF32X2-NEXT: add.rn.f32 %r10, %r3, %r7;
; CHECK-NOF32X2-NEXT: add.rn.f32 %r11, %r2, %r6;
@@ -228,8 +218,8 @@ define <4 x float> @test_fadd_v4(<4 x float> %a, <4 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_fadd_v4_param_1];
; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_v4_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_fadd_v4_param_1];
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd5, %rd2, %rd4;
; CHECK-F32X2-NEXT: add.rn.f32x2 %rd6, %rd1, %rd3;
; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd5};
@@ -314,8 +304,8 @@ define <2 x float> @test_fsub(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fsub_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fsub_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fsub_param_1];
; CHECK-NOF32X2-NEXT: sub.rn.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: sub.rn.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -326,8 +316,8 @@ define <2 x float> @test_fsub(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fsub_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fsub_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fsub_param_1];
; CHECK-F32X2-NEXT: sub.rn.f32x2 %rd3, %rd1, %rd2;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
@@ -350,11 +340,9 @@ define <2 x float> @test_fneg(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_fneg(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fneg_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fneg_param_0];
; CHECK-F32X2-NEXT: neg.f32 %r3, %r2;
; CHECK-F32X2-NEXT: neg.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -369,8 +357,8 @@ define <2 x float> @test_fmul(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fmul_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fmul_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fmul_param_1];
; CHECK-NOF32X2-NEXT: mul.rn.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: mul.rn.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -381,8 +369,8 @@ define <2 x float> @test_fmul(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmul_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fmul_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmul_param_1];
; CHECK-F32X2-NEXT: mul.rn.f32x2 %rd3, %rd1, %rd2;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
@@ -396,8 +384,8 @@ define <2 x float> @test_fdiv(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fdiv_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fdiv_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fdiv_param_1];
; CHECK-NOF32X2-NEXT: div.rn.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: div.rn.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -406,15 +394,12 @@ define <2 x float> @test_fdiv(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-LABEL: test_fdiv(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fdiv_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fdiv_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: div.rn.f32 %r5, %r4, %r2;
-; CHECK-F32X2-NEXT: div.rn.f32 %r6, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fdiv_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fdiv_param_1];
+; CHECK-F32X2-NEXT: div.rn.f32 %r5, %r2, %r4;
+; CHECK-F32X2-NEXT: div.rn.f32 %r6, %r1, %r3;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = fdiv <2 x float> %a, %b
@@ -427,8 +412,8 @@ define <2 x float> @test_frem(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<13>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_frem_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_frem_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_frem_param_1];
; CHECK-NOF32X2-NEXT: div.rn.f32 %r5, %r1, %r3;
; CHECK-NOF32X2-NEXT: cvt.rzi.f32.f32 %r6, %r5;
; CHECK-NOF32X2-NEXT: neg.f32 %r7, %r6;
@@ -443,13 +428,10 @@ define <2 x float> @test_frem(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-LABEL: test_frem(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<13>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_frem_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_frem_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd2;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_frem_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_frem_param_1];
; CHECK-F32X2-NEXT: div.rn.f32 %r5, %r1, %r3;
; CHECK-F32X2-NEXT: cvt.rzi.f32.f32 %r6, %r5;
; CHECK-F32X2-NEXT: neg.f32 %r7, %r6;
@@ -470,8 +452,8 @@ define <2 x float> @test_fadd_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fadd_ftz_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fadd_ftz_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fadd_ftz_param_1];
; CHECK-NOF32X2-NEXT: add.rn.ftz.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: add.rn.ftz.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -482,8 +464,8 @@ define <2 x float> @test_fadd_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fadd_ftz_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fadd_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fadd_ftz_param_1];
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd3, %rd1, %rd2;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
@@ -555,8 +537,8 @@ define <4 x float> @test_fadd_v4_ftz(<4 x float> %a, <4 x float> %b) #2 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<13>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [test_fadd_v4_ftz_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [test_fadd_v4_ftz_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [test_fadd_v4_ftz_param_1];
; CHECK-NOF32X2-NEXT: add.rn.ftz.f32 %r9, %r4, %r8;
; CHECK-NOF32X2-NEXT: add.rn.ftz.f32 %r10, %r3, %r7;
; CHECK-NOF32X2-NEXT: add.rn.ftz.f32 %r11, %r2, %r6;
@@ -569,8 +551,8 @@ define <4 x float> @test_fadd_v4_ftz(<4 x float> %a, <4 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_fadd_v4_ftz_param_1];
; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_fadd_v4_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_fadd_v4_ftz_param_1];
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd5, %rd2, %rd4;
; CHECK-F32X2-NEXT: add.rn.ftz.f32x2 %rd6, %rd1, %rd3;
; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd5};
@@ -655,8 +637,8 @@ define <2 x float> @test_fsub_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fsub_ftz_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fsub_ftz_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fsub_ftz_param_1];
; CHECK-NOF32X2-NEXT: sub.rn.ftz.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: sub.rn.ftz.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -667,8 +649,8 @@ define <2 x float> @test_fsub_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fsub_ftz_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fsub_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fsub_ftz_param_1];
; CHECK-F32X2-NEXT: sub.rn.ftz.f32x2 %rd3, %rd1, %rd2;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
@@ -691,11 +673,9 @@ define <2 x float> @test_fneg_ftz(<2 x float> %a) #2 {
; CHECK-F32X2-LABEL: test_fneg_ftz(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fneg_ftz_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fneg_ftz_param_0];
; CHECK-F32X2-NEXT: neg.ftz.f32 %r3, %r2;
; CHECK-F32X2-NEXT: neg.ftz.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -710,8 +690,8 @@ define <2 x float> @test_fmul_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fmul_ftz_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fmul_ftz_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fmul_ftz_param_1];
; CHECK-NOF32X2-NEXT: mul.rn.ftz.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: mul.rn.ftz.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -722,8 +702,8 @@ define <2 x float> @test_fmul_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmul_ftz_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fmul_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmul_ftz_param_1];
; CHECK-F32X2-NEXT: mul.rn.ftz.f32x2 %rd3, %rd1, %rd2;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
@@ -737,9 +717,9 @@ define <2 x float> @test_fma_ftz(<2 x float> %a, <2 x float> %b, <2 x float> %c)
; CHECK-NOF32X2-NEXT: .reg .b32 %r<9>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_fma_ftz_param_2];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fma_ftz_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fma_ftz_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fma_ftz_param_1];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_fma_ftz_param_2];
; CHECK-NOF32X2-NEXT: fma.rn.ftz.f32 %r7, %r2, %r4, %r6;
; CHECK-NOF32X2-NEXT: fma.rn.ftz.f32 %r8, %r1, %r3, %r5;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
@@ -750,9 +730,9 @@ define <2 x float> @test_fma_ftz(<2 x float> %a, <2 x float> %b, <2 x float> %c)
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fma_ftz_param_2];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fma_ftz_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fma_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fma_ftz_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fma_ftz_param_2];
; CHECK-F32X2-NEXT: fma.rn.ftz.f32x2 %rd4, %rd1, %rd2, %rd3;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
@@ -766,8 +746,8 @@ define <2 x float> @test_fdiv_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fdiv_ftz_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fdiv_ftz_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fdiv_ftz_param_1];
; CHECK-NOF32X2-NEXT: div.rn.ftz.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: div.rn.ftz.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -776,15 +756,12 @@ define <2 x float> @test_fdiv_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-LABEL: test_fdiv_ftz(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fdiv_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fdiv_ftz_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r5, %r4, %r2;
-; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r6, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fdiv_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fdiv_ftz_param_1];
+; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r5, %r2, %r4;
+; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r6, %r1, %r3;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = fdiv <2 x float> %a, %b
@@ -797,8 +774,8 @@ define <2 x float> @test_frem_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<13>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_frem_ftz_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_frem_ftz_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_frem_ftz_param_1];
; CHECK-NOF32X2-NEXT: div.rn.ftz.f32 %r5, %r1, %r3;
; CHECK-NOF32X2-NEXT: cvt.rzi.ftz.f32.f32 %r6, %r5;
; CHECK-NOF32X2-NEXT: neg.ftz.f32 %r7, %r6;
@@ -813,13 +790,10 @@ define <2 x float> @test_frem_ftz(<2 x float> %a, <2 x float> %b) #2 {
; CHECK-F32X2-LABEL: test_frem_ftz(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<13>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_frem_ftz_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_frem_ftz_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd2;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_frem_ftz_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_frem_ftz_param_1];
; CHECK-F32X2-NEXT: div.rn.ftz.f32 %r5, %r1, %r3;
; CHECK-F32X2-NEXT: cvt.rzi.ftz.f32.f32 %r6, %r5;
; CHECK-F32X2-NEXT: neg.ftz.f32 %r7, %r6;
@@ -841,9 +815,9 @@ define void @test_ldst_v2f32(ptr %a, ptr %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2f32_param_1];
; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v2f32_param_0];
; CHECK-NOF32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2f32_param_1];
; CHECK-NOF32X2-NEXT: st.v2.b32 [%rd2], {%r1, %r2};
; CHECK-NOF32X2-NEXT: ret;
;
@@ -852,10 +826,10 @@ define void @test_ldst_v2f32(ptr %a, ptr %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v2f32_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v2f32_param_0];
-; CHECK-F32X2-NEXT: ld.b64 %rd3, [%rd1];
-; CHECK-F32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-F32X2-NEXT: ld.b64 %rd2, [%rd1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_ldst_v2f32_param_1];
+; CHECK-F32X2-NEXT: st.b64 [%rd3], %rd2;
; CHECK-F32X2-NEXT: ret;
%t1 = load <2 x float>, ptr %a
store <2 x float> %t1, ptr %b, align 32
@@ -869,12 +843,12 @@ define void @test_ldst_v3f32(ptr %a, ptr %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v3f32_param_1];
; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v3f32_param_0];
-; CHECK-NOF32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-NOF32X2-NEXT: ld.b64 %rd2, [%rd1];
; CHECK-NOF32X2-NEXT: ld.b32 %r1, [%rd1+8];
-; CHECK-NOF32X2-NEXT: st.b32 [%rd2+8], %r1;
-; CHECK-NOF32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd3, [test_ldst_v3f32_param_1];
+; CHECK-NOF32X2-NEXT: st.b32 [%rd3+8], %r1;
+; CHECK-NOF32X2-NEXT: st.b64 [%rd3], %rd2;
; CHECK-NOF32X2-NEXT: ret;
;
; CHECK-F32X2-LABEL: test_ldst_v3f32(
@@ -883,12 +857,12 @@ define void @test_ldst_v3f32(ptr %a, ptr %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v3f32_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v3f32_param_0];
-; CHECK-F32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-F32X2-NEXT: ld.b64 %rd2, [%rd1];
; CHECK-F32X2-NEXT: ld.b32 %r1, [%rd1+8];
-; CHECK-F32X2-NEXT: st.b32 [%rd2+8], %r1;
-; CHECK-F32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_ldst_v3f32_param_1];
+; CHECK-F32X2-NEXT: st.b32 [%rd3+8], %r1;
+; CHECK-F32X2-NEXT: st.b64 [%rd3], %rd2;
; CHECK-F32X2-NEXT: ret;
%t1 = load <3 x float>, ptr %a
store <3 x float> %t1, ptr %b, align 32
@@ -902,9 +876,9 @@ define void @test_ldst_v4f32(ptr %a, ptr %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v4f32_param_1];
; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v4f32_param_0];
; CHECK-NOF32X2-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v4f32_param_1];
; CHECK-NOF32X2-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NOF32X2-NEXT: ret;
;
@@ -913,10 +887,10 @@ define void @test_ldst_v4f32(ptr %a, ptr %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v4f32_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v4f32_param_0];
-; CHECK-F32X2-NEXT: ld.v2.b64 {%rd3, %rd4}, [%rd1];
-; CHECK-F32X2-NEXT: st.v2.b64 [%rd2], {%rd3, %rd4};
+; CHECK-F32X2-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd4, [test_ldst_v4f32_param_1];
+; CHECK-F32X2-NEXT: st.v2.b64 [%rd4], {%rd2, %rd3};
; CHECK-F32X2-NEXT: ret;
%t1 = load <4 x float>, ptr %a
store <4 x float> %t1, ptr %b, align 32
@@ -930,10 +904,10 @@ define void @test_ldst_v8f32(ptr %a, ptr %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v8f32_param_1];
; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v8f32_param_0];
; CHECK-NOF32X2-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
; CHECK-NOF32X2-NEXT: ld.v4.b32 {%r5, %r6, %r7, %r8}, [%rd1+16];
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v8f32_param_1];
; CHECK-NOF32X2-NEXT: st.v4.b32 [%rd2+16], {%r5, %r6, %r7, %r8};
; CHECK-NOF32X2-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NOF32X2-NEXT: ret;
@@ -943,12 +917,12 @@ define void @test_ldst_v8f32(ptr %a, ptr %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v8f32_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v8f32_param_0];
-; CHECK-F32X2-NEXT: ld.v2.b64 {%rd3, %rd4}, [%rd1];
-; CHECK-F32X2-NEXT: ld.v2.b64 {%rd5, %rd6}, [%rd1+16];
-; CHECK-F32X2-NEXT: st.v2.b64 [%rd2+16], {%rd5, %rd6};
-; CHECK-F32X2-NEXT: st.v2.b64 [%rd2], {%rd3, %rd4};
+; CHECK-F32X2-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
+; CHECK-F32X2-NEXT: ld.v2.b64 {%rd4, %rd5}, [%rd1+16];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd6, [test_ldst_v8f32_param_1];
+; CHECK-F32X2-NEXT: st.v2.b64 [%rd6+16], {%rd4, %rd5};
+; CHECK-F32X2-NEXT: st.v2.b64 [%rd6], {%rd2, %rd3};
; CHECK-F32X2-NEXT: ret;
%t1 = load <8 x float>, ptr %a
store <8 x float> %t1, ptr %b, align 32
@@ -963,12 +937,12 @@ define <2 x float> @test_call(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_call_param_0];
; CHECK-NOF32X2-NEXT: { // callseq 0, 0
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 retval0[8];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_param_1];
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [param1], {%r3, %r4};
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [param0], {%r1, %r2};
; CHECK-NOF32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
@@ -982,12 +956,12 @@ define <2 x float> @test_call(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_call_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_call_param_0];
; CHECK-F32X2-NEXT: { // callseq 0, 0
; CHECK-F32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 retval0[8];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_call_param_1];
; CHECK-F32X2-NEXT: st.param::func.b64 [param1], %rd2;
; CHECK-F32X2-NEXT: st.param::func.b64 [param0], %rd1;
; CHECK-F32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
@@ -1005,13 +979,13 @@ define <2 x float> @test_call_flipped(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_flipped_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_call_flipped_param_0];
; CHECK-NOF32X2-NEXT: { // callseq 1, 0
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [param1], {%r1, %r2};
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_flipped_param_1];
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [param0], {%r3, %r4};
; CHECK-NOF32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [retval0];
@@ -1024,13 +998,13 @@ define <2 x float> @test_call_flipped(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_call_flipped_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_call_flipped_param_0];
; CHECK-F32X2-NEXT: { // callseq 1, 0
; CHECK-F32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-F32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_call_flipped_param_1];
; CHECK-F32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-F32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
@@ -1047,13 +1021,13 @@ define <2 x float> @test_tailcall_flipped(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_tailcall_flipped_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_tailcall_flipped_param_0];
; CHECK-NOF32X2-NEXT: { // callseq 2, 0
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-NOF32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [param1], {%r1, %r2};
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_tailcall_flipped_param_1];
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [param0], {%r3, %r4};
; CHECK-NOF32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [retval0];
@@ -1066,13 +1040,13 @@ define <2 x float> @test_tailcall_flipped(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_tailcall_flipped_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_tailcall_flipped_param_0];
; CHECK-F32X2-NEXT: { // callseq 2, 0
; CHECK-F32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-F32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-F32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_tailcall_flipped_param_1];
; CHECK-F32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-F32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
@@ -1087,34 +1061,38 @@ define <2 x float> @test_select(<2 x float> %a, <2 x float> %b, i1 zeroext %c) #
; CHECK-NOF32X2-LABEL: test_select(
; CHECK-NOF32X2: {
; CHECK-NOF32X2-NEXT: .reg .pred %p<2>;
-; CHECK-NOF32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
+; CHECK-NOF32X2-NEXT: .reg .b16 %rs<4>;
+; CHECK-NOF32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-NOF32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
; CHECK-NOF32X2-NEXT: ld.param.b8 %rs1, [test_select_param_2];
-; CHECK-NOF32X2-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-NOF32X2-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_param_1];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_param_0];
-; CHECK-NOF32X2-NEXT: selp.f32 %r5, %r2, %r4, %p1;
-; CHECK-NOF32X2-NEXT: selp.f32 %r6, %r1, %r3, %p1;
-; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-NOF32X2-NEXT: mov.b16 %rs2, %rs1;
+; CHECK-NOF32X2-NEXT: and.b16 %rs3, %rs2, 1;
+; CHECK-NOF32X2-NEXT: setp.ne.b16 %p1, %rs3, 0;
+; CHECK-NOF32X2-NEXT: mov.b64 %rd1, test_select_param_1;
+; CHECK-NOF32X2-NEXT: mov.b64 %rd2, test_select_param_0;
+; CHECK-NOF32X2-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [%rd3];
+; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r1, %r2};
; CHECK-NOF32X2-NEXT: ret;
;
; CHECK-F32X2-LABEL: test_select(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .pred %p<2>;
-; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-F32X2-NEXT: .reg .b16 %rs<4>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
; CHECK-F32X2-NEXT: ld.param::func.b8 %rs1, [test_select_param_2];
-; CHECK-F32X2-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-F32X2-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_select_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_select_param_0];
-; CHECK-F32X2-NEXT: selp.b64 %rd3, %rd1, %rd2, %p1;
-; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
+; CHECK-F32X2-NEXT: mov.b16 %rs2, %rs1;
+; CHECK-F32X2-NEXT: and.b16 %rs3, %rs2, 1;
+; CHECK-F32X2-NEXT: setp.ne.b16 %p1, %rs3, 0;
+; CHECK-F32X2-NEXT: mov.b64 %rd1, test_select_param_1;
+; CHECK-F32X2-NEXT: mov.b64 %rd2, test_select_param_0;
+; CHECK-F32X2-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd4, [%rd3];
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
%r = select i1 %c, <2 x float> %a, <2 x float> %b
ret <2 x float> %r
@@ -1127,14 +1105,14 @@ define <2 x float> @test_select_cc(<2 x float> %a, <2 x float> %b, <2 x float> %
; CHECK-NOF32X2-NEXT: .reg .b32 %r<11>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r7, %r8}, [test_select_cc_param_3];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_select_cc_param_2];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_param_0];
-; CHECK-NOF32X2-NEXT: setp.neu.f32 %p1, %r5, %r7;
-; CHECK-NOF32X2-NEXT: setp.neu.f32 %p2, %r6, %r8;
-; CHECK-NOF32X2-NEXT: selp.f32 %r9, %r2, %r4, %p2;
-; CHECK-NOF32X2-NEXT: selp.f32 %r10, %r1, %r3, %p1;
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_param_2];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_select_cc_param_3];
+; CHECK-NOF32X2-NEXT: setp.neu.f32 %p1, %r3, %r5;
+; CHECK-NOF32X2-NEXT: setp.neu.f32 %p2, %r4, %r6;
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r7, %r8}, [test_select_cc_param_1];
+; CHECK-NOF32X2-NEXT: selp.f32 %r9, %r2, %r8, %p2;
+; CHECK-NOF32X2-NEXT: selp.f32 %r10, %r1, %r7, %p1;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-NOF32X2-NEXT: ret;
;
@@ -1142,21 +1120,16 @@ define <2 x float> @test_select_cc(<2 x float> %a, <2 x float> %b, <2 x float> %
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<11>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd4, [test_select_cc_param_3];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_select_cc_param_2];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_select_cc_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_select_cc_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r3, %r1;
-; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r4, %r2;
-; CHECK-F32X2-NEXT: mov.b64 {%r5, %r6}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r7, %r8}, %rd1;
-; CHECK-F32X2-NEXT: selp.f32 %r9, %r8, %r6, %p2;
-; CHECK-F32X2-NEXT: selp.f32 %r10, %r7, %r5, %p1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_select_cc_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_select_cc_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [test_select_cc_param_3];
+; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r3, %r5;
+; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r4, %r6;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r7, %r8}, [test_select_cc_param_1];
+; CHECK-F32X2-NEXT: selp.f32 %r9, %r2, %r8, %p2;
+; CHECK-F32X2-NEXT: selp.f32 %r10, %r1, %r7, %p1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-F32X2-NEXT: ret;
%cc = fcmp une <2 x float> %c, %d
@@ -1172,12 +1145,12 @@ define <2 x double> @test_select_cc_f64_f32(<2 x double> %a, <2 x double> %b, <2
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f64_f32_param_3];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_f64_f32_param_2];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_select_cc_f64_f32_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_select_cc_f64_f32_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_f64_f32_param_2];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f64_f32_param_3];
; CHECK-NOF32X2-NEXT: setp.neu.f32 %p1, %r1, %r3;
; CHECK-NOF32X2-NEXT: setp.neu.f32 %p2, %r2, %r4;
+; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_select_cc_f64_f32_param_1];
; CHECK-NOF32X2-NEXT: selp.f64 %rd5, %rd2, %rd4, %p2;
; CHECK-NOF32X2-NEXT: selp.f64 %rd6, %rd1, %rd3, %p1;
; CHECK-NOF32X2-NEXT: st.param.v2.b64 [func_retval0], {%rd6, %rd5};
@@ -1187,20 +1160,18 @@ define <2 x double> @test_select_cc_f64_f32(<2 x double> %a, <2 x double> %b, <2
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<9>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_select_cc_f64_f32_param_1];
; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_select_cc_f64_f32_param_0];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd6, [test_select_cc_f64_f32_param_3];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd5, [test_select_cc_f64_f32_param_2];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd6;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd5;
-; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r3, %r1;
-; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r4, %r2;
-; CHECK-F32X2-NEXT: selp.f64 %rd7, %rd2, %rd4, %p2;
-; CHECK-F32X2-NEXT: selp.f64 %rd8, %rd1, %rd3, %p1;
-; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd8, %rd7};
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_select_cc_f64_f32_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_select_cc_f64_f32_param_3];
+; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r1, %r3;
+; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r2, %r4;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_select_cc_f64_f32_param_1];
+; CHECK-F32X2-NEXT: selp.f64 %rd5, %rd2, %rd4, %p2;
+; CHECK-F32X2-NEXT: selp.f64 %rd6, %rd1, %rd3, %p1;
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd6, %rd5};
; CHECK-F32X2-NEXT: ret;
%cc = fcmp une <2 x float> %c, %d
%r = select <2 x i1> %cc, <2 x double> %a, <2 x double> %b
@@ -1215,12 +1186,12 @@ define <2 x float> @test_select_cc_f32_f64(<2 x float> %a, <2 x float> %b, <2 x
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_select_cc_f32_f64_param_3];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_select_cc_f32_f64_param_2];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f32_f64_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_f32_f64_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_select_cc_f32_f64_param_2];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_select_cc_f32_f64_param_3];
; CHECK-NOF32X2-NEXT: setp.neu.f64 %p1, %rd1, %rd3;
; CHECK-NOF32X2-NEXT: setp.neu.f64 %p2, %rd2, %rd4;
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_f32_f64_param_1];
; CHECK-NOF32X2-NEXT: selp.f32 %r5, %r2, %r4, %p2;
; CHECK-NOF32X2-NEXT: selp.f32 %r6, %r1, %r3, %p1;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -1230,19 +1201,17 @@ define <2 x float> @test_select_cc_f32_f64(<2 x float> %a, <2 x float> %b, <2 x
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd5, %rd6}, [test_select_cc_f32_f64_param_3];
-; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_select_cc_f32_f64_param_2];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_select_cc_f32_f64_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_select_cc_f32_f64_param_0];
-; CHECK-F32X2-NEXT: setp.neu.f64 %p1, %rd3, %rd5;
-; CHECK-F32X2-NEXT: setp.neu.f64 %p2, %rd4, %rd6;
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: selp.f32 %r5, %r4, %r2, %p2;
-; CHECK-F32X2-NEXT: selp.f32 %r6, %r3, %r1, %p1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_select_cc_f32_f64_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_select_cc_f32_f64_param_2];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [test_select_cc_f32_f64_param_3];
+; CHECK-F32X2-NEXT: setp.neu.f64 %p1, %rd1, %rd3;
+; CHECK-F32X2-NEXT: setp.neu.f64 %p2, %rd2, %rd4;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_select_cc_f32_f64_param_1];
+; CHECK-F32X2-NEXT: selp.f32 %r5, %r2, %r4, %p2;
+; CHECK-F32X2-NEXT: selp.f32 %r6, %r1, %r3, %p1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%cc = fcmp une <2 x double> %c, %d
@@ -1258,8 +1227,8 @@ define <2 x i1> @test_fcmp_une(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_une_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_une_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_une_param_1];
; CHECK-NOF32X2-NEXT: setp.neu.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.neu.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1273,15 +1242,12 @@ define <2 x i1> @test_fcmp_une(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_une_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_une_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_une_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_une_param_1];
+; CHECK-F32X2-NEXT: setp.neu.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.neu.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1299,8 +1265,8 @@ define <2 x i1> @test_fcmp_ueq(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ueq_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_ueq_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ueq_param_1];
; CHECK-NOF32X2-NEXT: setp.equ.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.equ.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1314,15 +1280,12 @@ define <2 x i1> @test_fcmp_ueq(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ueq_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ueq_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.equ.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.equ.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_ueq_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_ueq_param_1];
+; CHECK-F32X2-NEXT: setp.equ.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.equ.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1340,8 +1303,8 @@ define <2 x i1> @test_fcmp_ugt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ugt_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_ugt_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ugt_param_1];
; CHECK-NOF32X2-NEXT: setp.gtu.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.gtu.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1355,15 +1318,12 @@ define <2 x i1> @test_fcmp_ugt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ugt_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ugt_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.gtu.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.gtu.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_ugt_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_ugt_param_1];
+; CHECK-F32X2-NEXT: setp.gtu.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.gtu.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1381,8 +1341,8 @@ define <2 x i1> @test_fcmp_uge(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_uge_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_uge_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_uge_param_1];
; CHECK-NOF32X2-NEXT: setp.geu.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.geu.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1396,15 +1356,12 @@ define <2 x i1> @test_fcmp_uge(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_uge_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_uge_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.geu.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.geu.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_uge_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_uge_param_1];
+; CHECK-F32X2-NEXT: setp.geu.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.geu.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1422,8 +1379,8 @@ define <2 x i1> @test_fcmp_ult(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ult_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_ult_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ult_param_1];
; CHECK-NOF32X2-NEXT: setp.ltu.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.ltu.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1437,15 +1394,12 @@ define <2 x i1> @test_fcmp_ult(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ult_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ult_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.ltu.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.ltu.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_ult_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_ult_param_1];
+; CHECK-F32X2-NEXT: setp.ltu.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.ltu.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1463,8 +1417,8 @@ define <2 x i1> @test_fcmp_ule(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ule_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_ule_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ule_param_1];
; CHECK-NOF32X2-NEXT: setp.leu.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.leu.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1478,15 +1432,12 @@ define <2 x i1> @test_fcmp_ule(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ule_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ule_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.leu.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.leu.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_ule_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_ule_param_1];
+; CHECK-F32X2-NEXT: setp.leu.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.leu.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1504,8 +1455,8 @@ define <2 x i1> @test_fcmp_uno(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_uno_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_uno_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_uno_param_1];
; CHECK-NOF32X2-NEXT: setp.nan.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.nan.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1519,15 +1470,12 @@ define <2 x i1> @test_fcmp_uno(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_uno_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_uno_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.nan.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.nan.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_uno_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_uno_param_1];
+; CHECK-F32X2-NEXT: setp.nan.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.nan.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1545,8 +1493,8 @@ define <2 x i1> @test_fcmp_one(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_one_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_one_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_one_param_1];
; CHECK-NOF32X2-NEXT: setp.ne.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.ne.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1560,15 +1508,12 @@ define <2 x i1> @test_fcmp_one(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_one_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_one_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.ne.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.ne.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_one_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_one_param_1];
+; CHECK-F32X2-NEXT: setp.ne.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.ne.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1586,8 +1531,8 @@ define <2 x i1> @test_fcmp_oeq(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_oeq_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_oeq_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_oeq_param_1];
; CHECK-NOF32X2-NEXT: setp.eq.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.eq.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1601,15 +1546,12 @@ define <2 x i1> @test_fcmp_oeq(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_oeq_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_oeq_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.eq.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.eq.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_oeq_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_oeq_param_1];
+; CHECK-F32X2-NEXT: setp.eq.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.eq.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1627,8 +1569,8 @@ define <2 x i1> @test_fcmp_ogt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ogt_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_ogt_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ogt_param_1];
; CHECK-NOF32X2-NEXT: setp.gt.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.gt.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1642,15 +1584,12 @@ define <2 x i1> @test_fcmp_ogt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ogt_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ogt_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.gt.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.gt.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_ogt_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_ogt_param_1];
+; CHECK-F32X2-NEXT: setp.gt.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.gt.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1668,8 +1607,8 @@ define <2 x i1> @test_fcmp_oge(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_oge_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_oge_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_oge_param_1];
; CHECK-NOF32X2-NEXT: setp.ge.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.ge.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1683,15 +1622,12 @@ define <2 x i1> @test_fcmp_oge(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_oge_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_oge_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.ge.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.ge.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_oge_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_oge_param_1];
+; CHECK-F32X2-NEXT: setp.ge.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.ge.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1709,8 +1645,8 @@ define <2 x i1> @test_fcmp_olt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_olt_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_olt_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_olt_param_1];
; CHECK-NOF32X2-NEXT: setp.lt.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.lt.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1724,15 +1660,12 @@ define <2 x i1> @test_fcmp_olt(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_olt_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_olt_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.lt.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.lt.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_olt_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_olt_param_1];
+; CHECK-F32X2-NEXT: setp.lt.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.lt.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1750,8 +1683,8 @@ define <2 x i1> @test_fcmp_ole(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ole_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_ole_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ole_param_1];
; CHECK-NOF32X2-NEXT: setp.le.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.le.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1765,15 +1698,12 @@ define <2 x i1> @test_fcmp_ole(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ole_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ole_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.le.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.le.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_ole_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_ole_param_1];
+; CHECK-F32X2-NEXT: setp.le.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.le.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1791,8 +1721,8 @@ define <2 x i1> @test_fcmp_ord(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ord_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fcmp_ord_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fcmp_ord_param_1];
; CHECK-NOF32X2-NEXT: setp.num.f32 %p1, %r2, %r4;
; CHECK-NOF32X2-NEXT: setp.num.f32 %p2, %r1, %r3;
; CHECK-NOF32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
@@ -1806,15 +1736,12 @@ define <2 x i1> @test_fcmp_ord(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fcmp_ord_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fcmp_ord_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: setp.num.f32 %p1, %r4, %r2;
-; CHECK-F32X2-NEXT: setp.num.f32 %p2, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fcmp_ord_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_fcmp_ord_param_1];
+; CHECK-F32X2-NEXT: setp.num.f32 %p1, %r2, %r4;
+; CHECK-F32X2-NEXT: setp.num.f32 %p2, %r1, %r3;
; CHECK-F32X2-NEXT: selp.b16 %rs1, -1, 0, %p2;
; CHECK-F32X2-NEXT: st.param::func.b8 [func_retval0], %rs1;
; CHECK-F32X2-NEXT: selp.b16 %rs2, -1, 0, %p1;
@@ -1839,11 +1766,9 @@ define <2 x i32> @test_fptosi_i32(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_fptosi_i32(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptosi_i32_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fptosi_i32_param_0];
; CHECK-F32X2-NEXT: cvt.rzi.s32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.s32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -1868,14 +1793,13 @@ define <2 x i64> @test_fptosi_i64(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_fptosi_i64(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptosi_i64_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: cvt.rzi.s64.f32 %rd2, %r2;
-; CHECK-F32X2-NEXT: cvt.rzi.s64.f32 %rd3, %r1;
-; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fptosi_i64_param_0];
+; CHECK-F32X2-NEXT: cvt.rzi.s64.f32 %rd1, %r2;
+; CHECK-F32X2-NEXT: cvt.rzi.s64.f32 %rd2, %r1;
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd2, %rd1};
; CHECK-F32X2-NEXT: ret;
%r = fptosi <2 x float> %a to <2 x i64>
ret <2 x i64> %r
@@ -1896,11 +1820,9 @@ define <2 x i32> @test_fptoui_2xi32(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_fptoui_2xi32(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptoui_2xi32_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fptoui_2xi32_param_0];
; CHECK-F32X2-NEXT: cvt.rzi.u32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.u32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -1925,14 +1847,13 @@ define <2 x i64> @test_fptoui_2xi64(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_fptoui_2xi64(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fptoui_2xi64_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: cvt.rzi.u64.f32 %rd2, %r2;
-; CHECK-F32X2-NEXT: cvt.rzi.u64.f32 %rd3, %r1;
-; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fptoui_2xi64_param_0];
+; CHECK-F32X2-NEXT: cvt.rzi.u64.f32 %rd1, %r2;
+; CHECK-F32X2-NEXT: cvt.rzi.u64.f32 %rd2, %r1;
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd2, %rd1};
; CHECK-F32X2-NEXT: ret;
%r = fptoui <2 x float> %a to <2 x i64>
ret <2 x i64> %r
@@ -1953,11 +1874,9 @@ define <2 x float> @test_uitofp_2xi32(<2 x i32> %a) #0 {
; CHECK-F32X2-LABEL: test_uitofp_2xi32(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_2xi32_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_uitofp_2xi32_param_0];
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2009,11 +1928,9 @@ define <2 x float> @test_sitofp_2xi32(<2 x i32> %a) #0 {
; CHECK-F32X2-LABEL: test_sitofp_2xi32(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sitofp_2xi32_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_sitofp_2xi32_param_0];
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2056,29 +1973,28 @@ define <2 x float> @test_uitofp_2xi32_fadd(<2 x i32> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<9>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_uitofp_2xi32_fadd_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_uitofp_2xi32_fadd_param_0];
-; CHECK-NOF32X2-NEXT: cvt.rn.f32.u32 %r5, %r1;
-; CHECK-NOF32X2-NEXT: cvt.rn.f32.u32 %r6, %r2;
-; CHECK-NOF32X2-NEXT: add.rn.f32 %r7, %r4, %r6;
-; CHECK-NOF32X2-NEXT: add.rn.f32 %r8, %r3, %r5;
+; CHECK-NOF32X2-NEXT: cvt.rn.f32.u32 %r3, %r1;
+; CHECK-NOF32X2-NEXT: cvt.rn.f32.u32 %r4, %r2;
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_uitofp_2xi32_fadd_param_1];
+; CHECK-NOF32X2-NEXT: add.rn.f32 %r7, %r6, %r4;
+; CHECK-NOF32X2-NEXT: add.rn.f32 %r8, %r5, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-NOF32X2-NEXT: ret;
;
; CHECK-F32X2-LABEL: test_uitofp_2xi32_fadd(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_uitofp_2xi32_fadd_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_2xi32_fadd_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_uitofp_2xi32_fadd_param_0];
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
-; CHECK-F32X2-NEXT: mov.b64 %rd3, {%r4, %r3};
-; CHECK-F32X2-NEXT: add.rn.f32x2 %rd4, %rd2, %rd3;
-; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
+; CHECK-F32X2-NEXT: mov.b64 %rd1, {%r4, %r3};
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_uitofp_2xi32_fadd_param_1];
+; CHECK-F32X2-NEXT: add.rn.f32x2 %rd3, %rd2, %rd1;
+; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
; CHECK-F32X2-NEXT: ret;
%c = uitofp <2 x i32> %a to <2 x float>
%r = fadd <2 x float> %b, %c
@@ -2130,14 +2046,13 @@ define <2 x double> @test_fpext_2xdouble(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_fpext_2xdouble(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fpext_2xdouble_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: cvt.f64.f32 %rd2, %r2;
-; CHECK-F32X2-NEXT: cvt.f64.f32 %rd3, %r1;
-; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fpext_2xdouble_param_0];
+; CHECK-F32X2-NEXT: cvt.f64.f32 %rd1, %r2;
+; CHECK-F32X2-NEXT: cvt.f64.f32 %rd2, %r1;
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd2, %rd1};
; CHECK-F32X2-NEXT: ret;
%r = fpext <2 x float> %a to <2 x double>
ret <2 x double> %r
@@ -2246,11 +2161,9 @@ define <2 x float> @test_sqrt(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_sqrt(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sqrt_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_sqrt_param_0];
; CHECK-F32X2-NEXT: sqrt.rn.f32 %r3, %r2;
; CHECK-F32X2-NEXT: sqrt.rn.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2281,11 +2194,9 @@ define <2 x float> @test_sin(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_sin(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sin_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_sin_param_0];
; CHECK-F32X2-NEXT: sin.approx.f32 %r3, %r2;
; CHECK-F32X2-NEXT: sin.approx.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2309,11 +2220,9 @@ define <2 x float> @test_cos(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_cos(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_cos_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_cos_param_0];
; CHECK-F32X2-NEXT: cos.approx.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cos.approx.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2371,9 +2280,9 @@ define <2 x float> @test_fma(<2 x float> %a, <2 x float> %b, <2 x float> %c) #0
; CHECK-NOF32X2-NEXT: .reg .b32 %r<9>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_fma_param_2];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fma_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fma_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fma_param_1];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_fma_param_2];
; CHECK-NOF32X2-NEXT: fma.rn.f32 %r7, %r2, %r4, %r6;
; CHECK-NOF32X2-NEXT: fma.rn.f32 %r8, %r1, %r3, %r5;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
@@ -2384,9 +2293,9 @@ define <2 x float> @test_fma(<2 x float> %a, <2 x float> %b, <2 x float> %c) #0
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fma_param_2];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fma_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fma_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fma_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fma_param_2];
; CHECK-F32X2-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
@@ -2409,11 +2318,9 @@ define <2 x float> @test_fabs(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_fabs(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fabs_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_fabs_param_0];
; CHECK-F32X2-NEXT: abs.f32 %r3, %r2;
; CHECK-F32X2-NEXT: abs.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2428,8 +2335,8 @@ define <2 x float> @test_minnum(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_minnum_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_minnum_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_minnum_param_1];
; CHECK-NOF32X2-NEXT: min.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: min.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -2438,15 +2345,12 @@ define <2 x float> @test_minnum(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-LABEL: test_minnum(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_minnum_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_minnum_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: min.f32 %r5, %r4, %r2;
-; CHECK-F32X2-NEXT: min.f32 %r6, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_minnum_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_minnum_param_1];
+; CHECK-F32X2-NEXT: min.f32 %r5, %r2, %r4;
+; CHECK-F32X2-NEXT: min.f32 %r6, %r1, %r3;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.minnum(<2 x float> %a, <2 x float> %b)
@@ -2459,8 +2363,8 @@ define <2 x float> @test_maxnum(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_maxnum_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_maxnum_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_maxnum_param_1];
; CHECK-NOF32X2-NEXT: max.f32 %r5, %r2, %r4;
; CHECK-NOF32X2-NEXT: max.f32 %r6, %r1, %r3;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -2469,15 +2373,12 @@ define <2 x float> @test_maxnum(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-LABEL: test_maxnum(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_maxnum_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_maxnum_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-F32X2-NEXT: max.f32 %r5, %r4, %r2;
-; CHECK-F32X2-NEXT: max.f32 %r6, %r3, %r1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_maxnum_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_maxnum_param_1];
+; CHECK-F32X2-NEXT: max.f32 %r5, %r2, %r4;
+; CHECK-F32X2-NEXT: max.f32 %r6, %r1, %r3;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.maxnum(<2 x float> %a, <2 x float> %b)
@@ -2490,8 +2391,8 @@ define <2 x float> @test_copysign(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_copysign_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_copysign_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_copysign_param_1];
; CHECK-NOF32X2-NEXT: copysign.f32 %r5, %r4, %r2;
; CHECK-NOF32X2-NEXT: copysign.f32 %r6, %r3, %r1;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -2500,13 +2401,10 @@ define <2 x float> @test_copysign(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-LABEL: test_copysign(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_copysign_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_copysign_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd2;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_copysign_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_copysign_param_1];
; CHECK-F32X2-NEXT: copysign.f32 %r5, %r4, %r2;
; CHECK-F32X2-NEXT: copysign.f32 %r6, %r3, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
@@ -2523,8 +2421,8 @@ define <2 x float> @test_copysign_f64(<2 x float> %a, <2 x double> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_copysign_f64_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_copysign_f64_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_copysign_f64_param_1];
; CHECK-NOF32X2-NEXT: abs.f32 %r3, %r2;
; CHECK-NOF32X2-NEXT: neg.f32 %r4, %r3;
; CHECK-NOF32X2-NEXT: shr.u64 %rd3, %rd2, 63;
@@ -2544,23 +2442,22 @@ define <2 x float> @test_copysign_f64(<2 x float> %a, <2 x double> %b) #0 {
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .pred %p<3>;
; CHECK-F32X2-NEXT: .reg .b32 %r<9>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<8>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [test_copysign_f64_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_copysign_f64_param_0];
-; CHECK-F32X2-NEXT: shr.u64 %rd4, %rd3, 63;
-; CHECK-F32X2-NEXT: and.b64 %rd5, %rd4, 1;
-; CHECK-F32X2-NEXT: setp.ne.b64 %p1, %rd5, 0;
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_copysign_f64_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [test_copysign_f64_param_1];
; CHECK-F32X2-NEXT: abs.f32 %r3, %r2;
; CHECK-F32X2-NEXT: neg.f32 %r4, %r3;
+; CHECK-F32X2-NEXT: shr.u64 %rd3, %rd2, 63;
+; CHECK-F32X2-NEXT: and.b64 %rd4, %rd3, 1;
+; CHECK-F32X2-NEXT: setp.ne.b64 %p1, %rd4, 0;
; CHECK-F32X2-NEXT: selp.f32 %r5, %r4, %r3, %p1;
-; CHECK-F32X2-NEXT: shr.u64 %rd6, %rd2, 63;
-; CHECK-F32X2-NEXT: and.b64 %rd7, %rd6, 1;
-; CHECK-F32X2-NEXT: setp.ne.b64 %p2, %rd7, 0;
; CHECK-F32X2-NEXT: abs.f32 %r6, %r1;
; CHECK-F32X2-NEXT: neg.f32 %r7, %r6;
+; CHECK-F32X2-NEXT: shr.u64 %rd5, %rd1, 63;
+; CHECK-F32X2-NEXT: and.b64 %rd6, %rd5, 1;
+; CHECK-F32X2-NEXT: setp.ne.b64 %p2, %rd6, 0;
; CHECK-F32X2-NEXT: selp.f32 %r8, %r7, %r6, %p2;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r5};
; CHECK-F32X2-NEXT: ret;
@@ -2576,8 +2473,8 @@ define <2 x double> @test_copysign_extended(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-NOF32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_copysign_extended_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_copysign_extended_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_copysign_extended_param_1];
; CHECK-NOF32X2-NEXT: copysign.f32 %r5, %r3, %r1;
; CHECK-NOF32X2-NEXT: copysign.f32 %r6, %r4, %r2;
; CHECK-NOF32X2-NEXT: cvt.f64.f32 %rd1, %r6;
@@ -2588,18 +2485,16 @@ define <2 x double> @test_copysign_extended(<2 x float> %a, <2 x float> %b) #0 {
; CHECK-F32X2-LABEL: test_copysign_extended(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_copysign_extended_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_copysign_extended_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-F32X2-NEXT: mov.b64 {%r3, %r4}, %rd2;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_copysign_extended_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_copysign_extended_param_1];
; CHECK-F32X2-NEXT: copysign.f32 %r5, %r3, %r1;
; CHECK-F32X2-NEXT: copysign.f32 %r6, %r4, %r2;
-; CHECK-F32X2-NEXT: cvt.f64.f32 %rd3, %r6;
-; CHECK-F32X2-NEXT: cvt.f64.f32 %rd4, %r5;
-; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd4, %rd3};
+; CHECK-F32X2-NEXT: cvt.f64.f32 %rd1, %r6;
+; CHECK-F32X2-NEXT: cvt.f64.f32 %rd2, %r5;
+; CHECK-F32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd2, %rd1};
; CHECK-F32X2-NEXT: ret;
%r = call <2 x float> @llvm.copysign(<2 x float> %a, <2 x float> %b)
%xr = fpext <2 x float> %r to <2 x double>
@@ -2621,11 +2516,9 @@ define <2 x float> @test_floor(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_floor(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_floor_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_floor_param_0];
; CHECK-F32X2-NEXT: cvt.rmi.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rmi.f32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2649,11 +2542,9 @@ define <2 x float> @test_ceil(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_ceil(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_ceil_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_ceil_param_0];
; CHECK-F32X2-NEXT: cvt.rpi.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rpi.f32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2677,11 +2568,9 @@ define <2 x float> @test_trunc(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_trunc(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_trunc_param_0];
; CHECK-F32X2-NEXT: cvt.rzi.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rzi.f32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2705,11 +2594,9 @@ define <2 x float> @test_rint(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_rint(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_rint_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_rint_param_0];
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2733,11 +2620,9 @@ define <2 x float> @test_nearbyint(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_nearbyint(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_nearbyint_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_nearbyint_param_0];
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2761,11 +2646,9 @@ define <2 x float> @test_roundeven(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_roundeven(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_roundeven_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_roundeven_param_0];
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rni.f32.f32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2810,11 +2693,9 @@ define <2 x float> @test_round(<2 x float> %a) #0 {
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .pred %p<5>;
; CHECK-F32X2-NEXT: .reg .b32 %r<19>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_round_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_round_param_0];
; CHECK-F32X2-NEXT: and.b32 %r3, %r2, -2147483648;
; CHECK-F32X2-NEXT: or.b32 %r4, %r3, 1056964608;
; CHECK-F32X2-NEXT: add.rn.f32 %r5, %r2, %r4;
@@ -2847,9 +2728,9 @@ define <2 x float> @test_fmuladd(<2 x float> %a, <2 x float> %b, <2 x float> %c)
; CHECK-NOF32X2-NEXT: .reg .b32 %r<9>;
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_fmuladd_param_2];
-; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fmuladd_param_1];
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fmuladd_param_0];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_fmuladd_param_1];
+; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_fmuladd_param_2];
; CHECK-NOF32X2-NEXT: fma.rn.f32 %r7, %r2, %r4, %r6;
; CHECK-NOF32X2-NEXT: fma.rn.f32 %r8, %r1, %r3, %r5;
; CHECK-NOF32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
@@ -2860,9 +2741,9 @@ define <2 x float> @test_fmuladd(<2 x float> %a, <2 x float> %b, <2 x float> %c)
; CHECK-F32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fmuladd_param_2];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmuladd_param_1];
; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_fmuladd_param_0];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_fmuladd_param_1];
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd3, [test_fmuladd_param_2];
; CHECK-F32X2-NEXT: fma.rn.f32x2 %rd4, %rd1, %rd2, %rd3;
; CHECK-F32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-F32X2-NEXT: ret;
@@ -2883,11 +2764,9 @@ define <2 x float> @test_shufflevector(<2 x float> %a) #0 {
; CHECK-F32X2-LABEL: test_shufflevector(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_shufflevector_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_shufflevector_param_0];
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-F32X2-NEXT: ret;
%s = shufflevector <2 x float> %a, <2 x float> poison, <2 x i32> <i32 1, i32 0>
@@ -2908,12 +2787,10 @@ define <2 x float> @test_insertelement(<2 x float> %a, float %x) #0 {
; CHECK-F32X2-LABEL: test_insertelement(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
; CHECK-F32X2-NEXT: ld.param::func.b32 %r1, [test_insertelement_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_insertelement_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r2, _}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.b32 %r2, [test_insertelement_param_0];
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-F32X2-NEXT: ret;
%i = insertelement <2 x float> %a, float %x, i64 1
@@ -2935,11 +2812,9 @@ define <2 x float> @test_sitofp_2xi32_to_2xfloat(<2 x i32> %a) #0 {
; CHECK-F32X2-LABEL: test_sitofp_2xi32_to_2xfloat(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_sitofp_2xi32_to_2xfloat_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_sitofp_2xi32_to_2xfloat_param_0];
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.s32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2963,11 +2838,9 @@ define <2 x float> @test_uitofp_2xi32_to_2xfloat(<2 x i32> %a) #0 {
; CHECK-F32X2-LABEL: test_uitofp_2xi32_to_2xfloat(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_2xi32_to_2xfloat_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_uitofp_2xi32_to_2xfloat_param_0];
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-F32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
; CHECK-F32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -2984,22 +2857,21 @@ define void @test_trunc_to_v2bf16(<2 x float> %a, ptr %p) {
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_trunc_to_v2bf16_param_0];
-; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_trunc_to_v2bf16_param_1];
; CHECK-NOF32X2-NEXT: cvt.rn.bf16x2.f32 %r3, %r2, %r1;
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_trunc_to_v2bf16_param_1];
; CHECK-NOF32X2-NEXT: st.b32 [%rd1], %r3;
; CHECK-NOF32X2-NEXT: ret;
;
; CHECK-F32X2-LABEL: test_trunc_to_v2bf16(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<4>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_trunc_to_v2bf16_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_to_v2bf16_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_trunc_to_v2bf16_param_0];
; CHECK-F32X2-NEXT: cvt.rn.bf16x2.f32 %r3, %r2, %r1;
-; CHECK-F32X2-NEXT: st.b32 [%rd2], %r3;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_to_v2bf16_param_1];
+; CHECK-F32X2-NEXT: st.b32 [%rd1], %r3;
; CHECK-F32X2-NEXT: ret;
%trunc = fptrunc <2 x float> %a to <2 x bfloat>
store <2 x bfloat> %trunc, ptr %p
@@ -3014,22 +2886,21 @@ define void @test_trunc_to_v2f16(<2 x float> %a, ptr %p) {
; CHECK-NOF32X2-EMPTY:
; CHECK-NOF32X2-NEXT: // %bb.0:
; CHECK-NOF32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_trunc_to_v2f16_param_0];
-; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_trunc_to_v2f16_param_1];
; CHECK-NOF32X2-NEXT: cvt.rn.f16x2.f32 %r3, %r2, %r1;
+; CHECK-NOF32X2-NEXT: ld.param.b64 %rd1, [test_trunc_to_v2f16_param_1];
; CHECK-NOF32X2-NEXT: st.b32 [%rd1], %r3;
; CHECK-NOF32X2-NEXT: ret;
;
; CHECK-F32X2-LABEL: test_trunc_to_v2f16(
; CHECK-F32X2: {
; CHECK-F32X2-NEXT: .reg .b32 %r<4>;
-; CHECK-F32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-F32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-F32X2-EMPTY:
; CHECK-F32X2-NEXT: // %bb.0:
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd2, [test_trunc_to_v2f16_param_1];
-; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_to_v2f16_param_0];
-; CHECK-F32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-F32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_trunc_to_v2f16_param_0];
; CHECK-F32X2-NEXT: cvt.rn.f16x2.f32 %r3, %r2, %r1;
-; CHECK-F32X2-NEXT: st.b32 [%rd2], %r3;
+; CHECK-F32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_to_v2f16_param_1];
+; CHECK-F32X2-NEXT: st.b32 [%rd1], %r3;
; CHECK-F32X2-NEXT: ret;
%trunc = fptrunc <2 x float> %a to <2 x half>
store <2 x half> %trunc, ptr %p
diff --git a/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll b/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll
index 3a4ff8e280b3a8..e7e7281260e45f 100644
--- a/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll
+++ b/llvm/test/CodeGen/NVPTX/gvn-scalar-pre-reg-pressure.ll
@@ -35,8 +35,8 @@ define void @test_scalar_pre_option(ptr %arr, i8 %cond) {
; NO-SCALAR-PRE-NEXT: .reg .b64 %rd<2>;
; NO-SCALAR-PRE-EMPTY:
; NO-SCALAR-PRE-NEXT: // %bb.0: // %entry
-; NO-SCALAR-PRE-NEXT: ld.param::func.b8 %rs1, [test_scalar_pre_option_param_1];
; NO-SCALAR-PRE-NEXT: ld.param::func.b64 %rd1, [test_scalar_pre_option_param_0];
+; NO-SCALAR-PRE-NEXT: ld.param::func.b8 %rs1, [test_scalar_pre_option_param_1];
; NO-SCALAR-PRE-NEXT: setp.eq.b16 %p1, %rs1, 0;
; NO-SCALAR-PRE-NEXT: ld.b32 %r1, [%rd1];
; NO-SCALAR-PRE-NEXT: @%p1 bra $L__BB0_2;
@@ -58,8 +58,8 @@ define void @test_scalar_pre_option(ptr %arr, i8 %cond) {
; SCALAR-PRE-NEXT: .reg .b64 %rd<2>;
; SCALAR-PRE-EMPTY:
; SCALAR-PRE-NEXT: // %bb.0: // %entry
-; SCALAR-PRE-NEXT: ld.param::func.b8 %rs1, [test_scalar_pre_option_param_1];
; SCALAR-PRE-NEXT: ld.param::func.b64 %rd1, [test_scalar_pre_option_param_0];
+; SCALAR-PRE-NEXT: ld.param::func.b8 %rs1, [test_scalar_pre_option_param_1];
; SCALAR-PRE-NEXT: setp.ne.b16 %p1, %rs1, 0;
; SCALAR-PRE-NEXT: ld.b32 %r1, [%rd1];
; SCALAR-PRE-NEXT: @%p1 bra $L__BB0_2;
diff --git a/llvm/test/CodeGen/NVPTX/i128-array.ll b/llvm/test/CodeGen/NVPTX/i128-array.ll
index 7bd8a0021f1b5c..7f0f91e28a073a 100644
--- a/llvm/test/CodeGen/NVPTX/i128-array.ll
+++ b/llvm/test/CodeGen/NVPTX/i128-array.ll
@@ -4,14 +4,12 @@
define [2 x i128] @foo(i64 %a, i32 %b) {
; CHECK-LABEL: foo(
; CHECK: {
-; CHECK-NEXT: .reg .b32 %r<2>;
; CHECK-NEXT: .reg .b64 %rd<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b32 %r1, [foo_param_1];
; CHECK-NEXT: ld.param.b64 %rd1, [foo_param_0];
; CHECK-NEXT: shr.s64 %rd2, %rd1, 63;
-; CHECK-NEXT: cvt.s64.s32 %rd3, %r1;
+; CHECK-NEXT: ld.param.s32 %rd3, [foo_param_1];
; CHECK-NEXT: shr.s64 %rd4, %rd3, 63;
; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
; CHECK-NEXT: st.param.v2.b64 [func_retval0+16], {%rd3, %rd4};
@@ -51,10 +49,10 @@ define [2 x i128] @foo3([2 x i128] %a) {
; CHECK-NEXT: .reg .b64 %rd<5>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [foo3_param_0+16];
-; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [foo3_param_0];
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd1, %rd2};
-; CHECK-NEXT: st.param.v2.b64 [func_retval0+16], {%rd3, %rd4};
+; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [foo3_param_0+16];
+; CHECK-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [foo3_param_0];
+; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd3, %rd4};
+; CHECK-NEXT: st.param.v2.b64 [func_retval0+16], {%rd1, %rd2};
; CHECK-NEXT: ret;
%1 = extractvalue [2 x i128] %a, 0
%2 = extractvalue [2 x i128] %a, 1
diff --git a/llvm/test/CodeGen/NVPTX/i128-ld-st.ll b/llvm/test/CodeGen/NVPTX/i128-ld-st.ll
index 83f1ed43960fe0..773629cd9f6da3 100644
--- a/llvm/test/CodeGen/NVPTX/i128-ld-st.ll
+++ b/llvm/test/CodeGen/NVPTX/i128-ld-st.ll
@@ -10,11 +10,11 @@ define i128 @foo(ptr %p, ptr %o) {
; CHECK-NEXT: .reg .b64 %rd<4>;
; CHECK-EMPTY:
; CHECK-NEXT: // %bb.0:
-; CHECK-NEXT: ld.param.b64 %rd2, [foo_param_1];
; CHECK-NEXT: ld.param.b64 %rd1, [foo_param_0];
-; CHECK-NEXT: ld.b8 %rd3, [%rd1];
-; CHECK-NEXT: st.v2.b64 [%rd2], {%rd3, 0};
-; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd3, 0};
+; CHECK-NEXT: ld.b8 %rd2, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd3, [foo_param_1];
+; CHECK-NEXT: st.v2.b64 [%rd3], {%rd2, 0};
+; CHECK-NEXT: st.param.v2.b64 [func_retval0], {%rd2, 0};
; CHECK-NEXT: ret;
%c = load i8, ptr %p, align 1
%i = zext i8 %c to i128
diff --git a/llvm/test/CodeGen/NVPTX/i128-param.ll b/llvm/test/CodeGen/NVPTX/i128-param.ll
index 79abca0a1dd8e2..28461adf78557d 100644
--- a/llvm/test/CodeGen/NVPTX/i128-param.ll
+++ b/llvm/test/CodeGen/NVPTX/i128-param.ll
@@ -26,12 +26,12 @@ define void @callee(i128, i128, ptr) {
define ptx_kernel void @caller_kernel(i128, i128, ptr) {
start:
; CHECK-DAG: ld.param.v2.b64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_kernel_param_0];
- ; CHECK-DAG: ld.param.v2.b64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [caller_kernel_param_1];
; CHECK: { // callseq [[CALLSEQ_ID:[0-9]]], 0
; CHECK-DAG: .param .align 16 .b8 param0[16];
; CHECK-DAG: .param .align 16 .b8 param1[16];
; CHECK-DAG: st.param.v2.b64 [param0], {%[[REG0]], %[[REG1]]}
+ ; CHECK-DAG: ld.param.v2.b64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [caller_kernel_param_1];
; CHECK-DAG: st.param.v2.b64 [param1], {%[[REG2]], %[[REG3]]}
; CHECK: } // callseq [[CALLSEQ_ID]]
call void @callee(i128 %0, i128 %1, ptr %2)
@@ -45,12 +45,12 @@ start:
define void @caller_func(i128, i128, ptr) {
start:
; CHECK-DAG: ld.param.v2.b64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_func_param_0]
- ; CHECK-DAG: ld.param.v2.b64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [caller_func_param_1]
; CHECK: { // callseq [[CALLSEQ_ID:[0-9]]], 0
; CHECK-DAG: .param .align 16 .b8 param0[16];
; CHECK-DAG: .param .align 16 .b8 param1[16];
; CHECK-DAG: st.param.v2.b64 [param0], {%[[REG0]], %[[REG1]]}
+ ; CHECK-DAG: ld.param.v2.b64 {%[[REG2:rd[0-9]+]], %[[REG3:rd[0-9]+]]}, [caller_func_param_1]
; CHECK-DAG: st.param.v2.b64 [param1], {%[[REG2]], %[[REG3]]}
; CHECK: } // callseq [[CALLSEQ_ID]]
call void @callee(i128 %0, i128 %1, ptr %2)
diff --git a/llvm/test/CodeGen/NVPTX/i128-retval.ll b/llvm/test/CodeGen/NVPTX/i128-retval.ll
index 7fea1c43aad27d..d9b87758fd6fcd 100644
--- a/llvm/test/CodeGen/NVPTX/i128-retval.ll
+++ b/llvm/test/CodeGen/NVPTX/i128-retval.ll
@@ -12,7 +12,6 @@ define i128 @callee(i128) {
define void @caller(i128, ptr) {
start:
; CHECK-DAG: ld.param.v2.b64 {%[[REG0:rd[0-9]+]], %[[REG1:rd[0-9]+]]}, [caller_param_0];
- ; CHECK-DAG: ld.param.b64 %[[OUT:rd[0-9]+]], [caller_param_1];
; CHECK: { // callseq 0, 0
; CHECK: .param .align 16 .b8 retval0[16];
@@ -21,6 +20,7 @@ start:
; CHECK: } // callseq 0
%a = call i128 @callee(i128 %0)
+ ; CHECK-DAG: ld.param.b64 %[[OUT:rd[0-9]+]], [caller_param_1];
; CHECK-DAG: st.v2.b64 [%[[OUT]]], {%[[REG2]], %[[REG3]]};
store i128 %a, ptr %1
diff --git a/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll b/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
index fb4aa711ba5ac9..e34f80174a9664 100644
--- a/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i16x2-instructions.ll
@@ -31,57 +31,27 @@ define <2 x i16> @test_ret_const() #0 {
}
define i16 @test_extract_0(<2 x i16> %a) #0 {
-; I16x2-LABEL: test_extract_0(
-; I16x2: {
-; I16x2-NEXT: .reg .b16 %rs<2>;
-; I16x2-NEXT: .reg .b32 %r<3>;
-; I16x2-EMPTY:
-; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b32 %r1, [test_extract_0_param_0];
-; I16x2-NEXT: mov.b32 {%rs1, _}, %r1;
-; I16x2-NEXT: cvt.u32.u16 %r2, %rs1;
-; I16x2-NEXT: st.param.b32 [func_retval0], %r2;
-; I16x2-NEXT: ret;
-;
-; NO-I16x2-LABEL: test_extract_0(
-; NO-I16x2: {
-; NO-I16x2-NEXT: .reg .b16 %rs<2>;
-; NO-I16x2-NEXT: .reg .b32 %r<3>;
-; NO-I16x2-EMPTY:
-; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_extract_0_param_0];
-; NO-I16x2-NEXT: { .reg .b16 tmp; mov.b32 {%rs1, tmp}, %r1; }
-; NO-I16x2-NEXT: cvt.u32.u16 %r2, %rs1;
-; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r2;
-; NO-I16x2-NEXT: ret;
+; COMMON-LABEL: test_extract_0(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.b16 %r1, [test_extract_0_param_0];
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
+; COMMON-NEXT: ret;
%e = extractelement <2 x i16> %a, i32 0
ret i16 %e
}
define i16 @test_extract_1(<2 x i16> %a) #0 {
-; I16x2-LABEL: test_extract_1(
-; I16x2: {
-; I16x2-NEXT: .reg .b16 %rs<2>;
-; I16x2-NEXT: .reg .b32 %r<3>;
-; I16x2-EMPTY:
-; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b32 %r1, [test_extract_1_param_0];
-; I16x2-NEXT: mov.b32 {_, %rs1}, %r1;
-; I16x2-NEXT: cvt.u32.u16 %r2, %rs1;
-; I16x2-NEXT: st.param.b32 [func_retval0], %r2;
-; I16x2-NEXT: ret;
-;
-; NO-I16x2-LABEL: test_extract_1(
-; NO-I16x2: {
-; NO-I16x2-NEXT: .reg .b16 %rs<2>;
-; NO-I16x2-NEXT: .reg .b32 %r<3>;
-; NO-I16x2-EMPTY:
-; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_extract_1_param_0];
-; NO-I16x2-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r1; }
-; NO-I16x2-NEXT: cvt.u32.u16 %r2, %rs1;
-; NO-I16x2-NEXT: st.param.b32 [func_retval0], %r2;
-; NO-I16x2-NEXT: ret;
+; COMMON-LABEL: test_extract_1(
+; COMMON: {
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.b16 %r1, [test_extract_1_param_0+2];
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
+; COMMON-NEXT: ret;
%e = extractelement <2 x i16> %a, i32 1
ret i16 %e
}
@@ -89,19 +59,18 @@ define i16 @test_extract_1(<2 x i16> %a) #0 {
define i16 @test_extract_i(<2 x i16> %a, i64 %idx) #0 {
; COMMON-LABEL: test_extract_i(
; COMMON: {
-; COMMON-NEXT: .reg .pred %p<2>;
-; COMMON-NEXT: .reg .b16 %rs<4>;
-; COMMON-NEXT: .reg .b32 %r<3>;
-; COMMON-NEXT: .reg .b64 %rd<2>;
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-NEXT: .reg .b64 %rd<7>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
; COMMON-NEXT: ld.param.b64 %rd1, [test_extract_i_param_1];
-; COMMON-NEXT: ld.param.b32 %r1, [test_extract_i_param_0];
-; COMMON-NEXT: setp.eq.b64 %p1, %rd1, 0;
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; COMMON-NEXT: selp.b16 %rs3, %rs1, %rs2, %p1;
-; COMMON-NEXT: cvt.u32.u16 %r2, %rs3;
-; COMMON-NEXT: st.param.b32 [func_retval0], %r2;
+; COMMON-NEXT: mov.b64 %rd2, %rd1;
+; COMMON-NEXT: and.b64 %rd3, %rd2, 1;
+; COMMON-NEXT: shl.b64 %rd4, %rd3, 1;
+; COMMON-NEXT: mov.b64 %rd5, test_extract_i_param_0;
+; COMMON-NEXT: add.s64 %rd6, %rd5, %rd4;
+; COMMON-NEXT: ld.param.b16 %r1, [%rd6];
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
; COMMON-NEXT: ret;
%e = extractelement <2 x i16> %a, i64 %idx
ret i16 %e
@@ -113,8 +82,8 @@ define <2 x i16> @test_add(<2 x i16> %a, <2 x i16> %b) #0 {
; I16x2-NEXT: .reg .b32 %r<4>;
; I16x2-EMPTY:
; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b32 %r2, [test_add_param_1];
; I16x2-NEXT: ld.param.b32 %r1, [test_add_param_0];
+; I16x2-NEXT: ld.param.b32 %r2, [test_add_param_1];
; I16x2-NEXT: add.s16x2 %r3, %r1, %r2;
; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
; I16x2-NEXT: ret;
@@ -122,15 +91,12 @@ define <2 x i16> @test_add(<2 x i16> %a, <2 x i16> %b) #0 {
; NO-I16x2-LABEL: test_add(
; NO-I16x2: {
; NO-I16x2-NEXT: .reg .b16 %rs<7>;
-; NO-I16x2-NEXT: .reg .b32 %r<3>;
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r2, [test_add_param_1];
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_add_param_0];
-; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; NO-I16x2-NEXT: add.s16 %rs5, %rs4, %rs2;
-; NO-I16x2-NEXT: add.s16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_add_param_0];
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_add_param_1];
+; NO-I16x2-NEXT: add.s16 %rs5, %rs2, %rs4;
+; NO-I16x2-NEXT: add.s16 %rs6, %rs1, %rs3;
; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; NO-I16x2-NEXT: ret;
%r = add <2 x i16> %a, %b
@@ -153,11 +119,9 @@ define <2 x i16> @test_add_imm_0(<2 x i16> %a) #0 {
; NO-I16x2-LABEL: test_add_imm_0(
; NO-I16x2: {
; NO-I16x2-NEXT: .reg .b16 %rs<5>;
-; NO-I16x2-NEXT: .reg .b32 %r<2>;
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_add_imm_0_param_0];
-; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_add_imm_0_param_0];
; NO-I16x2-NEXT: add.s16 %rs3, %rs2, 2;
; NO-I16x2-NEXT: add.s16 %rs4, %rs1, 1;
; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -181,11 +145,9 @@ define <2 x i16> @test_add_imm_1(<2 x i16> %a) #0 {
; NO-I16x2-LABEL: test_add_imm_1(
; NO-I16x2: {
; NO-I16x2-NEXT: .reg .b16 %rs<5>;
-; NO-I16x2-NEXT: .reg .b32 %r<2>;
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_add_imm_1_param_0];
-; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_add_imm_1_param_0];
; NO-I16x2-NEXT: add.s16 %rs3, %rs2, 2;
; NO-I16x2-NEXT: add.s16 %rs4, %rs1, 1;
; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -198,15 +160,12 @@ define <2 x i16> @test_sub(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-LABEL: test_sub(
; COMMON: {
; COMMON-NEXT: .reg .b16 %rs<7>;
-; COMMON-NEXT: .reg .b32 %r<3>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_sub_param_1];
-; COMMON-NEXT: ld.param.b32 %r1, [test_sub_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; COMMON-NEXT: sub.s16 %rs5, %rs4, %rs2;
-; COMMON-NEXT: sub.s16 %rs6, %rs3, %rs1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_sub_param_0];
+; COMMON-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_sub_param_1];
+; COMMON-NEXT: sub.s16 %rs5, %rs2, %rs4;
+; COMMON-NEXT: sub.s16 %rs6, %rs1, %rs3;
; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; COMMON-NEXT: ret;
%r = sub <2 x i16> %a, %b
@@ -219,8 +178,8 @@ define <2 x i16> @test_smax(<2 x i16> %a, <2 x i16> %b) #0 {
; I16x2-NEXT: .reg .b32 %r<4>;
; I16x2-EMPTY:
; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b32 %r2, [test_smax_param_1];
; I16x2-NEXT: ld.param.b32 %r1, [test_smax_param_0];
+; I16x2-NEXT: ld.param.b32 %r2, [test_smax_param_1];
; I16x2-NEXT: max.s16x2 %r3, %r1, %r2;
; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
; I16x2-NEXT: ret;
@@ -228,15 +187,12 @@ define <2 x i16> @test_smax(<2 x i16> %a, <2 x i16> %b) #0 {
; NO-I16x2-LABEL: test_smax(
; NO-I16x2: {
; NO-I16x2-NEXT: .reg .b16 %rs<7>;
-; NO-I16x2-NEXT: .reg .b32 %r<3>;
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r2, [test_smax_param_1];
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_smax_param_0];
-; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; NO-I16x2-NEXT: max.s16 %rs5, %rs4, %rs2;
-; NO-I16x2-NEXT: max.s16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_smax_param_0];
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_smax_param_1];
+; NO-I16x2-NEXT: max.s16 %rs5, %rs2, %rs4;
+; NO-I16x2-NEXT: max.s16 %rs6, %rs1, %rs3;
; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; NO-I16x2-NEXT: ret;
%cmp = icmp sgt <2 x i16> %a, %b
@@ -250,8 +206,8 @@ define <2 x i16> @test_umax(<2 x i16> %a, <2 x i16> %b) #0 {
; I16x2-NEXT: .reg .b32 %r<4>;
; I16x2-EMPTY:
; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b32 %r2, [test_umax_param_1];
; I16x2-NEXT: ld.param.b32 %r1, [test_umax_param_0];
+; I16x2-NEXT: ld.param.b32 %r2, [test_umax_param_1];
; I16x2-NEXT: max.u16x2 %r3, %r1, %r2;
; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
; I16x2-NEXT: ret;
@@ -259,15 +215,12 @@ define <2 x i16> @test_umax(<2 x i16> %a, <2 x i16> %b) #0 {
; NO-I16x2-LABEL: test_umax(
; NO-I16x2: {
; NO-I16x2-NEXT: .reg .b16 %rs<7>;
-; NO-I16x2-NEXT: .reg .b32 %r<3>;
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r2, [test_umax_param_1];
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_umax_param_0];
-; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; NO-I16x2-NEXT: max.u16 %rs5, %rs4, %rs2;
-; NO-I16x2-NEXT: max.u16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_umax_param_0];
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_umax_param_1];
+; NO-I16x2-NEXT: max.u16 %rs5, %rs2, %rs4;
+; NO-I16x2-NEXT: max.u16 %rs6, %rs1, %rs3;
; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; NO-I16x2-NEXT: ret;
%cmp = icmp ugt <2 x i16> %a, %b
@@ -281,8 +234,8 @@ define <2 x i16> @test_smin(<2 x i16> %a, <2 x i16> %b) #0 {
; I16x2-NEXT: .reg .b32 %r<4>;
; I16x2-EMPTY:
; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b32 %r2, [test_smin_param_1];
; I16x2-NEXT: ld.param.b32 %r1, [test_smin_param_0];
+; I16x2-NEXT: ld.param.b32 %r2, [test_smin_param_1];
; I16x2-NEXT: min.s16x2 %r3, %r1, %r2;
; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
; I16x2-NEXT: ret;
@@ -290,15 +243,12 @@ define <2 x i16> @test_smin(<2 x i16> %a, <2 x i16> %b) #0 {
; NO-I16x2-LABEL: test_smin(
; NO-I16x2: {
; NO-I16x2-NEXT: .reg .b16 %rs<7>;
-; NO-I16x2-NEXT: .reg .b32 %r<3>;
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r2, [test_smin_param_1];
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_smin_param_0];
-; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; NO-I16x2-NEXT: min.s16 %rs5, %rs4, %rs2;
-; NO-I16x2-NEXT: min.s16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_smin_param_0];
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_smin_param_1];
+; NO-I16x2-NEXT: min.s16 %rs5, %rs2, %rs4;
+; NO-I16x2-NEXT: min.s16 %rs6, %rs1, %rs3;
; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; NO-I16x2-NEXT: ret;
%cmp = icmp sle <2 x i16> %a, %b
@@ -312,8 +262,8 @@ define <2 x i16> @test_umin(<2 x i16> %a, <2 x i16> %b) #0 {
; I16x2-NEXT: .reg .b32 %r<4>;
; I16x2-EMPTY:
; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b32 %r2, [test_umin_param_1];
; I16x2-NEXT: ld.param.b32 %r1, [test_umin_param_0];
+; I16x2-NEXT: ld.param.b32 %r2, [test_umin_param_1];
; I16x2-NEXT: min.u16x2 %r3, %r1, %r2;
; I16x2-NEXT: st.param.b32 [func_retval0], %r3;
; I16x2-NEXT: ret;
@@ -321,15 +271,12 @@ define <2 x i16> @test_umin(<2 x i16> %a, <2 x i16> %b) #0 {
; NO-I16x2-LABEL: test_umin(
; NO-I16x2: {
; NO-I16x2-NEXT: .reg .b16 %rs<7>;
-; NO-I16x2-NEXT: .reg .b32 %r<3>;
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b32 %r2, [test_umin_param_1];
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_umin_param_0];
-; NO-I16x2-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; NO-I16x2-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; NO-I16x2-NEXT: min.u16 %rs5, %rs4, %rs2;
-; NO-I16x2-NEXT: min.u16 %rs6, %rs3, %rs1;
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_umin_param_0];
+; NO-I16x2-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_umin_param_1];
+; NO-I16x2-NEXT: min.u16 %rs5, %rs2, %rs4;
+; NO-I16x2-NEXT: min.u16 %rs6, %rs1, %rs3;
; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; NO-I16x2-NEXT: ret;
%cmp = icmp ule <2 x i16> %a, %b
@@ -341,15 +288,12 @@ define <2 x i16> @test_mul(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-LABEL: test_mul(
; COMMON: {
; COMMON-NEXT: .reg .b16 %rs<7>;
-; COMMON-NEXT: .reg .b32 %r<3>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_mul_param_1];
-; COMMON-NEXT: ld.param.b32 %r1, [test_mul_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; COMMON-NEXT: mul.lo.s16 %rs5, %rs4, %rs2;
-; COMMON-NEXT: mul.lo.s16 %rs6, %rs3, %rs1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_mul_param_0];
+; COMMON-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_mul_param_1];
+; COMMON-NEXT: mul.lo.s16 %rs5, %rs2, %rs4;
+; COMMON-NEXT: mul.lo.s16 %rs6, %rs1, %rs3;
; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; COMMON-NEXT: ret;
%r = mul <2 x i16> %a, %b
@@ -363,8 +307,8 @@ define <2 x i16> @test_or(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-NEXT: .reg .b32 %r<4>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_or_param_1];
; COMMON-NEXT: ld.param.b32 %r1, [test_or_param_0];
+; COMMON-NEXT: ld.param.b32 %r2, [test_or_param_1];
; COMMON-NEXT: or.b32 %r3, %r1, %r2;
; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
; COMMON-NEXT: ret;
@@ -424,8 +368,8 @@ define <2 x i16> @test_xor(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-NEXT: .reg .b32 %r<4>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_xor_param_1];
; COMMON-NEXT: ld.param.b32 %r1, [test_xor_param_0];
+; COMMON-NEXT: ld.param.b32 %r2, [test_xor_param_1];
; COMMON-NEXT: xor.b32 %r3, %r1, %r2;
; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
; COMMON-NEXT: ret;
@@ -489,8 +433,8 @@ define <2 x i16> @test_and(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-NEXT: .reg .b32 %r<4>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_and_param_1];
; COMMON-NEXT: ld.param.b32 %r1, [test_and_param_0];
+; COMMON-NEXT: ld.param.b32 %r2, [test_and_param_1];
; COMMON-NEXT: and.b32 %r3, %r1, %r2;
; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
; COMMON-NEXT: ret;
@@ -551,9 +495,9 @@ define void @test_ldst_v2i16(ptr %a, ptr %b) {
; COMMON-NEXT: .reg .b64 %rd<3>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b64 %rd2, [test_ldst_v2i16_param_1];
; COMMON-NEXT: ld.param.b64 %rd1, [test_ldst_v2i16_param_0];
; COMMON-NEXT: ld.b32 %r1, [%rd1];
+; COMMON-NEXT: ld.param.b64 %rd2, [test_ldst_v2i16_param_1];
; COMMON-NEXT: st.b32 [%rd2], %r1;
; COMMON-NEXT: ret;
%t1 = load <2 x i16>, ptr %a
@@ -571,12 +515,12 @@ define void @test_ldst_v3i16(ptr %a, ptr %b) {
; COMMON-NEXT: .reg .b64 %rd<5>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b64 %rd2, [test_ldst_v3i16_param_1];
; COMMON-NEXT: ld.param.b64 %rd1, [test_ldst_v3i16_param_0];
-; COMMON-NEXT: ld.b64 %rd3, [%rd1];
-; COMMON-NEXT: shr.u64 %rd4, %rd3, 32;
-; COMMON-NEXT: st.b32 [%rd2], %rd3;
-; COMMON-NEXT: st.b16 [%rd2+4], %rd4;
+; COMMON-NEXT: ld.b64 %rd2, [%rd1];
+; COMMON-NEXT: shr.u64 %rd3, %rd2, 32;
+; COMMON-NEXT: ld.param.b64 %rd4, [test_ldst_v3i16_param_1];
+; COMMON-NEXT: st.b32 [%rd4], %rd2;
+; COMMON-NEXT: st.b16 [%rd4+4], %rd3;
; COMMON-NEXT: ret;
%t1 = load <3 x i16>, ptr %a
store <3 x i16> %t1, ptr %b, align 16
@@ -590,9 +534,9 @@ define void @test_ldst_v4i16(ptr %a, ptr %b) {
; COMMON-NEXT: .reg .b64 %rd<3>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b64 %rd2, [test_ldst_v4i16_param_1];
; COMMON-NEXT: ld.param.b64 %rd1, [test_ldst_v4i16_param_0];
; COMMON-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; COMMON-NEXT: ld.param.b64 %rd2, [test_ldst_v4i16_param_1];
; COMMON-NEXT: st.v2.b32 [%rd2], {%r1, %r2};
; COMMON-NEXT: ret;
%t1 = load <4 x i16>, ptr %a
@@ -607,9 +551,9 @@ define void @test_ldst_v8i16(ptr %a, ptr %b) {
; COMMON-NEXT: .reg .b64 %rd<3>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b64 %rd2, [test_ldst_v8i16_param_1];
; COMMON-NEXT: ld.param.b64 %rd1, [test_ldst_v8i16_param_0];
; COMMON-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
+; COMMON-NEXT: ld.param.b64 %rd2, [test_ldst_v8i16_param_1];
; COMMON-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; COMMON-NEXT: ret;
%t1 = load <8 x i16>, ptr %a
@@ -625,12 +569,12 @@ define <2 x i16> @test_call(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-NEXT: .reg .b32 %r<4>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_call_param_1];
; COMMON-NEXT: ld.param.b32 %r1, [test_call_param_0];
; COMMON-NEXT: { // callseq 0, 0
; COMMON-NEXT: .param .align 4 .b8 param0[4];
; COMMON-NEXT: .param .align 4 .b8 param1[4];
; COMMON-NEXT: .param .align 4 .b8 retval0[4];
+; COMMON-NEXT: ld.param.b32 %r2, [test_call_param_1];
; COMMON-NEXT: st.param.b32 [param1], %r2;
; COMMON-NEXT: st.param.b32 [param0], %r1;
; COMMON-NEXT: call.uni (retval0), test_callee, (param0, param1);
@@ -648,13 +592,13 @@ define <2 x i16> @test_call_flipped(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-NEXT: .reg .b32 %r<4>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
; COMMON-NEXT: ld.param.b32 %r1, [test_call_flipped_param_0];
; COMMON-NEXT: { // callseq 1, 0
; COMMON-NEXT: .param .align 4 .b8 param0[4];
; COMMON-NEXT: .param .align 4 .b8 param1[4];
; COMMON-NEXT: .param .align 4 .b8 retval0[4];
; COMMON-NEXT: st.param.b32 [param1], %r1;
+; COMMON-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
; COMMON-NEXT: st.param.b32 [param0], %r2;
; COMMON-NEXT: call.uni (retval0), test_callee, (param0, param1);
; COMMON-NEXT: ld.param.b32 %r3, [retval0];
@@ -671,13 +615,13 @@ define <2 x i16> @test_tailcall_flipped(<2 x i16> %a, <2 x i16> %b) #0 {
; COMMON-NEXT: .reg .b32 %r<4>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
; COMMON-NEXT: ld.param.b32 %r1, [test_tailcall_flipped_param_0];
; COMMON-NEXT: { // callseq 2, 0
; COMMON-NEXT: .param .align 4 .b8 param0[4];
; COMMON-NEXT: .param .align 4 .b8 param1[4];
; COMMON-NEXT: .param .align 4 .b8 retval0[4];
; COMMON-NEXT: st.param.b32 [param1], %r1;
+; COMMON-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
; COMMON-NEXT: st.param.b32 [param0], %r2;
; COMMON-NEXT: call.uni (retval0), test_callee, (param0, param1);
; COMMON-NEXT: ld.param.b32 %r3, [retval0];
@@ -692,17 +636,20 @@ define <2 x i16> @test_select(<2 x i16> %a, <2 x i16> %b, i1 zeroext %c) #0 {
; COMMON-LABEL: test_select(
; COMMON: {
; COMMON-NEXT: .reg .pred %p<2>;
-; COMMON-NEXT: .reg .b16 %rs<3>;
-; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-NEXT: .reg .b16 %rs<4>;
+; COMMON-NEXT: .reg .b32 %r<2>;
+; COMMON-NEXT: .reg .b64 %rd<4>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
; COMMON-NEXT: ld.param.b8 %rs1, [test_select_param_2];
-; COMMON-NEXT: and.b16 %rs2, %rs1, 1;
-; COMMON-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; COMMON-NEXT: ld.param.b32 %r2, [test_select_param_1];
-; COMMON-NEXT: ld.param.b32 %r1, [test_select_param_0];
-; COMMON-NEXT: selp.b32 %r3, %r1, %r2, %p1;
-; COMMON-NEXT: st.param.b32 [func_retval0], %r3;
+; COMMON-NEXT: mov.b16 %rs2, %rs1;
+; COMMON-NEXT: and.b16 %rs3, %rs2, 1;
+; COMMON-NEXT: setp.ne.b16 %p1, %rs3, 0;
+; COMMON-NEXT: mov.b64 %rd1, test_select_param_1;
+; COMMON-NEXT: mov.b64 %rd2, test_select_param_0;
+; COMMON-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
+; COMMON-NEXT: ld.param.b32 %r1, [%rd3];
+; COMMON-NEXT: st.param.b32 [func_retval0], %r1;
; COMMON-NEXT: ret;
%r = select i1 %c, <2 x i16> %a, <2 x i16> %b
ret <2 x i16> %r
@@ -713,21 +660,16 @@ define <2 x i16> @test_select_cc(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c, <2 x
; COMMON: {
; COMMON-NEXT: .reg .pred %p<3>;
; COMMON-NEXT: .reg .b16 %rs<11>;
-; COMMON-NEXT: .reg .b32 %r<5>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r4, [test_select_cc_param_3];
-; COMMON-NEXT: ld.param.b32 %r3, [test_select_cc_param_2];
-; COMMON-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
-; COMMON-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r4;
-; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; COMMON-NEXT: setp.ne.b16 %p1, %rs3, %rs1;
-; COMMON-NEXT: setp.ne.b16 %p2, %rs4, %rs2;
-; COMMON-NEXT: mov.b32 {%rs5, %rs6}, %r2;
-; COMMON-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; COMMON-NEXT: selp.b16 %rs9, %rs8, %rs6, %p2;
-; COMMON-NEXT: selp.b16 %rs10, %rs7, %rs5, %p1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_select_cc_param_0];
+; COMMON-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_select_cc_param_2];
+; COMMON-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [test_select_cc_param_3];
+; COMMON-NEXT: setp.ne.b16 %p1, %rs3, %rs5;
+; COMMON-NEXT: setp.ne.b16 %p2, %rs4, %rs6;
+; COMMON-NEXT: ld.param.v2.b16 {%rs7, %rs8}, [test_select_cc_param_1];
+; COMMON-NEXT: selp.b16 %rs9, %rs2, %rs8, %p2;
+; COMMON-NEXT: selp.b16 %rs10, %rs1, %rs7, %p1;
; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs10, %rs9};
; COMMON-NEXT: ret;
%cc = icmp ne <2 x i16> %c, %d
@@ -740,20 +682,18 @@ define <2 x i32> @test_select_cc_i32_i16(<2 x i32> %a, <2 x i32> %b,
; COMMON: {
; COMMON-NEXT: .reg .pred %p<3>;
; COMMON-NEXT: .reg .b16 %rs<5>;
-; COMMON-NEXT: .reg .b32 %r<9>;
+; COMMON-NEXT: .reg .b32 %r<7>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_i32_i16_param_1];
; COMMON-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_i32_i16_param_0];
-; COMMON-NEXT: ld.param.b32 %r6, [test_select_cc_i32_i16_param_3];
-; COMMON-NEXT: ld.param.b32 %r5, [test_select_cc_i32_i16_param_2];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r6;
-; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r5;
-; COMMON-NEXT: setp.ne.b16 %p1, %rs3, %rs1;
-; COMMON-NEXT: setp.ne.b16 %p2, %rs4, %rs2;
-; COMMON-NEXT: selp.b32 %r7, %r2, %r4, %p2;
-; COMMON-NEXT: selp.b32 %r8, %r1, %r3, %p1;
-; COMMON-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_select_cc_i32_i16_param_2];
+; COMMON-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_select_cc_i32_i16_param_3];
+; COMMON-NEXT: setp.ne.b16 %p1, %rs1, %rs3;
+; COMMON-NEXT: setp.ne.b16 %p2, %rs2, %rs4;
+; COMMON-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_i32_i16_param_1];
+; COMMON-NEXT: selp.b32 %r5, %r2, %r4, %p2;
+; COMMON-NEXT: selp.b32 %r6, %r1, %r3, %p1;
+; COMMON-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
; COMMON-NEXT: ret;
<2 x i16> %c, <2 x i16> %d) #0 {
%cc = icmp ne <2 x i16> %c, %d
@@ -766,19 +706,17 @@ define <2 x i16> @test_select_cc_i16_i32(<2 x i16> %a, <2 x i16> %b,
; COMMON: {
; COMMON-NEXT: .reg .pred %p<3>;
; COMMON-NEXT: .reg .b16 %rs<7>;
-; COMMON-NEXT: .reg .b32 %r<7>;
+; COMMON-NEXT: .reg .b32 %r<5>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_select_cc_i16_i32_param_3];
-; COMMON-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_i16_i32_param_2];
-; COMMON-NEXT: ld.param.b32 %r2, [test_select_cc_i16_i32_param_1];
-; COMMON-NEXT: ld.param.b32 %r1, [test_select_cc_i16_i32_param_0];
-; COMMON-NEXT: setp.ne.b32 %p1, %r3, %r5;
-; COMMON-NEXT: setp.ne.b32 %p2, %r4, %r6;
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; COMMON-NEXT: mov.b32 {%rs3, %rs4}, %r1;
-; COMMON-NEXT: selp.b16 %rs5, %rs4, %rs2, %p2;
-; COMMON-NEXT: selp.b16 %rs6, %rs3, %rs1, %p1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_select_cc_i16_i32_param_0];
+; COMMON-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_i16_i32_param_2];
+; COMMON-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_i16_i32_param_3];
+; COMMON-NEXT: setp.ne.b32 %p1, %r1, %r3;
+; COMMON-NEXT: setp.ne.b32 %p2, %r2, %r4;
+; COMMON-NEXT: ld.param.v2.b16 {%rs3, %rs4}, [test_select_cc_i16_i32_param_1];
+; COMMON-NEXT: selp.b16 %rs5, %rs2, %rs4, %p2;
+; COMMON-NEXT: selp.b16 %rs6, %rs1, %rs3, %p1;
; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs6, %rs5};
; COMMON-NEXT: ret;
<2 x i32> %c, <2 x i32> %d) #0 {
@@ -810,8 +748,8 @@ define <2 x i16> @test_trunc_2xi32_muliple_use0(<2 x i32> %a, ptr %p) #0 {
; I16x2-EMPTY:
; I16x2-NEXT: // %bb.0:
; I16x2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_trunc_2xi32_muliple_use0_param_0];
-; I16x2-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_muliple_use0_param_1];
; I16x2-NEXT: prmt.b32 %r3, %r1, %r2, 0x5410U;
+; I16x2-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_muliple_use0_param_1];
; I16x2-NEXT: mov.b32 %r4, 65537;
; I16x2-NEXT: add.s16x2 %r5, %r3, %r4;
; I16x2-NEXT: st.b32 [%rd1], %r5;
@@ -826,10 +764,10 @@ define <2 x i16> @test_trunc_2xi32_muliple_use0(<2 x i32> %a, ptr %p) #0 {
; NO-I16x2-EMPTY:
; NO-I16x2-NEXT: // %bb.0:
; NO-I16x2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_trunc_2xi32_muliple_use0_param_0];
-; NO-I16x2-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_muliple_use0_param_1];
; NO-I16x2-NEXT: cvt.u16.u32 %rs1, %r2;
; NO-I16x2-NEXT: cvt.u16.u32 %rs2, %r1;
; NO-I16x2-NEXT: mov.b32 %r3, {%rs2, %rs1};
+; NO-I16x2-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_muliple_use0_param_1];
; NO-I16x2-NEXT: add.s16 %rs3, %rs1, 1;
; NO-I16x2-NEXT: add.s16 %rs4, %rs2, 1;
; NO-I16x2-NEXT: st.v2.b16 [%rd1], {%rs4, %rs3};
@@ -851,8 +789,8 @@ define <2 x i16> @test_trunc_2xi32_muliple_use1(<2 x i32> %a, ptr %p) #0 {
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
; COMMON-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_trunc_2xi32_muliple_use1_param_0];
-; COMMON-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_muliple_use1_param_1];
; COMMON-NEXT: prmt.b32 %r3, %r1, %r2, 0x5410U;
+; COMMON-NEXT: ld.param.b64 %rd1, [test_trunc_2xi32_muliple_use1_param_1];
; COMMON-NEXT: add.s32 %r4, %r2, 1;
; COMMON-NEXT: add.s32 %r5, %r1, 1;
; COMMON-NEXT: st.v2.b32 [%rd1], {%r5, %r4};
@@ -886,14 +824,13 @@ define <2 x i32> @test_zext_2xi32(<2 x i16> %a) #0 {
; COMMON-LABEL: test_zext_2xi32(
; COMMON: {
; COMMON-NEXT: .reg .b16 %rs<3>;
-; COMMON-NEXT: .reg .b32 %r<4>;
+; COMMON-NEXT: .reg .b32 %r<3>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r1, [test_zext_2xi32_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; COMMON-NEXT: cvt.u32.u16 %r2, %rs2;
-; COMMON-NEXT: cvt.u32.u16 %r3, %rs1;
-; COMMON-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_zext_2xi32_param_0];
+; COMMON-NEXT: cvt.u32.u16 %r1, %rs2;
+; COMMON-NEXT: cvt.u32.u16 %r2, %rs1;
+; COMMON-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; COMMON-NEXT: ret;
%r = zext <2 x i16> %a to <2 x i32>
ret <2 x i32> %r
@@ -903,12 +840,10 @@ define <2 x i64> @test_zext_2xi64(<2 x i16> %a) #0 {
; COMMON-LABEL: test_zext_2xi64(
; COMMON: {
; COMMON-NEXT: .reg .b16 %rs<3>;
-; COMMON-NEXT: .reg .b32 %r<2>;
; COMMON-NEXT: .reg .b64 %rd<3>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r1, [test_zext_2xi64_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_zext_2xi64_param_0];
; COMMON-NEXT: cvt.u64.u16 %rd1, %rs2;
; COMMON-NEXT: cvt.u64.u16 %rd2, %rs1;
; COMMON-NEXT: st.param.v2.b64 [func_retval0], {%rd2, %rd1};
@@ -963,11 +898,9 @@ define <2 x i16> @test_shufflevector(<2 x i16> %a) #0 {
; COMMON-LABEL: test_shufflevector(
; COMMON: {
; COMMON-NEXT: .reg .b16 %rs<3>;
-; COMMON-NEXT: .reg .b32 %r<2>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r1, [test_shufflevector_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_shufflevector_param_0];
; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs2, %rs1};
; COMMON-NEXT: ret;
%s = shufflevector <2 x i16> %a, <2 x i16> undef, <2 x i32> <i32 1, i32 0>
@@ -975,29 +908,15 @@ define <2 x i16> @test_shufflevector(<2 x i16> %a) #0 {
}
define <2 x i16> @test_insertelement(<2 x i16> %a, i16 %x) #0 {
-; I16x2-LABEL: test_insertelement(
-; I16x2: {
-; I16x2-NEXT: .reg .b16 %rs<3>;
-; I16x2-NEXT: .reg .b32 %r<2>;
-; I16x2-EMPTY:
-; I16x2-NEXT: // %bb.0:
-; I16x2-NEXT: ld.param.b16 %rs1, [test_insertelement_param_1];
-; I16x2-NEXT: ld.param.b32 %r1, [test_insertelement_param_0];
-; I16x2-NEXT: mov.b32 {%rs2, _}, %r1;
-; I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs2, %rs1};
-; I16x2-NEXT: ret;
-;
-; NO-I16x2-LABEL: test_insertelement(
-; NO-I16x2: {
-; NO-I16x2-NEXT: .reg .b16 %rs<3>;
-; NO-I16x2-NEXT: .reg .b32 %r<2>;
-; NO-I16x2-EMPTY:
-; NO-I16x2-NEXT: // %bb.0:
-; NO-I16x2-NEXT: ld.param.b16 %rs1, [test_insertelement_param_1];
-; NO-I16x2-NEXT: ld.param.b32 %r1, [test_insertelement_param_0];
-; NO-I16x2-NEXT: { .reg .b16 tmp; mov.b32 {%rs2, tmp}, %r1; }
-; NO-I16x2-NEXT: st.param.v2.b16 [func_retval0], {%rs2, %rs1};
-; NO-I16x2-NEXT: ret;
+; COMMON-LABEL: test_insertelement(
+; COMMON: {
+; COMMON-NEXT: .reg .b16 %rs<3>;
+; COMMON-EMPTY:
+; COMMON-NEXT: // %bb.0:
+; COMMON-NEXT: ld.param.b16 %rs1, [test_insertelement_param_1];
+; COMMON-NEXT: ld.param.b16 %rs2, [test_insertelement_param_0];
+; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs2, %rs1};
+; COMMON-NEXT: ret;
%i = insertelement <2 x i16> %a, i16 %x, i64 1
ret <2 x i16> %i
}
@@ -1006,11 +925,9 @@ define <2 x i16> @test_fptosi_2xhalf_to_2xi16(<2 x half> %a) #0 {
; COMMON-LABEL: test_fptosi_2xhalf_to_2xi16(
; COMMON: {
; COMMON-NEXT: .reg .b16 %rs<5>;
-; COMMON-NEXT: .reg .b32 %r<2>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r1, [test_fptosi_2xhalf_to_2xi16_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptosi_2xhalf_to_2xi16_param_0];
; COMMON-NEXT: cvt.rzi.s16.f16 %rs3, %rs2;
; COMMON-NEXT: cvt.rzi.s16.f16 %rs4, %rs1;
; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
@@ -1023,11 +940,9 @@ define <2 x i16> @test_fptoui_2xhalf_to_2xi16(<2 x half> %a) #0 {
; COMMON-LABEL: test_fptoui_2xhalf_to_2xi16(
; COMMON: {
; COMMON-NEXT: .reg .b16 %rs<5>;
-; COMMON-NEXT: .reg .b32 %r<2>;
; COMMON-EMPTY:
; COMMON-NEXT: // %bb.0:
-; COMMON-NEXT: ld.param.b32 %r1, [test_fptoui_2xhalf_to_2xi16_param_0];
-; COMMON-NEXT: mov.b32 {%rs1, %rs2}, %r1;
+; COMMON-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptoui_2xhalf_to_2xi16_param_0];
; COMMON-NEXT: cvt.rzi.u16.f16 %rs3, %rs2;
; COMMON-NEXT: cvt.rzi.u16.f16 %rs4, %rs1;
; COMMON-NEXT: st.param.v2.b16 [func_retval0], {%rs4, %rs3};
diff --git a/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll b/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
index 37fc1f140cd20a..e70a6661e78710 100644
--- a/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i32x2-instructions.ll
@@ -45,11 +45,9 @@ define i32 @test_extract_0(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_extract_0(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_0_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, _}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_extract_0_param_0];
; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-I32X2-NEXT: ret;
%e = extractelement <2 x i32> %a, i32 0
@@ -69,11 +67,9 @@ define i32 @test_extract_1(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_extract_1(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_1_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {_, %r1}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_extract_1_param_0+4];
; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-I32X2-NEXT: ret;
%e = extractelement <2 x i32> %a, i32 1
@@ -83,40 +79,34 @@ define i32 @test_extract_1(<2 x i32> %a) #0 {
define i32 @test_extract_i(<2 x i32> %a, i64 %idx) #0 {
; CHECK-NOI32X2-LABEL: test_extract_i(
; CHECK-NOI32X2: {
-; CHECK-NOI32X2-NEXT: .local .align 8 .b8 __local_depot3[8];
-; CHECK-NOI32X2-NEXT: .reg .b64 %SP;
-; CHECK-NOI32X2-NEXT: .reg .b64 %SPL;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<2>;
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: mov.b64 %SPL, __local_depot3;
-; CHECK-NOI32X2-NEXT: cvta.local.u64 %SP, %SPL;
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_extract_i_param_0];
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_extract_i_param_1];
-; CHECK-NOI32X2-NEXT: mov.b64 %rd1, %rd2;
-; CHECK-NOI32X2-NEXT: st.v2.b32 [%SP], {%r1, %r2};
-; CHECK-NOI32X2-NEXT: and.b64 %rd3, %rd1, 1;
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_extract_i_param_1];
+; CHECK-NOI32X2-NEXT: mov.b64 %rd2, %rd1;
+; CHECK-NOI32X2-NEXT: and.b64 %rd3, %rd2, 1;
; CHECK-NOI32X2-NEXT: shl.b64 %rd4, %rd3, 2;
-; CHECK-NOI32X2-NEXT: add.u64 %rd5, %SP, 0;
-; CHECK-NOI32X2-NEXT: or.b64 %rd6, %rd5, %rd4;
-; CHECK-NOI32X2-NEXT: ld.b32 %r3, [%rd6];
-; CHECK-NOI32X2-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NOI32X2-NEXT: mov.b64 %rd5, test_extract_i_param_0;
+; CHECK-NOI32X2-NEXT: add.s64 %rd6, %rd5, %rd4;
+; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [%rd6];
+; CHECK-NOI32X2-NEXT: st.param.b32 [func_retval0], %r1;
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_extract_i(
; CHECK-I32X2: {
-; CHECK-I32X2-NEXT: .reg .pred %p<2>;
-; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
+; CHECK-I32X2-NEXT: .reg .b64 %rd<7>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_extract_i_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_i_param_0];
-; CHECK-I32X2-NEXT: setp.eq.b64 %p1, %rd2, 0;
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-I32X2-NEXT: selp.b32 %r3, %r1, %r2, %p1;
-; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r3;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_extract_i_param_1];
+; CHECK-I32X2-NEXT: mov.b64 %rd2, %rd1;
+; CHECK-I32X2-NEXT: and.b64 %rd3, %rd2, 1;
+; CHECK-I32X2-NEXT: shl.b64 %rd4, %rd3, 2;
+; CHECK-I32X2-NEXT: mov.b64 %rd5, test_extract_i_param_0;
+; CHECK-I32X2-NEXT: add.s64 %rd6, %rd5, %rd4;
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [%rd6];
+; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r1;
; CHECK-I32X2-NEXT: ret;
%e = extractelement <2 x i32> %a, i64 %idx
ret i32 %e
@@ -128,8 +118,8 @@ define <2 x i32> @test_add(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_add_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_add_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_add_param_1];
; CHECK-NOI32X2-NEXT: add.s32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: add.s32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -138,15 +128,12 @@ define <2 x i32> @test_add(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_add(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_add_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_add_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: add.s32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: add.s32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_add_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_add_param_1];
+; CHECK-I32X2-NEXT: add.s32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: add.s32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = add <2 x i32> %a, %b
@@ -168,11 +155,9 @@ define <2 x i32> @test_add_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_add_imm_0(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_add_imm_0_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_add_imm_0_param_0];
; CHECK-I32X2-NEXT: add.s32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: add.s32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -196,11 +181,9 @@ define <2 x i32> @test_add_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_add_imm_1(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_add_imm_1_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_add_imm_1_param_0];
; CHECK-I32X2-NEXT: add.s32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: add.s32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -215,8 +198,8 @@ define <2 x i32> @test_sub(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_sub_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_sub_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_sub_param_1];
; CHECK-NOI32X2-NEXT: sub.s32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: sub.s32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -225,15 +208,12 @@ define <2 x i32> @test_sub(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_sub(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_sub_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_sub_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: sub.s32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: sub.s32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_sub_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_sub_param_1];
+; CHECK-I32X2-NEXT: sub.s32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: sub.s32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = sub <2 x i32> %a, %b
@@ -246,8 +226,8 @@ define <2 x i32> @test_smax(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_smax_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_smax_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_smax_param_1];
; CHECK-NOI32X2-NEXT: max.s32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: max.s32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -256,15 +236,12 @@ define <2 x i32> @test_smax(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_smax(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_smax_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_smax_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: max.s32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: max.s32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_smax_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_smax_param_1];
+; CHECK-I32X2-NEXT: max.s32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: max.s32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp sgt <2 x i32> %a, %b
@@ -278,8 +255,8 @@ define <2 x i32> @test_umax(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_umax_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_umax_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_umax_param_1];
; CHECK-NOI32X2-NEXT: max.u32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: max.u32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -288,15 +265,12 @@ define <2 x i32> @test_umax(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_umax(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_umax_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_umax_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: max.u32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: max.u32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_umax_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_umax_param_1];
+; CHECK-I32X2-NEXT: max.u32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: max.u32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp ugt <2 x i32> %a, %b
@@ -310,8 +284,8 @@ define <2 x i32> @test_smin(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_smin_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_smin_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_smin_param_1];
; CHECK-NOI32X2-NEXT: min.s32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: min.s32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -320,15 +294,12 @@ define <2 x i32> @test_smin(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_smin(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_smin_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_smin_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: min.s32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: min.s32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_smin_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_smin_param_1];
+; CHECK-I32X2-NEXT: min.s32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: min.s32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp sle <2 x i32> %a, %b
@@ -342,8 +313,8 @@ define <2 x i32> @test_umin(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_umin_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_umin_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_umin_param_1];
; CHECK-NOI32X2-NEXT: min.u32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: min.u32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -352,15 +323,12 @@ define <2 x i32> @test_umin(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_umin(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_umin_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_umin_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: min.u32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: min.u32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_umin_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_umin_param_1];
+; CHECK-I32X2-NEXT: min.u32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: min.u32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp ule <2 x i32> %a, %b
@@ -375,11 +343,11 @@ define <2 x i32> @test_eq(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<9>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_eq_param_2];
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_eq_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_eq_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_eq_param_1];
; CHECK-NOI32X2-NEXT: setp.eq.b32 %p1, %r1, %r3;
; CHECK-NOI32X2-NEXT: setp.eq.b32 %p2, %r2, %r4;
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_eq_param_2];
; CHECK-NOI32X2-NEXT: selp.b32 %r7, %r2, %r6, %p2;
; CHECK-NOI32X2-NEXT: selp.b32 %r8, %r1, %r5, %p1;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
@@ -389,19 +357,15 @@ define <2 x i32> @test_eq(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .pred %p<3>;
; CHECK-I32X2-NEXT: .reg .b32 %r<9>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_eq_param_2];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_eq_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_eq_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: setp.eq.b32 %p1, %r3, %r1;
-; CHECK-I32X2-NEXT: setp.eq.b32 %p2, %r4, %r2;
-; CHECK-I32X2-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-I32X2-NEXT: selp.b32 %r7, %r4, %r6, %p2;
-; CHECK-I32X2-NEXT: selp.b32 %r8, %r3, %r5, %p1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_eq_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_eq_param_1];
+; CHECK-I32X2-NEXT: setp.eq.b32 %p1, %r1, %r3;
+; CHECK-I32X2-NEXT: setp.eq.b32 %p2, %r2, %r4;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [test_eq_param_2];
+; CHECK-I32X2-NEXT: selp.b32 %r7, %r2, %r6, %p2;
+; CHECK-I32X2-NEXT: selp.b32 %r8, %r1, %r5, %p1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp eq <2 x i32> %a, %b
@@ -416,11 +380,11 @@ define <2 x i32> @test_ne(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<9>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_ne_param_2];
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_ne_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_ne_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_ne_param_1];
; CHECK-NOI32X2-NEXT: setp.ne.b32 %p1, %r1, %r3;
; CHECK-NOI32X2-NEXT: setp.ne.b32 %p2, %r2, %r4;
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_ne_param_2];
; CHECK-NOI32X2-NEXT: selp.b32 %r7, %r2, %r6, %p2;
; CHECK-NOI32X2-NEXT: selp.b32 %r8, %r1, %r5, %p1;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r8, %r7};
@@ -430,19 +394,15 @@ define <2 x i32> @test_ne(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) #0 {
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .pred %p<3>;
; CHECK-I32X2-NEXT: .reg .b32 %r<9>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_ne_param_2];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ne_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ne_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: setp.ne.b32 %p1, %r3, %r1;
-; CHECK-I32X2-NEXT: setp.ne.b32 %p2, %r4, %r2;
-; CHECK-I32X2-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-I32X2-NEXT: selp.b32 %r7, %r4, %r6, %p2;
-; CHECK-I32X2-NEXT: selp.b32 %r8, %r3, %r5, %p1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_ne_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_ne_param_1];
+; CHECK-I32X2-NEXT: setp.ne.b32 %p1, %r1, %r3;
+; CHECK-I32X2-NEXT: setp.ne.b32 %p2, %r2, %r4;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [test_ne_param_2];
+; CHECK-I32X2-NEXT: selp.b32 %r7, %r2, %r6, %p2;
+; CHECK-I32X2-NEXT: selp.b32 %r8, %r1, %r5, %p1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r8, %r7};
; CHECK-I32X2-NEXT: ret;
%cmp = icmp ne <2 x i32> %a, %b
@@ -456,8 +416,8 @@ define <2 x i32> @test_mul(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_mul_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_mul_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_mul_param_1];
; CHECK-NOI32X2-NEXT: mul.lo.s32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: mul.lo.s32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -466,15 +426,12 @@ define <2 x i32> @test_mul(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_mul(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_mul_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_mul_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: mul.lo.s32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: mul.lo.s32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_mul_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_mul_param_1];
+; CHECK-I32X2-NEXT: mul.lo.s32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: mul.lo.s32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = mul <2 x i32> %a, %b
@@ -487,8 +444,8 @@ define <2 x i32> @test_or(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_or_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_or_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_or_param_1];
; CHECK-NOI32X2-NEXT: or.b32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: or.b32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -497,15 +454,12 @@ define <2 x i32> @test_or(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_or(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_or_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_or_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: or.b32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: or.b32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_or_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_or_param_1];
+; CHECK-I32X2-NEXT: or.b32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: or.b32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = or <2 x i32> %a, %b
@@ -551,11 +505,9 @@ define <2 x i32> @test_or_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_or_imm_0(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_or_imm_0_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_or_imm_0_param_0];
; CHECK-I32X2-NEXT: or.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: or.b32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -579,11 +531,9 @@ define <2 x i32> @test_or_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_or_imm_1(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_or_imm_1_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_or_imm_1_param_0];
; CHECK-I32X2-NEXT: or.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: or.b32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -598,8 +548,8 @@ define <2 x i32> @test_xor(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_xor_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_xor_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_xor_param_1];
; CHECK-NOI32X2-NEXT: xor.b32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: xor.b32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -608,15 +558,12 @@ define <2 x i32> @test_xor(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_xor(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_xor_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_xor_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: xor.b32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: xor.b32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_xor_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_xor_param_1];
+; CHECK-I32X2-NEXT: xor.b32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: xor.b32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = xor <2 x i32> %a, %b
@@ -626,19 +573,15 @@ define <2 x i32> @test_xor(<2 x i32> %a, <2 x i32> %b) #0 {
define <2 x i32> @test_xor_computed(i32 %a) {
; CHECK-NOI32X2-LABEL: test_xor_computed(
; CHECK-NOI32X2: {
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<2>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_xor_computed_param_0];
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {0, 5};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_xor_computed(
; CHECK-I32X2: {
-; CHECK-I32X2-NEXT: .reg .b32 %r<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_xor_computed_param_0];
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {0, 5};
; CHECK-I32X2-NEXT: ret;
%ins.0 = insertelement <2 x i32> zeroinitializer, i32 %a, i32 0
@@ -662,11 +605,9 @@ define <2 x i32> @test_xor_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_xor_imm_0(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_xor_imm_0_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_xor_imm_0_param_0];
; CHECK-I32X2-NEXT: xor.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: xor.b32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -690,11 +631,9 @@ define <2 x i32> @test_xor_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_xor_imm_1(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_xor_imm_1_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_xor_imm_1_param_0];
; CHECK-I32X2-NEXT: xor.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: xor.b32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -709,8 +648,8 @@ define <2 x i32> @test_and(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_and_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_and_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_and_param_1];
; CHECK-NOI32X2-NEXT: and.b32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: and.b32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
@@ -719,15 +658,12 @@ define <2 x i32> @test_and(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-LABEL: test_and(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<7>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_and_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_and_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-I32X2-NEXT: and.b32 %r5, %r4, %r2;
-; CHECK-I32X2-NEXT: and.b32 %r6, %r3, %r1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_and_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_and_param_1];
+; CHECK-I32X2-NEXT: and.b32 %r5, %r2, %r4;
+; CHECK-I32X2-NEXT: and.b32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r6, %r5};
; CHECK-I32X2-NEXT: ret;
%r = and <2 x i32> %a, %b
@@ -773,11 +709,9 @@ define <2 x i32> @test_and_imm_0(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_and_imm_0(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_and_imm_0_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_and_imm_0_param_0];
; CHECK-I32X2-NEXT: and.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: and.b32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -801,11 +735,9 @@ define <2 x i32> @test_and_imm_1(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_and_imm_1(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_and_imm_1_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_and_imm_1_param_0];
; CHECK-I32X2-NEXT: and.b32 %r3, %r2, 2;
; CHECK-I32X2-NEXT: and.b32 %r4, %r1, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -821,9 +753,9 @@ define void @test_ldst_v2i32(ptr %a, ptr %b) {
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2i32_param_1];
; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v2i32_param_0];
; CHECK-NOI32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2i32_param_1];
; CHECK-NOI32X2-NEXT: st.v2.b32 [%rd2], {%r1, %r2};
; CHECK-NOI32X2-NEXT: ret;
;
@@ -832,10 +764,10 @@ define void @test_ldst_v2i32(ptr %a, ptr %b) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v2i32_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v2i32_param_0];
-; CHECK-I32X2-NEXT: ld.b64 %rd3, [%rd1];
-; CHECK-I32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-I32X2-NEXT: ld.b64 %rd2, [%rd1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_ldst_v2i32_param_1];
+; CHECK-I32X2-NEXT: st.b64 [%rd3], %rd2;
; CHECK-I32X2-NEXT: ret;
%t1 = load <2 x i32>, ptr %a
store <2 x i32> %t1, ptr %b, align 16
@@ -849,12 +781,12 @@ define void @test_ldst_v3i32(ptr %a, ptr %b) {
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v3i32_param_1];
; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v3i32_param_0];
-; CHECK-NOI32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-NOI32X2-NEXT: ld.b64 %rd2, [%rd1];
; CHECK-NOI32X2-NEXT: ld.b32 %r1, [%rd1+8];
-; CHECK-NOI32X2-NEXT: st.b32 [%rd2+8], %r1;
-; CHECK-NOI32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_ldst_v3i32_param_1];
+; CHECK-NOI32X2-NEXT: st.b32 [%rd3+8], %r1;
+; CHECK-NOI32X2-NEXT: st.b64 [%rd3], %rd2;
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_ldst_v3i32(
@@ -863,12 +795,12 @@ define void @test_ldst_v3i32(ptr %a, ptr %b) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v3i32_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v3i32_param_0];
-; CHECK-I32X2-NEXT: ld.b64 %rd3, [%rd1];
+; CHECK-I32X2-NEXT: ld.b64 %rd2, [%rd1];
; CHECK-I32X2-NEXT: ld.b32 %r1, [%rd1+8];
-; CHECK-I32X2-NEXT: st.b32 [%rd2+8], %r1;
-; CHECK-I32X2-NEXT: st.b64 [%rd2], %rd3;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_ldst_v3i32_param_1];
+; CHECK-I32X2-NEXT: st.b32 [%rd3+8], %r1;
+; CHECK-I32X2-NEXT: st.b64 [%rd3], %rd2;
; CHECK-I32X2-NEXT: ret;
%t1 = load <3 x i32>, ptr %a
store <3 x i32> %t1, ptr %b, align 16
@@ -882,9 +814,9 @@ define void @test_ldst_v4i32(ptr %a, ptr %b) {
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v4i32_param_1];
; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v4i32_param_0];
; CHECK-NOI32X2-NEXT: ld.v4.b32 {%r1, %r2, %r3, %r4}, [%rd1];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v4i32_param_1];
; CHECK-NOI32X2-NEXT: st.v4.b32 [%rd2], {%r1, %r2, %r3, %r4};
; CHECK-NOI32X2-NEXT: ret;
;
@@ -893,10 +825,10 @@ define void @test_ldst_v4i32(ptr %a, ptr %b) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v4i32_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v4i32_param_0];
-; CHECK-I32X2-NEXT: ld.v2.b64 {%rd3, %rd4}, [%rd1];
-; CHECK-I32X2-NEXT: st.v2.b64 [%rd2], {%rd3, %rd4};
+; CHECK-I32X2-NEXT: ld.v2.b64 {%rd2, %rd3}, [%rd1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd4, [test_ldst_v4i32_param_1];
+; CHECK-I32X2-NEXT: st.v2.b64 [%rd4], {%rd2, %rd3};
; CHECK-I32X2-NEXT: ret;
%t1 = load <4 x i32>, ptr %a
store <4 x i32> %t1, ptr %b, align 16
@@ -910,7 +842,6 @@ define void @test_ldst_v2i32_unaligned(ptr %a, ptr %b) {
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2i32_unaligned_param_1];
; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_ldst_v2i32_unaligned_param_0];
; CHECK-NOI32X2-NEXT: ld.b8 %r1, [%rd1+2];
; CHECK-NOI32X2-NEXT: shl.b32 %r2, %r1, 16;
@@ -923,6 +854,7 @@ define void @test_ldst_v2i32_unaligned(ptr %a, ptr %b) {
; CHECK-NOI32X2-NEXT: ld.b8 %r9, [%rd1+5];
; CHECK-NOI32X2-NEXT: ld.b8 %r10, [%rd1+6];
; CHECK-NOI32X2-NEXT: ld.b8 %r11, [%rd1+7];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_ldst_v2i32_unaligned_param_1];
; CHECK-NOI32X2-NEXT: st.b8 [%rd2+7], %r11;
; CHECK-NOI32X2-NEXT: st.b8 [%rd2+6], %r10;
; CHECK-NOI32X2-NEXT: st.b8 [%rd2+5], %r9;
@@ -939,41 +871,41 @@ define void @test_ldst_v2i32_unaligned(ptr %a, ptr %b) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<28>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_ldst_v2i32_unaligned_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_ldst_v2i32_unaligned_param_0];
-; CHECK-I32X2-NEXT: ld.b8 %rd3, [%rd1];
-; CHECK-I32X2-NEXT: ld.b8 %rd4, [%rd1+1];
-; CHECK-I32X2-NEXT: shl.b64 %rd5, %rd4, 8;
-; CHECK-I32X2-NEXT: or.b64 %rd6, %rd5, %rd3;
-; CHECK-I32X2-NEXT: ld.b8 %rd7, [%rd1+2];
-; CHECK-I32X2-NEXT: shl.b64 %rd8, %rd7, 16;
-; CHECK-I32X2-NEXT: ld.b8 %rd9, [%rd1+3];
-; CHECK-I32X2-NEXT: shl.b64 %rd10, %rd9, 24;
-; CHECK-I32X2-NEXT: or.b64 %rd11, %rd10, %rd8;
-; CHECK-I32X2-NEXT: or.b64 %rd12, %rd11, %rd6;
-; CHECK-I32X2-NEXT: ld.b8 %rd13, [%rd1+4];
-; CHECK-I32X2-NEXT: ld.b8 %rd14, [%rd1+5];
-; CHECK-I32X2-NEXT: shl.b64 %rd15, %rd14, 8;
-; CHECK-I32X2-NEXT: or.b64 %rd16, %rd15, %rd13;
-; CHECK-I32X2-NEXT: ld.b8 %rd17, [%rd1+6];
-; CHECK-I32X2-NEXT: shl.b64 %rd18, %rd17, 16;
-; CHECK-I32X2-NEXT: ld.b8 %rd19, [%rd1+7];
-; CHECK-I32X2-NEXT: shl.b64 %rd20, %rd19, 24;
-; CHECK-I32X2-NEXT: or.b64 %rd21, %rd20, %rd18;
-; CHECK-I32X2-NEXT: or.b64 %rd22, %rd21, %rd16;
-; CHECK-I32X2-NEXT: shl.b64 %rd23, %rd22, 32;
-; CHECK-I32X2-NEXT: or.b64 %rd24, %rd23, %rd12;
-; CHECK-I32X2-NEXT: st.b8 [%rd2+6], %rd17;
-; CHECK-I32X2-NEXT: shr.u64 %rd25, %rd24, 56;
-; CHECK-I32X2-NEXT: st.b8 [%rd2+7], %rd25;
-; CHECK-I32X2-NEXT: st.b8 [%rd2+4], %rd13;
-; CHECK-I32X2-NEXT: shr.u64 %rd26, %rd24, 40;
-; CHECK-I32X2-NEXT: st.b8 [%rd2+5], %rd26;
-; CHECK-I32X2-NEXT: st.b8 [%rd2+1], %rd4;
-; CHECK-I32X2-NEXT: st.b8 [%rd2], %rd3;
-; CHECK-I32X2-NEXT: st.b8 [%rd2+3], %rd9;
-; CHECK-I32X2-NEXT: shr.u64 %rd27, %rd24, 16;
-; CHECK-I32X2-NEXT: st.b8 [%rd2+2], %rd27;
+; CHECK-I32X2-NEXT: ld.b8 %rd2, [%rd1];
+; CHECK-I32X2-NEXT: ld.b8 %rd3, [%rd1+1];
+; CHECK-I32X2-NEXT: shl.b64 %rd4, %rd3, 8;
+; CHECK-I32X2-NEXT: or.b64 %rd5, %rd4, %rd2;
+; CHECK-I32X2-NEXT: ld.b8 %rd6, [%rd1+2];
+; CHECK-I32X2-NEXT: shl.b64 %rd7, %rd6, 16;
+; CHECK-I32X2-NEXT: ld.b8 %rd8, [%rd1+3];
+; CHECK-I32X2-NEXT: shl.b64 %rd9, %rd8, 24;
+; CHECK-I32X2-NEXT: or.b64 %rd10, %rd9, %rd7;
+; CHECK-I32X2-NEXT: or.b64 %rd11, %rd10, %rd5;
+; CHECK-I32X2-NEXT: ld.b8 %rd12, [%rd1+4];
+; CHECK-I32X2-NEXT: ld.b8 %rd13, [%rd1+5];
+; CHECK-I32X2-NEXT: shl.b64 %rd14, %rd13, 8;
+; CHECK-I32X2-NEXT: or.b64 %rd15, %rd14, %rd12;
+; CHECK-I32X2-NEXT: ld.b8 %rd16, [%rd1+6];
+; CHECK-I32X2-NEXT: shl.b64 %rd17, %rd16, 16;
+; CHECK-I32X2-NEXT: ld.b8 %rd18, [%rd1+7];
+; CHECK-I32X2-NEXT: shl.b64 %rd19, %rd18, 24;
+; CHECK-I32X2-NEXT: or.b64 %rd20, %rd19, %rd17;
+; CHECK-I32X2-NEXT: or.b64 %rd21, %rd20, %rd15;
+; CHECK-I32X2-NEXT: shl.b64 %rd22, %rd21, 32;
+; CHECK-I32X2-NEXT: or.b64 %rd23, %rd22, %rd11;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd24, [test_ldst_v2i32_unaligned_param_1];
+; CHECK-I32X2-NEXT: st.b8 [%rd24+6], %rd16;
+; CHECK-I32X2-NEXT: shr.u64 %rd25, %rd23, 56;
+; CHECK-I32X2-NEXT: st.b8 [%rd24+7], %rd25;
+; CHECK-I32X2-NEXT: st.b8 [%rd24+4], %rd12;
+; CHECK-I32X2-NEXT: shr.u64 %rd26, %rd23, 40;
+; CHECK-I32X2-NEXT: st.b8 [%rd24+5], %rd26;
+; CHECK-I32X2-NEXT: st.b8 [%rd24+1], %rd3;
+; CHECK-I32X2-NEXT: st.b8 [%rd24], %rd2;
+; CHECK-I32X2-NEXT: st.b8 [%rd24+3], %rd8;
+; CHECK-I32X2-NEXT: shr.u64 %rd27, %rd23, 16;
+; CHECK-I32X2-NEXT: st.b8 [%rd24+2], %rd27;
; CHECK-I32X2-NEXT: ret;
%t1 = load <2 x i32>, ptr %a, align 1
store <2 x i32> %t1, ptr %b, align 1
@@ -988,12 +920,12 @@ define <2 x i32> @test_call(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_call_param_0];
; CHECK-NOI32X2-NEXT: { // callseq 0, 0
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 retval0[8];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_param_1];
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [param1], {%r3, %r4};
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [param0], {%r1, %r2};
; CHECK-NOI32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
@@ -1007,12 +939,12 @@ define <2 x i32> @test_call(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_call_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_call_param_0];
; CHECK-I32X2-NEXT: { // callseq 0, 0
; CHECK-I32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 retval0[8];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_call_param_1];
; CHECK-I32X2-NEXT: st.param::func.b64 [param1], %rd2;
; CHECK-I32X2-NEXT: st.param::func.b64 [param0], %rd1;
; CHECK-I32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
@@ -1030,13 +962,13 @@ define <2 x i32> @test_call_flipped(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_flipped_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_call_flipped_param_0];
; CHECK-NOI32X2-NEXT: { // callseq 1, 0
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [param1], {%r1, %r2};
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_call_flipped_param_1];
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [param0], {%r3, %r4};
; CHECK-NOI32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [retval0];
@@ -1049,13 +981,13 @@ define <2 x i32> @test_call_flipped(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_call_flipped_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_call_flipped_param_0];
; CHECK-I32X2-NEXT: { // callseq 1, 0
; CHECK-I32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-I32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_call_flipped_param_1];
; CHECK-I32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-I32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
@@ -1072,13 +1004,13 @@ define <2 x i32> @test_tailcall_flipped(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_tailcall_flipped_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_tailcall_flipped_param_0];
; CHECK-NOI32X2-NEXT: { // callseq 2, 0
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-NOI32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [param1], {%r1, %r2};
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_tailcall_flipped_param_1];
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [param0], {%r3, %r4};
; CHECK-NOI32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [retval0];
@@ -1091,13 +1023,13 @@ define <2 x i32> @test_tailcall_flipped(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_tailcall_flipped_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_tailcall_flipped_param_0];
; CHECK-I32X2-NEXT: { // callseq 2, 0
; CHECK-I32X2-NEXT: .param .align 8 .b8 param0[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 param1[8];
; CHECK-I32X2-NEXT: .param .align 8 .b8 retval0[8];
; CHECK-I32X2-NEXT: st.param::func.b64 [param1], %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_tailcall_flipped_param_1];
; CHECK-I32X2-NEXT: st.param::func.b64 [param0], %rd2;
; CHECK-I32X2-NEXT: call.uni (retval0), test_callee, (param0, param1);
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [retval0];
@@ -1112,34 +1044,38 @@ define <2 x i32> @test_select(<2 x i32> %a, <2 x i32> %b, i1 zeroext %c) #0 {
; CHECK-NOI32X2-LABEL: test_select(
; CHECK-NOI32X2: {
; CHECK-NOI32X2-NEXT: .reg .pred %p<2>;
-; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<7>;
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<4>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<3>;
+; CHECK-NOI32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
; CHECK-NOI32X2-NEXT: ld.param.b8 %rs1, [test_select_param_2];
-; CHECK-NOI32X2-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-NOI32X2-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_param_1];
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_param_0];
-; CHECK-NOI32X2-NEXT: selp.b32 %r5, %r2, %r4, %p1;
-; CHECK-NOI32X2-NEXT: selp.b32 %r6, %r1, %r3, %p1;
-; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r6, %r5};
+; CHECK-NOI32X2-NEXT: mov.b16 %rs2, %rs1;
+; CHECK-NOI32X2-NEXT: and.b16 %rs3, %rs2, 1;
+; CHECK-NOI32X2-NEXT: setp.ne.b16 %p1, %rs3, 0;
+; CHECK-NOI32X2-NEXT: mov.b64 %rd1, test_select_param_1;
+; CHECK-NOI32X2-NEXT: mov.b64 %rd2, test_select_param_0;
+; CHECK-NOI32X2-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [%rd3];
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r1, %r2};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_select(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .pred %p<2>;
-; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-I32X2-NEXT: .reg .b16 %rs<4>;
+; CHECK-I32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
; CHECK-I32X2-NEXT: ld.param::func.b8 %rs1, [test_select_param_2];
-; CHECK-I32X2-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-I32X2-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_select_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_select_param_0];
-; CHECK-I32X2-NEXT: selp.b64 %rd3, %rd1, %rd2, %p1;
-; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd3;
+; CHECK-I32X2-NEXT: mov.b16 %rs2, %rs1;
+; CHECK-I32X2-NEXT: and.b16 %rs3, %rs2, 1;
+; CHECK-I32X2-NEXT: setp.ne.b16 %p1, %rs3, 0;
+; CHECK-I32X2-NEXT: mov.b64 %rd1, test_select_param_1;
+; CHECK-I32X2-NEXT: mov.b64 %rd2, test_select_param_0;
+; CHECK-I32X2-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd4, [%rd3];
+; CHECK-I32X2-NEXT: st.param::func.b64 [func_retval0], %rd4;
; CHECK-I32X2-NEXT: ret;
%r = select i1 %c, <2 x i32> %a, <2 x i32> %b
ret <2 x i32> %r
@@ -1152,14 +1088,14 @@ define <2 x i32> @test_select_cc(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x
; CHECK-NOI32X2-NEXT: .reg .b32 %r<11>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r7, %r8}, [test_select_cc_param_3];
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_select_cc_param_2];
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_select_cc_param_0];
-; CHECK-NOI32X2-NEXT: setp.ne.b32 %p1, %r5, %r7;
-; CHECK-NOI32X2-NEXT: setp.ne.b32 %p2, %r6, %r8;
-; CHECK-NOI32X2-NEXT: selp.b32 %r9, %r2, %r4, %p2;
-; CHECK-NOI32X2-NEXT: selp.b32 %r10, %r1, %r3, %p1;
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_select_cc_param_2];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r5, %r6}, [test_select_cc_param_3];
+; CHECK-NOI32X2-NEXT: setp.ne.b32 %p1, %r3, %r5;
+; CHECK-NOI32X2-NEXT: setp.ne.b32 %p2, %r4, %r6;
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r7, %r8}, [test_select_cc_param_1];
+; CHECK-NOI32X2-NEXT: selp.b32 %r9, %r2, %r8, %p2;
+; CHECK-NOI32X2-NEXT: selp.b32 %r10, %r1, %r7, %p1;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-NOI32X2-NEXT: ret;
;
@@ -1167,21 +1103,16 @@ define <2 x i32> @test_select_cc(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c, <2 x
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .pred %p<3>;
; CHECK-I32X2-NEXT: .reg .b32 %r<11>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<5>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd4, [test_select_cc_param_3];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_select_cc_param_2];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_select_cc_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_select_cc_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-I32X2-NEXT: setp.ne.b32 %p1, %r3, %r1;
-; CHECK-I32X2-NEXT: setp.ne.b32 %p2, %r4, %r2;
-; CHECK-I32X2-NEXT: mov.b64 {%r5, %r6}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {%r7, %r8}, %rd1;
-; CHECK-I32X2-NEXT: selp.b32 %r9, %r8, %r6, %p2;
-; CHECK-I32X2-NEXT: selp.b32 %r10, %r7, %r5, %p1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_select_cc_param_0];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r3, %r4}, [test_select_cc_param_2];
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [test_select_cc_param_3];
+; CHECK-I32X2-NEXT: setp.ne.b32 %p1, %r3, %r5;
+; CHECK-I32X2-NEXT: setp.ne.b32 %p2, %r4, %r6;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r7, %r8}, [test_select_cc_param_1];
+; CHECK-I32X2-NEXT: selp.b32 %r9, %r2, %r8, %p2;
+; CHECK-I32X2-NEXT: selp.b32 %r10, %r1, %r7, %p1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r10, %r9};
; CHECK-I32X2-NEXT: ret;
%cc = icmp ne <2 x i32> %c, %d
@@ -1203,11 +1134,9 @@ define <2 x i16> @test_trunc_2xi32_to_2xi16(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_trunc_2xi32_to_2xi16(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_2xi32_to_2xi16_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_trunc_2xi32_to_2xi16_param_0];
; CHECK-I32X2-NEXT: prmt.b32 %r3, %r1, %r2, 0x5410U;
; CHECK-I32X2-NEXT: st.param::func.b32 [func_retval0], %r3;
; CHECK-I32X2-NEXT: ret;
@@ -1232,11 +1161,9 @@ define <2 x i8> @test_trunc_2xi32_to_2xi8(<2 x i32> %a) #0 {
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_2xi32_to_2xi8_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_trunc_2xi32_to_2xi8_param_0];
; CHECK-I32X2-NEXT: cvt.u16.u32 %rs1, %r2;
; CHECK-I32X2-NEXT: cvt.u16.u32 %rs2, %r1;
; CHECK-I32X2-NEXT: st.param::func.v2.b8 [func_retval0], {%rs2, %rs1};
@@ -1259,11 +1186,9 @@ define <2 x i1> @test_trunc_2xi32_to_2xi1(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_trunc_2xi32_to_2xi1(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_trunc_2xi32_to_2xi1_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_trunc_2xi32_to_2xi1_param_0];
; CHECK-I32X2-NEXT: st.param::func.b8 [func_retval0], %r1;
; CHECK-I32X2-NEXT: st.param::func.b8 [func_retval0+1], %r2;
; CHECK-I32X2-NEXT: ret;
@@ -1303,27 +1228,25 @@ define <2 x i32> @test_zext_2xi16_to_2xi32(<2 x i16> %a) #0 {
; CHECK-NOI32X2-LABEL: test_zext_2xi16_to_2xi32(
; CHECK-NOI32X2: {
; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_zext_2xi16_to_2xi32_param_0];
-; CHECK-NOI32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_zext_2xi16_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_zext_2xi16_to_2xi32(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_zext_2xi16_to_2xi32_param_0];
-; CHECK-I32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: ld.param::func.v2.b16 {%rs1, %rs2}, [test_zext_2xi16_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%r = zext <2 x i16> %a to <2 x i32>
ret <2 x i32> %r
@@ -1333,27 +1256,25 @@ define <2 x i32> @test_zext_2xi8_to_2xi32(<2 x i8> %a) #0 {
; CHECK-NOI32X2-LABEL: test_zext_2xi8_to_2xi32(
; CHECK-NOI32X2: {
; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
; CHECK-NOI32X2-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_zext_2xi8_to_2xi32_param_0];
-; CHECK-NOI32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_zext_2xi8_to_2xi32(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
; CHECK-I32X2-NEXT: ld.param::func.v2.b8 {%rs1, %rs2}, [test_zext_2xi8_to_2xi32_param_0];
-; CHECK-I32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r3, %rs1;
-; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%r = zext <2 x i8> %a to <2 x i32>
ret <2 x i32> %r
@@ -1362,40 +1283,24 @@ define <2 x i32> @test_zext_2xi8_to_2xi32(<2 x i8> %a) #0 {
define <2 x i32> @test_zext_2xi1_to_2xi32(<2 x i1> %a) #0 {
; CHECK-NOI32X2-LABEL: test_zext_2xi1_to_2xi32(
; CHECK-NOI32X2: {
-; CHECK-NOI32X2-NEXT: .reg .pred %p<3>;
-; CHECK-NOI32X2-NEXT: .reg .b16 %rs<5>;
; CHECK-NOI32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b8 %rs1, [test_zext_2xi1_to_2xi32_param_0+1];
-; CHECK-NOI32X2-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-NOI32X2-NEXT: setp.ne.b16 %p2, %rs2, 0;
-; CHECK-NOI32X2-NEXT: ld.param.b8 %rs3, [test_zext_2xi1_to_2xi32_param_0];
-; CHECK-NOI32X2-NEXT: and.b16 %rs4, %rs3, 1;
-; CHECK-NOI32X2-NEXT: setp.ne.b16 %p1, %rs4, 0;
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r1, %rs1;
+; CHECK-NOI32X2-NEXT: ld.param.b8 %r1, [test_zext_2xi1_to_2xi32_param_0+1];
; CHECK-NOI32X2-NEXT: and.b32 %r2, %r1, 1;
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r3, %rs3;
+; CHECK-NOI32X2-NEXT: ld.param.b8 %r3, [test_zext_2xi1_to_2xi32_param_0];
; CHECK-NOI32X2-NEXT: and.b32 %r4, %r3, 1;
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r2};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_zext_2xi1_to_2xi32(
; CHECK-I32X2: {
-; CHECK-I32X2-NEXT: .reg .pred %p<3>;
-; CHECK-I32X2-NEXT: .reg .b16 %rs<5>;
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b8 %rs1, [test_zext_2xi1_to_2xi32_param_0+1];
-; CHECK-I32X2-NEXT: and.b16 %rs2, %rs1, 1;
-; CHECK-I32X2-NEXT: setp.ne.b16 %p2, %rs2, 0;
-; CHECK-I32X2-NEXT: ld.param::func.b8 %rs3, [test_zext_2xi1_to_2xi32_param_0];
-; CHECK-I32X2-NEXT: and.b16 %rs4, %rs3, 1;
-; CHECK-I32X2-NEXT: setp.ne.b16 %p1, %rs4, 0;
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r1, %rs1;
+; CHECK-I32X2-NEXT: ld.param::func.b8 %r1, [test_zext_2xi1_to_2xi32_param_0+1];
; CHECK-I32X2-NEXT: and.b32 %r2, %r1, 1;
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r3, %rs3;
+; CHECK-I32X2-NEXT: ld.param::func.b8 %r3, [test_zext_2xi1_to_2xi32_param_0];
; CHECK-I32X2-NEXT: and.b32 %r4, %r3, 1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r2};
; CHECK-I32X2-NEXT: ret;
@@ -1419,14 +1324,13 @@ define <2 x i64> @test_zext_2xi64(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_zext_2xi64(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
+; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_zext_2xi64_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
-; CHECK-I32X2-NEXT: cvt.u64.u32 %rd2, %r2;
-; CHECK-I32X2-NEXT: cvt.u64.u32 %rd3, %r1;
-; CHECK-I32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd3, %rd2};
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_zext_2xi64_param_0];
+; CHECK-I32X2-NEXT: cvt.u64.u32 %rd1, %r2;
+; CHECK-I32X2-NEXT: cvt.u64.u32 %rd2, %r1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b64 [func_retval0], {%rd2, %rd1};
; CHECK-I32X2-NEXT: ret;
%r = zext <2 x i32> %a to <2 x i64>
ret <2 x i64> %r
@@ -1559,11 +1463,9 @@ define <2 x i32> @test_shufflevector(<2 x i32> %a) #0 {
; CHECK-I32X2-LABEL: test_shufflevector(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_shufflevector_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_shufflevector_param_0];
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%s = shufflevector <2 x i32> %a, <2 x i32> poison, <2 x i32> <i32 1, i32 0>
@@ -1576,21 +1478,18 @@ define <2 x i32> @test_shufflevector_2(<2 x i32> %a, <2 x i32> %b) #0 {
; CHECK-NOI32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_shufflevector_2_param_1];
; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_shufflevector_2_param_0];
+; CHECK-NOI32X2-NEXT: ld.param.v2.b32 {%r3, %r4}, [test_shufflevector_2_param_1];
; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r4};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_shufflevector_2(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_shufflevector_2_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_shufflevector_2_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {_, %r1}, %rd2;
-; CHECK-I32X2-NEXT: mov.b64 {_, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_shufflevector_2_param_1+4];
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r2, [test_shufflevector_2_param_0+4];
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%s = shufflevector <2 x i32> %a, <2 x i32> %b, <2 x i32> <i32 1, i32 3>
@@ -1612,12 +1511,10 @@ define <2 x i32> @test_insertelement(<2 x i32> %a, i32 %x) #0 {
; CHECK-I32X2-LABEL: test_insertelement(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_insertelement_param_1];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_insertelement_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r2, _}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.b32 %r2, [test_insertelement_param_0];
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%i = insertelement <2 x i32> %a, i32 %x, i64 1
@@ -1628,27 +1525,25 @@ define <2 x i32> @test_fptosi_2xhalf_to_2xi32(<2 x half> %a) #0 {
; CHECK-NOI32X2-LABEL: test_fptosi_2xhalf_to_2xi32(
; CHECK-NOI32X2: {
; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_fptosi_2xhalf_to_2xi32_param_0];
-; CHECK-NOI32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOI32X2-NEXT: cvt.rzi.s32.f16 %r2, %rs2;
-; CHECK-NOI32X2-NEXT: cvt.rzi.s32.f16 %r3, %rs1;
-; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptosi_2xhalf_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: cvt.rzi.s32.f16 %r1, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.rzi.s32.f16 %r2, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_fptosi_2xhalf_to_2xi32(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_fptosi_2xhalf_to_2xi32_param_0];
-; CHECK-I32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-I32X2-NEXT: cvt.rzi.s32.f16 %r2, %rs2;
-; CHECK-I32X2-NEXT: cvt.rzi.s32.f16 %r3, %rs1;
-; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: ld.param::func.v2.b16 {%rs1, %rs2}, [test_fptosi_2xhalf_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: cvt.rzi.s32.f16 %r1, %rs2;
+; CHECK-I32X2-NEXT: cvt.rzi.s32.f16 %r2, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%r = fptosi <2 x half> %a to <2 x i32>
ret <2 x i32> %r
@@ -1658,27 +1553,25 @@ define <2 x i32> @test_fptoui_2xhalf_to_2xi32(<2 x half> %a) #0 {
; CHECK-NOI32X2-LABEL: test_fptoui_2xhalf_to_2xi32(
; CHECK-NOI32X2: {
; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_fptoui_2xhalf_to_2xi32_param_0];
-; CHECK-NOI32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-NOI32X2-NEXT: cvt.rzi.u32.f16 %r2, %rs2;
-; CHECK-NOI32X2-NEXT: cvt.rzi.u32.f16 %r3, %rs1;
-; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-NOI32X2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_fptoui_2xhalf_to_2xi32_param_0];
+; CHECK-NOI32X2-NEXT: cvt.rzi.u32.f16 %r1, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.rzi.u32.f16 %r2, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_fptoui_2xhalf_to_2xi32(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_fptoui_2xhalf_to_2xi32_param_0];
-; CHECK-I32X2-NEXT: mov.b32 {%rs1, %rs2}, %r1;
-; CHECK-I32X2-NEXT: cvt.rzi.u32.f16 %r2, %rs2;
-; CHECK-I32X2-NEXT: cvt.rzi.u32.f16 %r3, %rs1;
-; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r3, %r2};
+; CHECK-I32X2-NEXT: ld.param::func.v2.b16 {%rs1, %rs2}, [test_fptoui_2xhalf_to_2xi32_param_0];
+; CHECK-I32X2-NEXT: cvt.rzi.u32.f16 %r1, %rs2;
+; CHECK-I32X2-NEXT: cvt.rzi.u32.f16 %r2, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%r = fptoui <2 x half> %a to <2 x i32>
ret <2 x i32> %r
@@ -1691,11 +1584,11 @@ define void @test_srem_v2i32(ptr %a, ptr %b, ptr %c) {
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0: // %entry
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_srem_v2i32_param_2];
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_srem_v2i32_param_1];
; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_srem_v2i32_param_0];
; CHECK-NOI32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_srem_v2i32_param_1];
; CHECK-NOI32X2-NEXT: ld.v2.b32 {%r3, %r4}, [%rd2];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_srem_v2i32_param_2];
; CHECK-NOI32X2-NEXT: rem.s32 %r5, %r2, %r4;
; CHECK-NOI32X2-NEXT: rem.s32 %r6, %r1, %r3;
; CHECK-NOI32X2-NEXT: st.v2.b32 [%rd3], {%r6, %r5};
@@ -1707,11 +1600,11 @@ define void @test_srem_v2i32(ptr %a, ptr %b, ptr %c) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0: // %entry
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_srem_v2i32_param_2];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_srem_v2i32_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_srem_v2i32_param_0];
; CHECK-I32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_srem_v2i32_param_1];
; CHECK-I32X2-NEXT: ld.v2.b32 {%r3, %r4}, [%rd2];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_srem_v2i32_param_2];
; CHECK-I32X2-NEXT: rem.s32 %r5, %r2, %r4;
; CHECK-I32X2-NEXT: rem.s32 %r6, %r1, %r3;
; CHECK-I32X2-NEXT: st.v2.b32 [%rd3], {%r6, %r5};
@@ -1731,17 +1624,17 @@ define void @test_srem_v3i32(ptr %a, ptr %b, ptr %c) {
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<10>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0: // %entry
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_srem_v3i32_param_2];
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_srem_v3i32_param_1];
; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_srem_v3i32_param_0];
; CHECK-NOI32X2-NEXT: ld.b32 %r1, [%rd1+8];
-; CHECK-NOI32X2-NEXT: ld.b64 %rd4, [%rd1];
-; CHECK-NOI32X2-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r2}, %rd4; }
-; CHECK-NOI32X2-NEXT: cvt.u32.u64 %r3, %rd4;
-; CHECK-NOI32X2-NEXT: ld.b32 %r4, [%rd2+8];
-; CHECK-NOI32X2-NEXT: ld.b64 %rd5, [%rd2];
-; CHECK-NOI32X2-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r5}, %rd5; }
-; CHECK-NOI32X2-NEXT: cvt.u32.u64 %r6, %rd5;
+; CHECK-NOI32X2-NEXT: ld.b64 %rd2, [%rd1];
+; CHECK-NOI32X2-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r2}, %rd2; }
+; CHECK-NOI32X2-NEXT: cvt.u32.u64 %r3, %rd2;
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_srem_v3i32_param_1];
+; CHECK-NOI32X2-NEXT: ld.b32 %r4, [%rd3+8];
+; CHECK-NOI32X2-NEXT: ld.b64 %rd4, [%rd3];
+; CHECK-NOI32X2-NEXT: { .reg .b32 tmp; mov.b64 {tmp, %r5}, %rd4; }
+; CHECK-NOI32X2-NEXT: cvt.u32.u64 %r6, %rd4;
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd5, [test_srem_v3i32_param_2];
; CHECK-NOI32X2-NEXT: rem.s32 %r7, %r3, %r6;
; CHECK-NOI32X2-NEXT: cvt.u64.u32 %rd6, %r7;
; CHECK-NOI32X2-NEXT: rem.s32 %r8, %r2, %r5;
@@ -1749,8 +1642,8 @@ define void @test_srem_v3i32(ptr %a, ptr %b, ptr %c) {
; CHECK-NOI32X2-NEXT: shl.b64 %rd8, %rd7, 32;
; CHECK-NOI32X2-NEXT: or.b64 %rd9, %rd6, %rd8;
; CHECK-NOI32X2-NEXT: rem.s32 %r9, %r1, %r4;
-; CHECK-NOI32X2-NEXT: st.b32 [%rd3+8], %r9;
-; CHECK-NOI32X2-NEXT: st.b64 [%rd3], %rd9;
+; CHECK-NOI32X2-NEXT: st.b32 [%rd5+8], %r9;
+; CHECK-NOI32X2-NEXT: st.b64 [%rd5], %rd9;
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_srem_v3i32(
@@ -1759,13 +1652,13 @@ define void @test_srem_v3i32(ptr %a, ptr %b, ptr %c) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0: // %entry
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_srem_v3i32_param_2];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_srem_v3i32_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_srem_v3i32_param_0];
; CHECK-I32X2-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
; CHECK-I32X2-NEXT: ld.b32 %r3, [%rd1+8];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_srem_v3i32_param_1];
; CHECK-I32X2-NEXT: ld.v2.b32 {%r4, %r5}, [%rd2];
; CHECK-I32X2-NEXT: ld.b32 %r6, [%rd2+8];
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_srem_v3i32_param_2];
; CHECK-I32X2-NEXT: rem.s32 %r7, %r3, %r6;
; CHECK-I32X2-NEXT: rem.s32 %r8, %r2, %r5;
; CHECK-I32X2-NEXT: rem.s32 %r9, %r1, %r4;
@@ -1788,13 +1681,13 @@ define void @test_sext_v2i1_to_v2i32(ptr %a, ptr %b, ptr %c) {
; CHECK-NOI32X2-NEXT: .reg .b64 %rd<4>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0: // %entry
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_sext_v2i1_to_v2i32_param_2];
-; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_sext_v2i1_to_v2i32_param_1];
; CHECK-NOI32X2-NEXT: ld.param.b64 %rd1, [test_sext_v2i1_to_v2i32_param_0];
; CHECK-NOI32X2-NEXT: ld.b32 %r1, [%rd1];
; CHECK-NOI32X2-NEXT: ld.b32 %r2, [%rd1+4];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd2, [test_sext_v2i1_to_v2i32_param_1];
; CHECK-NOI32X2-NEXT: ld.b32 %r3, [%rd2];
; CHECK-NOI32X2-NEXT: ld.b32 %r4, [%rd2+4];
+; CHECK-NOI32X2-NEXT: ld.param.b64 %rd3, [test_sext_v2i1_to_v2i32_param_2];
; CHECK-NOI32X2-NEXT: setp.gt.u32 %p1, %r2, %r4;
; CHECK-NOI32X2-NEXT: setp.gt.u32 %p2, %r1, %r3;
; CHECK-NOI32X2-NEXT: selp.b32 %r5, -1, 0, %p2;
@@ -1810,26 +1703,26 @@ define void @test_sext_v2i1_to_v2i32(ptr %a, ptr %b, ptr %c) {
; CHECK-I32X2-NEXT: .reg .b64 %rd<13>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0: // %entry
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd3, [test_sext_v2i1_to_v2i32_param_2];
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd2, [test_sext_v2i1_to_v2i32_param_1];
; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_sext_v2i1_to_v2i32_param_0];
-; CHECK-I32X2-NEXT: ld.b32 %rd4, [%rd1];
-; CHECK-I32X2-NEXT: ld.b32 %rd5, [%rd1+4];
-; CHECK-I32X2-NEXT: shl.b64 %rd6, %rd5, 32;
-; CHECK-I32X2-NEXT: or.b64 %rd7, %rd6, %rd4;
-; CHECK-I32X2-NEXT: ld.b32 %rd8, [%rd2];
-; CHECK-I32X2-NEXT: ld.b32 %rd9, [%rd2+4];
-; CHECK-I32X2-NEXT: shl.b64 %rd10, %rd9, 32;
-; CHECK-I32X2-NEXT: or.b64 %rd11, %rd10, %rd8;
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd11;
-; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd7;
+; CHECK-I32X2-NEXT: ld.b32 %rd2, [%rd1];
+; CHECK-I32X2-NEXT: ld.b32 %rd3, [%rd1+4];
+; CHECK-I32X2-NEXT: shl.b64 %rd4, %rd3, 32;
+; CHECK-I32X2-NEXT: or.b64 %rd5, %rd4, %rd2;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd6, [test_sext_v2i1_to_v2i32_param_1];
+; CHECK-I32X2-NEXT: ld.b32 %rd7, [%rd6];
+; CHECK-I32X2-NEXT: ld.b32 %rd8, [%rd6+4];
+; CHECK-I32X2-NEXT: shl.b64 %rd9, %rd8, 32;
+; CHECK-I32X2-NEXT: or.b64 %rd10, %rd9, %rd7;
+; CHECK-I32X2-NEXT: ld.param::func.b64 %rd11, [test_sext_v2i1_to_v2i32_param_2];
+; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd10;
+; CHECK-I32X2-NEXT: mov.b64 {%r3, %r4}, %rd5;
; CHECK-I32X2-NEXT: setp.gt.u32 %p1, %r3, %r1;
; CHECK-I32X2-NEXT: setp.gt.u32 %p2, %r4, %r2;
; CHECK-I32X2-NEXT: selp.b32 %r5, -1, 0, %p2;
; CHECK-I32X2-NEXT: selp.b32 %r6, -1, 0, %p1;
; CHECK-I32X2-NEXT: mov.b64 %rd12, {%r6, %r5};
-; CHECK-I32X2-NEXT: st.b32 [%rd3+4], %r5;
-; CHECK-I32X2-NEXT: st.b32 [%rd3], %rd12;
+; CHECK-I32X2-NEXT: st.b32 [%rd11+4], %r5;
+; CHECK-I32X2-NEXT: st.b32 [%rd11], %rd12;
; CHECK-I32X2-NEXT: ret;
entry:
%t1 = load <2 x i32>, ptr %a, align 4
@@ -1844,31 +1737,29 @@ define <2 x i32> @test_sext_v2i8_to_v2i32 (<2 x i8> %a) {
; CHECK-NOI32X2-LABEL: test_sext_v2i8_to_v2i32(
; CHECK-NOI32X2: {
; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<6>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<5>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
; CHECK-NOI32X2-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_sext_v2i8_to_v2i32_param_0];
-; CHECK-NOI32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-NOI32X2-NEXT: cvt.s32.s8 %r3, %r2;
-; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r4, %rs1;
-; CHECK-NOI32X2-NEXT: cvt.s32.s8 %r5, %r4;
-; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r5, %r3};
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.s32.s8 %r2, %r1;
+; CHECK-NOI32X2-NEXT: cvt.u32.u16 %r3, %rs1;
+; CHECK-NOI32X2-NEXT: cvt.s32.s8 %r4, %r3;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r4, %r2};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_sext_v2i8_to_v2i32(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
-; CHECK-I32X2-NEXT: .reg .b32 %r<6>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
; CHECK-I32X2-NEXT: ld.param::func.v2.b8 {%rs1, %rs2}, [test_sext_v2i8_to_v2i32_param_0];
-; CHECK-I32X2-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r2, %rs2;
-; CHECK-I32X2-NEXT: cvt.s32.s8 %r3, %r2;
-; CHECK-I32X2-NEXT: cvt.u32.u16 %r4, %rs1;
-; CHECK-I32X2-NEXT: cvt.s32.s8 %r5, %r4;
-; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r5, %r3};
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r1, %rs2;
+; CHECK-I32X2-NEXT: cvt.s32.s8 %r2, %r1;
+; CHECK-I32X2-NEXT: cvt.u32.u16 %r3, %rs1;
+; CHECK-I32X2-NEXT: cvt.s32.s8 %r4, %r3;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r2};
; CHECK-I32X2-NEXT: ret;
%r = sext <2 x i8> %a to <2 x i32>
ret <2 x i32> %r
@@ -1877,28 +1768,26 @@ define <2 x i32> @test_sext_v2i8_to_v2i32 (<2 x i8> %a) {
define <2 x i32> @test_sext_v2i16_to_v2i32 (<2 x i16> %a) {
; CHECK-NOI32X2-LABEL: test_sext_v2i16_to_v2i32(
; CHECK-NOI32X2: {
-; CHECK-NOI32X2-NEXT: .reg .b16 %rs<2>;
-; CHECK-NOI32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-NOI32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-NOI32X2-NEXT: .reg .b32 %r<3>;
; CHECK-NOI32X2-EMPTY:
; CHECK-NOI32X2-NEXT: // %bb.0:
-; CHECK-NOI32X2-NEXT: ld.param.b32 %r1, [test_sext_v2i16_to_v2i32_param_0];
-; CHECK-NOI32X2-NEXT: cvt.s32.s16 %r2, %r1;
-; CHECK-NOI32X2-NEXT: { .reg .b16 tmp; mov.b32 {tmp, %rs1}, %r1; }
-; CHECK-NOI32X2-NEXT: cvt.s32.s16 %r3, %rs1;
-; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r3};
+; CHECK-NOI32X2-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [test_sext_v2i16_to_v2i32_param_0];
+; CHECK-NOI32X2-NEXT: cvt.s32.s16 %r1, %rs2;
+; CHECK-NOI32X2-NEXT: cvt.s32.s16 %r2, %rs1;
+; CHECK-NOI32X2-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-NOI32X2-NEXT: ret;
;
; CHECK-I32X2-LABEL: test_sext_v2i16_to_v2i32(
; CHECK-I32X2: {
-; CHECK-I32X2-NEXT: .reg .b16 %rs<2>;
-; CHECK-I32X2-NEXT: .reg .b32 %r<4>;
+; CHECK-I32X2-NEXT: .reg .b16 %rs<3>;
+; CHECK-I32X2-NEXT: .reg .b32 %r<3>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b32 %r1, [test_sext_v2i16_to_v2i32_param_0];
-; CHECK-I32X2-NEXT: cvt.s32.s16 %r2, %r1;
-; CHECK-I32X2-NEXT: mov.b32 {_, %rs1}, %r1;
-; CHECK-I32X2-NEXT: cvt.s32.s16 %r3, %rs1;
-; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r3};
+; CHECK-I32X2-NEXT: ld.param::func.v2.b16 {%rs1, %rs2}, [test_sext_v2i16_to_v2i32_param_0];
+; CHECK-I32X2-NEXT: cvt.s32.s16 %r1, %rs2;
+; CHECK-I32X2-NEXT: cvt.s32.s16 %r2, %rs1;
+; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r2, %r1};
; CHECK-I32X2-NEXT: ret;
%r = sext <2 x i16> %a to <2 x i32>
ret <2 x i32> %r
@@ -1919,11 +1808,9 @@ define <2 x float> @test_uitofp_v2i32(<2 x i32> %a) {
; CHECK-I32X2-LABEL: test_uitofp_v2i32(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_uitofp_v2i32_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_uitofp_v2i32_param_0];
; CHECK-I32X2-NEXT: cvt.rn.f32.u32 %r3, %r2;
; CHECK-I32X2-NEXT: cvt.rn.f32.u32 %r4, %r1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
@@ -1947,11 +1834,9 @@ define <2 x float> @test_sitofp_v2i32(<2 x i32> %a) {
; CHECK-I32X2-LABEL: test_sitofp_v2i32(
; CHECK-I32X2: {
; CHECK-I32X2-NEXT: .reg .b32 %r<5>;
-; CHECK-I32X2-NEXT: .reg .b64 %rd<2>;
; CHECK-I32X2-EMPTY:
; CHECK-I32X2-NEXT: // %bb.0:
-; CHECK-I32X2-NEXT: ld.param::func.b64 %rd1, [test_sitofp_v2i32_param_0];
-; CHECK-I32X2-NEXT: mov.b64 {%r1, %r2}, %rd1;
+; CHECK-I32X2-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [test_sitofp_v2i32_param_0];
; CHECK-I32X2-NEXT: cvt.rn.f32.s32 %r3, %r2;
; CHECK-I32X2-NEXT: cvt.rn.f32.s32 %r4, %r1;
; CHECK-I32X2-NEXT: st.param::func.v2.b32 [func_retval0], {%r4, %r3};
diff --git a/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll b/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
index db19495b5a4ba4..47e316609d76c7 100644
--- a/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i8x2-instructions.ll
@@ -20,16 +20,11 @@ target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
define i16 @test_bitcast_2xi8_i16(<2 x i8> %a) {
; O0-LABEL: test_bitcast_2xi8_i16(
; O0: {
-; O0-NEXT: .reg .b16 %rs<5>;
-; O0-NEXT: .reg .b32 %r<3>;
+; O0-NEXT: .reg .b32 %r<2>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_bitcast_2xi8_i16_param_0];
-; O0-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; O0-NEXT: shl.b16 %rs3, %rs2, 8;
-; O0-NEXT: or.b16 %rs4, %rs1, %rs3;
-; O0-NEXT: cvt.u32.u16 %r2, %rs4;
-; O0-NEXT: st.param.b32 [func_retval0], %r2;
+; O0-NEXT: ld.param.b16 %r1, [test_bitcast_2xi8_i16_param_0];
+; O0-NEXT: st.param.b32 [func_retval0], %r1;
; O0-NEXT: ret;
;
; O3-LABEL: test_bitcast_2xi8_i16(
@@ -70,11 +65,9 @@ define <2 x i8> @test_call_2xi8(<2 x i8> %a) {
; O0-LABEL: test_call_2xi8(
; O0: {
; O0-NEXT: .reg .b16 %rs<5>;
-; O0-NEXT: .reg .b32 %r<2>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
; O0-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_call_2xi8_param_0];
-; O0-NEXT: mov.b32 %r1, {%rs1, %rs2};
; O0-NEXT: { // callseq 0, 0
; O0-NEXT: .param .align 2 .b8 param0[2];
; O0-NEXT: .param .align 2 .b8 retval0[2];
@@ -108,14 +101,13 @@ define <2 x float> @test_uitofp_2xi8(<2 x i8> %a) {
; O0-LABEL: test_uitofp_2xi8(
; O0: {
; O0-NEXT: .reg .b16 %rs<3>;
-; O0-NEXT: .reg .b32 %r<4>;
+; O0-NEXT: .reg .b32 %r<3>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
; O0-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_uitofp_2xi8_param_0];
-; O0-NEXT: mov.b32 %r1, {%rs1, %rs2};
-; O0-NEXT: cvt.rn.f32.u16 %r2, %rs2;
-; O0-NEXT: cvt.rn.f32.u16 %r3, %rs1;
-; O0-NEXT: st.param.v2.b32 [func_retval0], {%r3, %r2};
+; O0-NEXT: cvt.rn.f32.u16 %r1, %rs2;
+; O0-NEXT: cvt.rn.f32.u16 %r2, %rs1;
+; O0-NEXT: st.param.v2.b32 [func_retval0], {%r2, %r1};
; O0-NEXT: ret;
;
; O3-LABEL: test_uitofp_2xi8(
@@ -137,13 +129,11 @@ define void @test_store_i8x2_unaligned(ptr %ptr, <2 x i8> %a) {
; O0-LABEL: test_store_i8x2_unaligned(
; O0: {
; O0-NEXT: .reg .b16 %rs<3>;
-; O0-NEXT: .reg .b32 %r<2>;
; O0-NEXT: .reg .b64 %rd<2>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
; O0-NEXT: ld.param.b64 %rd1, [test_store_i8x2_unaligned_param_0];
; O0-NEXT: ld.param.v2.b8 {%rs1, %rs2}, [test_store_i8x2_unaligned_param_1];
-; O0-NEXT: mov.b32 %r1, {%rs1, %rs2};
; O0-NEXT: st.b8 [%rd1+1], %rs2;
; O0-NEXT: st.b8 [%rd1], %rs1;
; O0-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
index c3c365a3c704db..9d5770d4a049bb 100644
--- a/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
+++ b/llvm/test/CodeGen/NVPTX/i8x4-instructions.ll
@@ -83,111 +83,59 @@ define i8 @test_extract_3(<4 x i8> %a) #0 {
}
define i8 @test_extract_i(<4 x i8> %a, i64 %idx) #0 {
-; O0-LABEL: test_extract_i(
-; O0: {
-; O0-NEXT: .reg .b32 %r<5>;
-; O0-NEXT: .reg .b64 %rd<2>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd1, [test_extract_i_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_extract_i_param_0];
-; O0-NEXT: cvt.u32.u64 %r2, %rd1;
-; O0-NEXT: or.b32 %r3, %r2, 30576;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, %r3;
-; O0-NEXT: st.param.b32 [func_retval0], %r4;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_extract_i(
-; O3: {
-; O3-NEXT: .reg .b32 %r<5>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_extract_i_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_extract_i_param_1];
-; O3-NEXT: or.b32 %r3, %r2, 30576;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, %r3;
-; O3-NEXT: st.param.b32 [func_retval0], %r4;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_extract_i(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_extract_i_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_extract_i_param_1];
+; CHECK-NEXT: or.b32 %r3, %r2, 30576;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, %r3;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r4;
+; CHECK-NEXT: ret;
%e = extractelement <4 x i8> %a, i64 %idx
ret i8 %e
}
define <4 x i8> @test_add(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_add(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<13>;
-; O0-NEXT: .reg .b32 %r<18>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_add_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_add_param_0];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
-; O0-NEXT: cvt.u16.u32 %rs1, %r3;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
-; O0-NEXT: cvt.u16.u32 %rs2, %r4;
-; O0-NEXT: add.s16 %rs3, %rs2, %rs1;
-; O0-NEXT: cvt.u32.u16 %r5, %rs3;
-; O0-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
-; O0-NEXT: cvt.u16.u32 %rs4, %r6;
-; O0-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
-; O0-NEXT: cvt.u16.u32 %rs5, %r7;
-; O0-NEXT: add.s16 %rs6, %rs5, %rs4;
-; O0-NEXT: cvt.u32.u16 %r8, %rs6;
-; O0-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O0-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
-; O0-NEXT: cvt.u16.u32 %rs7, %r10;
-; O0-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
-; O0-NEXT: cvt.u16.u32 %rs8, %r11;
-; O0-NEXT: add.s16 %rs9, %rs8, %rs7;
-; O0-NEXT: cvt.u32.u16 %r12, %rs9;
-; O0-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
-; O0-NEXT: cvt.u16.u32 %rs10, %r13;
-; O0-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
-; O0-NEXT: cvt.u16.u32 %rs11, %r14;
-; O0-NEXT: add.s16 %rs12, %rs11, %rs10;
-; O0-NEXT: cvt.u32.u16 %r15, %rs12;
-; O0-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r17;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_add(
-; O3: {
-; O3-NEXT: .reg .b16 %rs<13>;
-; O3-NEXT: .reg .b32 %r<18>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_add_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_add_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
-; O3-NEXT: cvt.u16.u32 %rs1, %r3;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
-; O3-NEXT: cvt.u16.u32 %rs2, %r4;
-; O3-NEXT: add.s16 %rs3, %rs2, %rs1;
-; O3-NEXT: cvt.u32.u16 %r5, %rs3;
-; O3-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
-; O3-NEXT: cvt.u16.u32 %rs4, %r6;
-; O3-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
-; O3-NEXT: cvt.u16.u32 %rs5, %r7;
-; O3-NEXT: add.s16 %rs6, %rs5, %rs4;
-; O3-NEXT: cvt.u32.u16 %r8, %rs6;
-; O3-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O3-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
-; O3-NEXT: cvt.u16.u32 %rs7, %r10;
-; O3-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
-; O3-NEXT: cvt.u16.u32 %rs8, %r11;
-; O3-NEXT: add.s16 %rs9, %rs8, %rs7;
-; O3-NEXT: cvt.u32.u16 %r12, %rs9;
-; O3-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
-; O3-NEXT: cvt.u16.u32 %rs10, %r13;
-; O3-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
-; O3-NEXT: cvt.u16.u32 %rs11, %r14;
-; O3-NEXT: add.s16 %rs12, %rs11, %rs10;
-; O3-NEXT: cvt.u32.u16 %r15, %rs12;
-; O3-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r17;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_add(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<13>;
+; CHECK-NEXT: .reg .b32 %r<18>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_add_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_add_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
+; CHECK-NEXT: cvt.u16.u32 %rs1, %r3;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
+; CHECK-NEXT: cvt.u16.u32 %rs2, %r4;
+; CHECK-NEXT: add.s16 %rs3, %rs2, %rs1;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs3;
+; CHECK-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
+; CHECK-NEXT: cvt.u16.u32 %rs4, %r6;
+; CHECK-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
+; CHECK-NEXT: cvt.u16.u32 %rs5, %r7;
+; CHECK-NEXT: add.s16 %rs6, %rs5, %rs4;
+; CHECK-NEXT: cvt.u32.u16 %r8, %rs6;
+; CHECK-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
+; CHECK-NEXT: cvt.u16.u32 %rs7, %r10;
+; CHECK-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
+; CHECK-NEXT: cvt.u16.u32 %rs8, %r11;
+; CHECK-NEXT: add.s16 %rs9, %rs8, %rs7;
+; CHECK-NEXT: cvt.u32.u16 %r12, %rs9;
+; CHECK-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
+; CHECK-NEXT: cvt.u16.u32 %rs10, %r13;
+; CHECK-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
+; CHECK-NEXT: cvt.u16.u32 %rs11, %r14;
+; CHECK-NEXT: add.s16 %rs12, %rs11, %rs10;
+; CHECK-NEXT: cvt.u32.u16 %r15, %rs12;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r17;
+; CHECK-NEXT: ret;
%r = add <4 x i8> %a, %b
ret <4 x i8> %r
}
@@ -259,629 +207,336 @@ define <4 x i8> @test_add_imm_1(<4 x i8> %a) #0 {
}
define <4 x i8> @test_sub(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_sub(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<13>;
-; O0-NEXT: .reg .b32 %r<18>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_sub_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_sub_param_0];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
-; O0-NEXT: cvt.u16.u32 %rs1, %r3;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
-; O0-NEXT: cvt.u16.u32 %rs2, %r4;
-; O0-NEXT: sub.s16 %rs3, %rs2, %rs1;
-; O0-NEXT: cvt.u32.u16 %r5, %rs3;
-; O0-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
-; O0-NEXT: cvt.u16.u32 %rs4, %r6;
-; O0-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
-; O0-NEXT: cvt.u16.u32 %rs5, %r7;
-; O0-NEXT: sub.s16 %rs6, %rs5, %rs4;
-; O0-NEXT: cvt.u32.u16 %r8, %rs6;
-; O0-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O0-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
-; O0-NEXT: cvt.u16.u32 %rs7, %r10;
-; O0-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
-; O0-NEXT: cvt.u16.u32 %rs8, %r11;
-; O0-NEXT: sub.s16 %rs9, %rs8, %rs7;
-; O0-NEXT: cvt.u32.u16 %r12, %rs9;
-; O0-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
-; O0-NEXT: cvt.u16.u32 %rs10, %r13;
-; O0-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
-; O0-NEXT: cvt.u16.u32 %rs11, %r14;
-; O0-NEXT: sub.s16 %rs12, %rs11, %rs10;
-; O0-NEXT: cvt.u32.u16 %r15, %rs12;
-; O0-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r17;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_sub(
-; O3: {
-; O3-NEXT: .reg .b16 %rs<13>;
-; O3-NEXT: .reg .b32 %r<18>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_sub_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_sub_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
-; O3-NEXT: cvt.u16.u32 %rs1, %r3;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
-; O3-NEXT: cvt.u16.u32 %rs2, %r4;
-; O3-NEXT: sub.s16 %rs3, %rs2, %rs1;
-; O3-NEXT: cvt.u32.u16 %r5, %rs3;
-; O3-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
-; O3-NEXT: cvt.u16.u32 %rs4, %r6;
-; O3-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
-; O3-NEXT: cvt.u16.u32 %rs5, %r7;
-; O3-NEXT: sub.s16 %rs6, %rs5, %rs4;
-; O3-NEXT: cvt.u32.u16 %r8, %rs6;
-; O3-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O3-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
-; O3-NEXT: cvt.u16.u32 %rs7, %r10;
-; O3-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
-; O3-NEXT: cvt.u16.u32 %rs8, %r11;
-; O3-NEXT: sub.s16 %rs9, %rs8, %rs7;
-; O3-NEXT: cvt.u32.u16 %r12, %rs9;
-; O3-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
-; O3-NEXT: cvt.u16.u32 %rs10, %r13;
-; O3-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
-; O3-NEXT: cvt.u16.u32 %rs11, %r14;
-; O3-NEXT: sub.s16 %rs12, %rs11, %rs10;
-; O3-NEXT: cvt.u32.u16 %r15, %rs12;
-; O3-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r17;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_sub(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<13>;
+; CHECK-NEXT: .reg .b32 %r<18>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_sub_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_sub_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
+; CHECK-NEXT: cvt.u16.u32 %rs1, %r3;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
+; CHECK-NEXT: cvt.u16.u32 %rs2, %r4;
+; CHECK-NEXT: sub.s16 %rs3, %rs2, %rs1;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs3;
+; CHECK-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
+; CHECK-NEXT: cvt.u16.u32 %rs4, %r6;
+; CHECK-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
+; CHECK-NEXT: cvt.u16.u32 %rs5, %r7;
+; CHECK-NEXT: sub.s16 %rs6, %rs5, %rs4;
+; CHECK-NEXT: cvt.u32.u16 %r8, %rs6;
+; CHECK-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
+; CHECK-NEXT: cvt.u16.u32 %rs7, %r10;
+; CHECK-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
+; CHECK-NEXT: cvt.u16.u32 %rs8, %r11;
+; CHECK-NEXT: sub.s16 %rs9, %rs8, %rs7;
+; CHECK-NEXT: cvt.u32.u16 %r12, %rs9;
+; CHECK-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
+; CHECK-NEXT: cvt.u16.u32 %rs10, %r13;
+; CHECK-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
+; CHECK-NEXT: cvt.u16.u32 %rs11, %r14;
+; CHECK-NEXT: sub.s16 %rs12, %rs11, %rs10;
+; CHECK-NEXT: cvt.u32.u16 %r15, %rs12;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r17;
+; CHECK-NEXT: ret;
%r = sub <4 x i8> %a, %b
ret <4 x i8> %r
}
define <4 x i8> @test_smax(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_smax(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<26>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_smax_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_smax_param_0];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x8880U;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x8880U;
-; O0-NEXT: setp.gt.s32 %p1, %r4, %r3;
-; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x9991U;
-; O0-NEXT: prmt.b32 %r6, %r1, 0, 0x9991U;
-; O0-NEXT: setp.gt.s32 %p2, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r2, 0, 0xaaa2U;
-; O0-NEXT: prmt.b32 %r8, %r1, 0, 0xaaa2U;
-; O0-NEXT: setp.gt.s32 %p3, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r2, 0, 0xbbb3U;
-; O0-NEXT: prmt.b32 %r10, %r1, 0, 0xbbb3U;
-; O0-NEXT: setp.gt.s32 %p4, %r10, %r9;
-; O0-NEXT: prmt.b32 %r11, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r12, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r13, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r14, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r15, %r1, 0, 0x7773U;
-; O0-NEXT: selp.b32 %r16, %r15, %r14, %p4;
-; O0-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
-; O0-NEXT: selp.b32 %r18, %r17, %r13, %p3;
-; O0-NEXT: prmt.b32 %r19, %r18, %r16, 0x3340U;
-; O0-NEXT: prmt.b32 %r20, %r1, 0, 0x7771U;
-; O0-NEXT: selp.b32 %r21, %r20, %r12, %p2;
-; O0-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
-; O0-NEXT: selp.b32 %r23, %r22, %r11, %p1;
-; O0-NEXT: prmt.b32 %r24, %r23, %r21, 0x3340U;
-; O0-NEXT: prmt.b32 %r25, %r24, %r19, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r25;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_smax(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<26>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_smax_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_smax_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x8880U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x8880U;
-; O3-NEXT: setp.gt.s32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x9991U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x9991U;
-; O3-NEXT: setp.gt.s32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0xaaa2U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0xaaa2U;
-; O3-NEXT: setp.gt.s32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0xbbb3U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0xbbb3U;
-; O3-NEXT: setp.gt.s32 %p4, %r10, %r9;
-; O3-NEXT: prmt.b32 %r11, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r12, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r13, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r14, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r15, %r1, 0, 0x7773U;
-; O3-NEXT: selp.b32 %r16, %r15, %r14, %p4;
-; O3-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
-; O3-NEXT: selp.b32 %r18, %r17, %r13, %p3;
-; O3-NEXT: prmt.b32 %r19, %r18, %r16, 0x3340U;
-; O3-NEXT: prmt.b32 %r20, %r1, 0, 0x7771U;
-; O3-NEXT: selp.b32 %r21, %r20, %r12, %p2;
-; O3-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
-; O3-NEXT: selp.b32 %r23, %r22, %r11, %p1;
-; O3-NEXT: prmt.b32 %r24, %r23, %r21, 0x3340U;
-; O3-NEXT: prmt.b32 %r25, %r24, %r19, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r25;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_smax(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<26>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_smax_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_smax_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x8880U;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x8880U;
+; CHECK-NEXT: setp.gt.s32 %p1, %r4, %r3;
+; CHECK-NEXT: prmt.b32 %r5, %r2, 0, 0x9991U;
+; CHECK-NEXT: prmt.b32 %r6, %r1, 0, 0x9991U;
+; CHECK-NEXT: setp.gt.s32 %p2, %r6, %r5;
+; CHECK-NEXT: prmt.b32 %r7, %r2, 0, 0xaaa2U;
+; CHECK-NEXT: prmt.b32 %r8, %r1, 0, 0xaaa2U;
+; CHECK-NEXT: setp.gt.s32 %p3, %r8, %r7;
+; CHECK-NEXT: prmt.b32 %r9, %r2, 0, 0xbbb3U;
+; CHECK-NEXT: prmt.b32 %r10, %r1, 0, 0xbbb3U;
+; CHECK-NEXT: setp.gt.s32 %p4, %r10, %r9;
+; CHECK-NEXT: prmt.b32 %r11, %r2, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r12, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r13, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r14, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r15, %r1, 0, 0x7773U;
+; CHECK-NEXT: selp.b32 %r16, %r15, %r14, %p4;
+; CHECK-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
+; CHECK-NEXT: selp.b32 %r18, %r17, %r13, %p3;
+; CHECK-NEXT: prmt.b32 %r19, %r18, %r16, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r20, %r1, 0, 0x7771U;
+; CHECK-NEXT: selp.b32 %r21, %r20, %r12, %p2;
+; CHECK-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
+; CHECK-NEXT: selp.b32 %r23, %r22, %r11, %p1;
+; CHECK-NEXT: prmt.b32 %r24, %r23, %r21, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r25, %r24, %r19, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r25;
+; CHECK-NEXT: ret;
%cmp = icmp sgt <4 x i8> %a, %b
%r = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %r
}
define <4 x i8> @test_umax(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_umax(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<18>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_umax_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_umax_param_0];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O0-NEXT: setp.gt.u32 %p1, %r4, %r3;
-; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O0-NEXT: setp.gt.u32 %p2, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O0-NEXT: setp.gt.u32 %p3, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O0-NEXT: setp.gt.u32 %p4, %r10, %r9;
-; O0-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O0-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O0-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O0-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O0-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O0-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r17;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_umax(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<18>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_umax_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_umax_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O3-NEXT: setp.gt.u32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O3-NEXT: setp.gt.u32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O3-NEXT: setp.gt.u32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O3-NEXT: setp.gt.u32 %p4, %r10, %r9;
-; O3-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O3-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O3-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O3-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O3-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O3-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r17;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_umax(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<18>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_umax_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_umax_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
+; CHECK-NEXT: setp.gt.u32 %p1, %r4, %r3;
+; CHECK-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
+; CHECK-NEXT: setp.gt.u32 %p2, %r6, %r5;
+; CHECK-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
+; CHECK-NEXT: setp.gt.u32 %p3, %r8, %r7;
+; CHECK-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
+; CHECK-NEXT: setp.gt.u32 %p4, %r10, %r9;
+; CHECK-NEXT: selp.b32 %r11, %r10, %r9, %p4;
+; CHECK-NEXT: selp.b32 %r12, %r8, %r7, %p3;
+; CHECK-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
+; CHECK-NEXT: selp.b32 %r14, %r6, %r5, %p2;
+; CHECK-NEXT: selp.b32 %r15, %r4, %r3, %p1;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r17;
+; CHECK-NEXT: ret;
%cmp = icmp ugt <4 x i8> %a, %b
%r = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %r
}
define <4 x i8> @test_smin(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_smin(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<26>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_smin_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_smin_param_0];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x8880U;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x8880U;
-; O0-NEXT: setp.le.s32 %p1, %r4, %r3;
-; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x9991U;
-; O0-NEXT: prmt.b32 %r6, %r1, 0, 0x9991U;
-; O0-NEXT: setp.le.s32 %p2, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r2, 0, 0xaaa2U;
-; O0-NEXT: prmt.b32 %r8, %r1, 0, 0xaaa2U;
-; O0-NEXT: setp.le.s32 %p3, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r2, 0, 0xbbb3U;
-; O0-NEXT: prmt.b32 %r10, %r1, 0, 0xbbb3U;
-; O0-NEXT: setp.le.s32 %p4, %r10, %r9;
-; O0-NEXT: prmt.b32 %r11, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r12, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r13, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r14, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r15, %r1, 0, 0x7773U;
-; O0-NEXT: selp.b32 %r16, %r15, %r14, %p4;
-; O0-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
-; O0-NEXT: selp.b32 %r18, %r17, %r13, %p3;
-; O0-NEXT: prmt.b32 %r19, %r18, %r16, 0x3340U;
-; O0-NEXT: prmt.b32 %r20, %r1, 0, 0x7771U;
-; O0-NEXT: selp.b32 %r21, %r20, %r12, %p2;
-; O0-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
-; O0-NEXT: selp.b32 %r23, %r22, %r11, %p1;
-; O0-NEXT: prmt.b32 %r24, %r23, %r21, 0x3340U;
-; O0-NEXT: prmt.b32 %r25, %r24, %r19, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r25;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_smin(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<26>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_smin_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_smin_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x8880U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x8880U;
-; O3-NEXT: setp.le.s32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x9991U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x9991U;
-; O3-NEXT: setp.le.s32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0xaaa2U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0xaaa2U;
-; O3-NEXT: setp.le.s32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0xbbb3U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0xbbb3U;
-; O3-NEXT: setp.le.s32 %p4, %r10, %r9;
-; O3-NEXT: prmt.b32 %r11, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r12, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r13, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r14, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r15, %r1, 0, 0x7773U;
-; O3-NEXT: selp.b32 %r16, %r15, %r14, %p4;
-; O3-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
-; O3-NEXT: selp.b32 %r18, %r17, %r13, %p3;
-; O3-NEXT: prmt.b32 %r19, %r18, %r16, 0x3340U;
-; O3-NEXT: prmt.b32 %r20, %r1, 0, 0x7771U;
-; O3-NEXT: selp.b32 %r21, %r20, %r12, %p2;
-; O3-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
-; O3-NEXT: selp.b32 %r23, %r22, %r11, %p1;
-; O3-NEXT: prmt.b32 %r24, %r23, %r21, 0x3340U;
-; O3-NEXT: prmt.b32 %r25, %r24, %r19, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r25;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_smin(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<26>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_smin_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_smin_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x8880U;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x8880U;
+; CHECK-NEXT: setp.le.s32 %p1, %r4, %r3;
+; CHECK-NEXT: prmt.b32 %r5, %r2, 0, 0x9991U;
+; CHECK-NEXT: prmt.b32 %r6, %r1, 0, 0x9991U;
+; CHECK-NEXT: setp.le.s32 %p2, %r6, %r5;
+; CHECK-NEXT: prmt.b32 %r7, %r2, 0, 0xaaa2U;
+; CHECK-NEXT: prmt.b32 %r8, %r1, 0, 0xaaa2U;
+; CHECK-NEXT: setp.le.s32 %p3, %r8, %r7;
+; CHECK-NEXT: prmt.b32 %r9, %r2, 0, 0xbbb3U;
+; CHECK-NEXT: prmt.b32 %r10, %r1, 0, 0xbbb3U;
+; CHECK-NEXT: setp.le.s32 %p4, %r10, %r9;
+; CHECK-NEXT: prmt.b32 %r11, %r2, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r12, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r13, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r14, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r15, %r1, 0, 0x7773U;
+; CHECK-NEXT: selp.b32 %r16, %r15, %r14, %p4;
+; CHECK-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
+; CHECK-NEXT: selp.b32 %r18, %r17, %r13, %p3;
+; CHECK-NEXT: prmt.b32 %r19, %r18, %r16, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r20, %r1, 0, 0x7771U;
+; CHECK-NEXT: selp.b32 %r21, %r20, %r12, %p2;
+; CHECK-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
+; CHECK-NEXT: selp.b32 %r23, %r22, %r11, %p1;
+; CHECK-NEXT: prmt.b32 %r24, %r23, %r21, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r25, %r24, %r19, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r25;
+; CHECK-NEXT: ret;
%cmp = icmp sle <4 x i8> %a, %b
%r = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %r
}
define <4 x i8> @test_umin(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_umin(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<18>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_umin_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_umin_param_0];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O0-NEXT: setp.le.u32 %p1, %r4, %r3;
-; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O0-NEXT: setp.le.u32 %p2, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O0-NEXT: setp.le.u32 %p3, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O0-NEXT: setp.le.u32 %p4, %r10, %r9;
-; O0-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O0-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O0-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O0-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O0-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O0-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r17;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_umin(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<18>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_umin_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_umin_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O3-NEXT: setp.le.u32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O3-NEXT: setp.le.u32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O3-NEXT: setp.le.u32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O3-NEXT: setp.le.u32 %p4, %r10, %r9;
-; O3-NEXT: selp.b32 %r11, %r10, %r9, %p4;
-; O3-NEXT: selp.b32 %r12, %r8, %r7, %p3;
-; O3-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O3-NEXT: selp.b32 %r14, %r6, %r5, %p2;
-; O3-NEXT: selp.b32 %r15, %r4, %r3, %p1;
-; O3-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r17;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_umin(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<18>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_umin_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_umin_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
+; CHECK-NEXT: setp.le.u32 %p1, %r4, %r3;
+; CHECK-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
+; CHECK-NEXT: setp.le.u32 %p2, %r6, %r5;
+; CHECK-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
+; CHECK-NEXT: setp.le.u32 %p3, %r8, %r7;
+; CHECK-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
+; CHECK-NEXT: setp.le.u32 %p4, %r10, %r9;
+; CHECK-NEXT: selp.b32 %r11, %r10, %r9, %p4;
+; CHECK-NEXT: selp.b32 %r12, %r8, %r7, %p3;
+; CHECK-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
+; CHECK-NEXT: selp.b32 %r14, %r6, %r5, %p2;
+; CHECK-NEXT: selp.b32 %r15, %r4, %r3, %p1;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r17;
+; CHECK-NEXT: ret;
%cmp = icmp ule <4 x i8> %a, %b
%r = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %r
}
define <4 x i8> @test_eq(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c) #0 {
-; O0-LABEL: test_eq(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<23>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r3, [test_eq_param_2];
-; O0-NEXT: ld.param.b32 %r2, [test_eq_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_eq_param_0];
-; O0-NEXT: prmt.b32 %r4, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r5, %r1, 0, 0x7770U;
-; O0-NEXT: setp.eq.b32 %p1, %r5, %r4;
-; O0-NEXT: prmt.b32 %r6, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r7, %r1, 0, 0x7771U;
-; O0-NEXT: setp.eq.b32 %p2, %r7, %r6;
-; O0-NEXT: prmt.b32 %r8, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r9, %r1, 0, 0x7772U;
-; O0-NEXT: setp.eq.b32 %p3, %r9, %r8;
-; O0-NEXT: prmt.b32 %r10, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r11, %r1, 0, 0x7773U;
-; O0-NEXT: setp.eq.b32 %p4, %r11, %r10;
-; O0-NEXT: prmt.b32 %r12, %r3, 0, 0x7773U;
-; O0-NEXT: selp.b32 %r13, %r11, %r12, %p4;
-; O0-NEXT: prmt.b32 %r14, %r3, 0, 0x7772U;
-; O0-NEXT: selp.b32 %r15, %r9, %r14, %p3;
-; O0-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r3, 0, 0x7771U;
-; O0-NEXT: selp.b32 %r18, %r7, %r17, %p2;
-; O0-NEXT: prmt.b32 %r19, %r3, 0, 0x7770U;
-; O0-NEXT: selp.b32 %r20, %r5, %r19, %p1;
-; O0-NEXT: prmt.b32 %r21, %r20, %r18, 0x3340U;
-; O0-NEXT: prmt.b32 %r22, %r21, %r16, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r22;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_eq(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<23>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_eq_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_eq_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O3-NEXT: setp.eq.b32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O3-NEXT: setp.eq.b32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O3-NEXT: setp.eq.b32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O3-NEXT: setp.eq.b32 %p4, %r10, %r9;
-; O3-NEXT: ld.param.b32 %r11, [test_eq_param_2];
-; O3-NEXT: prmt.b32 %r12, %r11, 0, 0x7773U;
-; O3-NEXT: selp.b32 %r13, %r10, %r12, %p4;
-; O3-NEXT: prmt.b32 %r14, %r11, 0, 0x7772U;
-; O3-NEXT: selp.b32 %r15, %r8, %r14, %p3;
-; O3-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r11, 0, 0x7771U;
-; O3-NEXT: selp.b32 %r18, %r6, %r17, %p2;
-; O3-NEXT: prmt.b32 %r19, %r11, 0, 0x7770U;
-; O3-NEXT: selp.b32 %r20, %r4, %r19, %p1;
-; O3-NEXT: prmt.b32 %r21, %r20, %r18, 0x3340U;
-; O3-NEXT: prmt.b32 %r22, %r21, %r16, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r22;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_eq(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<23>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_eq_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_eq_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
+; CHECK-NEXT: setp.eq.b32 %p1, %r4, %r3;
+; CHECK-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
+; CHECK-NEXT: setp.eq.b32 %p2, %r6, %r5;
+; CHECK-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
+; CHECK-NEXT: setp.eq.b32 %p3, %r8, %r7;
+; CHECK-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
+; CHECK-NEXT: setp.eq.b32 %p4, %r10, %r9;
+; CHECK-NEXT: ld.param.b32 %r11, [test_eq_param_2];
+; CHECK-NEXT: prmt.b32 %r12, %r11, 0, 0x7773U;
+; CHECK-NEXT: selp.b32 %r13, %r10, %r12, %p4;
+; CHECK-NEXT: prmt.b32 %r14, %r11, 0, 0x7772U;
+; CHECK-NEXT: selp.b32 %r15, %r8, %r14, %p3;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r11, 0, 0x7771U;
+; CHECK-NEXT: selp.b32 %r18, %r6, %r17, %p2;
+; CHECK-NEXT: prmt.b32 %r19, %r11, 0, 0x7770U;
+; CHECK-NEXT: selp.b32 %r20, %r4, %r19, %p1;
+; CHECK-NEXT: prmt.b32 %r21, %r20, %r18, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r22, %r21, %r16, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r22;
+; CHECK-NEXT: ret;
%cmp = icmp eq <4 x i8> %a, %b
%r = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %c
ret <4 x i8> %r
}
define <4 x i8> @test_ne(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c) #0 {
-; O0-LABEL: test_ne(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<23>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r3, [test_ne_param_2];
-; O0-NEXT: ld.param.b32 %r2, [test_ne_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_ne_param_0];
-; O0-NEXT: prmt.b32 %r4, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r5, %r1, 0, 0x7770U;
-; O0-NEXT: setp.ne.b32 %p1, %r5, %r4;
-; O0-NEXT: prmt.b32 %r6, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r7, %r1, 0, 0x7771U;
-; O0-NEXT: setp.ne.b32 %p2, %r7, %r6;
-; O0-NEXT: prmt.b32 %r8, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r9, %r1, 0, 0x7772U;
-; O0-NEXT: setp.ne.b32 %p3, %r9, %r8;
-; O0-NEXT: prmt.b32 %r10, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r11, %r1, 0, 0x7773U;
-; O0-NEXT: setp.ne.b32 %p4, %r11, %r10;
-; O0-NEXT: prmt.b32 %r12, %r3, 0, 0x7773U;
-; O0-NEXT: selp.b32 %r13, %r11, %r12, %p4;
-; O0-NEXT: prmt.b32 %r14, %r3, 0, 0x7772U;
-; O0-NEXT: selp.b32 %r15, %r9, %r14, %p3;
-; O0-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r3, 0, 0x7771U;
-; O0-NEXT: selp.b32 %r18, %r7, %r17, %p2;
-; O0-NEXT: prmt.b32 %r19, %r3, 0, 0x7770U;
-; O0-NEXT: selp.b32 %r20, %r5, %r19, %p1;
-; O0-NEXT: prmt.b32 %r21, %r20, %r18, 0x3340U;
-; O0-NEXT: prmt.b32 %r22, %r21, %r16, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r22;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_ne(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<23>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_ne_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_ne_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O3-NEXT: setp.ne.b32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O3-NEXT: setp.ne.b32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O3-NEXT: setp.ne.b32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O3-NEXT: setp.ne.b32 %p4, %r10, %r9;
-; O3-NEXT: ld.param.b32 %r11, [test_ne_param_2];
-; O3-NEXT: prmt.b32 %r12, %r11, 0, 0x7773U;
-; O3-NEXT: selp.b32 %r13, %r10, %r12, %p4;
-; O3-NEXT: prmt.b32 %r14, %r11, 0, 0x7772U;
-; O3-NEXT: selp.b32 %r15, %r8, %r14, %p3;
-; O3-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r11, 0, 0x7771U;
-; O3-NEXT: selp.b32 %r18, %r6, %r17, %p2;
-; O3-NEXT: prmt.b32 %r19, %r11, 0, 0x7770U;
-; O3-NEXT: selp.b32 %r20, %r4, %r19, %p1;
-; O3-NEXT: prmt.b32 %r21, %r20, %r18, 0x3340U;
-; O3-NEXT: prmt.b32 %r22, %r21, %r16, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r22;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_ne(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<23>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_ne_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_ne_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
+; CHECK-NEXT: setp.ne.b32 %p1, %r4, %r3;
+; CHECK-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
+; CHECK-NEXT: setp.ne.b32 %p2, %r6, %r5;
+; CHECK-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
+; CHECK-NEXT: setp.ne.b32 %p3, %r8, %r7;
+; CHECK-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
+; CHECK-NEXT: setp.ne.b32 %p4, %r10, %r9;
+; CHECK-NEXT: ld.param.b32 %r11, [test_ne_param_2];
+; CHECK-NEXT: prmt.b32 %r12, %r11, 0, 0x7773U;
+; CHECK-NEXT: selp.b32 %r13, %r10, %r12, %p4;
+; CHECK-NEXT: prmt.b32 %r14, %r11, 0, 0x7772U;
+; CHECK-NEXT: selp.b32 %r15, %r8, %r14, %p3;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r13, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r11, 0, 0x7771U;
+; CHECK-NEXT: selp.b32 %r18, %r6, %r17, %p2;
+; CHECK-NEXT: prmt.b32 %r19, %r11, 0, 0x7770U;
+; CHECK-NEXT: selp.b32 %r20, %r4, %r19, %p1;
+; CHECK-NEXT: prmt.b32 %r21, %r20, %r18, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r22, %r21, %r16, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r22;
+; CHECK-NEXT: ret;
%cmp = icmp ne <4 x i8> %a, %b
%r = select <4 x i1> %cmp, <4 x i8> %a, <4 x i8> %c
ret <4 x i8> %r
}
define <4 x i8> @test_mul(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_mul(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<13>;
-; O0-NEXT: .reg .b32 %r<18>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_mul_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_mul_param_0];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
-; O0-NEXT: cvt.u16.u32 %rs1, %r3;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
-; O0-NEXT: cvt.u16.u32 %rs2, %r4;
-; O0-NEXT: mul.lo.s16 %rs3, %rs2, %rs1;
-; O0-NEXT: cvt.u32.u16 %r5, %rs3;
-; O0-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
-; O0-NEXT: cvt.u16.u32 %rs4, %r6;
-; O0-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
-; O0-NEXT: cvt.u16.u32 %rs5, %r7;
-; O0-NEXT: mul.lo.s16 %rs6, %rs5, %rs4;
-; O0-NEXT: cvt.u32.u16 %r8, %rs6;
-; O0-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O0-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
-; O0-NEXT: cvt.u16.u32 %rs7, %r10;
-; O0-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
-; O0-NEXT: cvt.u16.u32 %rs8, %r11;
-; O0-NEXT: mul.lo.s16 %rs9, %rs8, %rs7;
-; O0-NEXT: cvt.u32.u16 %r12, %rs9;
-; O0-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
-; O0-NEXT: cvt.u16.u32 %rs10, %r13;
-; O0-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
-; O0-NEXT: cvt.u16.u32 %rs11, %r14;
-; O0-NEXT: mul.lo.s16 %rs12, %rs11, %rs10;
-; O0-NEXT: cvt.u32.u16 %r15, %rs12;
-; O0-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r17;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_mul(
-; O3: {
-; O3-NEXT: .reg .b16 %rs<13>;
-; O3-NEXT: .reg .b32 %r<18>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_mul_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_mul_param_1];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
-; O3-NEXT: cvt.u16.u32 %rs1, %r3;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
-; O3-NEXT: cvt.u16.u32 %rs2, %r4;
-; O3-NEXT: mul.lo.s16 %rs3, %rs2, %rs1;
-; O3-NEXT: cvt.u32.u16 %r5, %rs3;
-; O3-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
-; O3-NEXT: cvt.u16.u32 %rs4, %r6;
-; O3-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
-; O3-NEXT: cvt.u16.u32 %rs5, %r7;
-; O3-NEXT: mul.lo.s16 %rs6, %rs5, %rs4;
-; O3-NEXT: cvt.u32.u16 %r8, %rs6;
-; O3-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O3-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
-; O3-NEXT: cvt.u16.u32 %rs7, %r10;
-; O3-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
-; O3-NEXT: cvt.u16.u32 %rs8, %r11;
-; O3-NEXT: mul.lo.s16 %rs9, %rs8, %rs7;
-; O3-NEXT: cvt.u32.u16 %r12, %rs9;
-; O3-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
-; O3-NEXT: cvt.u16.u32 %rs10, %r13;
-; O3-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
-; O3-NEXT: cvt.u16.u32 %rs11, %r14;
-; O3-NEXT: mul.lo.s16 %rs12, %rs11, %rs10;
-; O3-NEXT: cvt.u32.u16 %r15, %rs12;
-; O3-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r17;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_mul(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<13>;
+; CHECK-NEXT: .reg .b32 %r<18>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_mul_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_mul_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7773U;
+; CHECK-NEXT: cvt.u16.u32 %rs1, %r3;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7773U;
+; CHECK-NEXT: cvt.u16.u32 %rs2, %r4;
+; CHECK-NEXT: mul.lo.s16 %rs3, %rs2, %rs1;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs3;
+; CHECK-NEXT: prmt.b32 %r6, %r2, 0, 0x7772U;
+; CHECK-NEXT: cvt.u16.u32 %rs4, %r6;
+; CHECK-NEXT: prmt.b32 %r7, %r1, 0, 0x7772U;
+; CHECK-NEXT: cvt.u16.u32 %rs5, %r7;
+; CHECK-NEXT: mul.lo.s16 %rs6, %rs5, %rs4;
+; CHECK-NEXT: cvt.u32.u16 %r8, %rs6;
+; CHECK-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r10, %r2, 0, 0x7771U;
+; CHECK-NEXT: cvt.u16.u32 %rs7, %r10;
+; CHECK-NEXT: prmt.b32 %r11, %r1, 0, 0x7771U;
+; CHECK-NEXT: cvt.u16.u32 %rs8, %r11;
+; CHECK-NEXT: mul.lo.s16 %rs9, %rs8, %rs7;
+; CHECK-NEXT: cvt.u32.u16 %r12, %rs9;
+; CHECK-NEXT: prmt.b32 %r13, %r2, 0, 0x7770U;
+; CHECK-NEXT: cvt.u16.u32 %rs10, %r13;
+; CHECK-NEXT: prmt.b32 %r14, %r1, 0, 0x7770U;
+; CHECK-NEXT: cvt.u16.u32 %rs11, %r14;
+; CHECK-NEXT: mul.lo.s16 %rs12, %rs11, %rs10;
+; CHECK-NEXT: cvt.u32.u16 %r15, %rs12;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r12, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r16, %r9, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r17;
+; CHECK-NEXT: ret;
%r = mul <4 x i8> %a, %b
ret <4 x i8> %r
}
define <4 x i8> @test_or(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_or(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_or_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_or_param_0];
-; O0-NEXT: or.b32 %r3, %r1, %r2;
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_or(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_or_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_or_param_1];
-; O3-NEXT: or.b32 %r3, %r1, %r2;
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_or(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_or_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_or_param_1];
+; CHECK-NEXT: or.b32 %r3, %r1, %r2;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = or <4 x i8> %a, %b
ret <4 x i8> %r
}
@@ -889,12 +544,10 @@ define <4 x i8> @test_or(<4 x i8> %a, <4 x i8> %b) #0 {
define <4 x i8> @test_or_computed(i8 %a) {
; O0-LABEL: test_or_computed(
; O0: {
-; O0-NEXT: .reg .b16 %rs<2>;
; O0-NEXT: .reg .b32 %r<5>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b8 %rs1, [test_or_computed_param_0];
-; O0-NEXT: cvt.u32.u16 %r1, %rs1;
+; O0-NEXT: ld.param.b8 %r1, [test_or_computed_param_0];
; O0-NEXT: prmt.b32 %r2, %r1, 5, 0x3340U;
; O0-NEXT: prmt.b32 %r3, 0, 0, 0x3340U;
; O0-NEXT: prmt.b32 %r4, %r2, %r3, 0x5410U;
@@ -946,27 +599,16 @@ define <4 x i8> @test_or_imm_1(<4 x i8> %a) #0 {
}
define <4 x i8> @test_xor(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_xor(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_xor_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_xor_param_0];
-; O0-NEXT: xor.b32 %r3, %r1, %r2;
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_xor(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_xor_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_xor_param_1];
-; O3-NEXT: xor.b32 %r3, %r1, %r2;
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_xor(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_xor_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_xor_param_1];
+; CHECK-NEXT: xor.b32 %r3, %r1, %r2;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = xor <4 x i8> %a, %b
ret <4 x i8> %r
}
@@ -974,12 +616,10 @@ define <4 x i8> @test_xor(<4 x i8> %a, <4 x i8> %b) #0 {
define <4 x i8> @test_xor_computed(i8 %a) {
; O0-LABEL: test_xor_computed(
; O0: {
-; O0-NEXT: .reg .b16 %rs<2>;
; O0-NEXT: .reg .b32 %r<8>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b8 %rs1, [test_xor_computed_param_0];
-; O0-NEXT: cvt.u32.u16 %r1, %rs1;
+; O0-NEXT: ld.param.b8 %r1, [test_xor_computed_param_0];
; O0-NEXT: prmt.b32 %r2, %r1, 0, 0x3340U;
; O0-NEXT: prmt.b32 %r3, 0, 0, 0x3340U;
; O0-NEXT: prmt.b32 %r4, %r2, %r3, 0x5410U;
@@ -1037,27 +677,16 @@ define <4 x i8> @test_xor_imm_1(<4 x i8> %a) #0 {
}
define <4 x i8> @test_and(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_and(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_and_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_and_param_0];
-; O0-NEXT: and.b32 %r3, %r1, %r2;
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_and(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_and_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_and_param_1];
-; O3-NEXT: and.b32 %r3, %r1, %r2;
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_and(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_and_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_and_param_1];
+; CHECK-NEXT: and.b32 %r3, %r1, %r2;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = and <4 x i8> %a, %b
ret <4 x i8> %r
}
@@ -1065,12 +694,10 @@ define <4 x i8> @test_and(<4 x i8> %a, <4 x i8> %b) #0 {
define <4 x i8> @test_and_computed(i8 %a) {
; O0-LABEL: test_and_computed(
; O0: {
-; O0-NEXT: .reg .b16 %rs<2>;
; O0-NEXT: .reg .b32 %r<5>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b8 %rs1, [test_and_computed_param_0];
-; O0-NEXT: cvt.u32.u16 %r1, %rs1;
+; O0-NEXT: ld.param.b8 %r1, [test_and_computed_param_0];
; O0-NEXT: prmt.b32 %r2, %r1, 0, 0x3340U;
; O0-NEXT: prmt.b32 %r3, 0, 0, 0x3340U;
; O0-NEXT: prmt.b32 %r4, %r2, %r3, 0x5410U;
@@ -1122,91 +749,53 @@ define <4 x i8> @test_and_imm_1(<4 x i8> %a) #0 {
}
define void @test_ldst_v2i8(ptr %a, ptr %b) {
-; O0-LABEL: test_ldst_v2i8(
-; O0: {
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-NEXT: .reg .b64 %rd<3>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd2, [test_ldst_v2i8_param_1];
-; O0-NEXT: ld.param.b64 %rd1, [test_ldst_v2i8_param_0];
-; O0-NEXT: ld.b32 %r1, [%rd1];
-; O0-NEXT: st.b32 [%rd2], %r1;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_ldst_v2i8(
-; O3: {
-; O3-NEXT: .reg .b32 %r<2>;
-; O3-NEXT: .reg .b64 %rd<3>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b64 %rd1, [test_ldst_v2i8_param_0];
-; O3-NEXT: ld.b32 %r1, [%rd1];
-; O3-NEXT: ld.param.b64 %rd2, [test_ldst_v2i8_param_1];
-; O3-NEXT: st.b32 [%rd2], %r1;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_ldst_v2i8(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v2i8_param_0];
+; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v2i8_param_1];
+; CHECK-NEXT: st.b32 [%rd2], %r1;
+; CHECK-NEXT: ret;
%t1 = load <4 x i8>, ptr %a
store <4 x i8> %t1, ptr %b, align 16
ret void
}
define void @test_ldst_v3i8(ptr %a, ptr %b) {
-; O0-LABEL: test_ldst_v3i8(
-; O0: {
-; O0-NEXT: .reg .b32 %r<3>;
-; O0-NEXT: .reg .b64 %rd<3>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd2, [test_ldst_v3i8_param_1];
-; O0-NEXT: ld.param.b64 %rd1, [test_ldst_v3i8_param_0];
-; O0-NEXT: ld.b32 %r1, [%rd1];
-; O0-NEXT: st.b16 [%rd2], %r1;
-; O0-NEXT: prmt.b32 %r2, %r1, 0, 0x7772U;
-; O0-NEXT: st.b8 [%rd2+2], %r2;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_ldst_v3i8(
-; O3: {
-; O3-NEXT: .reg .b32 %r<3>;
-; O3-NEXT: .reg .b64 %rd<3>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b64 %rd1, [test_ldst_v3i8_param_0];
-; O3-NEXT: ld.b32 %r1, [%rd1];
-; O3-NEXT: ld.param.b64 %rd2, [test_ldst_v3i8_param_1];
-; O3-NEXT: st.b16 [%rd2], %r1;
-; O3-NEXT: prmt.b32 %r2, %r1, 0, 0x7772U;
-; O3-NEXT: st.b8 [%rd2+2], %r2;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_ldst_v3i8(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v3i8_param_0];
+; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v3i8_param_1];
+; CHECK-NEXT: st.b16 [%rd2], %r1;
+; CHECK-NEXT: prmt.b32 %r2, %r1, 0, 0x7772U;
+; CHECK-NEXT: st.b8 [%rd2+2], %r2;
+; CHECK-NEXT: ret;
%t1 = load <3 x i8>, ptr %a
store <3 x i8> %t1, ptr %b, align 16
ret void
}
define void @test_ldst_v4i8(ptr %a, ptr %b) {
-; O0-LABEL: test_ldst_v4i8(
-; O0: {
-; O0-NEXT: .reg .b32 %r<2>;
-; O0-NEXT: .reg .b64 %rd<3>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd2, [test_ldst_v4i8_param_1];
-; O0-NEXT: ld.param.b64 %rd1, [test_ldst_v4i8_param_0];
-; O0-NEXT: ld.b32 %r1, [%rd1];
-; O0-NEXT: st.b32 [%rd2], %r1;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_ldst_v4i8(
-; O3: {
-; O3-NEXT: .reg .b32 %r<2>;
-; O3-NEXT: .reg .b64 %rd<3>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b64 %rd1, [test_ldst_v4i8_param_0];
-; O3-NEXT: ld.b32 %r1, [%rd1];
-; O3-NEXT: ld.param.b64 %rd2, [test_ldst_v4i8_param_1];
-; O3-NEXT: st.b32 [%rd2], %r1;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_ldst_v4i8(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<2>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v4i8_param_0];
+; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v4i8_param_1];
+; CHECK-NEXT: st.b32 [%rd2], %r1;
+; CHECK-NEXT: ret;
%t1 = load <4 x i8>, ptr %a
store <4 x i8> %t1, ptr %b, align 16
ret void
@@ -1219,12 +808,12 @@ define void @test_ldst_v4i8_unaligned(ptr %a, ptr %b) {
; O0-NEXT: .reg .b64 %rd<3>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd2, [test_ldst_v4i8_unaligned_param_1];
; O0-NEXT: ld.param.b64 %rd1, [test_ldst_v4i8_unaligned_param_0];
; O0-NEXT: ld.b8 %r1, [%rd1];
; O0-NEXT: ld.b8 %r2, [%rd1+1];
; O0-NEXT: ld.b8 %r3, [%rd1+2];
; O0-NEXT: ld.b8 %r4, [%rd1+3];
+; O0-NEXT: ld.param.b64 %rd2, [test_ldst_v4i8_unaligned_param_1];
; O0-NEXT: st.b8 [%rd2+3], %r4;
; O0-NEXT: st.b8 [%rd2+2], %r3;
; O0-NEXT: st.b8 [%rd2+1], %r2;
@@ -1255,29 +844,17 @@ define void @test_ldst_v4i8_unaligned(ptr %a, ptr %b) {
define void @test_ldst_v8i8(ptr %a, ptr %b) {
-; O0-LABEL: test_ldst_v8i8(
-; O0: {
-; O0-NEXT: .reg .b32 %r<3>;
-; O0-NEXT: .reg .b64 %rd<3>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b64 %rd2, [test_ldst_v8i8_param_1];
-; O0-NEXT: ld.param.b64 %rd1, [test_ldst_v8i8_param_0];
-; O0-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
-; O0-NEXT: st.v2.b32 [%rd2], {%r1, %r2};
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_ldst_v8i8(
-; O3: {
-; O3-NEXT: .reg .b32 %r<3>;
-; O3-NEXT: .reg .b64 %rd<3>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b64 %rd1, [test_ldst_v8i8_param_0];
-; O3-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
-; O3-NEXT: ld.param.b64 %rd2, [test_ldst_v8i8_param_1];
-; O3-NEXT: st.v2.b32 [%rd2], {%r1, %r2};
-; O3-NEXT: ret;
+; CHECK-LABEL: test_ldst_v8i8(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<3>;
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b64 %rd1, [test_ldst_v8i8_param_0];
+; CHECK-NEXT: ld.v2.b32 {%r1, %r2}, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_ldst_v8i8_param_1];
+; CHECK-NEXT: st.v2.b32 [%rd2], {%r1, %r2};
+; CHECK-NEXT: ret;
%t1 = load <8 x i8>, ptr %a
store <8 x i8> %t1, ptr %b, align 16
ret void
@@ -1286,127 +863,70 @@ define void @test_ldst_v8i8(ptr %a, ptr %b) {
declare <4 x i8> @test_callee(<4 x i8> %a, <4 x i8> %b) #0
define <4 x i8> @test_call(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_call(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_call_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_call_param_0];
-; O0-NEXT: { // callseq 0, 0
-; O0-NEXT: .param .align 4 .b8 param0[4];
-; O0-NEXT: .param .align 4 .b8 param1[4];
-; O0-NEXT: .param .align 4 .b8 retval0[4];
-; O0-NEXT: st.param.b32 [param1], %r2;
-; O0-NEXT: st.param.b32 [param0], %r1;
-; O0-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; O0-NEXT: ld.param.b32 %r3, [retval0];
-; O0-NEXT: } // callseq 0
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_call(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_call_param_0];
-; O3-NEXT: { // callseq 0, 0
-; O3-NEXT: .param .align 4 .b8 param0[4];
-; O3-NEXT: .param .align 4 .b8 param1[4];
-; O3-NEXT: .param .align 4 .b8 retval0[4];
-; O3-NEXT: ld.param.b32 %r2, [test_call_param_1];
-; O3-NEXT: st.param.b32 [param1], %r2;
-; O3-NEXT: st.param.b32 [param0], %r1;
-; O3-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; O3-NEXT: ld.param.b32 %r3, [retval0];
-; O3-NEXT: } // callseq 0
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_call(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_call_param_0];
+; CHECK-NEXT: { // callseq 0, 0
+; CHECK-NEXT: .param .align 4 .b8 param0[4];
+; CHECK-NEXT: .param .align 4 .b8 param1[4];
+; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: ld.param.b32 %r2, [test_call_param_1];
+; CHECK-NEXT: st.param.b32 [param1], %r2;
+; CHECK-NEXT: st.param.b32 [param0], %r1;
+; CHECK-NEXT: call.uni (retval0), test_callee, (param0, param1);
+; CHECK-NEXT: ld.param.b32 %r3, [retval0];
+; CHECK-NEXT: } // callseq 0
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <4 x i8> @test_callee(<4 x i8> %a, <4 x i8> %b)
ret <4 x i8> %r
}
define <4 x i8> @test_call_flipped(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_call_flipped(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_call_flipped_param_0];
-; O0-NEXT: { // callseq 1, 0
-; O0-NEXT: .param .align 4 .b8 param0[4];
-; O0-NEXT: .param .align 4 .b8 param1[4];
-; O0-NEXT: .param .align 4 .b8 retval0[4];
-; O0-NEXT: st.param.b32 [param1], %r1;
-; O0-NEXT: st.param.b32 [param0], %r2;
-; O0-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; O0-NEXT: ld.param.b32 %r3, [retval0];
-; O0-NEXT: } // callseq 1
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_call_flipped(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_call_flipped_param_0];
-; O3-NEXT: { // callseq 1, 0
-; O3-NEXT: .param .align 4 .b8 param0[4];
-; O3-NEXT: .param .align 4 .b8 param1[4];
-; O3-NEXT: .param .align 4 .b8 retval0[4];
-; O3-NEXT: st.param.b32 [param1], %r1;
-; O3-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
-; O3-NEXT: st.param.b32 [param0], %r2;
-; O3-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; O3-NEXT: ld.param.b32 %r3, [retval0];
-; O3-NEXT: } // callseq 1
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_call_flipped(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_call_flipped_param_0];
+; CHECK-NEXT: { // callseq 1, 0
+; CHECK-NEXT: .param .align 4 .b8 param0[4];
+; CHECK-NEXT: .param .align 4 .b8 param1[4];
+; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: st.param.b32 [param1], %r1;
+; CHECK-NEXT: ld.param.b32 %r2, [test_call_flipped_param_1];
+; CHECK-NEXT: st.param.b32 [param0], %r2;
+; CHECK-NEXT: call.uni (retval0), test_callee, (param0, param1);
+; CHECK-NEXT: ld.param.b32 %r3, [retval0];
+; CHECK-NEXT: } // callseq 1
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = call <4 x i8> @test_callee(<4 x i8> %b, <4 x i8> %a)
ret <4 x i8> %r
}
define <4 x i8> @test_tailcall_flipped(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_tailcall_flipped(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_tailcall_flipped_param_0];
-; O0-NEXT: { // callseq 2, 0
-; O0-NEXT: .param .align 4 .b8 param0[4];
-; O0-NEXT: .param .align 4 .b8 param1[4];
-; O0-NEXT: .param .align 4 .b8 retval0[4];
-; O0-NEXT: st.param.b32 [param1], %r1;
-; O0-NEXT: st.param.b32 [param0], %r2;
-; O0-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; O0-NEXT: ld.param.b32 %r3, [retval0];
-; O0-NEXT: } // callseq 2
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_tailcall_flipped(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_tailcall_flipped_param_0];
-; O3-NEXT: { // callseq 2, 0
-; O3-NEXT: .param .align 4 .b8 param0[4];
-; O3-NEXT: .param .align 4 .b8 param1[4];
-; O3-NEXT: .param .align 4 .b8 retval0[4];
-; O3-NEXT: st.param.b32 [param1], %r1;
-; O3-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
-; O3-NEXT: st.param.b32 [param0], %r2;
-; O3-NEXT: call.uni (retval0), test_callee, (param0, param1);
-; O3-NEXT: ld.param.b32 %r3, [retval0];
-; O3-NEXT: } // callseq 2
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_tailcall_flipped(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_tailcall_flipped_param_0];
+; CHECK-NEXT: { // callseq 2, 0
+; CHECK-NEXT: .param .align 4 .b8 param0[4];
+; CHECK-NEXT: .param .align 4 .b8 param1[4];
+; CHECK-NEXT: .param .align 4 .b8 retval0[4];
+; CHECK-NEXT: st.param.b32 [param1], %r1;
+; CHECK-NEXT: ld.param.b32 %r2, [test_tailcall_flipped_param_1];
+; CHECK-NEXT: st.param.b32 [param0], %r2;
+; CHECK-NEXT: call.uni (retval0), test_callee, (param0, param1);
+; CHECK-NEXT: ld.param.b32 %r3, [retval0];
+; CHECK-NEXT: } // callseq 2
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%r = tail call <4 x i8> @test_callee(<4 x i8> %b, <4 x i8> %a)
ret <4 x i8> %r
}
@@ -1415,17 +935,20 @@ define <4 x i8> @test_select(<4 x i8> %a, <4 x i8> %b, i1 zeroext %c) #0 {
; O0-LABEL: test_select(
; O0: {
; O0-NEXT: .reg .pred %p<2>;
-; O0-NEXT: .reg .b16 %rs<3>;
-; O0-NEXT: .reg .b32 %r<4>;
+; O0-NEXT: .reg .b16 %rs<4>;
+; O0-NEXT: .reg .b32 %r<2>;
+; O0-NEXT: .reg .b64 %rd<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
; O0-NEXT: ld.param.b8 %rs1, [test_select_param_2];
-; O0-NEXT: and.b16 %rs2, %rs1, 1;
-; O0-NEXT: setp.ne.b16 %p1, %rs2, 0;
-; O0-NEXT: ld.param.b32 %r2, [test_select_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_select_param_0];
-; O0-NEXT: selp.b32 %r3, %r1, %r2, %p1;
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
+; O0-NEXT: mov.b16 %rs2, %rs1;
+; O0-NEXT: and.b16 %rs3, %rs2, 1;
+; O0-NEXT: setp.ne.b16 %p1, %rs3, 0;
+; O0-NEXT: mov.b64 %rd1, test_select_param_1;
+; O0-NEXT: mov.b64 %rd2, test_select_param_0;
+; O0-NEXT: selp.b64 %rd3, %rd2, %rd1, %p1;
+; O0-NEXT: ld.param.b32 %r1, [%rd3];
+; O0-NEXT: st.param.b32 [func_retval0], %r1;
; O0-NEXT: ret;
;
; O3-LABEL: test_select(
@@ -1450,148 +973,79 @@ define <4 x i8> @test_select(<4 x i8> %a, <4 x i8> %b, i1 zeroext %c) #0 {
}
define <4 x i8> @test_select_cc(<4 x i8> %a, <4 x i8> %b, <4 x i8> %c, <4 x i8> %d) #0 {
-; O0-LABEL: test_select_cc(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<28>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r4, [test_select_cc_param_3];
-; O0-NEXT: ld.param.b32 %r3, [test_select_cc_param_2];
-; O0-NEXT: ld.param.b32 %r2, [test_select_cc_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
-; O0-NEXT: prmt.b32 %r5, %r4, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r6, %r3, 0, 0x7770U;
-; O0-NEXT: setp.ne.b32 %p1, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r4, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r8, %r3, 0, 0x7771U;
-; O0-NEXT: setp.ne.b32 %p2, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r4, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r10, %r3, 0, 0x7772U;
-; O0-NEXT: setp.ne.b32 %p3, %r10, %r9;
-; O0-NEXT: prmt.b32 %r11, %r4, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r12, %r3, 0, 0x7773U;
-; O0-NEXT: setp.ne.b32 %p4, %r12, %r11;
-; O0-NEXT: prmt.b32 %r13, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r14, %r1, 0, 0x7773U;
-; O0-NEXT: selp.b32 %r15, %r14, %r13, %p4;
-; O0-NEXT: prmt.b32 %r16, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
-; O0-NEXT: selp.b32 %r18, %r17, %r16, %p3;
-; O0-NEXT: prmt.b32 %r19, %r18, %r15, 0x3340U;
-; O0-NEXT: prmt.b32 %r20, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r21, %r1, 0, 0x7771U;
-; O0-NEXT: selp.b32 %r22, %r21, %r20, %p2;
-; O0-NEXT: prmt.b32 %r23, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r24, %r1, 0, 0x7770U;
-; O0-NEXT: selp.b32 %r25, %r24, %r23, %p1;
-; O0-NEXT: prmt.b32 %r26, %r25, %r22, 0x3340U;
-; O0-NEXT: prmt.b32 %r27, %r26, %r19, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r27;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_select_cc(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<28>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_select_cc_param_3];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: ld.param.b32 %r4, [test_select_cc_param_2];
-; O3-NEXT: prmt.b32 %r5, %r4, 0, 0x7770U;
-; O3-NEXT: setp.ne.b32 %p1, %r5, %r3;
-; O3-NEXT: prmt.b32 %r6, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r7, %r4, 0, 0x7771U;
-; O3-NEXT: setp.ne.b32 %p2, %r7, %r6;
-; O3-NEXT: prmt.b32 %r8, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r9, %r4, 0, 0x7772U;
-; O3-NEXT: setp.ne.b32 %p3, %r9, %r8;
-; O3-NEXT: prmt.b32 %r10, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r11, %r4, 0, 0x7773U;
-; O3-NEXT: setp.ne.b32 %p4, %r11, %r10;
-; O3-NEXT: ld.param.b32 %r12, [test_select_cc_param_1];
-; O3-NEXT: prmt.b32 %r13, %r12, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r14, %r1, 0, 0x7773U;
-; O3-NEXT: selp.b32 %r15, %r14, %r13, %p4;
-; O3-NEXT: prmt.b32 %r16, %r12, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
-; O3-NEXT: selp.b32 %r18, %r17, %r16, %p3;
-; O3-NEXT: prmt.b32 %r19, %r18, %r15, 0x3340U;
-; O3-NEXT: prmt.b32 %r20, %r12, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r21, %r1, 0, 0x7771U;
-; O3-NEXT: selp.b32 %r22, %r21, %r20, %p2;
-; O3-NEXT: prmt.b32 %r23, %r12, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r24, %r1, 0, 0x7770U;
-; O3-NEXT: selp.b32 %r25, %r24, %r23, %p1;
-; O3-NEXT: prmt.b32 %r26, %r25, %r22, 0x3340U;
-; O3-NEXT: prmt.b32 %r27, %r26, %r19, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r27;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_select_cc(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<28>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_select_cc_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_select_cc_param_3];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
+; CHECK-NEXT: ld.param.b32 %r4, [test_select_cc_param_2];
+; CHECK-NEXT: prmt.b32 %r5, %r4, 0, 0x7770U;
+; CHECK-NEXT: setp.ne.b32 %p1, %r5, %r3;
+; CHECK-NEXT: prmt.b32 %r6, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r7, %r4, 0, 0x7771U;
+; CHECK-NEXT: setp.ne.b32 %p2, %r7, %r6;
+; CHECK-NEXT: prmt.b32 %r8, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r9, %r4, 0, 0x7772U;
+; CHECK-NEXT: setp.ne.b32 %p3, %r9, %r8;
+; CHECK-NEXT: prmt.b32 %r10, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r11, %r4, 0, 0x7773U;
+; CHECK-NEXT: setp.ne.b32 %p4, %r11, %r10;
+; CHECK-NEXT: ld.param.b32 %r12, [test_select_cc_param_1];
+; CHECK-NEXT: prmt.b32 %r13, %r12, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r14, %r1, 0, 0x7773U;
+; CHECK-NEXT: selp.b32 %r15, %r14, %r13, %p4;
+; CHECK-NEXT: prmt.b32 %r16, %r12, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r17, %r1, 0, 0x7772U;
+; CHECK-NEXT: selp.b32 %r18, %r17, %r16, %p3;
+; CHECK-NEXT: prmt.b32 %r19, %r18, %r15, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r20, %r12, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r21, %r1, 0, 0x7771U;
+; CHECK-NEXT: selp.b32 %r22, %r21, %r20, %p2;
+; CHECK-NEXT: prmt.b32 %r23, %r12, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r24, %r1, 0, 0x7770U;
+; CHECK-NEXT: selp.b32 %r25, %r24, %r23, %p1;
+; CHECK-NEXT: prmt.b32 %r26, %r25, %r22, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r27, %r26, %r19, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r27;
+; CHECK-NEXT: ret;
%cc = icmp ne <4 x i8> %c, %d
%r = select <4 x i1> %cc, <4 x i8> %a, <4 x i8> %b
ret <4 x i8> %r
}
define <4 x i32> @test_select_cc_i32_i8(<4 x i32> %a, <4 x i32> %b,
-; O0-LABEL: test_select_cc_i32_i8(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<23>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [test_select_cc_i32_i8_param_1];
-; O0-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [test_select_cc_i32_i8_param_0];
-; O0-NEXT: ld.param.b32 %r10, [test_select_cc_i32_i8_param_3];
-; O0-NEXT: ld.param.b32 %r9, [test_select_cc_i32_i8_param_2];
-; O0-NEXT: prmt.b32 %r11, %r10, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r12, %r9, 0, 0x7770U;
-; O0-NEXT: setp.ne.b32 %p1, %r12, %r11;
-; O0-NEXT: prmt.b32 %r13, %r10, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r14, %r9, 0, 0x7771U;
-; O0-NEXT: setp.ne.b32 %p2, %r14, %r13;
-; O0-NEXT: prmt.b32 %r15, %r10, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r16, %r9, 0, 0x7772U;
-; O0-NEXT: setp.ne.b32 %p3, %r16, %r15;
-; O0-NEXT: prmt.b32 %r17, %r10, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r18, %r9, 0, 0x7773U;
-; O0-NEXT: setp.ne.b32 %p4, %r18, %r17;
-; O0-NEXT: selp.b32 %r19, %r4, %r8, %p4;
-; O0-NEXT: selp.b32 %r20, %r3, %r7, %p3;
-; O0-NEXT: selp.b32 %r21, %r2, %r6, %p2;
-; O0-NEXT: selp.b32 %r22, %r1, %r5, %p1;
-; O0-NEXT: st.param.v4.b32 [func_retval0], {%r22, %r21, %r20, %r19};
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_select_cc_i32_i8(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<23>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [test_select_cc_i32_i8_param_0];
-; O3-NEXT: ld.param.b32 %r5, [test_select_cc_i32_i8_param_3];
-; O3-NEXT: prmt.b32 %r6, %r5, 0, 0x7770U;
-; O3-NEXT: ld.param.b32 %r7, [test_select_cc_i32_i8_param_2];
-; O3-NEXT: prmt.b32 %r8, %r7, 0, 0x7770U;
-; O3-NEXT: setp.ne.b32 %p1, %r8, %r6;
-; O3-NEXT: prmt.b32 %r9, %r5, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r10, %r7, 0, 0x7771U;
-; O3-NEXT: setp.ne.b32 %p2, %r10, %r9;
-; O3-NEXT: prmt.b32 %r11, %r5, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r12, %r7, 0, 0x7772U;
-; O3-NEXT: setp.ne.b32 %p3, %r12, %r11;
-; O3-NEXT: prmt.b32 %r13, %r5, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r14, %r7, 0, 0x7773U;
-; O3-NEXT: setp.ne.b32 %p4, %r14, %r13;
-; O3-NEXT: ld.param.v4.b32 {%r15, %r16, %r17, %r18}, [test_select_cc_i32_i8_param_1];
-; O3-NEXT: selp.b32 %r19, %r4, %r18, %p4;
-; O3-NEXT: selp.b32 %r20, %r3, %r17, %p3;
-; O3-NEXT: selp.b32 %r21, %r2, %r16, %p2;
-; O3-NEXT: selp.b32 %r22, %r1, %r15, %p1;
-; O3-NEXT: st.param.v4.b32 [func_retval0], {%r22, %r21, %r20, %r19};
-; O3-NEXT: ret;
+; CHECK-LABEL: test_select_cc_i32_i8(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<23>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [test_select_cc_i32_i8_param_0];
+; CHECK-NEXT: ld.param.b32 %r5, [test_select_cc_i32_i8_param_3];
+; CHECK-NEXT: prmt.b32 %r6, %r5, 0, 0x7770U;
+; CHECK-NEXT: ld.param.b32 %r7, [test_select_cc_i32_i8_param_2];
+; CHECK-NEXT: prmt.b32 %r8, %r7, 0, 0x7770U;
+; CHECK-NEXT: setp.ne.b32 %p1, %r8, %r6;
+; CHECK-NEXT: prmt.b32 %r9, %r5, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r10, %r7, 0, 0x7771U;
+; CHECK-NEXT: setp.ne.b32 %p2, %r10, %r9;
+; CHECK-NEXT: prmt.b32 %r11, %r5, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r12, %r7, 0, 0x7772U;
+; CHECK-NEXT: setp.ne.b32 %p3, %r12, %r11;
+; CHECK-NEXT: prmt.b32 %r13, %r5, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r14, %r7, 0, 0x7773U;
+; CHECK-NEXT: setp.ne.b32 %p4, %r14, %r13;
+; CHECK-NEXT: ld.param.v4.b32 {%r15, %r16, %r17, %r18}, [test_select_cc_i32_i8_param_1];
+; CHECK-NEXT: selp.b32 %r19, %r4, %r18, %p4;
+; CHECK-NEXT: selp.b32 %r20, %r3, %r17, %p3;
+; CHECK-NEXT: selp.b32 %r21, %r2, %r16, %p2;
+; CHECK-NEXT: selp.b32 %r22, %r1, %r15, %p1;
+; CHECK-NEXT: st.param.v4.b32 [func_retval0], {%r22, %r21, %r20, %r19};
+; CHECK-NEXT: ret;
<4 x i8> %c, <4 x i8> %d) #0 {
%cc = icmp ne <4 x i8> %c, %d
%r = select <4 x i1> %cc, <4 x i32> %a, <4 x i32> %b
@@ -1599,69 +1053,37 @@ define <4 x i32> @test_select_cc_i32_i8(<4 x i32> %a, <4 x i32> %b,
}
define <4 x i8> @test_select_cc_i8_i32(<4 x i8> %a, <4 x i8> %b,
-; O0-LABEL: test_select_cc_i8_i32(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<26>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.v4.b32 {%r7, %r8, %r9, %r10}, [test_select_cc_i8_i32_param_3];
-; O0-NEXT: ld.param.v4.b32 {%r3, %r4, %r5, %r6}, [test_select_cc_i8_i32_param_2];
-; O0-NEXT: ld.param.b32 %r2, [test_select_cc_i8_i32_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_select_cc_i8_i32_param_0];
-; O0-NEXT: setp.ne.b32 %p1, %r3, %r7;
-; O0-NEXT: setp.ne.b32 %p2, %r4, %r8;
-; O0-NEXT: setp.ne.b32 %p3, %r5, %r9;
-; O0-NEXT: setp.ne.b32 %p4, %r6, %r10;
-; O0-NEXT: prmt.b32 %r11, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r12, %r1, 0, 0x7773U;
-; O0-NEXT: selp.b32 %r13, %r12, %r11, %p4;
-; O0-NEXT: prmt.b32 %r14, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r15, %r1, 0, 0x7772U;
-; O0-NEXT: selp.b32 %r16, %r15, %r14, %p3;
-; O0-NEXT: prmt.b32 %r17, %r16, %r13, 0x3340U;
-; O0-NEXT: prmt.b32 %r18, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r19, %r1, 0, 0x7771U;
-; O0-NEXT: selp.b32 %r20, %r19, %r18, %p2;
-; O0-NEXT: prmt.b32 %r21, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
-; O0-NEXT: selp.b32 %r23, %r22, %r21, %p1;
-; O0-NEXT: prmt.b32 %r24, %r23, %r20, 0x3340U;
-; O0-NEXT: prmt.b32 %r25, %r24, %r17, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r25;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_select_cc_i8_i32(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<26>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_select_cc_i8_i32_param_0];
-; O3-NEXT: ld.param.v4.b32 {%r2, %r3, %r4, %r5}, [test_select_cc_i8_i32_param_2];
-; O3-NEXT: ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [test_select_cc_i8_i32_param_3];
-; O3-NEXT: setp.ne.b32 %p1, %r2, %r6;
-; O3-NEXT: setp.ne.b32 %p2, %r3, %r7;
-; O3-NEXT: setp.ne.b32 %p3, %r4, %r8;
-; O3-NEXT: setp.ne.b32 %p4, %r5, %r9;
-; O3-NEXT: ld.param.b32 %r10, [test_select_cc_i8_i32_param_1];
-; O3-NEXT: prmt.b32 %r11, %r10, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r12, %r1, 0, 0x7773U;
-; O3-NEXT: selp.b32 %r13, %r12, %r11, %p4;
-; O3-NEXT: prmt.b32 %r14, %r10, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r15, %r1, 0, 0x7772U;
-; O3-NEXT: selp.b32 %r16, %r15, %r14, %p3;
-; O3-NEXT: prmt.b32 %r17, %r16, %r13, 0x3340U;
-; O3-NEXT: prmt.b32 %r18, %r10, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r19, %r1, 0, 0x7771U;
-; O3-NEXT: selp.b32 %r20, %r19, %r18, %p2;
-; O3-NEXT: prmt.b32 %r21, %r10, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
-; O3-NEXT: selp.b32 %r23, %r22, %r21, %p1;
-; O3-NEXT: prmt.b32 %r24, %r23, %r20, 0x3340U;
-; O3-NEXT: prmt.b32 %r25, %r24, %r17, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r25;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_select_cc_i8_i32(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<26>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_select_cc_i8_i32_param_0];
+; CHECK-NEXT: ld.param.v4.b32 {%r2, %r3, %r4, %r5}, [test_select_cc_i8_i32_param_2];
+; CHECK-NEXT: ld.param.v4.b32 {%r6, %r7, %r8, %r9}, [test_select_cc_i8_i32_param_3];
+; CHECK-NEXT: setp.ne.b32 %p1, %r2, %r6;
+; CHECK-NEXT: setp.ne.b32 %p2, %r3, %r7;
+; CHECK-NEXT: setp.ne.b32 %p3, %r4, %r8;
+; CHECK-NEXT: setp.ne.b32 %p4, %r5, %r9;
+; CHECK-NEXT: ld.param.b32 %r10, [test_select_cc_i8_i32_param_1];
+; CHECK-NEXT: prmt.b32 %r11, %r10, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r12, %r1, 0, 0x7773U;
+; CHECK-NEXT: selp.b32 %r13, %r12, %r11, %p4;
+; CHECK-NEXT: prmt.b32 %r14, %r10, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r15, %r1, 0, 0x7772U;
+; CHECK-NEXT: selp.b32 %r16, %r15, %r14, %p3;
+; CHECK-NEXT: prmt.b32 %r17, %r16, %r13, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r18, %r10, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r19, %r1, 0, 0x7771U;
+; CHECK-NEXT: selp.b32 %r20, %r19, %r18, %p2;
+; CHECK-NEXT: prmt.b32 %r21, %r10, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r22, %r1, 0, 0x7770U;
+; CHECK-NEXT: selp.b32 %r23, %r22, %r21, %p1;
+; CHECK-NEXT: prmt.b32 %r24, %r23, %r20, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r25, %r24, %r17, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r25;
+; CHECK-NEXT: ret;
<4 x i32> %c, <4 x i32> %d) #0 {
%cc = icmp ne <4 x i32> %c, %d
%r = select <4 x i1> %cc, <4 x i8> %a, <4 x i8> %b
@@ -1686,41 +1108,23 @@ define <4 x i8> @test_trunc_2xi32(<4 x i32> %a) #0 {
}
define <4 x i8> @test_trunc_2xi64(<4 x i64> %a) #0 {
-; O0-LABEL: test_trunc_2xi64(
-; O0: {
-; O0-NEXT: .reg .b32 %r<8>;
-; O0-NEXT: .reg .b64 %rd<5>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_trunc_2xi64_param_0+16];
-; O0-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_trunc_2xi64_param_0];
-; O0-NEXT: cvt.u32.u64 %r1, %rd4;
-; O0-NEXT: cvt.u32.u64 %r2, %rd3;
-; O0-NEXT: prmt.b32 %r3, %r2, %r1, 0x3340U;
-; O0-NEXT: cvt.u32.u64 %r4, %rd2;
-; O0-NEXT: cvt.u32.u64 %r5, %rd1;
-; O0-NEXT: prmt.b32 %r6, %r5, %r4, 0x3340U;
-; O0-NEXT: prmt.b32 %r7, %r6, %r3, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r7;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_trunc_2xi64(
-; O3: {
-; O3-NEXT: .reg .b32 %r<8>;
-; O3-NEXT: .reg .b64 %rd<5>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_trunc_2xi64_param_0];
-; O3-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_trunc_2xi64_param_0+16];
-; O3-NEXT: cvt.u32.u64 %r1, %rd4;
-; O3-NEXT: cvt.u32.u64 %r2, %rd3;
-; O3-NEXT: prmt.b32 %r3, %r2, %r1, 0x3340U;
-; O3-NEXT: cvt.u32.u64 %r4, %rd2;
-; O3-NEXT: cvt.u32.u64 %r5, %rd1;
-; O3-NEXT: prmt.b32 %r6, %r5, %r4, 0x3340U;
-; O3-NEXT: prmt.b32 %r7, %r6, %r3, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r7;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_trunc_2xi64(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<8>;
+; CHECK-NEXT: .reg .b64 %rd<5>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v2.b64 {%rd1, %rd2}, [test_trunc_2xi64_param_0];
+; CHECK-NEXT: ld.param.v2.b64 {%rd3, %rd4}, [test_trunc_2xi64_param_0+16];
+; CHECK-NEXT: cvt.u32.u64 %r1, %rd4;
+; CHECK-NEXT: cvt.u32.u64 %r2, %rd3;
+; CHECK-NEXT: prmt.b32 %r3, %r2, %r1, 0x3340U;
+; CHECK-NEXT: cvt.u32.u64 %r4, %rd2;
+; CHECK-NEXT: cvt.u32.u64 %r5, %rd1;
+; CHECK-NEXT: prmt.b32 %r6, %r5, %r4, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r7, %r6, %r3, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r7;
+; CHECK-NEXT: ret;
%r = trunc <4 x i64> %a to <4 x i8>
ret <4 x i8> %r
}
@@ -1840,12 +1244,10 @@ define float @test_bitcast_4xi8_to_float(<4 x i8> %a) #0 {
define <2 x half> @test_bitcast_4xi8_to_2xhalf(i8 %a) #0 {
; O0-LABEL: test_bitcast_4xi8_to_2xhalf(
; O0: {
-; O0-NEXT: .reg .b16 %rs<2>;
; O0-NEXT: .reg .b32 %r<5>;
; O0-EMPTY:
; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b8 %rs1, [test_bitcast_4xi8_to_2xhalf_param_0];
-; O0-NEXT: cvt.u32.u16 %r1, %rs1;
+; O0-NEXT: ld.param.b8 %r1, [test_bitcast_4xi8_to_2xhalf_param_0];
; O0-NEXT: prmt.b32 %r2, %r1, 5, 0x3340U;
; O0-NEXT: prmt.b32 %r3, 6, 7, 0x3340U;
; O0-NEXT: prmt.b32 %r4, %r2, %r3, 0x5410U;
@@ -1897,252 +1299,134 @@ define <4 x i8> @test_shufflevector(<4 x i8> %a) #0 {
}
define <4 x i8> @test_shufflevector_2(<4 x i8> %a, <4 x i8> %b) #0 {
-; O0-LABEL: test_shufflevector_2(
-; O0: {
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b32 %r2, [test_shufflevector_2_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_shufflevector_2_param_0];
-; O0-NEXT: prmt.b32 %r3, %r1, %r2, 0x2537U;
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_shufflevector_2(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_shufflevector_2_param_0];
-; O3-NEXT: ld.param.b32 %r2, [test_shufflevector_2_param_1];
-; O3-NEXT: prmt.b32 %r3, %r1, %r2, 0x2537U;
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_shufflevector_2(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_shufflevector_2_param_0];
+; CHECK-NEXT: ld.param.b32 %r2, [test_shufflevector_2_param_1];
+; CHECK-NEXT: prmt.b32 %r3, %r1, %r2, 0x2537U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%s = shufflevector <4 x i8> %a, <4 x i8> %b, <4 x i32> <i32 7, i32 3, i32 5, i32 2>
ret <4 x i8> %s
}
define <4 x i8> @test_insertelement(<4 x i8> %a, i8 %x) #0 {
-; O0-LABEL: test_insertelement(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<2>;
-; O0-NEXT: .reg .b32 %r<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.b8 %rs1, [test_insertelement_param_1];
-; O0-NEXT: ld.param.b32 %r1, [test_insertelement_param_0];
-; O0-NEXT: cvt.u32.u16 %r2, %rs1;
-; O0-NEXT: bfi.b32 %r3, %r2, %r1, 8, 8;
-; O0-NEXT: st.param.b32 [func_retval0], %r3;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_insertelement(
-; O3: {
-; O3-NEXT: .reg .b32 %r<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.b32 %r1, [test_insertelement_param_0];
-; O3-NEXT: ld.param.b8 %r2, [test_insertelement_param_1];
-; O3-NEXT: bfi.b32 %r3, %r2, %r1, 8, 8;
-; O3-NEXT: st.param.b32 [func_retval0], %r3;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_insertelement(
+; CHECK: {
+; CHECK-NEXT: .reg .b32 %r<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.b32 %r1, [test_insertelement_param_0];
+; CHECK-NEXT: ld.param.b8 %r2, [test_insertelement_param_1];
+; CHECK-NEXT: bfi.b32 %r3, %r2, %r1, 8, 8;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r3;
+; CHECK-NEXT: ret;
%i = insertelement <4 x i8> %a, i8 %x, i64 1
ret <4 x i8> %i
}
define <4 x i8> @test_fptosi_4xhalf_to_4xi8(<4 x half> %a) #0 {
-; O0-LABEL: test_fptosi_4xhalf_to_4xi8(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<13>;
-; O0-NEXT: .reg .b32 %r<12>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fptosi_4xhalf_to_4xi8_param_0];
-; O0-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; O0-NEXT: cvt.rzi.s16.f16 %rs3, %rs2;
-; O0-NEXT: cvt.rzi.s16.f16 %rs4, %rs1;
-; O0-NEXT: mov.b32 %r3, {%rs4, %rs3};
-; O0-NEXT: mov.b32 {%rs5, %rs6}, %r3;
-; O0-NEXT: cvt.u32.u16 %r4, %rs6;
-; O0-NEXT: cvt.u32.u16 %r5, %rs5;
-; O0-NEXT: prmt.b32 %r6, %r5, %r4, 0x3340U;
-; O0-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; O0-NEXT: cvt.rzi.s16.f16 %rs9, %rs8;
-; O0-NEXT: cvt.rzi.s16.f16 %rs10, %rs7;
-; O0-NEXT: mov.b32 %r7, {%rs10, %rs9};
-; O0-NEXT: mov.b32 {%rs11, %rs12}, %r7;
-; O0-NEXT: cvt.u32.u16 %r8, %rs12;
-; O0-NEXT: cvt.u32.u16 %r9, %rs11;
-; O0-NEXT: prmt.b32 %r10, %r9, %r8, 0x3340U;
-; O0-NEXT: prmt.b32 %r11, %r10, %r6, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r11;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_fptosi_4xhalf_to_4xi8(
-; O3: {
-; O3-NEXT: .reg .b16 %rs<13>;
-; O3-NEXT: .reg .b32 %r<10>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [test_fptosi_4xhalf_to_4xi8_param_0];
-; O3-NEXT: cvt.rzi.s16.f16 %rs5, %rs4;
-; O3-NEXT: cvt.rzi.s16.f16 %rs6, %rs3;
-; O3-NEXT: mov.b32 %r1, {%rs6, %rs5};
-; O3-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; O3-NEXT: cvt.u32.u16 %r2, %rs8;
-; O3-NEXT: cvt.u32.u16 %r3, %rs7;
-; O3-NEXT: prmt.b32 %r4, %r3, %r2, 0x3340U;
-; O3-NEXT: cvt.rzi.s16.f16 %rs9, %rs2;
-; O3-NEXT: cvt.rzi.s16.f16 %rs10, %rs1;
-; O3-NEXT: mov.b32 %r5, {%rs10, %rs9};
-; O3-NEXT: mov.b32 {%rs11, %rs12}, %r5;
-; O3-NEXT: cvt.u32.u16 %r6, %rs12;
-; O3-NEXT: cvt.u32.u16 %r7, %rs11;
-; O3-NEXT: prmt.b32 %r8, %r7, %r6, 0x3340U;
-; O3-NEXT: prmt.b32 %r9, %r8, %r4, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r9;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_fptosi_4xhalf_to_4xi8(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<13>;
+; CHECK-NEXT: .reg .b32 %r<10>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [test_fptosi_4xhalf_to_4xi8_param_0];
+; CHECK-NEXT: cvt.rzi.s16.f16 %rs5, %rs4;
+; CHECK-NEXT: cvt.rzi.s16.f16 %rs6, %rs3;
+; CHECK-NEXT: mov.b32 %r1, {%rs6, %rs5};
+; CHECK-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-NEXT: cvt.u32.u16 %r2, %rs8;
+; CHECK-NEXT: cvt.u32.u16 %r3, %rs7;
+; CHECK-NEXT: prmt.b32 %r4, %r3, %r2, 0x3340U;
+; CHECK-NEXT: cvt.rzi.s16.f16 %rs9, %rs2;
+; CHECK-NEXT: cvt.rzi.s16.f16 %rs10, %rs1;
+; CHECK-NEXT: mov.b32 %r5, {%rs10, %rs9};
+; CHECK-NEXT: mov.b32 {%rs11, %rs12}, %r5;
+; CHECK-NEXT: cvt.u32.u16 %r6, %rs12;
+; CHECK-NEXT: cvt.u32.u16 %r7, %rs11;
+; CHECK-NEXT: prmt.b32 %r8, %r7, %r6, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r9, %r8, %r4, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: ret;
%r = fptosi <4 x half> %a to <4 x i8>
ret <4 x i8> %r
}
define <4 x i8> @test_fptoui_4xhalf_to_4xi8(<4 x half> %a) #0 {
-; O0-LABEL: test_fptoui_4xhalf_to_4xi8(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<13>;
-; O0-NEXT: .reg .b32 %r<12>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0:
-; O0-NEXT: ld.param.v2.b32 {%r1, %r2}, [test_fptoui_4xhalf_to_4xi8_param_0];
-; O0-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; O0-NEXT: cvt.rzi.u16.f16 %rs3, %rs2;
-; O0-NEXT: cvt.rzi.u16.f16 %rs4, %rs1;
-; O0-NEXT: mov.b32 %r3, {%rs4, %rs3};
-; O0-NEXT: mov.b32 {%rs5, %rs6}, %r3;
-; O0-NEXT: cvt.u32.u16 %r4, %rs6;
-; O0-NEXT: cvt.u32.u16 %r5, %rs5;
-; O0-NEXT: prmt.b32 %r6, %r5, %r4, 0x3340U;
-; O0-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; O0-NEXT: cvt.rzi.u16.f16 %rs9, %rs8;
-; O0-NEXT: cvt.rzi.u16.f16 %rs10, %rs7;
-; O0-NEXT: mov.b32 %r7, {%rs10, %rs9};
-; O0-NEXT: mov.b32 {%rs11, %rs12}, %r7;
-; O0-NEXT: cvt.u32.u16 %r8, %rs12;
-; O0-NEXT: cvt.u32.u16 %r9, %rs11;
-; O0-NEXT: prmt.b32 %r10, %r9, %r8, 0x3340U;
-; O0-NEXT: prmt.b32 %r11, %r10, %r6, 0x5410U;
-; O0-NEXT: st.param.b32 [func_retval0], %r11;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_fptoui_4xhalf_to_4xi8(
-; O3: {
-; O3-NEXT: .reg .b16 %rs<13>;
-; O3-NEXT: .reg .b32 %r<10>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0:
-; O3-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [test_fptoui_4xhalf_to_4xi8_param_0];
-; O3-NEXT: cvt.rzi.u16.f16 %rs5, %rs4;
-; O3-NEXT: cvt.rzi.u16.f16 %rs6, %rs3;
-; O3-NEXT: mov.b32 %r1, {%rs6, %rs5};
-; O3-NEXT: mov.b32 {%rs7, %rs8}, %r1;
-; O3-NEXT: cvt.u32.u16 %r2, %rs8;
-; O3-NEXT: cvt.u32.u16 %r3, %rs7;
-; O3-NEXT: prmt.b32 %r4, %r3, %r2, 0x3340U;
-; O3-NEXT: cvt.rzi.u16.f16 %rs9, %rs2;
-; O3-NEXT: cvt.rzi.u16.f16 %rs10, %rs1;
-; O3-NEXT: mov.b32 %r5, {%rs10, %rs9};
-; O3-NEXT: mov.b32 {%rs11, %rs12}, %r5;
-; O3-NEXT: cvt.u32.u16 %r6, %rs12;
-; O3-NEXT: cvt.u32.u16 %r7, %rs11;
-; O3-NEXT: prmt.b32 %r8, %r7, %r6, 0x3340U;
-; O3-NEXT: prmt.b32 %r9, %r8, %r4, 0x5410U;
-; O3-NEXT: st.param.b32 [func_retval0], %r9;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_fptoui_4xhalf_to_4xi8(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<13>;
+; CHECK-NEXT: .reg .b32 %r<10>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [test_fptoui_4xhalf_to_4xi8_param_0];
+; CHECK-NEXT: cvt.rzi.u16.f16 %rs5, %rs4;
+; CHECK-NEXT: cvt.rzi.u16.f16 %rs6, %rs3;
+; CHECK-NEXT: mov.b32 %r1, {%rs6, %rs5};
+; CHECK-NEXT: mov.b32 {%rs7, %rs8}, %r1;
+; CHECK-NEXT: cvt.u32.u16 %r2, %rs8;
+; CHECK-NEXT: cvt.u32.u16 %r3, %rs7;
+; CHECK-NEXT: prmt.b32 %r4, %r3, %r2, 0x3340U;
+; CHECK-NEXT: cvt.rzi.u16.f16 %rs9, %rs2;
+; CHECK-NEXT: cvt.rzi.u16.f16 %rs10, %rs1;
+; CHECK-NEXT: mov.b32 %r5, {%rs10, %rs9};
+; CHECK-NEXT: mov.b32 {%rs11, %rs12}, %r5;
+; CHECK-NEXT: cvt.u32.u16 %r6, %rs12;
+; CHECK-NEXT: cvt.u32.u16 %r7, %rs11;
+; CHECK-NEXT: prmt.b32 %r8, %r7, %r6, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r9, %r8, %r4, 0x5410U;
+; CHECK-NEXT: st.param.b32 [func_retval0], %r9;
+; CHECK-NEXT: ret;
%r = fptoui <4 x half> %a to <4 x i8>
ret <4 x i8> %r
}
define void @test_srem_v4i8(ptr %a, ptr %b, ptr %c) {
-; O0-LABEL: test_srem_v4i8(
-; O0: {
-; O0-NEXT: .reg .b16 %rs<13>;
-; O0-NEXT: .reg .b32 %r<16>;
-; O0-NEXT: .reg .b64 %rd<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0: // %entry
-; O0-NEXT: ld.param.b64 %rd3, [test_srem_v4i8_param_2];
-; O0-NEXT: ld.param.b64 %rd2, [test_srem_v4i8_param_1];
-; O0-NEXT: ld.param.b64 %rd1, [test_srem_v4i8_param_0];
-; O0-NEXT: ld.b32 %r1, [%rd1];
-; O0-NEXT: ld.b32 %r2, [%rd2];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0xbbb3U;
-; O0-NEXT: cvt.u16.u32 %rs1, %r3;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0xbbb3U;
-; O0-NEXT: cvt.u16.u32 %rs2, %r4;
-; O0-NEXT: rem.s16 %rs3, %rs2, %rs1;
-; O0-NEXT: cvt.u32.u16 %r5, %rs3;
-; O0-NEXT: prmt.b32 %r6, %r2, 0, 0xaaa2U;
-; O0-NEXT: cvt.u16.u32 %rs4, %r6;
-; O0-NEXT: prmt.b32 %r7, %r1, 0, 0xaaa2U;
-; O0-NEXT: cvt.u16.u32 %rs5, %r7;
-; O0-NEXT: rem.s16 %rs6, %rs5, %rs4;
-; O0-NEXT: cvt.u32.u16 %r8, %rs6;
-; O0-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O0-NEXT: cvt.s8.s32 %rs7, %r2;
-; O0-NEXT: cvt.s8.s32 %rs8, %r1;
-; O0-NEXT: rem.s16 %rs9, %rs8, %rs7;
-; O0-NEXT: cvt.u32.u16 %r10, %rs9;
-; O0-NEXT: prmt.b32 %r11, %r2, 0, 0x9991U;
-; O0-NEXT: cvt.u16.u32 %rs10, %r11;
-; O0-NEXT: prmt.b32 %r12, %r1, 0, 0x9991U;
-; O0-NEXT: cvt.u16.u32 %rs11, %r12;
-; O0-NEXT: rem.s16 %rs12, %rs11, %rs10;
-; O0-NEXT: cvt.u32.u16 %r13, %rs12;
-; O0-NEXT: prmt.b32 %r14, %r10, %r13, 0x3340U;
-; O0-NEXT: prmt.b32 %r15, %r14, %r9, 0x5410U;
-; O0-NEXT: st.b32 [%rd3], %r15;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_srem_v4i8(
-; O3: {
-; O3-NEXT: .reg .b16 %rs<13>;
-; O3-NEXT: .reg .b32 %r<16>;
-; O3-NEXT: .reg .b64 %rd<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0: // %entry
-; O3-NEXT: ld.param.b64 %rd1, [test_srem_v4i8_param_0];
-; O3-NEXT: ld.b32 %r1, [%rd1];
-; O3-NEXT: ld.param.b64 %rd2, [test_srem_v4i8_param_1];
-; O3-NEXT: ld.b32 %r2, [%rd2];
-; O3-NEXT: ld.param.b64 %rd3, [test_srem_v4i8_param_2];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0xbbb3U;
-; O3-NEXT: cvt.u16.u32 %rs1, %r3;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0xbbb3U;
-; O3-NEXT: cvt.u16.u32 %rs2, %r4;
-; O3-NEXT: rem.s16 %rs3, %rs2, %rs1;
-; O3-NEXT: cvt.u32.u16 %r5, %rs3;
-; O3-NEXT: prmt.b32 %r6, %r2, 0, 0xaaa2U;
-; O3-NEXT: cvt.u16.u32 %rs4, %r6;
-; O3-NEXT: prmt.b32 %r7, %r1, 0, 0xaaa2U;
-; O3-NEXT: cvt.u16.u32 %rs5, %r7;
-; O3-NEXT: rem.s16 %rs6, %rs5, %rs4;
-; O3-NEXT: cvt.u32.u16 %r8, %rs6;
-; O3-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
-; O3-NEXT: cvt.s8.s32 %rs7, %r2;
-; O3-NEXT: cvt.s8.s32 %rs8, %r1;
-; O3-NEXT: rem.s16 %rs9, %rs8, %rs7;
-; O3-NEXT: cvt.u32.u16 %r10, %rs9;
-; O3-NEXT: prmt.b32 %r11, %r2, 0, 0x9991U;
-; O3-NEXT: cvt.u16.u32 %rs10, %r11;
-; O3-NEXT: prmt.b32 %r12, %r1, 0, 0x9991U;
-; O3-NEXT: cvt.u16.u32 %rs11, %r12;
-; O3-NEXT: rem.s16 %rs12, %rs11, %rs10;
-; O3-NEXT: cvt.u32.u16 %r13, %rs12;
-; O3-NEXT: prmt.b32 %r14, %r10, %r13, 0x3340U;
-; O3-NEXT: prmt.b32 %r15, %r14, %r9, 0x5410U;
-; O3-NEXT: st.b32 [%rd3], %r15;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_srem_v4i8(
+; CHECK: {
+; CHECK-NEXT: .reg .b16 %rs<13>;
+; CHECK-NEXT: .reg .b32 %r<16>;
+; CHECK-NEXT: .reg .b64 %rd<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_srem_v4i8_param_0];
+; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_srem_v4i8_param_1];
+; CHECK-NEXT: ld.b32 %r2, [%rd2];
+; CHECK-NEXT: ld.param.b64 %rd3, [test_srem_v4i8_param_2];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0xbbb3U;
+; CHECK-NEXT: cvt.u16.u32 %rs1, %r3;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0xbbb3U;
+; CHECK-NEXT: cvt.u16.u32 %rs2, %r4;
+; CHECK-NEXT: rem.s16 %rs3, %rs2, %rs1;
+; CHECK-NEXT: cvt.u32.u16 %r5, %rs3;
+; CHECK-NEXT: prmt.b32 %r6, %r2, 0, 0xaaa2U;
+; CHECK-NEXT: cvt.u16.u32 %rs4, %r6;
+; CHECK-NEXT: prmt.b32 %r7, %r1, 0, 0xaaa2U;
+; CHECK-NEXT: cvt.u16.u32 %rs5, %r7;
+; CHECK-NEXT: rem.s16 %rs6, %rs5, %rs4;
+; CHECK-NEXT: cvt.u32.u16 %r8, %rs6;
+; CHECK-NEXT: prmt.b32 %r9, %r8, %r5, 0x3340U;
+; CHECK-NEXT: cvt.s8.s32 %rs7, %r2;
+; CHECK-NEXT: cvt.s8.s32 %rs8, %r1;
+; CHECK-NEXT: rem.s16 %rs9, %rs8, %rs7;
+; CHECK-NEXT: cvt.u32.u16 %r10, %rs9;
+; CHECK-NEXT: prmt.b32 %r11, %r2, 0, 0x9991U;
+; CHECK-NEXT: cvt.u16.u32 %rs10, %r11;
+; CHECK-NEXT: prmt.b32 %r12, %r1, 0, 0x9991U;
+; CHECK-NEXT: cvt.u16.u32 %rs11, %r12;
+; CHECK-NEXT: rem.s16 %rs12, %rs11, %rs10;
+; CHECK-NEXT: cvt.u32.u16 %r13, %rs12;
+; CHECK-NEXT: prmt.b32 %r14, %r10, %r13, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r15, %r14, %r9, 0x5410U;
+; CHECK-NEXT: st.b32 [%rd3], %r15;
+; CHECK-NEXT: ret;
entry:
%t57 = load <4 x i8>, ptr %a, align 4
%t59 = load <4 x i8>, ptr %b, align 4
@@ -2165,8 +1449,6 @@ define void @test_srem_v3i8(ptr %a, ptr %b, ptr %c) {
; O0-NEXT: .reg .b64 %rd<4>;
; O0-EMPTY:
; O0-NEXT: // %bb.0: // %entry
-; O0-NEXT: ld.param.b64 %rd3, [test_srem_v3i8_param_2];
-; O0-NEXT: ld.param.b64 %rd2, [test_srem_v3i8_param_1];
; O0-NEXT: ld.param.b64 %rd1, [test_srem_v3i8_param_0];
; O0-NEXT: ld.b8 %rs1, [%rd1];
; O0-NEXT: ld.b8 %rs2, [%rd1+1];
@@ -2174,12 +1456,14 @@ define void @test_srem_v3i8(ptr %a, ptr %b, ptr %c) {
; O0-NEXT: or.b16 %rs4, %rs3, %rs1;
; O0-NEXT: cvt.u32.u16 %r1, %rs4;
; O0-NEXT: ld.s8 %rs5, [%rd1+2];
+; O0-NEXT: ld.param.b64 %rd2, [test_srem_v3i8_param_1];
; O0-NEXT: ld.b8 %rs6, [%rd2];
; O0-NEXT: ld.b8 %rs7, [%rd2+1];
; O0-NEXT: shl.b16 %rs8, %rs7, 8;
; O0-NEXT: or.b16 %rs9, %rs8, %rs6;
; O0-NEXT: cvt.u32.u16 %r2, %rs9;
; O0-NEXT: ld.s8 %rs10, [%rd2+2];
+; O0-NEXT: ld.param.b64 %rd3, [test_srem_v3i8_param_2];
; O0-NEXT: cvt.s16.s8 %rs11, %rs9;
; O0-NEXT: cvt.s16.s8 %rs12, %rs4;
; O0-NEXT: rem.s16 %rs13, %rs12, %rs11;
@@ -2248,73 +1532,39 @@ entry:
}
define void @test_sext_v4i1_to_v4i8(ptr %a, ptr %b, ptr %c) {
-; O0-LABEL: test_sext_v4i1_to_v4i8(
-; O0: {
-; O0-NEXT: .reg .pred %p<5>;
-; O0-NEXT: .reg .b32 %r<18>;
-; O0-NEXT: .reg .b64 %rd<4>;
-; O0-EMPTY:
-; O0-NEXT: // %bb.0: // %entry
-; O0-NEXT: ld.param.b64 %rd3, [test_sext_v4i1_to_v4i8_param_2];
-; O0-NEXT: ld.param.b64 %rd2, [test_sext_v4i1_to_v4i8_param_1];
-; O0-NEXT: ld.param.b64 %rd1, [test_sext_v4i1_to_v4i8_param_0];
-; O0-NEXT: ld.b32 %r1, [%rd1];
-; O0-NEXT: ld.b32 %r2, [%rd2];
-; O0-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O0-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O0-NEXT: setp.gt.u32 %p1, %r4, %r3;
-; O0-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O0-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O0-NEXT: setp.gt.u32 %p2, %r6, %r5;
-; O0-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O0-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O0-NEXT: setp.gt.u32 %p3, %r8, %r7;
-; O0-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O0-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O0-NEXT: setp.gt.u32 %p4, %r10, %r9;
-; O0-NEXT: selp.b32 %r11, -1, 0, %p4;
-; O0-NEXT: selp.b32 %r12, -1, 0, %p3;
-; O0-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O0-NEXT: selp.b32 %r14, -1, 0, %p2;
-; O0-NEXT: selp.b32 %r15, -1, 0, %p1;
-; O0-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O0-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
-; O0-NEXT: st.b32 [%rd3], %r17;
-; O0-NEXT: ret;
-;
-; O3-LABEL: test_sext_v4i1_to_v4i8(
-; O3: {
-; O3-NEXT: .reg .pred %p<5>;
-; O3-NEXT: .reg .b32 %r<18>;
-; O3-NEXT: .reg .b64 %rd<4>;
-; O3-EMPTY:
-; O3-NEXT: // %bb.0: // %entry
-; O3-NEXT: ld.param.b64 %rd1, [test_sext_v4i1_to_v4i8_param_0];
-; O3-NEXT: ld.b32 %r1, [%rd1];
-; O3-NEXT: ld.param.b64 %rd2, [test_sext_v4i1_to_v4i8_param_1];
-; O3-NEXT: ld.b32 %r2, [%rd2];
-; O3-NEXT: ld.param.b64 %rd3, [test_sext_v4i1_to_v4i8_param_2];
-; O3-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
-; O3-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
-; O3-NEXT: setp.gt.u32 %p1, %r4, %r3;
-; O3-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
-; O3-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
-; O3-NEXT: setp.gt.u32 %p2, %r6, %r5;
-; O3-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
-; O3-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
-; O3-NEXT: setp.gt.u32 %p3, %r8, %r7;
-; O3-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
-; O3-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
-; O3-NEXT: setp.gt.u32 %p4, %r10, %r9;
-; O3-NEXT: selp.b32 %r11, -1, 0, %p4;
-; O3-NEXT: selp.b32 %r12, -1, 0, %p3;
-; O3-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
-; O3-NEXT: selp.b32 %r14, -1, 0, %p2;
-; O3-NEXT: selp.b32 %r15, -1, 0, %p1;
-; O3-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
-; O3-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
-; O3-NEXT: st.b32 [%rd3], %r17;
-; O3-NEXT: ret;
+; CHECK-LABEL: test_sext_v4i1_to_v4i8(
+; CHECK: {
+; CHECK-NEXT: .reg .pred %p<5>;
+; CHECK-NEXT: .reg .b32 %r<18>;
+; CHECK-NEXT: .reg .b64 %rd<4>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0: // %entry
+; CHECK-NEXT: ld.param.b64 %rd1, [test_sext_v4i1_to_v4i8_param_0];
+; CHECK-NEXT: ld.b32 %r1, [%rd1];
+; CHECK-NEXT: ld.param.b64 %rd2, [test_sext_v4i1_to_v4i8_param_1];
+; CHECK-NEXT: ld.b32 %r2, [%rd2];
+; CHECK-NEXT: ld.param.b64 %rd3, [test_sext_v4i1_to_v4i8_param_2];
+; CHECK-NEXT: prmt.b32 %r3, %r2, 0, 0x7770U;
+; CHECK-NEXT: prmt.b32 %r4, %r1, 0, 0x7770U;
+; CHECK-NEXT: setp.gt.u32 %p1, %r4, %r3;
+; CHECK-NEXT: prmt.b32 %r5, %r2, 0, 0x7771U;
+; CHECK-NEXT: prmt.b32 %r6, %r1, 0, 0x7771U;
+; CHECK-NEXT: setp.gt.u32 %p2, %r6, %r5;
+; CHECK-NEXT: prmt.b32 %r7, %r2, 0, 0x7772U;
+; CHECK-NEXT: prmt.b32 %r8, %r1, 0, 0x7772U;
+; CHECK-NEXT: setp.gt.u32 %p3, %r8, %r7;
+; CHECK-NEXT: prmt.b32 %r9, %r2, 0, 0x7773U;
+; CHECK-NEXT: prmt.b32 %r10, %r1, 0, 0x7773U;
+; CHECK-NEXT: setp.gt.u32 %p4, %r10, %r9;
+; CHECK-NEXT: selp.b32 %r11, -1, 0, %p4;
+; CHECK-NEXT: selp.b32 %r12, -1, 0, %p3;
+; CHECK-NEXT: prmt.b32 %r13, %r12, %r11, 0x3340U;
+; CHECK-NEXT: selp.b32 %r14, -1, 0, %p2;
+; CHECK-NEXT: selp.b32 %r15, -1, 0, %p1;
+; CHECK-NEXT: prmt.b32 %r16, %r15, %r14, 0x3340U;
+; CHECK-NEXT: prmt.b32 %r17, %r16, %r13, 0x5410U;
+; CHECK-NEXT: st.b32 [%rd3], %r17;
+; CHECK-NEXT: ret;
entry:
%t1 = load <4 x i8>, ptr %a, align 4
%t2 = load <4 x i8>, ptr %b, align 4
diff --git a/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll b/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
index 34c0a7519eef93..564e1e291e2176 100644
--- a/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
+++ b/llvm/test/CodeGen/NVPTX/lower-aggr-copies.ll
@@ -124,8 +124,7 @@ entry:
; IR-NEXT: store i8 [[VAL]], ptr [[STOREPTR]]
; PTX-LABEL: .visible .func (.param .b64 func_retval0) memset_caller(
-; PTX: ld.param.b32 %r[[C:[0-9]+]]
-; PTX: cvt.u16.u32 %rs[[REG:[0-9]+]], %r[[C]];
+; PTX: ld.param.b8 %rs[[REG:[0-9]+]], [memset_caller_param_1];
; PTX: $L__BB[[LABEL:[_0-9]+]]:
; PTX: st.b8 [%rd{{[0-9]+}}], %rs[[REG]]
; PTX: add.s64 %rd[[COUNTER:[0-9]+]], %rd{{[0-9]+}}, 1
diff --git a/llvm/test/CodeGen/NVPTX/mulwide.ll b/llvm/test/CodeGen/NVPTX/mulwide.ll
index 05d0b193dafddb..b7dab016f249dc 100644
--- a/llvm/test/CodeGen/NVPTX/mulwide.ll
+++ b/llvm/test/CodeGen/NVPTX/mulwide.ll
@@ -19,14 +19,11 @@ define i32 @mulwide16(i16 %a, i16 %b) {
;
; NOOPT-LABEL: mulwide16(
; NOOPT: {
-; NOOPT-NEXT: .reg .b16 %rs<3>;
; NOOPT-NEXT: .reg .b32 %r<4>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b16 %rs2, [mulwide16_param_1];
-; NOOPT-NEXT: ld.param.b16 %rs1, [mulwide16_param_0];
-; NOOPT-NEXT: cvt.s32.s16 %r1, %rs1;
-; NOOPT-NEXT: cvt.s32.s16 %r2, %rs2;
+; NOOPT-NEXT: ld.param.s16 %r1, [mulwide16_param_0];
+; NOOPT-NEXT: ld.param.s16 %r2, [mulwide16_param_1];
; NOOPT-NEXT: mul.lo.s32 %r3, %r1, %r2;
; NOOPT-NEXT: st.param.b32 [func_retval0], %r3;
; NOOPT-NEXT: ret;
@@ -51,14 +48,11 @@ define i32 @mulwideu16(i16 %a, i16 %b) {
;
; NOOPT-LABEL: mulwideu16(
; NOOPT: {
-; NOOPT-NEXT: .reg .b16 %rs<3>;
; NOOPT-NEXT: .reg .b32 %r<4>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b16 %rs2, [mulwideu16_param_1];
-; NOOPT-NEXT: ld.param.b16 %rs1, [mulwideu16_param_0];
-; NOOPT-NEXT: cvt.u32.u16 %r1, %rs1;
-; NOOPT-NEXT: cvt.u32.u16 %r2, %rs2;
+; NOOPT-NEXT: ld.param.b16 %r1, [mulwideu16_param_0];
+; NOOPT-NEXT: ld.param.b16 %r2, [mulwideu16_param_1];
; NOOPT-NEXT: mul.lo.s32 %r3, %r1, %r2;
; NOOPT-NEXT: st.param.b32 [func_retval0], %r3;
; NOOPT-NEXT: ret;
@@ -83,18 +77,13 @@ define i32 @mulwide8(i8 %a, i8 %b) {
;
; NOOPT-LABEL: mulwide8(
; NOOPT: {
-; NOOPT-NEXT: .reg .b16 %rs<3>;
-; NOOPT-NEXT: .reg .b32 %r<6>;
+; NOOPT-NEXT: .reg .b32 %r<4>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b8 %rs2, [mulwide8_param_1];
-; NOOPT-NEXT: ld.param.b8 %rs1, [mulwide8_param_0];
-; NOOPT-NEXT: cvt.u32.u16 %r1, %rs1;
-; NOOPT-NEXT: cvt.s32.s8 %r2, %r1;
-; NOOPT-NEXT: cvt.u32.u16 %r3, %rs2;
-; NOOPT-NEXT: cvt.s32.s8 %r4, %r3;
-; NOOPT-NEXT: mul.lo.s32 %r5, %r2, %r4;
-; NOOPT-NEXT: st.param.b32 [func_retval0], %r5;
+; NOOPT-NEXT: ld.param.s8 %r1, [mulwide8_param_0];
+; NOOPT-NEXT: ld.param.s8 %r2, [mulwide8_param_1];
+; NOOPT-NEXT: mul.lo.s32 %r3, %r1, %r2;
+; NOOPT-NEXT: st.param.b32 [func_retval0], %r3;
; NOOPT-NEXT: ret;
%val0 = sext i8 %a to i32
%val1 = sext i8 %b to i32
@@ -117,14 +106,11 @@ define i32 @mulwideu8(i8 %a, i8 %b) {
;
; NOOPT-LABEL: mulwideu8(
; NOOPT: {
-; NOOPT-NEXT: .reg .b16 %rs<3>;
; NOOPT-NEXT: .reg .b32 %r<4>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b8 %rs2, [mulwideu8_param_1];
-; NOOPT-NEXT: ld.param.b8 %rs1, [mulwideu8_param_0];
-; NOOPT-NEXT: cvt.u32.u16 %r1, %rs1;
-; NOOPT-NEXT: cvt.u32.u16 %r2, %rs2;
+; NOOPT-NEXT: ld.param.b8 %r1, [mulwideu8_param_0];
+; NOOPT-NEXT: ld.param.b8 %r2, [mulwideu8_param_1];
; NOOPT-NEXT: mul.lo.s32 %r3, %r1, %r2;
; NOOPT-NEXT: st.param.b32 [func_retval0], %r3;
; NOOPT-NEXT: ret;
@@ -149,14 +135,11 @@ define i64 @mulwide32(i32 %a, i32 %b) {
;
; NOOPT-LABEL: mulwide32(
; NOOPT: {
-; NOOPT-NEXT: .reg .b32 %r<3>;
; NOOPT-NEXT: .reg .b64 %rd<4>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b32 %r2, [mulwide32_param_1];
-; NOOPT-NEXT: ld.param.b32 %r1, [mulwide32_param_0];
-; NOOPT-NEXT: cvt.s64.s32 %rd1, %r1;
-; NOOPT-NEXT: cvt.s64.s32 %rd2, %r2;
+; NOOPT-NEXT: ld.param.s32 %rd1, [mulwide32_param_0];
+; NOOPT-NEXT: ld.param.s32 %rd2, [mulwide32_param_1];
; NOOPT-NEXT: mul.lo.s64 %rd3, %rd1, %rd2;
; NOOPT-NEXT: st.param.b64 [func_retval0], %rd3;
; NOOPT-NEXT: ret;
@@ -181,14 +164,11 @@ define i64 @mulwideu32(i32 %a, i32 %b) {
;
; NOOPT-LABEL: mulwideu32(
; NOOPT: {
-; NOOPT-NEXT: .reg .b32 %r<3>;
; NOOPT-NEXT: .reg .b64 %rd<4>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b32 %r2, [mulwideu32_param_1];
-; NOOPT-NEXT: ld.param.b32 %r1, [mulwideu32_param_0];
-; NOOPT-NEXT: cvt.u64.u32 %rd1, %r1;
-; NOOPT-NEXT: cvt.u64.u32 %rd2, %r2;
+; NOOPT-NEXT: ld.param.b32 %rd1, [mulwideu32_param_0];
+; NOOPT-NEXT: ld.param.b32 %rd2, [mulwideu32_param_1];
; NOOPT-NEXT: mul.lo.s64 %rd3, %rd1, %rd2;
; NOOPT-NEXT: st.param.b64 [func_retval0], %rd3;
; NOOPT-NEXT: ret;
@@ -215,21 +195,12 @@ define i64 @mulwideu7(i7 %a, i7 %b) {
;
; NOOPT-LABEL: mulwideu7(
; NOOPT: {
-; NOOPT-NEXT: .reg .b16 %rs<9>;
; NOOPT-NEXT: .reg .b64 %rd<6>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b8 %rs3, [mulwideu7_param_0+1];
-; NOOPT-NEXT: shl.b16 %rs4, %rs3, 8;
-; NOOPT-NEXT: ld.param.b8 %rs5, [mulwideu7_param_0];
-; NOOPT-NEXT: or.b16 %rs1, %rs4, %rs5;
-; NOOPT-NEXT: ld.param.b8 %rs6, [mulwideu7_param_1+1];
-; NOOPT-NEXT: shl.b16 %rs7, %rs6, 8;
-; NOOPT-NEXT: ld.param.b8 %rs8, [mulwideu7_param_1];
-; NOOPT-NEXT: or.b16 %rs2, %rs7, %rs8;
-; NOOPT-NEXT: cvt.u64.u16 %rd1, %rs5;
+; NOOPT-NEXT: ld.param.b8 %rd1, [mulwideu7_param_0];
; NOOPT-NEXT: and.b64 %rd2, %rd1, 127;
-; NOOPT-NEXT: cvt.u64.u16 %rd3, %rs8;
+; NOOPT-NEXT: ld.param.b8 %rd3, [mulwideu7_param_1];
; NOOPT-NEXT: and.b64 %rd4, %rd3, 127;
; NOOPT-NEXT: mul.lo.s64 %rd5, %rd2, %rd4;
; NOOPT-NEXT: st.param.b64 [func_retval0], %rd5;
@@ -257,20 +228,11 @@ define i64 @mulwides7(i7 %a, i7 %b) {
;
; NOOPT-LABEL: mulwides7(
; NOOPT: {
-; NOOPT-NEXT: .reg .b16 %rs<9>;
; NOOPT-NEXT: .reg .b64 %rd<8>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b8 %rs3, [mulwides7_param_0+1];
-; NOOPT-NEXT: shl.b16 %rs4, %rs3, 8;
-; NOOPT-NEXT: ld.param.b8 %rs5, [mulwides7_param_0];
-; NOOPT-NEXT: or.b16 %rs1, %rs4, %rs5;
-; NOOPT-NEXT: ld.param.b8 %rs6, [mulwides7_param_1];
-; NOOPT-NEXT: cvt.u64.u16 %rd1, %rs6;
-; NOOPT-NEXT: cvt.u64.u16 %rd2, %rs5;
-; NOOPT-NEXT: ld.param.b8 %rs7, [mulwides7_param_1+1];
-; NOOPT-NEXT: shl.b16 %rs8, %rs7, 8;
-; NOOPT-NEXT: or.b16 %rs2, %rs8, %rs6;
+; NOOPT-NEXT: ld.param.b8 %rd1, [mulwides7_param_1];
+; NOOPT-NEXT: ld.param.b8 %rd2, [mulwides7_param_0];
; NOOPT-NEXT: shl.b64 %rd3, %rd2, 57;
; NOOPT-NEXT: shr.s64 %rd4, %rd3, 57;
; NOOPT-NEXT: shl.b64 %rd5, %rd1, 57;
@@ -298,12 +260,10 @@ define i64 @shl30(i32 %a) {
;
; NOOPT-LABEL: shl30(
; NOOPT: {
-; NOOPT-NEXT: .reg .b32 %r<2>;
; NOOPT-NEXT: .reg .b64 %rd<3>;
; NOOPT-EMPTY:
; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b32 %r1, [shl30_param_0];
-; NOOPT-NEXT: cvt.s64.s32 %rd1, %r1;
+; NOOPT-NEXT: ld.param.s32 %rd1, [shl30_param_0];
; NOOPT-NEXT: shl.b64 %rd2, %rd1, 30;
; NOOPT-NEXT: st.param.b64 [func_retval0], %rd2;
; NOOPT-NEXT: ret;
@@ -313,27 +273,15 @@ define i64 @shl30(i32 %a) {
}
define i64 @shl31(i32 %a) {
-; OPT-LABEL: shl31(
-; OPT: {
-; OPT-NEXT: .reg .b64 %rd<3>;
-; OPT-EMPTY:
-; OPT-NEXT: // %bb.0:
-; OPT-NEXT: ld.param.s32 %rd1, [shl31_param_0];
-; OPT-NEXT: shl.b64 %rd2, %rd1, 31;
-; OPT-NEXT: st.param.b64 [func_retval0], %rd2;
-; OPT-NEXT: ret;
-;
-; NOOPT-LABEL: shl31(
-; NOOPT: {
-; NOOPT-NEXT: .reg .b32 %r<2>;
-; NOOPT-NEXT: .reg .b64 %rd<3>;
-; NOOPT-EMPTY:
-; NOOPT-NEXT: // %bb.0:
-; NOOPT-NEXT: ld.param.b32 %r1, [shl31_param_0];
-; NOOPT-NEXT: cvt.s64.s32 %rd1, %r1;
-; NOOPT-NEXT: shl.b64 %rd2, %rd1, 31;
-; NOOPT-NEXT: st.param.b64 [func_retval0], %rd2;
-; NOOPT-NEXT: ret;
+; CHECK-LABEL: shl31(
+; CHECK: {
+; CHECK-NEXT: .reg .b64 %rd<3>;
+; CHECK-EMPTY:
+; CHECK-NEXT: // %bb.0:
+; CHECK-NEXT: ld.param.s32 %rd1, [shl31_param_0];
+; CHECK-NEXT: shl.b64 %rd2, %rd1, 31;
+; CHECK-NEXT: st.param.b64 [func_retval0], %rd2;
+; CHECK-NEXT: ret;
%conv = sext i32 %a to i64
%shl = shl i64 %conv, 31
ret i64 %shl
diff --git a/llvm/test/CodeGen/NVPTX/param-load-store.ll b/llvm/test/CodeGen/NVPTX/param-load-store.ll
index 90c8b921009b67..5090a72dd2cd82 100644
--- a/llvm/test/CodeGen/NVPTX/param-load-store.ll
+++ b/llvm/test/CodeGen/NVPTX/param-load-store.ll
@@ -24,13 +24,10 @@
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i1(
; CHECK-NEXT: .param .b32 test_i1_param_0
-; CHECK: ld.param.b8 [[A8:%rs[0-9]+]], [test_i1_param_0];
-; CHECK: and.b16 [[A:%rs[0-9]+]], [[A8]], 1;
-; CHECK: setp.ne.b16 %p1, [[A]], 0
; CHECK-DAG: .param .b32 param0;
; CHECK-DAG: .param .b32 retval0;
-; CHECK: cvt.u32.u16 [[B:%r[0-9]+]], [[A8]]
-; CHECK-DAG: st.param.b32 [param0], [[B]]
+; CHECK: ld.param.b8 [[A:%r[0-9]+]], [test_i1_param_0];
+; CHECK: st.param.b32 [param0], [[A]]
; CHECK: call.uni (retval0), test_i1,
; CHECK: ld.param.b32 [[R8:%r[0-9]+]], [retval0];
; CHECK: st.param.b32 [func_retval0], [[R8]];
@@ -45,8 +42,7 @@ define i1 @test_i1(i1 %a) {
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i1s(
; CHECK-NEXT: .param .b32 test_i1s_param_0
-; CHECK: ld.param.b8 [[A8:%rs[0-9]+]], [test_i1s_param_0];
-; CHECK: cvt.u32.u16 [[A32:%r[0-9]+]], [[A8]];
+; CHECK: ld.param.b8 [[A32:%r[0-9]+]], [test_i1s_param_0];
; CHECK: .param .b32 param0;
; CHECK: .param .b32 retval0;
; CHECK: and.b32 [[A1:%r[0-9]+]], [[A32]], 1;
@@ -129,7 +125,7 @@ define <5 x i1> @test_v5i1(<5 x i1> %a) {
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i2(
; CHECK-NEXT: .param .b32 test_i2_param_0
-; CHECK: ld.param.b8 {{%rs[0-9]+}}, [test_i2_param_0];
+; CHECK: ld.param.b8 {{%r[0-9]+}}, [test_i2_param_0];
; CHECK: .param .b32 param0;
; CHECK: .param .b32 retval0;
; CHECK: st.param.b32 [param0], {{%r[0-9]+}};
@@ -145,7 +141,7 @@ define i2 @test_i2(i2 %a) {
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i3(
; CHECK-NEXT: .param .b32 test_i3_param_0
-; CHECK: ld.param.b8 {{%rs[0-9]+}}, [test_i3_param_0];
+; CHECK: ld.param.b8 {{%r[0-9]+}}, [test_i3_param_0];
; CHECK: .param .b32 param0;
; CHECK: .param .b32 retval0;
; CHECK: st.param.b32 [param0], {{%r[0-9]+}};
@@ -162,10 +158,9 @@ define i3 @test_i3(i3 %a) {
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i8(
; CHECK-NEXT: .param .b32 test_i8_param_0
-; CHECK: ld.param.b8 [[A8:%rs[0-9]+]], [test_i8_param_0];
; CHECK: .param .b32 param0;
; CHECK: .param .b32 retval0;
-; CHECK: cvt.u32.u16 [[A32:%r[0-9]+]], [[A8]];
+; CHECK: ld.param.b8 [[A32:%r[0-9]+]], [test_i8_param_0];
; CHECK: st.param.b32 [param0], [[A32]];
; CHECK: call.uni (retval0), test_i8,
; CHECK: ld.param.b32 [[R32:%r[0-9]+]], [retval0];
@@ -254,8 +249,8 @@ define <5 x i8> @test_v5i8(<5 x i8> %a) {
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i11(
; CHECK-NEXT: .param .b32 test_i11_param_0
-; CHECK: ld.param.b16 {{%rs[0-9]+}}, [test_i11_param_0];
; CHECK: .param .b32 retval0;
+; CHECK: ld.param.b16 {{%r[0-9]+}}, [test_i11_param_0];
; CHECK: st.param.b32 [param0], {{%r[0-9]+}};
; CHECK: call.uni (retval0), test_i11,
; CHECK: ld.param.b32 {{%r[0-9]+}}, [retval0];
@@ -269,10 +264,9 @@ define i11 @test_i11(i11 %a) {
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i16(
; CHECK-NEXT: .param .b32 test_i16_param_0
-; CHECK: ld.param.b16 [[E16:%rs[0-9]+]], [test_i16_param_0];
; CHECK: .param .b32 param0;
; CHECK: .param .b32 retval0;
-; CHECK: cvt.u32.u16 [[E32:%r[0-9]+]], [[E16]];
+; CHECK: ld.param.b16 [[E32:%r[0-9]+]], [test_i16_param_0];
; CHECK: st.param.b32 [param0], [[E32]];
; CHECK: call.uni (retval0), test_i16,
; CHECK: ld.param.b32 [[RE32:%r[0-9]+]], [retval0];
@@ -286,10 +280,9 @@ define i16 @test_i16(i16 %a) {
; CHECK: .func (.param .b32 func_retval0)
; CHECK-LABEL: test_i16s(
; CHECK-NEXT: .param .b32 test_i16s_param_0
-; CHECK: ld.param.b16 [[E16:%rs[0-9]+]], [test_i16s_param_0];
+; CHECK: ld.param.s16 [[E32:%r[0-9]+]], [test_i16s_param_0];
; CHECK: .param .b32 param0;
; CHECK: .param .b32 retval0;
-; CHECK: cvt.s32.s16 [[E32:%r[0-9]+]], [[E16]];
; CHECK: st.param.b32 [param0], [[E32]];
; CHECK: call.uni (retval0), test_i16s,
; CHECK: ld.param.b32 [[RE32:%r[0-9]+]], [retval0];
@@ -1003,11 +996,11 @@ define %s_i32x4 @test_s_i32x4(%s_i32x4 %a) {
; CHECK:.visible .func (.param .align 8 .b8 func_retval0[32])
; CHECK-LABEL: test_s_i1i32x4(
; CHECK: .param .align 8 .b8 test_s_i1i32x4_param_0[32]
-; CHECK: ld.param.b64 [[E5:%rd[0-9]+]], [test_s_i1i32x4_param_0+24];
-; CHECK: ld.param.b32 [[E4:%r[0-9]+]], [test_s_i1i32x4_param_0+16];
-; CHECK: ld.param.b32 [[E3:%r[0-9]+]], [test_s_i1i32x4_param_0+12];
-; CHECK: ld.param.b8 [[E2:%rs[0-9]+]], [test_s_i1i32x4_param_0+8];
-; CHECK: ld.param.v2.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]]}, [test_s_i1i32x4_param_0];
+; CHECK-DAG: ld.param.b64 [[E5:%rd[0-9]+]], [test_s_i1i32x4_param_0+24];
+; CHECK-DAG: ld.param.b32 [[E4:%r[0-9]+]], [test_s_i1i32x4_param_0+16];
+; CHECK-DAG: ld.param.b32 [[E3:%r[0-9]+]], [test_s_i1i32x4_param_0+12];
+; CHECK-DAG: ld.param.b8 [[E2:%rs[0-9]+]], [test_s_i1i32x4_param_0+8];
+; CHECK-DAG: ld.param.v2.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]]}, [test_s_i1i32x4_param_0];
; CHECK: .param .align 8 .b8 param0[32];
; CHECK: .param .align 8 .b8 retval0[32];
; CHECK-DAG: st.param.v2.b32 [param0], {[[E0]], [[E1]]};
@@ -1152,12 +1145,12 @@ define %s_i8i32x4p @test_s_i1i32x4p(%s_i8i32x4p %a) {
; CHECK:.visible .func (.param .align 16 .b8 func_retval0[80])
; CHECK-LABEL: test_s_crossfield(
; CHECK: .param .align 16 .b8 test_s_crossfield_param_0[80]
-; CHECK: ld.param.b32 [[E15:%r[0-9]+]], [test_s_crossfield_param_0+64];
-; CHECK: ld.param.v4.b32 {[[E11:%r[0-9]+]], [[E12:%r[0-9]+]], [[E13:%r[0-9]+]], [[E14:%r[0-9]+]]}, [test_s_crossfield_param_0+48];
-; CHECK: ld.param.v4.b32 {[[E7:%r[0-9]+]], [[E8:%r[0-9]+]], [[E9:%r[0-9]+]], [[E10:%r[0-9]+]]}, [test_s_crossfield_param_0+32];
-; CHECK: ld.param.v4.b32 {[[E3:%r[0-9]+]], [[E4:%r[0-9]+]], [[E5:%r[0-9]+]], [[E6:%r[0-9]+]]}, [test_s_crossfield_param_0+16];
-; CHECK: ld.param.b32 [[E2:%r[0-9]+]], [test_s_crossfield_param_0+8];
-; CHECK: ld.param.v2.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]]}, [test_s_crossfield_param_0];
+; CHECK-DAG: ld.param.b32 [[E15:%r[0-9]+]], [test_s_crossfield_param_0+64];
+; CHECK-DAG: ld.param.v4.b32 {[[E11:%r[0-9]+]], [[E12:%r[0-9]+]], [[E13:%r[0-9]+]], [[E14:%r[0-9]+]]}, [test_s_crossfield_param_0+48];
+; CHECK-DAG: ld.param.v4.b32 {[[E7:%r[0-9]+]], [[E8:%r[0-9]+]], [[E9:%r[0-9]+]], [[E10:%r[0-9]+]]}, [test_s_crossfield_param_0+32];
+; CHECK-DAG: ld.param.v4.b32 {[[E3:%r[0-9]+]], [[E4:%r[0-9]+]], [[E5:%r[0-9]+]], [[E6:%r[0-9]+]]}, [test_s_crossfield_param_0+16];
+; CHECK-DAG: ld.param.b32 [[E2:%r[0-9]+]], [test_s_crossfield_param_0+8];
+; CHECK-DAG: ld.param.v2.b32 {[[E0:%r[0-9]+]], [[E1:%r[0-9]+]]}, [test_s_crossfield_param_0];
; CHECK: .param .align 16 .b8 param0[80];
; CHECK: .param .align 16 .b8 retval0[80];
; CHECK-DAG: st.param.v2.b32 [param0], {[[E0]], [[E1]]};
diff --git a/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll b/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
index d6f3f8c9ef14db..824fe7704956a5 100644
--- a/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
+++ b/llvm/test/CodeGen/NVPTX/reduction-intrinsics.ll
@@ -108,17 +108,17 @@ define half @reduce_fadd_half_reassoc_nonpow2(<7 x half> %in) {
; CHECK-SM80-NEXT: .reg .b16 %rs<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fadd_half_reassoc_nonpow2_param_0+12];
-; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_fadd_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_fadd_half_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fadd_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs2, %rs3}, [reduce_fadd_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_fadd_half_reassoc_nonpow2_param_0];
; CHECK-SM80-NEXT: mov.b16 %rs8, 0x0000;
-; CHECK-SM80-NEXT: add.rn.f16 %rs9, %rs1, %rs8;
-; CHECK-SM80-NEXT: add.rn.f16 %rs10, %rs9, %rs2;
-; CHECK-SM80-NEXT: add.rn.f16 %rs11, %rs10, %rs3;
-; CHECK-SM80-NEXT: add.rn.f16 %rs12, %rs11, %rs4;
-; CHECK-SM80-NEXT: add.rn.f16 %rs13, %rs12, %rs5;
-; CHECK-SM80-NEXT: add.rn.f16 %rs14, %rs13, %rs6;
-; CHECK-SM80-NEXT: add.rn.f16 %rs15, %rs14, %rs7;
+; CHECK-SM80-NEXT: add.rn.f16 %rs9, %rs4, %rs8;
+; CHECK-SM80-NEXT: add.rn.f16 %rs10, %rs9, %rs5;
+; CHECK-SM80-NEXT: add.rn.f16 %rs11, %rs10, %rs6;
+; CHECK-SM80-NEXT: add.rn.f16 %rs12, %rs11, %rs7;
+; CHECK-SM80-NEXT: add.rn.f16 %rs13, %rs12, %rs2;
+; CHECK-SM80-NEXT: add.rn.f16 %rs14, %rs13, %rs3;
+; CHECK-SM80-NEXT: add.rn.f16 %rs15, %rs14, %rs1;
; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs15;
; CHECK-SM80-NEXT: ret;
;
@@ -127,17 +127,17 @@ define half @reduce_fadd_half_reassoc_nonpow2(<7 x half> %in) {
; CHECK-SM100-NEXT: .reg .b16 %rs<16>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fadd_half_reassoc_nonpow2_param_0+12];
-; CHECK-SM100-NEXT: ld.param::func.v2.b16 {%rs5, %rs6}, [reduce_fadd_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: ld.param::func.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_fadd_half_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fadd_half_reassoc_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.v2.b16 {%rs2, %rs3}, [reduce_fadd_half_reassoc_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_fadd_half_reassoc_nonpow2_param_0];
; CHECK-SM100-NEXT: mov.b16 %rs8, 0x0000;
-; CHECK-SM100-NEXT: add.rn.f16 %rs9, %rs1, %rs8;
-; CHECK-SM100-NEXT: add.rn.f16 %rs10, %rs9, %rs2;
-; CHECK-SM100-NEXT: add.rn.f16 %rs11, %rs10, %rs3;
-; CHECK-SM100-NEXT: add.rn.f16 %rs12, %rs11, %rs4;
-; CHECK-SM100-NEXT: add.rn.f16 %rs13, %rs12, %rs5;
-; CHECK-SM100-NEXT: add.rn.f16 %rs14, %rs13, %rs6;
-; CHECK-SM100-NEXT: add.rn.f16 %rs15, %rs14, %rs7;
+; CHECK-SM100-NEXT: add.rn.f16 %rs9, %rs4, %rs8;
+; CHECK-SM100-NEXT: add.rn.f16 %rs10, %rs9, %rs5;
+; CHECK-SM100-NEXT: add.rn.f16 %rs11, %rs10, %rs6;
+; CHECK-SM100-NEXT: add.rn.f16 %rs12, %rs11, %rs7;
+; CHECK-SM100-NEXT: add.rn.f16 %rs13, %rs12, %rs2;
+; CHECK-SM100-NEXT: add.rn.f16 %rs14, %rs13, %rs3;
+; CHECK-SM100-NEXT: add.rn.f16 %rs15, %rs14, %rs1;
; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs15;
; CHECK-SM100-NEXT: ret;
%res = call half @llvm.vector.reduce.fadd(half 0.0, <7 x half> %in)
@@ -150,39 +150,34 @@ define float @reduce_fadd_float(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<17>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fadd_float_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_float_param_0];
-; CHECK-SM80-NEXT: add.rn.f32 %r9, %r1, 0f00000000;
-; CHECK-SM80-NEXT: add.rn.f32 %r10, %r9, %r2;
-; CHECK-SM80-NEXT: add.rn.f32 %r11, %r10, %r3;
-; CHECK-SM80-NEXT: add.rn.f32 %r12, %r11, %r4;
-; CHECK-SM80-NEXT: add.rn.f32 %r13, %r12, %r5;
-; CHECK-SM80-NEXT: add.rn.f32 %r14, %r13, %r6;
-; CHECK-SM80-NEXT: add.rn.f32 %r15, %r14, %r7;
-; CHECK-SM80-NEXT: add.rn.f32 %r16, %r15, %r8;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_float_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fadd_float_param_0];
+; CHECK-SM80-NEXT: add.rn.f32 %r9, %r5, 0f00000000;
+; CHECK-SM80-NEXT: add.rn.f32 %r10, %r9, %r6;
+; CHECK-SM80-NEXT: add.rn.f32 %r11, %r10, %r7;
+; CHECK-SM80-NEXT: add.rn.f32 %r12, %r11, %r8;
+; CHECK-SM80-NEXT: add.rn.f32 %r13, %r12, %r1;
+; CHECK-SM80-NEXT: add.rn.f32 %r14, %r13, %r2;
+; CHECK-SM80-NEXT: add.rn.f32 %r15, %r14, %r3;
+; CHECK-SM80-NEXT: add.rn.f32 %r16, %r15, %r4;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r16;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fadd_float(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<17>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fadd_float_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fadd_float_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd2;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd1;
-; CHECK-SM100-NEXT: add.rn.f32 %r9, %r7, 0f00000000;
-; CHECK-SM100-NEXT: add.rn.f32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: add.rn.f32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: add.rn.f32 %r12, %r11, %r6;
-; CHECK-SM100-NEXT: add.rn.f32 %r13, %r12, %r3;
-; CHECK-SM100-NEXT: add.rn.f32 %r14, %r13, %r4;
-; CHECK-SM100-NEXT: add.rn.f32 %r15, %r14, %r1;
-; CHECK-SM100-NEXT: add.rn.f32 %r16, %r15, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fadd_float_param_0];
+; CHECK-SM100-NEXT: add.rn.f32 %r9, %r5, 0f00000000;
+; CHECK-SM100-NEXT: add.rn.f32 %r10, %r9, %r6;
+; CHECK-SM100-NEXT: add.rn.f32 %r11, %r10, %r7;
+; CHECK-SM100-NEXT: add.rn.f32 %r12, %r11, %r8;
+; CHECK-SM100-NEXT: add.rn.f32 %r13, %r12, %r1;
+; CHECK-SM100-NEXT: add.rn.f32 %r14, %r13, %r2;
+; CHECK-SM100-NEXT: add.rn.f32 %r15, %r14, %r3;
+; CHECK-SM100-NEXT: add.rn.f32 %r16, %r15, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r16;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fadd(float 0.0, <8 x float> %in)
@@ -195,13 +190,13 @@ define float @reduce_fadd_float_reassoc(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<17>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fadd_float_reassoc_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_float_reassoc_param_0];
-; CHECK-SM80-NEXT: add.rn.f32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: add.rn.f32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_float_reassoc_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fadd_float_reassoc_param_0];
+; CHECK-SM80-NEXT: add.rn.f32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: add.rn.f32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: add.rn.f32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: add.rn.f32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: add.rn.f32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: add.rn.f32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: add.rn.f32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: add.rn.f32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: add.rn.f32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: add.rn.f32 %r16, %r15, 0f00000000;
@@ -214,10 +209,10 @@ define float @reduce_fadd_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fadd_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fadd_float_reassoc_param_0];
-; CHECK-SM100-NEXT: add.rn.f32x2 %rd5, %rd2, %rd4;
-; CHECK-SM100-NEXT: add.rn.f32x2 %rd6, %rd1, %rd3;
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fadd_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fadd_float_reassoc_param_0];
+; CHECK-SM100-NEXT: add.rn.f32x2 %rd5, %rd4, %rd2;
+; CHECK-SM100-NEXT: add.rn.f32x2 %rd6, %rd3, %rd1;
; CHECK-SM100-NEXT: add.rn.f32x2 %rd7, %rd6, %rd5;
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd7;
; CHECK-SM100-NEXT: add.rn.f32 %r3, %r1, %r2;
@@ -234,14 +229,14 @@ define float @reduce_fadd_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<15>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fadd_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fadd_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fadd_float_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: add.rn.f32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: add.rn.f32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_fadd_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_fadd_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fadd_float_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: add.rn.f32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: add.rn.f32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: add.rn.f32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: add.rn.f32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: add.rn.f32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: add.rn.f32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: add.rn.f32 %r12, %r11, %r7;
; CHECK-SM80-NEXT: add.rn.f32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: add.rn.f32 %r14, %r13, 0f00000000;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r14;
@@ -249,25 +244,22 @@ define float @reduce_fadd_float_reassoc_nonpow2(<7 x float> %in) {
;
; CHECK-SM100-LABEL: reduce_fadd_float_reassoc_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b32 %r<13>;
+; CHECK-SM100-NEXT: .reg .b32 %r<7>;
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fadd_float_reassoc_nonpow2_param_0+24];
; CHECK-SM100-NEXT: ld.param::func.b64 %rd1, [reduce_fadd_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd1;
; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [reduce_fadd_float_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fadd_float_reassoc_nonpow2_param_0+24];
; CHECK-SM100-NEXT: add.rn.f32x2 %rd4, %rd2, %rd1;
-; CHECK-SM100-NEXT: mov.b32 %r8, 0f80000000;
-; CHECK-SM100-NEXT: mov.b64 %rd5, {%r7, %r8};
+; CHECK-SM100-NEXT: mov.b32 %r2, 0f80000000;
+; CHECK-SM100-NEXT: mov.b64 %rd5, {%r1, %r2};
; CHECK-SM100-NEXT: add.rn.f32x2 %rd6, %rd3, %rd5;
; CHECK-SM100-NEXT: add.rn.f32x2 %rd7, %rd4, %rd6;
-; CHECK-SM100-NEXT: mov.b64 {%r9, %r10}, %rd7;
-; CHECK-SM100-NEXT: add.rn.f32 %r11, %r9, %r10;
-; CHECK-SM100-NEXT: add.rn.f32 %r12, %r11, 0f00000000;
-; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
+; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd7;
+; CHECK-SM100-NEXT: add.rn.f32 %r5, %r3, %r4;
+; CHECK-SM100-NEXT: add.rn.f32 %r6, %r5, 0f00000000;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r6;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fadd(float 0.0, <7 x float> %in)
ret float %res
@@ -356,46 +348,40 @@ define half @reduce_fmul_half_reassoc(<8 x half> %in) {
define half @reduce_fmul_half_reassoc_nonpow2(<7 x half> %in) {
; CHECK-SM80-LABEL: reduce_fmul_half_reassoc_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<8>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fmul_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmul_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmul_half_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmul_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: mul.rn.f16x2 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0x3C00;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0x3C00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: mul.rn.f16x2 %r6, %r3, %r5;
; CHECK-SM80-NEXT: mul.rn.f16x2 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: mul.rn.f16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: mul.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmul_half_reassoc_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fmul_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmul_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmul_half_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmul_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: mul.rn.f16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0x3C00;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0x3C00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: mul.rn.f16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: mul.rn.f16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: mul.rn.f16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: mul.rn.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmul(half 1.0, <7 x half> %in)
ret half %res
@@ -407,37 +393,32 @@ define float @reduce_fmul_float(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmul_float_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_float_param_0];
-; CHECK-SM80-NEXT: mul.rn.f32 %r9, %r1, %r2;
-; CHECK-SM80-NEXT: mul.rn.f32 %r10, %r9, %r3;
-; CHECK-SM80-NEXT: mul.rn.f32 %r11, %r10, %r4;
-; CHECK-SM80-NEXT: mul.rn.f32 %r12, %r11, %r5;
-; CHECK-SM80-NEXT: mul.rn.f32 %r13, %r12, %r6;
-; CHECK-SM80-NEXT: mul.rn.f32 %r14, %r13, %r7;
-; CHECK-SM80-NEXT: mul.rn.f32 %r15, %r14, %r8;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_float_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmul_float_param_0];
+; CHECK-SM80-NEXT: mul.rn.f32 %r9, %r5, %r6;
+; CHECK-SM80-NEXT: mul.rn.f32 %r10, %r9, %r7;
+; CHECK-SM80-NEXT: mul.rn.f32 %r11, %r10, %r8;
+; CHECK-SM80-NEXT: mul.rn.f32 %r12, %r11, %r1;
+; CHECK-SM80-NEXT: mul.rn.f32 %r13, %r12, %r2;
+; CHECK-SM80-NEXT: mul.rn.f32 %r14, %r13, %r3;
+; CHECK-SM80-NEXT: mul.rn.f32 %r15, %r14, %r4;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmul_float(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmul_float_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmul_float_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd2;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd1;
-; CHECK-SM100-NEXT: mul.rn.f32 %r9, %r7, %r8;
-; CHECK-SM100-NEXT: mul.rn.f32 %r10, %r9, %r5;
-; CHECK-SM100-NEXT: mul.rn.f32 %r11, %r10, %r6;
-; CHECK-SM100-NEXT: mul.rn.f32 %r12, %r11, %r3;
-; CHECK-SM100-NEXT: mul.rn.f32 %r13, %r12, %r4;
-; CHECK-SM100-NEXT: mul.rn.f32 %r14, %r13, %r1;
-; CHECK-SM100-NEXT: mul.rn.f32 %r15, %r14, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmul_float_param_0];
+; CHECK-SM100-NEXT: mul.rn.f32 %r9, %r5, %r6;
+; CHECK-SM100-NEXT: mul.rn.f32 %r10, %r9, %r7;
+; CHECK-SM100-NEXT: mul.rn.f32 %r11, %r10, %r8;
+; CHECK-SM100-NEXT: mul.rn.f32 %r12, %r11, %r1;
+; CHECK-SM100-NEXT: mul.rn.f32 %r13, %r12, %r2;
+; CHECK-SM100-NEXT: mul.rn.f32 %r14, %r13, %r3;
+; CHECK-SM100-NEXT: mul.rn.f32 %r15, %r14, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmul(float 1.0, <8 x float> %in)
@@ -450,13 +431,13 @@ define float @reduce_fmul_float_reassoc(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmul_float_reassoc_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_float_reassoc_param_0];
-; CHECK-SM80-NEXT: mul.rn.f32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: mul.rn.f32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_float_reassoc_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmul_float_reassoc_param_0];
+; CHECK-SM80-NEXT: mul.rn.f32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: mul.rn.f32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: mul.rn.f32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: mul.rn.f32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: mul.rn.f32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: mul.rn.f32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: mul.rn.f32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: mul.rn.f32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: mul.rn.f32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -468,10 +449,10 @@ define float @reduce_fmul_float_reassoc(<8 x float> %in) {
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmul_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmul_float_reassoc_param_0];
-; CHECK-SM100-NEXT: mul.rn.f32x2 %rd5, %rd2, %rd4;
-; CHECK-SM100-NEXT: mul.rn.f32x2 %rd6, %rd1, %rd3;
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmul_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmul_float_reassoc_param_0];
+; CHECK-SM100-NEXT: mul.rn.f32x2 %rd5, %rd4, %rd2;
+; CHECK-SM100-NEXT: mul.rn.f32x2 %rd6, %rd3, %rd1;
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd7, %rd6, %rd5;
; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd7;
; CHECK-SM100-NEXT: mul.rn.f32 %r3, %r1, %r2;
@@ -487,38 +468,35 @@ define float @reduce_fmul_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fmul_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmul_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmul_float_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: mul.rn.f32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: mul.rn.f32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_fmul_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_fmul_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fmul_float_reassoc_nonpow2_param_0];
+; CHECK-SM80-NEXT: mul.rn.f32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: mul.rn.f32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: mul.rn.f32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: mul.rn.f32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: mul.rn.f32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: mul.rn.f32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: mul.rn.f32 %r12, %r11, %r7;
; CHECK-SM80-NEXT: mul.rn.f32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmul_float_reassoc_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b32 %r<12>;
+; CHECK-SM100-NEXT: .reg .b32 %r<6>;
; CHECK-SM100-NEXT: .reg .b64 %rd<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmul_float_reassoc_nonpow2_param_0+24];
; CHECK-SM100-NEXT: ld.param::func.b64 %rd1, [reduce_fmul_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd1;
; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd2, %rd3}, [reduce_fmul_float_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd2;
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmul_float_reassoc_nonpow2_param_0+24];
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd4, %rd2, %rd1;
-; CHECK-SM100-NEXT: mov.b32 %r8, 0f3F800000;
-; CHECK-SM100-NEXT: mov.b64 %rd5, {%r7, %r8};
+; CHECK-SM100-NEXT: mov.b32 %r2, 0f3F800000;
+; CHECK-SM100-NEXT: mov.b64 %rd5, {%r1, %r2};
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd6, %rd3, %rd5;
; CHECK-SM100-NEXT: mul.rn.f32x2 %rd7, %rd4, %rd6;
-; CHECK-SM100-NEXT: mov.b64 {%r9, %r10}, %rd7;
-; CHECK-SM100-NEXT: mul.rn.f32 %r11, %r9, %r10;
-; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r11;
+; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd7;
+; CHECK-SM100-NEXT: mul.rn.f32 %r5, %r3, %r4;
+; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r5;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmul(float 1.0, <7 x float> %in)
ret float %res
@@ -595,46 +573,40 @@ define half @reduce_fmax_half_reassoc(<8 x half> %in) {
define half @reduce_fmax_half_reassoc_nonpow2(<7 x half> %in) {
; CHECK-SM80-LABEL: reduce_fmax_half_reassoc_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<8>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fmax_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmax_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmax_half_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmax_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: max.f16x2 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0xFE00;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0xFE00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: max.f16x2 %r6, %r3, %r5;
; CHECK-SM80-NEXT: max.f16x2 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: max.f16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: max.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmax_half_reassoc_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fmax_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmax_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmax_half_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmax_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: max.f16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0xFE00;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0xFE00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: max.f16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: max.f16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: max.f16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: max.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmax(<7 x half> %in)
ret half %res
@@ -677,46 +649,40 @@ define half @reduce_fmax_half_nnan(<8 x half> %in) {
define half @reduce_fmax_half_nnan_nonpow2(<7 x half> %in) {
; CHECK-SM80-LABEL: reduce_fmax_half_nnan_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<8>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fmax_half_nnan_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmax_half_nnan_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmax_half_nnan_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmax_half_nnan_nonpow2_param_0+12];
; CHECK-SM80-NEXT: max.f16x2 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0xFC00;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0xFC00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: max.f16x2 %r6, %r3, %r5;
; CHECK-SM80-NEXT: max.f16x2 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: max.f16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: max.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmax_half_nnan_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fmax_half_nnan_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmax_half_nnan_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmax_half_nnan_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmax_half_nnan_nonpow2_param_0+12];
; CHECK-SM100-NEXT: max.f16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0xFC00;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0xFC00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: max.f16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: max.f16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: max.f16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: max.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
; CHECK-SM100-NEXT: ret;
%res = call nnan half @llvm.vector.reduce.fmax(<7 x half> %in)
ret half %res
@@ -728,8 +694,8 @@ define float @reduce_fmax_float(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_param_0+16];
; CHECK-SM80-NEXT: max.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: max.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: max.f32 %r11, %r10, %r9;
@@ -743,19 +709,14 @@ define float @reduce_fmax_float(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmax_float(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: max.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: max.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_param_0];
+; CHECK-SM100-NEXT: max.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: max.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmax(<8 x float> %in)
@@ -768,8 +729,8 @@ define float @reduce_fmax_float_reassoc(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_reassoc_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: max.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: max.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: max.f32 %r11, %r10, %r9;
@@ -783,19 +744,14 @@ define float @reduce_fmax_float_reassoc(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmax_float_reassoc(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_reassoc_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: max.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: max.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_reassoc_param_0];
+; CHECK-SM100-NEXT: max.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: max.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmax(<8 x float> %in)
@@ -808,11 +764,11 @@ define float @reduce_fmax_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fmax_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmax_float_reassoc_nonpow2_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: max.f32 %r8, %r5, %r6;
-; CHECK-SM80-NEXT: max.f32 %r9, %r8, %r7;
+; CHECK-SM80-NEXT: ld.param.b32 %r5, [reduce_fmax_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r6, %r7}, [reduce_fmax_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: max.f32 %r8, %r6, %r7;
+; CHECK-SM80-NEXT: max.f32 %r9, %r8, %r5;
; CHECK-SM80-NEXT: max.f32 %r10, %r3, %r4;
; CHECK-SM80-NEXT: max.f32 %r11, %r1, %r2;
; CHECK-SM80-NEXT: max.f32 %r12, %r11, %r10;
@@ -825,12 +781,12 @@ define float @reduce_fmax_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmax_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmax_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: max.f32 %r8, %r4, %r5, %r6;
-; CHECK-SM100-NEXT: max.f32 %r9, %r1, %r2, %r3;
-; CHECK-SM100-NEXT: max.f32 %r10, %r9, %r8, %r7;
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmax_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmax_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fmax_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: max.f32 %r8, %r7, %r2, %r3;
+; CHECK-SM100-NEXT: max.f32 %r9, %r4, %r5, %r6;
+; CHECK-SM100-NEXT: max.f32 %r10, %r9, %r8, %r1;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmax(<7 x float> %in)
@@ -843,8 +799,8 @@ define float @reduce_fmax_float_nnan(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_nnan_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_nnan_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_nnan_param_0+16];
; CHECK-SM80-NEXT: max.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: max.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: max.f32 %r11, %r10, %r9;
@@ -858,19 +814,14 @@ define float @reduce_fmax_float_nnan(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmax_float_nnan(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmax_float_nnan_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmax_float_nnan_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: max.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: max.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_nnan_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmax_float_nnan_param_0];
+; CHECK-SM100-NEXT: max.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: max.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: max.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: max.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmax(<8 x float> %in)
@@ -883,11 +834,11 @@ define float @reduce_fmax_float_nnan_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fmax_float_nnan_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmax_float_nnan_nonpow2_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_nnan_nonpow2_param_0];
-; CHECK-SM80-NEXT: max.f32 %r8, %r5, %r6;
-; CHECK-SM80-NEXT: max.f32 %r9, %r8, %r7;
+; CHECK-SM80-NEXT: ld.param.b32 %r5, [reduce_fmax_float_nnan_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r6, %r7}, [reduce_fmax_float_nnan_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: max.f32 %r8, %r6, %r7;
+; CHECK-SM80-NEXT: max.f32 %r9, %r8, %r5;
; CHECK-SM80-NEXT: max.f32 %r10, %r3, %r4;
; CHECK-SM80-NEXT: max.f32 %r11, %r1, %r2;
; CHECK-SM80-NEXT: max.f32 %r12, %r11, %r10;
@@ -900,12 +851,12 @@ define float @reduce_fmax_float_nnan_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmax_float_nnan_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmax_float_nnan_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmax_float_nnan_nonpow2_param_0];
-; CHECK-SM100-NEXT: max.f32 %r8, %r4, %r5, %r6;
-; CHECK-SM100-NEXT: max.f32 %r9, %r1, %r2, %r3;
-; CHECK-SM100-NEXT: max.f32 %r10, %r9, %r8, %r7;
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmax_float_nnan_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmax_float_nnan_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fmax_float_nnan_nonpow2_param_0];
+; CHECK-SM100-NEXT: max.f32 %r8, %r7, %r2, %r3;
+; CHECK-SM100-NEXT: max.f32 %r9, %r4, %r5, %r6;
+; CHECK-SM100-NEXT: max.f32 %r10, %r9, %r8, %r1;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmax(<7 x float> %in)
@@ -983,46 +934,40 @@ define half @reduce_fmin_half_reassoc(<8 x half> %in) {
define half @reduce_fmin_half_reassoc_nonpow2(<7 x half> %in) {
; CHECK-SM80-LABEL: reduce_fmin_half_reassoc_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<8>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fmin_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmin_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmin_half_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmin_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: min.f16x2 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0x7E00;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0x7E00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: min.f16x2 %r6, %r3, %r5;
; CHECK-SM80-NEXT: min.f16x2 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: min.f16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: min.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmin_half_reassoc_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fmin_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmin_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmin_half_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmin_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: min.f16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0x7E00;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0x7E00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: min.f16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: min.f16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: min.f16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: min.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmin(<7 x half> %in)
ret half %res
@@ -1065,46 +1010,40 @@ define half @reduce_fmin_half_nnan(<8 x half> %in) {
define half @reduce_fmin_half_nnan_nonpow2(<7 x half> %in) {
; CHECK-SM80-LABEL: reduce_fmin_half_nnan_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<8>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fmin_half_nnan_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmin_half_nnan_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmin_half_nnan_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmin_half_nnan_nonpow2_param_0+12];
; CHECK-SM80-NEXT: min.f16x2 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0x7C00;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0x7C00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: min.f16x2 %r6, %r3, %r5;
; CHECK-SM80-NEXT: min.f16x2 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: min.f16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: min.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmin_half_nnan_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fmin_half_nnan_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmin_half_nnan_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmin_half_nnan_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmin_half_nnan_nonpow2_param_0+12];
; CHECK-SM100-NEXT: min.f16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0x7C00;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0x7C00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: min.f16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: min.f16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: min.f16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: min.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
; CHECK-SM100-NEXT: ret;
%res = call nnan half @llvm.vector.reduce.fmin(<7 x half> %in)
ret half %res
@@ -1116,8 +1055,8 @@ define float @reduce_fmin_float(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_param_0+16];
; CHECK-SM80-NEXT: min.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: min.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: min.f32 %r11, %r10, %r9;
@@ -1131,19 +1070,14 @@ define float @reduce_fmin_float(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmin_float(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: min.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: min.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_param_0];
+; CHECK-SM100-NEXT: min.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: min.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmin(<8 x float> %in)
@@ -1156,8 +1090,8 @@ define float @reduce_fmin_float_reassoc(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_reassoc_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: min.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: min.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: min.f32 %r11, %r10, %r9;
@@ -1171,19 +1105,14 @@ define float @reduce_fmin_float_reassoc(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmin_float_reassoc(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_reassoc_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: min.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: min.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_reassoc_param_0];
+; CHECK-SM100-NEXT: min.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: min.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmin(<8 x float> %in)
@@ -1196,11 +1125,11 @@ define float @reduce_fmin_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fmin_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmin_float_reassoc_nonpow2_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: min.f32 %r8, %r5, %r6;
-; CHECK-SM80-NEXT: min.f32 %r9, %r8, %r7;
+; CHECK-SM80-NEXT: ld.param.b32 %r5, [reduce_fmin_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r6, %r7}, [reduce_fmin_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: min.f32 %r8, %r6, %r7;
+; CHECK-SM80-NEXT: min.f32 %r9, %r8, %r5;
; CHECK-SM80-NEXT: min.f32 %r10, %r3, %r4;
; CHECK-SM80-NEXT: min.f32 %r11, %r1, %r2;
; CHECK-SM80-NEXT: min.f32 %r12, %r11, %r10;
@@ -1213,12 +1142,12 @@ define float @reduce_fmin_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmin_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmin_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: min.f32 %r8, %r4, %r5, %r6;
-; CHECK-SM100-NEXT: min.f32 %r9, %r1, %r2, %r3;
-; CHECK-SM100-NEXT: min.f32 %r10, %r9, %r8, %r7;
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmin_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmin_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fmin_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: min.f32 %r8, %r7, %r2, %r3;
+; CHECK-SM100-NEXT: min.f32 %r9, %r4, %r5, %r6;
+; CHECK-SM100-NEXT: min.f32 %r10, %r9, %r8, %r1;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmin(<7 x float> %in)
@@ -1231,8 +1160,8 @@ define float @reduce_fmin_float_nnan(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_nnan_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_nnan_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_nnan_param_0+16];
; CHECK-SM80-NEXT: min.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: min.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: min.f32 %r11, %r10, %r9;
@@ -1246,19 +1175,14 @@ define float @reduce_fmin_float_nnan(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmin_float_nnan(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmin_float_nnan_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmin_float_nnan_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: min.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: min.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_nnan_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmin_float_nnan_param_0];
+; CHECK-SM100-NEXT: min.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: min.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: min.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: min.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmin(<8 x float> %in)
@@ -1271,11 +1195,11 @@ define float @reduce_fmin_float_nnan_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fmin_float_nnan_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmin_float_nnan_nonpow2_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_nnan_nonpow2_param_0];
-; CHECK-SM80-NEXT: min.f32 %r8, %r5, %r6;
-; CHECK-SM80-NEXT: min.f32 %r9, %r8, %r7;
+; CHECK-SM80-NEXT: ld.param.b32 %r5, [reduce_fmin_float_nnan_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r6, %r7}, [reduce_fmin_float_nnan_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: min.f32 %r8, %r6, %r7;
+; CHECK-SM80-NEXT: min.f32 %r9, %r8, %r5;
; CHECK-SM80-NEXT: min.f32 %r10, %r3, %r4;
; CHECK-SM80-NEXT: min.f32 %r11, %r1, %r2;
; CHECK-SM80-NEXT: min.f32 %r12, %r11, %r10;
@@ -1288,12 +1212,12 @@ define float @reduce_fmin_float_nnan_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmin_float_nnan_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmin_float_nnan_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmin_float_nnan_nonpow2_param_0];
-; CHECK-SM100-NEXT: min.f32 %r8, %r4, %r5, %r6;
-; CHECK-SM100-NEXT: min.f32 %r9, %r1, %r2, %r3;
-; CHECK-SM100-NEXT: min.f32 %r10, %r9, %r8, %r7;
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmin_float_nnan_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmin_float_nnan_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fmin_float_nnan_nonpow2_param_0];
+; CHECK-SM100-NEXT: min.f32 %r8, %r7, %r2, %r3;
+; CHECK-SM100-NEXT: min.f32 %r9, %r4, %r5, %r6;
+; CHECK-SM100-NEXT: min.f32 %r10, %r9, %r8, %r1;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call nnan float @llvm.vector.reduce.fmin(<7 x float> %in)
@@ -1371,46 +1295,40 @@ define half @reduce_fmaximum_half_reassoc(<8 x half> %in) {
define half @reduce_fmaximum_half_reassoc_nonpow2(<7 x half> %in) {
; CHECK-SM80-LABEL: reduce_fmaximum_half_reassoc_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<8>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fmaximum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fmaximum_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fmaximum_half_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fmaximum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: max.NaN.f16x2 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0xFC00;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0xFC00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: max.NaN.f16x2 %r6, %r3, %r5;
; CHECK-SM80-NEXT: max.NaN.f16x2 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: max.NaN.f16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: max.NaN.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fmaximum_half_reassoc_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fmaximum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmaximum_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmaximum_half_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fmaximum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: max.NaN.f16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0xFC00;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0xFC00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: max.NaN.f16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: max.NaN.f16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: max.NaN.f16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: max.NaN.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fmaximum(<7 x half> %in)
ret half %res
@@ -1422,8 +1340,8 @@ define float @reduce_fmaximum_float(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmaximum_float_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmaximum_float_param_0+16];
; CHECK-SM80-NEXT: max.NaN.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: max.NaN.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: max.NaN.f32 %r11, %r10, %r9;
@@ -1437,19 +1355,14 @@ define float @reduce_fmaximum_float(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmaximum_float(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmaximum_float_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmaximum_float_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: max.NaN.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: max.NaN.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: max.NaN.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmaximum_float_param_0];
+; CHECK-SM100-NEXT: max.NaN.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: max.NaN.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: max.NaN.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fmaximum(<8 x float> %in)
@@ -1462,8 +1375,8 @@ define float @reduce_fmaximum_float_reassoc(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmaximum_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_reassoc_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmaximum_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: max.NaN.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: max.NaN.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: max.NaN.f32 %r11, %r10, %r9;
@@ -1477,19 +1390,14 @@ define float @reduce_fmaximum_float_reassoc(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fmaximum_float_reassoc(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fmaximum_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fmaximum_float_reassoc_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: max.NaN.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: max.NaN.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: max.NaN.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fmaximum_float_reassoc_param_0];
+; CHECK-SM100-NEXT: max.NaN.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: max.NaN.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: max.NaN.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmaximum(<8 x float> %in)
@@ -1502,11 +1410,11 @@ define float @reduce_fmaximum_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fmaximum_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fmaximum_float_reassoc_nonpow2_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: max.NaN.f32 %r8, %r5, %r6;
-; CHECK-SM80-NEXT: max.NaN.f32 %r9, %r8, %r7;
+; CHECK-SM80-NEXT: ld.param.b32 %r5, [reduce_fmaximum_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r6, %r7}, [reduce_fmaximum_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: max.NaN.f32 %r8, %r6, %r7;
+; CHECK-SM80-NEXT: max.NaN.f32 %r9, %r8, %r5;
; CHECK-SM80-NEXT: max.NaN.f32 %r10, %r3, %r4;
; CHECK-SM80-NEXT: max.NaN.f32 %r11, %r1, %r2;
; CHECK-SM80-NEXT: max.NaN.f32 %r12, %r11, %r10;
@@ -1519,12 +1427,12 @@ define float @reduce_fmaximum_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fmaximum_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fmaximum_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fmaximum_float_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: max.NaN.f32 %r8, %r4, %r5, %r6;
-; CHECK-SM100-NEXT: max.NaN.f32 %r9, %r1, %r2, %r3;
-; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r9, %r8, %r7;
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fmaximum_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fmaximum_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fmaximum_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: max.NaN.f32 %r8, %r7, %r2, %r3;
+; CHECK-SM100-NEXT: max.NaN.f32 %r9, %r4, %r5, %r6;
+; CHECK-SM100-NEXT: max.NaN.f32 %r10, %r9, %r8, %r1;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fmaximum(<7 x float> %in)
@@ -1602,46 +1510,40 @@ define half @reduce_fminimum_half_reassoc(<8 x half> %in) {
define half @reduce_fminimum_half_reassoc_nonpow2(<7 x half> %in) {
; CHECK-SM80-LABEL: reduce_fminimum_half_reassoc_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<8>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_fminimum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_fminimum_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_fminimum_half_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_fminimum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM80-NEXT: min.NaN.f16x2 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0x7C00;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0x7C00;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: min.NaN.f16x2 %r6, %r3, %r5;
; CHECK-SM80-NEXT: min.NaN.f16x2 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: min.NaN.f16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: min.NaN.f16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: st.param.b16 [func_retval0], %rs5;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_fminimum_half_reassoc_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<8>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_fminimum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fminimum_half_reassoc_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fminimum_half_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_fminimum_half_reassoc_nonpow2_param_0+12];
; CHECK-SM100-NEXT: min.NaN.f16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0x7C00;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0x7C00;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: min.NaN.f16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: min.NaN.f16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: min.NaN.f16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: min.NaN.f16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: st.param::func.b16 [func_retval0], %rs5;
; CHECK-SM100-NEXT: ret;
%res = call reassoc half @llvm.vector.reduce.fminimum(<7 x half> %in)
ret half %res
@@ -1653,8 +1555,8 @@ define float @reduce_fminimum_float(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fminimum_float_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fminimum_float_param_0+16];
; CHECK-SM80-NEXT: min.NaN.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: min.NaN.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: min.NaN.f32 %r11, %r10, %r9;
@@ -1668,19 +1570,14 @@ define float @reduce_fminimum_float(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fminimum_float(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fminimum_float_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fminimum_float_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: min.NaN.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: min.NaN.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: min.NaN.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fminimum_float_param_0];
+; CHECK-SM100-NEXT: min.NaN.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: min.NaN.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: min.NaN.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call float @llvm.vector.reduce.fminimum(<8 x float> %in)
@@ -1693,8 +1590,8 @@ define float @reduce_fminimum_float_reassoc(<8 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fminimum_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_reassoc_param_0];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fminimum_float_reassoc_param_0+16];
; CHECK-SM80-NEXT: min.NaN.f32 %r9, %r7, %r8;
; CHECK-SM80-NEXT: min.NaN.f32 %r10, %r5, %r6;
; CHECK-SM80-NEXT: min.NaN.f32 %r11, %r10, %r9;
@@ -1708,19 +1605,14 @@ define float @reduce_fminimum_float_reassoc(<8 x float> %in) {
; CHECK-SM100-LABEL: reduce_fminimum_float_reassoc(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<13>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_fminimum_float_reassoc_param_0+16];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_fminimum_float_reassoc_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd1;
-; CHECK-SM100-NEXT: mov.b64 {%r5, %r6}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r7, %r8}, %rd2;
-; CHECK-SM100-NEXT: min.NaN.f32 %r9, %r8, %r5, %r6;
-; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r3, %r4, %r7;
-; CHECK-SM100-NEXT: min.NaN.f32 %r11, %r10, %r9, %r1;
-; CHECK-SM100-NEXT: min.NaN.f32 %r12, %r11, %r2;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_reassoc_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_fminimum_float_reassoc_param_0];
+; CHECK-SM100-NEXT: min.NaN.f32 %r9, %r8, %r1, %r2;
+; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r5, %r6, %r7;
+; CHECK-SM100-NEXT: min.NaN.f32 %r11, %r10, %r9, %r3;
+; CHECK-SM100-NEXT: min.NaN.f32 %r12, %r11, %r4;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r12;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fminimum(<8 x float> %in)
@@ -1733,11 +1625,11 @@ define float @reduce_fminimum_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_fminimum_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_fminimum_float_reassoc_nonpow2_param_0+16];
; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_reassoc_nonpow2_param_0];
-; CHECK-SM80-NEXT: min.NaN.f32 %r8, %r5, %r6;
-; CHECK-SM80-NEXT: min.NaN.f32 %r9, %r8, %r7;
+; CHECK-SM80-NEXT: ld.param.b32 %r5, [reduce_fminimum_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r6, %r7}, [reduce_fminimum_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: min.NaN.f32 %r8, %r6, %r7;
+; CHECK-SM80-NEXT: min.NaN.f32 %r9, %r8, %r5;
; CHECK-SM80-NEXT: min.NaN.f32 %r10, %r3, %r4;
; CHECK-SM80-NEXT: min.NaN.f32 %r11, %r1, %r2;
; CHECK-SM80-NEXT: min.NaN.f32 %r12, %r11, %r10;
@@ -1750,12 +1642,12 @@ define float @reduce_fminimum_float_reassoc_nonpow2(<7 x float> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<11>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_fminimum_float_reassoc_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_fminimum_float_reassoc_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_fminimum_float_reassoc_nonpow2_param_0];
-; CHECK-SM100-NEXT: min.NaN.f32 %r8, %r4, %r5, %r6;
-; CHECK-SM100-NEXT: min.NaN.f32 %r9, %r1, %r2, %r3;
-; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r9, %r8, %r7;
+; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_fminimum_float_reassoc_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_fminimum_float_reassoc_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_fminimum_float_reassoc_nonpow2_param_0];
+; CHECK-SM100-NEXT: min.NaN.f32 %r8, %r7, %r2, %r3;
+; CHECK-SM100-NEXT: min.NaN.f32 %r9, %r4, %r5, %r6;
+; CHECK-SM100-NEXT: min.NaN.f32 %r10, %r9, %r8, %r1;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r10;
; CHECK-SM100-NEXT: ret;
%res = call reassoc float @llvm.vector.reduce.fminimum(<7 x float> %in)
@@ -1811,14 +1703,14 @@ define i16 @reduce_add_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<2>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_add_i16_nonpow2_param_0+12];
-; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_add_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_add_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: add.s16 %rs8, %rs3, %rs7;
-; CHECK-SM80-NEXT: add.s16 %rs9, %rs1, %rs5;
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [reduce_add_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.b16 %rs3, [reduce_add_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_add_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: add.s16 %rs8, %rs6, %rs3;
+; CHECK-SM80-NEXT: add.s16 %rs9, %rs4, %rs1;
; CHECK-SM80-NEXT: add.s16 %rs10, %rs9, %rs8;
-; CHECK-SM80-NEXT: add.s16 %rs11, %rs2, %rs6;
-; CHECK-SM80-NEXT: add.s16 %rs12, %rs11, %rs4;
+; CHECK-SM80-NEXT: add.s16 %rs11, %rs5, %rs2;
+; CHECK-SM80-NEXT: add.s16 %rs12, %rs11, %rs7;
; CHECK-SM80-NEXT: add.s16 %rs13, %rs10, %rs12;
; CHECK-SM80-NEXT: cvt.u32.u16 %r1, %rs13;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r1;
@@ -1826,24 +1718,21 @@ define i16 @reduce_add_i16_nonpow2(<7 x i16> %in) {
;
; CHECK-SM100-LABEL: reduce_add_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_add_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_add_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_add_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_add_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: add.s16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: add.s16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: add.s16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: add.s16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: add.s16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.add(<7 x i16> %in)
@@ -1856,13 +1745,13 @@ define i32 @reduce_add_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_add_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_param_0];
-; CHECK-SM80-NEXT: add.s32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: add.s32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_add_i32_param_0];
+; CHECK-SM80-NEXT: add.s32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: add.s32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: add.s32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: add.s32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: add.s32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: add.s32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: add.s32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: add.s32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: add.s32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -1871,20 +1760,15 @@ define i32 @reduce_add_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_add_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_add_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_add_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: add.s32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: add.s32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: add.s32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: add.s32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: add.s32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_add_i32_param_0];
+; CHECK-SM100-NEXT: add.s32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: add.s32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: add.s32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: add.s32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: add.s32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: add.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: add.s32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -1899,14 +1783,14 @@ define i32 @reduce_add_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_add_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_add_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: add.s32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: add.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_add_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_add_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_add_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: add.s32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: add.s32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: add.s32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: add.s32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: add.s32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: add.s32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: add.s32 %r12, %r11, %r7;
; CHECK-SM80-NEXT: add.s32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -1916,14 +1800,14 @@ define i32 @reduce_add_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_add_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_add_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_add_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: add.s32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: add.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_add_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_add_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_add_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: add.s32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: add.s32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: add.s32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: add.s32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: add.s32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: add.s32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: add.s32 %r12, %r11, %r7;
; CHECK-SM100-NEXT: add.s32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -1986,14 +1870,14 @@ define i16 @reduce_mul_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<2>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_mul_i16_nonpow2_param_0+12];
-; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_mul_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_mul_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: mul.lo.s16 %rs8, %rs3, %rs7;
-; CHECK-SM80-NEXT: mul.lo.s16 %rs9, %rs1, %rs5;
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [reduce_mul_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.b16 %rs3, [reduce_mul_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_mul_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: mul.lo.s16 %rs8, %rs6, %rs3;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs9, %rs4, %rs1;
; CHECK-SM80-NEXT: mul.lo.s16 %rs10, %rs9, %rs8;
-; CHECK-SM80-NEXT: mul.lo.s16 %rs11, %rs2, %rs6;
-; CHECK-SM80-NEXT: mul.lo.s16 %rs12, %rs4, %rs11;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs11, %rs5, %rs2;
+; CHECK-SM80-NEXT: mul.lo.s16 %rs12, %rs7, %rs11;
; CHECK-SM80-NEXT: mul.lo.s16 %rs13, %rs10, %rs12;
; CHECK-SM80-NEXT: cvt.u32.u16 %r1, %rs13;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2005,14 +1889,14 @@ define i16 @reduce_mul_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<2>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_mul_i16_nonpow2_param_0+12];
-; CHECK-SM100-NEXT: ld.param::func.v2.b16 {%rs5, %rs6}, [reduce_mul_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: ld.param::func.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_mul_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mul.lo.s16 %rs8, %rs3, %rs7;
-; CHECK-SM100-NEXT: mul.lo.s16 %rs9, %rs1, %rs5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b16 {%rs1, %rs2}, [reduce_mul_i16_nonpow2_param_0+8];
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs3, [reduce_mul_i16_nonpow2_param_0+12];
+; CHECK-SM100-NEXT: ld.param::func.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_mul_i16_nonpow2_param_0];
+; CHECK-SM100-NEXT: mul.lo.s16 %rs8, %rs6, %rs3;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs9, %rs4, %rs1;
; CHECK-SM100-NEXT: mul.lo.s16 %rs10, %rs9, %rs8;
-; CHECK-SM100-NEXT: mul.lo.s16 %rs11, %rs2, %rs6;
-; CHECK-SM100-NEXT: mul.lo.s16 %rs12, %rs4, %rs11;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs11, %rs5, %rs2;
+; CHECK-SM100-NEXT: mul.lo.s16 %rs12, %rs7, %rs11;
; CHECK-SM100-NEXT: mul.lo.s16 %rs13, %rs10, %rs12;
; CHECK-SM100-NEXT: cvt.u32.u16 %r1, %rs13;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r1;
@@ -2027,13 +1911,13 @@ define i32 @reduce_mul_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_mul_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_param_0];
-; CHECK-SM80-NEXT: mul.lo.s32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: mul.lo.s32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_mul_i32_param_0];
+; CHECK-SM80-NEXT: mul.lo.s32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: mul.lo.s32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: mul.lo.s32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: mul.lo.s32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: mul.lo.s32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: mul.lo.s32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: mul.lo.s32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: mul.lo.s32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: mul.lo.s32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -2042,20 +1926,15 @@ define i32 @reduce_mul_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_mul_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_mul_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_mul_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: mul.lo.s32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: mul.lo.s32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: mul.lo.s32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: mul.lo.s32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: mul.lo.s32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_mul_i32_param_0];
+; CHECK-SM100-NEXT: mul.lo.s32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: mul.lo.s32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: mul.lo.s32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: mul.lo.s32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: mul.lo.s32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: mul.lo.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: mul.lo.s32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -2070,14 +1949,14 @@ define i32 @reduce_mul_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_mul_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_mul_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: mul.lo.s32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: mul.lo.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_mul_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_mul_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_mul_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: mul.lo.s32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: mul.lo.s32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: mul.lo.s32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: mul.lo.s32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: mul.lo.s32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: mul.lo.s32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: mul.lo.s32 %r12, %r7, %r11;
; CHECK-SM80-NEXT: mul.lo.s32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -2087,14 +1966,14 @@ define i32 @reduce_mul_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_mul_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_mul_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_mul_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: mul.lo.s32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: mul.lo.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_mul_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_mul_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_mul_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: mul.lo.s32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: mul.lo.s32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: mul.lo.s32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: mul.lo.s32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: mul.lo.s32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: mul.lo.s32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: mul.lo.s32 %r12, %r7, %r11;
; CHECK-SM100-NEXT: mul.lo.s32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -2151,14 +2030,14 @@ define i16 @reduce_umax_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<2>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_umax_i16_nonpow2_param_0+12];
-; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_umax_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_umax_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: max.u16 %rs8, %rs3, %rs7;
-; CHECK-SM80-NEXT: max.u16 %rs9, %rs1, %rs5;
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [reduce_umax_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.b16 %rs3, [reduce_umax_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_umax_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: max.u16 %rs8, %rs6, %rs3;
+; CHECK-SM80-NEXT: max.u16 %rs9, %rs4, %rs1;
; CHECK-SM80-NEXT: max.u16 %rs10, %rs9, %rs8;
-; CHECK-SM80-NEXT: max.u16 %rs11, %rs2, %rs6;
-; CHECK-SM80-NEXT: max.u16 %rs12, %rs4, %rs11;
+; CHECK-SM80-NEXT: max.u16 %rs11, %rs5, %rs2;
+; CHECK-SM80-NEXT: max.u16 %rs12, %rs7, %rs11;
; CHECK-SM80-NEXT: max.u16 %rs13, %rs10, %rs12;
; CHECK-SM80-NEXT: cvt.u32.u16 %r1, %rs13;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2166,24 +2045,21 @@ define i16 @reduce_umax_i16_nonpow2(<7 x i16> %in) {
;
; CHECK-SM100-LABEL: reduce_umax_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_umax_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_umax_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_umax_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_umax_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: max.u16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: max.u16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: max.u16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: max.u16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: max.u16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.umax(<7 x i16> %in)
@@ -2196,13 +2072,13 @@ define i32 @reduce_umax_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_umax_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_param_0];
-; CHECK-SM80-NEXT: max.u32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: max.u32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_umax_i32_param_0];
+; CHECK-SM80-NEXT: max.u32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: max.u32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: max.u32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: max.u32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: max.u32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: max.u32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: max.u32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: max.u32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: max.u32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -2211,20 +2087,15 @@ define i32 @reduce_umax_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_umax_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_umax_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_umax_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: max.u32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: max.u32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: max.u32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: max.u32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: max.u32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_umax_i32_param_0];
+; CHECK-SM100-NEXT: max.u32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: max.u32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: max.u32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: max.u32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: max.u32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: max.u32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: max.u32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -2239,14 +2110,14 @@ define i32 @reduce_umax_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_umax_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_umax_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: max.u32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: max.u32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_umax_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_umax_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_umax_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: max.u32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: max.u32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: max.u32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: max.u32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: max.u32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: max.u32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: max.u32 %r12, %r7, %r11;
; CHECK-SM80-NEXT: max.u32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -2256,14 +2127,14 @@ define i32 @reduce_umax_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_umax_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_umax_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umax_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: max.u32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: max.u32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_umax_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_umax_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_umax_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: max.u32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: max.u32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: max.u32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: max.u32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: max.u32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: max.u32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: max.u32 %r12, %r7, %r11;
; CHECK-SM100-NEXT: max.u32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -2320,14 +2191,14 @@ define i16 @reduce_umin_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<2>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_umin_i16_nonpow2_param_0+12];
-; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_umin_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_umin_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: min.u16 %rs8, %rs3, %rs7;
-; CHECK-SM80-NEXT: min.u16 %rs9, %rs1, %rs5;
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [reduce_umin_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.b16 %rs3, [reduce_umin_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_umin_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: min.u16 %rs8, %rs6, %rs3;
+; CHECK-SM80-NEXT: min.u16 %rs9, %rs4, %rs1;
; CHECK-SM80-NEXT: min.u16 %rs10, %rs9, %rs8;
-; CHECK-SM80-NEXT: min.u16 %rs11, %rs2, %rs6;
-; CHECK-SM80-NEXT: min.u16 %rs12, %rs4, %rs11;
+; CHECK-SM80-NEXT: min.u16 %rs11, %rs5, %rs2;
+; CHECK-SM80-NEXT: min.u16 %rs12, %rs7, %rs11;
; CHECK-SM80-NEXT: min.u16 %rs13, %rs10, %rs12;
; CHECK-SM80-NEXT: cvt.u32.u16 %r1, %rs13;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2335,24 +2206,21 @@ define i16 @reduce_umin_i16_nonpow2(<7 x i16> %in) {
;
; CHECK-SM100-LABEL: reduce_umin_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_umin_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_umin_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_umin_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_umin_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: min.u16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, -1;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, -1;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: min.u16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: min.u16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: min.u16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: min.u16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.umin(<7 x i16> %in)
@@ -2365,13 +2233,13 @@ define i32 @reduce_umin_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_umin_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_param_0];
-; CHECK-SM80-NEXT: min.u32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: min.u32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_umin_i32_param_0];
+; CHECK-SM80-NEXT: min.u32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: min.u32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: min.u32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: min.u32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: min.u32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: min.u32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: min.u32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: min.u32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: min.u32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -2380,20 +2248,15 @@ define i32 @reduce_umin_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_umin_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_umin_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_umin_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: min.u32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: min.u32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: min.u32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: min.u32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: min.u32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_umin_i32_param_0];
+; CHECK-SM100-NEXT: min.u32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: min.u32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: min.u32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: min.u32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: min.u32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: min.u32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: min.u32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -2408,14 +2271,14 @@ define i32 @reduce_umin_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_umin_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_umin_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: min.u32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: min.u32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_umin_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_umin_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_umin_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: min.u32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: min.u32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: min.u32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: min.u32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: min.u32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: min.u32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: min.u32 %r12, %r7, %r11;
; CHECK-SM80-NEXT: min.u32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -2425,14 +2288,14 @@ define i32 @reduce_umin_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_umin_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_umin_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_umin_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: min.u32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: min.u32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_umin_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_umin_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_umin_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: min.u32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: min.u32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: min.u32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: min.u32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: min.u32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: min.u32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: min.u32 %r12, %r7, %r11;
; CHECK-SM100-NEXT: min.u32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -2489,14 +2352,14 @@ define i16 @reduce_smax_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<2>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_smax_i16_nonpow2_param_0+12];
-; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_smax_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_smax_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: max.s16 %rs8, %rs3, %rs7;
-; CHECK-SM80-NEXT: max.s16 %rs9, %rs1, %rs5;
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [reduce_smax_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.b16 %rs3, [reduce_smax_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_smax_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: max.s16 %rs8, %rs6, %rs3;
+; CHECK-SM80-NEXT: max.s16 %rs9, %rs4, %rs1;
; CHECK-SM80-NEXT: max.s16 %rs10, %rs9, %rs8;
-; CHECK-SM80-NEXT: max.s16 %rs11, %rs2, %rs6;
-; CHECK-SM80-NEXT: max.s16 %rs12, %rs4, %rs11;
+; CHECK-SM80-NEXT: max.s16 %rs11, %rs5, %rs2;
+; CHECK-SM80-NEXT: max.s16 %rs12, %rs7, %rs11;
; CHECK-SM80-NEXT: max.s16 %rs13, %rs10, %rs12;
; CHECK-SM80-NEXT: cvt.u32.u16 %r1, %rs13;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2504,24 +2367,21 @@ define i16 @reduce_smax_i16_nonpow2(<7 x i16> %in) {
;
; CHECK-SM100-LABEL: reduce_smax_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_smax_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_smax_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_smax_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_smax_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: max.s16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, -32768;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, -32768;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: max.s16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: max.s16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: max.s16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: max.s16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.smax(<7 x i16> %in)
@@ -2534,13 +2394,13 @@ define i32 @reduce_smax_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_smax_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_param_0];
-; CHECK-SM80-NEXT: max.s32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: max.s32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_smax_i32_param_0];
+; CHECK-SM80-NEXT: max.s32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: max.s32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: max.s32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: max.s32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: max.s32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: max.s32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: max.s32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: max.s32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: max.s32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -2549,20 +2409,15 @@ define i32 @reduce_smax_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_smax_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_smax_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_smax_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: max.s32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: max.s32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: max.s32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: max.s32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: max.s32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_smax_i32_param_0];
+; CHECK-SM100-NEXT: max.s32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: max.s32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: max.s32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: max.s32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: max.s32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: max.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: max.s32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -2577,14 +2432,14 @@ define i32 @reduce_smax_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_smax_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_smax_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: max.s32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: max.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_smax_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_smax_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_smax_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: max.s32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: max.s32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: max.s32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: max.s32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: max.s32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: max.s32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: max.s32 %r12, %r7, %r11;
; CHECK-SM80-NEXT: max.s32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -2594,14 +2449,14 @@ define i32 @reduce_smax_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_smax_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_smax_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smax_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: max.s32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: max.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_smax_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_smax_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_smax_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: max.s32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: max.s32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: max.s32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: max.s32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: max.s32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: max.s32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: max.s32 %r12, %r7, %r11;
; CHECK-SM100-NEXT: max.s32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -2658,14 +2513,14 @@ define i16 @reduce_smin_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<2>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_smin_i16_nonpow2_param_0+12];
-; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs5, %rs6}, [reduce_smin_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs1, %rs2, %rs3, %rs4}, [reduce_smin_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: min.s16 %rs8, %rs3, %rs7;
-; CHECK-SM80-NEXT: min.s16 %rs9, %rs1, %rs5;
+; CHECK-SM80-NEXT: ld.param.v2.b16 {%rs1, %rs2}, [reduce_smin_i16_nonpow2_param_0+8];
+; CHECK-SM80-NEXT: ld.param.b16 %rs3, [reduce_smin_i16_nonpow2_param_0+12];
+; CHECK-SM80-NEXT: ld.param.v4.b16 {%rs4, %rs5, %rs6, %rs7}, [reduce_smin_i16_nonpow2_param_0];
+; CHECK-SM80-NEXT: min.s16 %rs8, %rs6, %rs3;
+; CHECK-SM80-NEXT: min.s16 %rs9, %rs4, %rs1;
; CHECK-SM80-NEXT: min.s16 %rs10, %rs9, %rs8;
-; CHECK-SM80-NEXT: min.s16 %rs11, %rs2, %rs6;
-; CHECK-SM80-NEXT: min.s16 %rs12, %rs4, %rs11;
+; CHECK-SM80-NEXT: min.s16 %rs11, %rs5, %rs2;
+; CHECK-SM80-NEXT: min.s16 %rs12, %rs7, %rs11;
; CHECK-SM80-NEXT: min.s16 %rs13, %rs10, %rs12;
; CHECK-SM80-NEXT: cvt.u32.u16 %r1, %rs13;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r1;
@@ -2673,24 +2528,21 @@ define i16 @reduce_smin_i16_nonpow2(<7 x i16> %in) {
;
; CHECK-SM100-LABEL: reduce_smin_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_smin_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_smin_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_smin_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_smin_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: min.s16x2 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 32767;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 32767;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: min.s16x2 %r6, %r3, %r5;
; CHECK-SM100-NEXT: min.s16x2 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: min.s16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: min.s16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.smin(<7 x i16> %in)
@@ -2703,13 +2555,13 @@ define i32 @reduce_smin_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_smin_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_param_0];
-; CHECK-SM80-NEXT: min.s32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: min.s32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_smin_i32_param_0];
+; CHECK-SM80-NEXT: min.s32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: min.s32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: min.s32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: min.s32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: min.s32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: min.s32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: min.s32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: min.s32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: min.s32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -2718,20 +2570,15 @@ define i32 @reduce_smin_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_smin_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_smin_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_smin_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: min.s32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: min.s32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: min.s32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: min.s32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: min.s32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_smin_i32_param_0];
+; CHECK-SM100-NEXT: min.s32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: min.s32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: min.s32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: min.s32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: min.s32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: min.s32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: min.s32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -2746,14 +2593,14 @@ define i32 @reduce_smin_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_smin_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_smin_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: min.s32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: min.s32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_smin_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_smin_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_smin_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: min.s32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: min.s32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: min.s32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: min.s32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: min.s32 %r12, %r4, %r11;
+; CHECK-SM80-NEXT: min.s32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: min.s32 %r12, %r7, %r11;
; CHECK-SM80-NEXT: min.s32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -2763,14 +2610,14 @@ define i32 @reduce_smin_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_smin_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_smin_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_smin_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: min.s32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: min.s32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_smin_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_smin_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_smin_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: min.s32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: min.s32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: min.s32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: min.s32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: min.s32 %r12, %r4, %r11;
+; CHECK-SM100-NEXT: min.s32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: min.s32 %r12, %r7, %r11;
; CHECK-SM100-NEXT: min.s32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -2817,47 +2664,41 @@ define i16 @reduce_and_i16(<8 x i16> %in) {
define i16 @reduce_and_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-LABEL: reduce_and_i16_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<9>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_and_i16_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_and_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_and_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_and_i16_nonpow2_param_0+12];
; CHECK-SM80-NEXT: and.b32 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, -1;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, -1;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: and.b32 %r6, %r3, %r5;
; CHECK-SM80-NEXT: and.b32 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: and.b16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: and.b16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_and_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_and_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_and_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_and_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_and_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: and.b32 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, -1;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, -1;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: and.b32 %r6, %r3, %r5;
; CHECK-SM100-NEXT: and.b32 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: and.b16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: and.b16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.and(<7 x i16> %in)
@@ -2870,13 +2711,13 @@ define i32 @reduce_and_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_and_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_param_0];
-; CHECK-SM80-NEXT: and.b32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: and.b32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_and_i32_param_0];
+; CHECK-SM80-NEXT: and.b32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: and.b32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: and.b32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: and.b32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: and.b32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: and.b32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: and.b32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: and.b32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: and.b32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -2885,20 +2726,15 @@ define i32 @reduce_and_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_and_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_and_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_and_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: and.b32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: and.b32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: and.b32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: and.b32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: and.b32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_and_i32_param_0];
+; CHECK-SM100-NEXT: and.b32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: and.b32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: and.b32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: and.b32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: and.b32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: and.b32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: and.b32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -2913,14 +2749,14 @@ define i32 @reduce_and_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_and_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_and_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: and.b32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: and.b32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_and_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_and_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_and_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: and.b32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: and.b32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: and.b32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: and.b32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: and.b32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: and.b32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: and.b32 %r12, %r11, %r7;
; CHECK-SM80-NEXT: and.b32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -2930,14 +2766,14 @@ define i32 @reduce_and_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_and_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_and_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_and_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: and.b32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: and.b32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_and_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_and_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_and_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: and.b32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: and.b32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: and.b32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: and.b32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: and.b32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: and.b32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: and.b32 %r12, %r11, %r7;
; CHECK-SM100-NEXT: and.b32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -2984,47 +2820,41 @@ define i16 @reduce_or_i16(<8 x i16> %in) {
define i16 @reduce_or_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-LABEL: reduce_or_i16_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<9>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_or_i16_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_or_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_or_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_or_i16_nonpow2_param_0+12];
; CHECK-SM80-NEXT: or.b32 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: or.b32 %r6, %r3, %r5;
; CHECK-SM80-NEXT: or.b32 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: or.b16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: or.b16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_or_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_or_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_or_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_or_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_or_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: or.b32 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: or.b32 %r6, %r3, %r5;
; CHECK-SM100-NEXT: or.b32 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: or.b16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: or.b16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.or(<7 x i16> %in)
@@ -3037,13 +2867,13 @@ define i32 @reduce_or_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_or_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_param_0];
-; CHECK-SM80-NEXT: or.b32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: or.b32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_or_i32_param_0];
+; CHECK-SM80-NEXT: or.b32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: or.b32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: or.b32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: or.b32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: or.b32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: or.b32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: or.b32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: or.b32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: or.b32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -3052,20 +2882,15 @@ define i32 @reduce_or_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_or_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_or_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_or_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: or.b32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: or.b32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: or.b32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: or.b32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: or.b32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_or_i32_param_0];
+; CHECK-SM100-NEXT: or.b32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: or.b32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: or.b32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: or.b32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: or.b32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: or.b32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: or.b32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -3080,14 +2905,14 @@ define i32 @reduce_or_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_or_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_or_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: or.b32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: or.b32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_or_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_or_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_or_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: or.b32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: or.b32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: or.b32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: or.b32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: or.b32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: or.b32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: or.b32 %r12, %r11, %r7;
; CHECK-SM80-NEXT: or.b32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -3097,14 +2922,14 @@ define i32 @reduce_or_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_or_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_or_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_or_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: or.b32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: or.b32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_or_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_or_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_or_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: or.b32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: or.b32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: or.b32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: or.b32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: or.b32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: or.b32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: or.b32 %r12, %r11, %r7;
; CHECK-SM100-NEXT: or.b32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
@@ -3151,47 +2976,41 @@ define i16 @reduce_xor_i16(<8 x i16> %in) {
define i16 @reduce_xor_i16_nonpow2(<7 x i16> %in) {
; CHECK-SM80-LABEL: reduce_xor_i16_nonpow2(
; CHECK-SM80: {
-; CHECK-SM80-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM80-NEXT: .reg .b16 %rs<6>;
; CHECK-SM80-NEXT: .reg .b32 %r<9>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
+; CHECK-SM80-NEXT: ld.param.b16 %rs1, [reduce_xor_i16_nonpow2_param_0+12];
; CHECK-SM80-NEXT: ld.param.b32 %r1, [reduce_xor_i16_nonpow2_param_0+8];
-; CHECK-SM80-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM80-NEXT: ld.param.v2.b32 {%r2, %r3}, [reduce_xor_i16_nonpow2_param_0];
-; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM80-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM80-NEXT: ld.param.b16 %rs7, [reduce_xor_i16_nonpow2_param_0+12];
; CHECK-SM80-NEXT: xor.b32 %r4, %r2, %r1;
-; CHECK-SM80-NEXT: mov.b16 %rs8, 0;
-; CHECK-SM80-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM80-NEXT: mov.b16 %rs2, 0;
+; CHECK-SM80-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM80-NEXT: xor.b32 %r6, %r3, %r5;
; CHECK-SM80-NEXT: xor.b32 %r7, %r4, %r6;
-; CHECK-SM80-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM80-NEXT: xor.b16 %rs11, %rs9, %rs10;
-; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM80-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM80-NEXT: xor.b16 %rs5, %rs3, %rs4;
+; CHECK-SM80-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r8;
; CHECK-SM80-NEXT: ret;
;
; CHECK-SM100-LABEL: reduce_xor_i16_nonpow2(
; CHECK-SM100: {
-; CHECK-SM100-NEXT: .reg .b16 %rs<12>;
+; CHECK-SM100-NEXT: .reg .b16 %rs<6>;
; CHECK-SM100-NEXT: .reg .b32 %r<9>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.b16 %rs1, [reduce_xor_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: ld.param::func.b32 %r1, [reduce_xor_i16_nonpow2_param_0+8];
-; CHECK-SM100-NEXT: mov.b32 {%rs5, %rs6}, %r1;
; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r2, %r3}, [reduce_xor_i16_nonpow2_param_0];
-; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r3;
-; CHECK-SM100-NEXT: mov.b32 {%rs1, %rs2}, %r2;
-; CHECK-SM100-NEXT: ld.param::func.b16 %rs7, [reduce_xor_i16_nonpow2_param_0+12];
; CHECK-SM100-NEXT: xor.b32 %r4, %r2, %r1;
-; CHECK-SM100-NEXT: mov.b16 %rs8, 0;
-; CHECK-SM100-NEXT: mov.b32 %r5, {%rs7, %rs8};
+; CHECK-SM100-NEXT: mov.b16 %rs2, 0;
+; CHECK-SM100-NEXT: mov.b32 %r5, {%rs1, %rs2};
; CHECK-SM100-NEXT: xor.b32 %r6, %r3, %r5;
; CHECK-SM100-NEXT: xor.b32 %r7, %r4, %r6;
-; CHECK-SM100-NEXT: mov.b32 {%rs9, %rs10}, %r7;
-; CHECK-SM100-NEXT: xor.b16 %rs11, %rs9, %rs10;
-; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs11;
+; CHECK-SM100-NEXT: mov.b32 {%rs3, %rs4}, %r7;
+; CHECK-SM100-NEXT: xor.b16 %rs5, %rs3, %rs4;
+; CHECK-SM100-NEXT: cvt.u32.u16 %r8, %rs5;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r8;
; CHECK-SM100-NEXT: ret;
%res = call i16 @llvm.vector.reduce.xor(<7 x i16> %in)
@@ -3204,13 +3023,13 @@ define i32 @reduce_xor_i32(<8 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<16>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_xor_i32_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_param_0];
-; CHECK-SM80-NEXT: xor.b32 %r9, %r4, %r8;
-; CHECK-SM80-NEXT: xor.b32 %r10, %r2, %r6;
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_param_0+16];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_xor_i32_param_0];
+; CHECK-SM80-NEXT: xor.b32 %r9, %r8, %r4;
+; CHECK-SM80-NEXT: xor.b32 %r10, %r6, %r2;
; CHECK-SM80-NEXT: xor.b32 %r11, %r10, %r9;
-; CHECK-SM80-NEXT: xor.b32 %r12, %r3, %r7;
-; CHECK-SM80-NEXT: xor.b32 %r13, %r1, %r5;
+; CHECK-SM80-NEXT: xor.b32 %r12, %r7, %r3;
+; CHECK-SM80-NEXT: xor.b32 %r13, %r5, %r1;
; CHECK-SM80-NEXT: xor.b32 %r14, %r13, %r12;
; CHECK-SM80-NEXT: xor.b32 %r15, %r14, %r11;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r15;
@@ -3219,20 +3038,15 @@ define i32 @reduce_xor_i32(<8 x i32> %in) {
; CHECK-SM100-LABEL: reduce_xor_i32(
; CHECK-SM100: {
; CHECK-SM100-NEXT: .reg .b32 %r<16>;
-; CHECK-SM100-NEXT: .reg .b64 %rd<5>;
-; CHECK-SM100-EMPTY:
-; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd3, %rd4}, [reduce_xor_i32_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v2.b64 {%rd1, %rd2}, [reduce_xor_i32_param_0];
-; CHECK-SM100-NEXT: mov.b64 {%r1, %r2}, %rd4;
-; CHECK-SM100-NEXT: mov.b64 {%r3, %r4}, %rd2;
-; CHECK-SM100-NEXT: xor.b32 %r5, %r4, %r2;
-; CHECK-SM100-NEXT: mov.b64 {%r6, %r7}, %rd3;
-; CHECK-SM100-NEXT: mov.b64 {%r8, %r9}, %rd1;
-; CHECK-SM100-NEXT: xor.b32 %r10, %r9, %r7;
-; CHECK-SM100-NEXT: xor.b32 %r11, %r10, %r5;
-; CHECK-SM100-NEXT: xor.b32 %r12, %r3, %r1;
-; CHECK-SM100-NEXT: xor.b32 %r13, %r8, %r6;
+; CHECK-SM100-EMPTY:
+; CHECK-SM100-NEXT: // %bb.0:
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r5, %r6, %r7, %r8}, [reduce_xor_i32_param_0];
+; CHECK-SM100-NEXT: xor.b32 %r9, %r8, %r4;
+; CHECK-SM100-NEXT: xor.b32 %r10, %r6, %r2;
+; CHECK-SM100-NEXT: xor.b32 %r11, %r10, %r9;
+; CHECK-SM100-NEXT: xor.b32 %r12, %r7, %r3;
+; CHECK-SM100-NEXT: xor.b32 %r13, %r5, %r1;
; CHECK-SM100-NEXT: xor.b32 %r14, %r13, %r12;
; CHECK-SM100-NEXT: xor.b32 %r15, %r14, %r11;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r15;
@@ -3247,14 +3061,14 @@ define i32 @reduce_xor_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM80-NEXT: .reg .b32 %r<14>;
; CHECK-SM80-EMPTY:
; CHECK-SM80-NEXT: // %bb.0:
-; CHECK-SM80-NEXT: ld.param.b32 %r7, [reduce_xor_i32_nonpow2_param_0+24];
-; CHECK-SM80-NEXT: ld.param.v2.b32 {%r5, %r6}, [reduce_xor_i32_nonpow2_param_0+16];
-; CHECK-SM80-NEXT: ld.param.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_nonpow2_param_0];
-; CHECK-SM80-NEXT: xor.b32 %r8, %r3, %r7;
-; CHECK-SM80-NEXT: xor.b32 %r9, %r1, %r5;
+; CHECK-SM80-NEXT: ld.param.v2.b32 {%r1, %r2}, [reduce_xor_i32_nonpow2_param_0+16];
+; CHECK-SM80-NEXT: ld.param.b32 %r3, [reduce_xor_i32_nonpow2_param_0+24];
+; CHECK-SM80-NEXT: ld.param.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_xor_i32_nonpow2_param_0];
+; CHECK-SM80-NEXT: xor.b32 %r8, %r6, %r3;
+; CHECK-SM80-NEXT: xor.b32 %r9, %r4, %r1;
; CHECK-SM80-NEXT: xor.b32 %r10, %r9, %r8;
-; CHECK-SM80-NEXT: xor.b32 %r11, %r2, %r6;
-; CHECK-SM80-NEXT: xor.b32 %r12, %r11, %r4;
+; CHECK-SM80-NEXT: xor.b32 %r11, %r5, %r2;
+; CHECK-SM80-NEXT: xor.b32 %r12, %r11, %r7;
; CHECK-SM80-NEXT: xor.b32 %r13, %r10, %r12;
; CHECK-SM80-NEXT: st.param.b32 [func_retval0], %r13;
; CHECK-SM80-NEXT: ret;
@@ -3264,14 +3078,14 @@ define i32 @reduce_xor_i32_nonpow2(<7 x i32> %in) {
; CHECK-SM100-NEXT: .reg .b32 %r<14>;
; CHECK-SM100-EMPTY:
; CHECK-SM100-NEXT: // %bb.0:
-; CHECK-SM100-NEXT: ld.param::func.b32 %r7, [reduce_xor_i32_nonpow2_param_0+24];
-; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r5, %r6}, [reduce_xor_i32_nonpow2_param_0+16];
-; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r1, %r2, %r3, %r4}, [reduce_xor_i32_nonpow2_param_0];
-; CHECK-SM100-NEXT: xor.b32 %r8, %r3, %r7;
-; CHECK-SM100-NEXT: xor.b32 %r9, %r1, %r5;
+; CHECK-SM100-NEXT: ld.param::func.v2.b32 {%r1, %r2}, [reduce_xor_i32_nonpow2_param_0+16];
+; CHECK-SM100-NEXT: ld.param::func.b32 %r3, [reduce_xor_i32_nonpow2_param_0+24];
+; CHECK-SM100-NEXT: ld.param::func.v4.b32 {%r4, %r5, %r6, %r7}, [reduce_xor_i32_nonpow2_param_0];
+; CHECK-SM100-NEXT: xor.b32 %r8, %r6, %r3;
+; CHECK-SM100-NEXT: xor.b32 %r9, %r4, %r1;
; CHECK-SM100-NEXT: xor.b32 %r10, %r9, %r8;
-; CHECK-SM100-NEXT: xor.b32 %r11, %r2, %r6;
-; CHECK-SM100-NEXT: xor.b32 %r12, %r11, %r4;
+; CHECK-SM100-NEXT: xor.b32 %r11, %r5, %r2;
+; CHECK-SM100-NEXT: xor.b32 %r12, %r11, %r7;
; CHECK-SM100-NEXT: xor.b32 %r13, %r10, %r12;
; CHECK-SM100-NEXT: st.param::func.b32 [func_retval0], %r13;
; CHECK-SM100-NEXT: ret;
diff --git a/llvm/test/CodeGen/NVPTX/vaargs.ll b/llvm/test/CodeGen/NVPTX/vaargs.ll
index 3c40bd47c79844..cc82547e1f02d6 100644
--- a/llvm/test/CodeGen/NVPTX/vaargs.ll
+++ b/llvm/test/CodeGen/NVPTX/vaargs.ll
@@ -22,8 +22,8 @@ define i32 @foo(i32 %a, ...) {
; CHECK32-EMPTY:
; CHECK32-NEXT: // %bb.0: // %entry
; CHECK32-NEXT: mov.b32 %SPL, __local_depot0;
-; CHECK32-NEXT: ld.param.b32 %r2, [foo_param_1];
; CHECK32-NEXT: ld.param.b32 %r1, [foo_param_0];
+; CHECK32-NEXT: ld.param.b32 %r2, [foo_param_1];
; CHECK32-NEXT: add.u32 %r3, %SPL, 0;
; CHECK32-NEXT: cvta.local.u32 %r4, %r3;
; CHECK32-NEXT: add.u32 %r5, %SPL, 16;
@@ -98,8 +98,8 @@ define i32 @foo(i32 %a, ...) {
; CHECK64-EMPTY:
; CHECK64-NEXT: // %bb.0: // %entry
; CHECK64-NEXT: mov.b64 %SPL, __local_depot0;
-; CHECK64-NEXT: ld.param.b64 %rd1, [foo_param_1];
; CHECK64-NEXT: ld.param.b32 %r1, [foo_param_0];
+; CHECK64-NEXT: ld.param.b64 %rd1, [foo_param_1];
; CHECK64-NEXT: add.u64 %rd2, %SPL, 0;
; CHECK64-NEXT: cvta.local.u64 %rd3, %rd2;
; CHECK64-NEXT: add.u64 %rd4, %SPL, 24;
@@ -216,30 +216,31 @@ define i32 @test_foo(i32 %i, i64 %l, double %d, ptr %p) {
; CHECK32-NEXT: .reg .b32 %SPL;
; CHECK32-NEXT: .reg .b32 %r<9>;
; CHECK32-NEXT: .reg .b64 %rd<3>;
-; CHECK32: $L__prototype_0:
-; CHECK32-NEXT: .callprototype (.param .b32 _) _ (.param .b32 _, .param .b32 _);
+; CHECK32-EMPTY:
+; CHECK32-NEXT: $L__prototype_0:
+; CHECK32-NEXT: .callprototype (.param .b32 _) _ (.param .b32 _, .param .b32 _);
; CHECK32-NEXT: // %bb.0: // %entry
; CHECK32-NEXT: mov.b32 %SPL, __local_depot1;
-; CHECK32-NEXT: ld.param.b32 %r2, [test_foo_param_3];
-; CHECK32-NEXT: ld.param.b64 %rd2, [test_foo_param_2];
-; CHECK32-NEXT: ld.param.b64 %rd1, [test_foo_param_1];
; CHECK32-NEXT: ld.param.b32 %r1, [test_foo_param_0];
-; CHECK32-NEXT: add.u32 %r3, %SPL, 0;
-; CHECK32-NEXT: cvta.local.u32 %r4, %r3;
-; CHECK32-NEXT: mov.b32 %r5, foo_ptr;
-; CHECK32-NEXT: cvta.global.u32 %r6, %r5;
-; CHECK32-NEXT: ld.b32 %r7, [%r6];
-; CHECK32-NEXT: st.b32 [%r4], %r1;
-; CHECK32-NEXT: st.b64 [%r4+8], %rd1;
-; CHECK32-NEXT: st.b64 [%r4+16], %rd2;
-; CHECK32-NEXT: st.b32 [%r4+24], %r2;
+; CHECK32-NEXT: ld.param.b64 %rd1, [test_foo_param_1];
+; CHECK32-NEXT: add.u32 %r2, %SPL, 0;
+; CHECK32-NEXT: cvta.local.u32 %r3, %r2;
+; CHECK32-NEXT: ld.param.b64 %rd2, [test_foo_param_2];
+; CHECK32-NEXT: mov.b32 %r4, foo_ptr;
+; CHECK32-NEXT: cvta.global.u32 %r5, %r4;
+; CHECK32-NEXT: ld.b32 %r6, [%r5];
+; CHECK32-NEXT: ld.param.b32 %r7, [test_foo_param_3];
+; CHECK32-NEXT: st.b32 [%r3], %r1;
+; CHECK32-NEXT: st.b64 [%r3+8], %rd1;
+; CHECK32-NEXT: st.b64 [%r3+16], %rd2;
+; CHECK32-NEXT: st.b32 [%r3+24], %r7;
; CHECK32-NEXT: { // callseq 1, 0
; CHECK32-NEXT: .param .b32 param0;
; CHECK32-NEXT: .param .b32 param1;
; CHECK32-NEXT: .param .b32 retval0;
-; CHECK32-NEXT: st.param.b32 [param1], %r3;
+; CHECK32-NEXT: st.param.b32 [param1], %r2;
; CHECK32-NEXT: st.param.b32 [param0], 4;
-; CHECK32-NEXT: call (retval0), %r7, (param0, param1), $L__prototype_0;
+; CHECK32-NEXT: call (retval0), %r6, (param0, param1), $L__prototype_0;
; CHECK32-NEXT: ld.param.b32 %r8, [retval0];
; CHECK32-NEXT: } // callseq 1
; CHECK32-NEXT: st.param.b32 [func_retval0], %r8;
@@ -252,30 +253,31 @@ define i32 @test_foo(i32 %i, i64 %l, double %d, ptr %p) {
; CHECK64-NEXT: .reg .b64 %SPL;
; CHECK64-NEXT: .reg .b32 %r<3>;
; CHECK64-NEXT: .reg .b64 %rd<9>;
-; CHECK64: $L__prototype_0:
-; CHECK64-NEXT: .callprototype (.param .b32 _) _ (.param .b32 _, .param .b64 _);
+; CHECK64-EMPTY:
+; CHECK64-NEXT: $L__prototype_0:
+; CHECK64-NEXT: .callprototype (.param .b32 _) _ (.param .b32 _, .param .b64 _);
; CHECK64-NEXT: // %bb.0: // %entry
; CHECK64-NEXT: mov.b64 %SPL, __local_depot1;
-; CHECK64-NEXT: ld.param.b64 %rd3, [test_foo_param_3];
-; CHECK64-NEXT: ld.param.b64 %rd2, [test_foo_param_2];
-; CHECK64-NEXT: ld.param.b64 %rd1, [test_foo_param_1];
; CHECK64-NEXT: ld.param.b32 %r1, [test_foo_param_0];
-; CHECK64-NEXT: add.u64 %rd4, %SPL, 0;
-; CHECK64-NEXT: cvta.local.u64 %rd5, %rd4;
-; CHECK64-NEXT: mov.b64 %rd6, foo_ptr;
-; CHECK64-NEXT: cvta.global.u64 %rd7, %rd6;
-; CHECK64-NEXT: ld.b64 %rd8, [%rd7];
-; CHECK64-NEXT: st.b32 [%rd5], %r1;
-; CHECK64-NEXT: st.b64 [%rd5+8], %rd1;
-; CHECK64-NEXT: st.b64 [%rd5+16], %rd2;
-; CHECK64-NEXT: st.b64 [%rd5+24], %rd3;
+; CHECK64-NEXT: ld.param.b64 %rd1, [test_foo_param_1];
+; CHECK64-NEXT: add.u64 %rd2, %SPL, 0;
+; CHECK64-NEXT: cvta.local.u64 %rd3, %rd2;
+; CHECK64-NEXT: ld.param.b64 %rd4, [test_foo_param_2];
+; CHECK64-NEXT: mov.b64 %rd5, foo_ptr;
+; CHECK64-NEXT: cvta.global.u64 %rd6, %rd5;
+; CHECK64-NEXT: ld.b64 %rd7, [%rd6];
+; CHECK64-NEXT: ld.param.b64 %rd8, [test_foo_param_3];
+; CHECK64-NEXT: st.b32 [%rd3], %r1;
+; CHECK64-NEXT: st.b64 [%rd3+8], %rd1;
+; CHECK64-NEXT: st.b64 [%rd3+16], %rd4;
+; CHECK64-NEXT: st.b64 [%rd3+24], %rd8;
; CHECK64-NEXT: { // callseq 1, 0
; CHECK64-NEXT: .param .b32 param0;
; CHECK64-NEXT: .param .b64 param1;
; CHECK64-NEXT: .param .b32 retval0;
-; CHECK64-NEXT: st.param.b64 [param1], %rd4;
+; CHECK64-NEXT: st.param.b64 [param1], %rd2;
; CHECK64-NEXT: st.param.b32 [param0], 4;
-; CHECK64-NEXT: call (retval0), %rd8, (param0, param1), $L__prototype_0;
+; CHECK64-NEXT: call (retval0), %rd7, (param0, param1), $L__prototype_0;
; CHECK64-NEXT: ld.param.b32 %r2, [retval0];
; CHECK64-NEXT: } // callseq 1
; CHECK64-NEXT: st.param.b32 [func_retval0], %r2;
diff --git a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
index 3fcff5878a7950..429161c0aece71 100644
--- a/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
+++ b/llvm/test/CodeGen/PowerPC/ppcsoftops.ll
@@ -313,10 +313,7 @@ define zeroext i1 @ppcf128_soften(ppc_fp128 %a) #0 {
; PPC-LABEL: ppcf128_soften:
; PPC: # %bb.0: # %entry
; PPC-NEXT: stwu 1, -16(1)
-; PPC-NEXT: stw 5, 8(1) # 4-byte Folded Spill
-; PPC-NEXT: mr 5, 4
-; PPC-NEXT: lwz 4, 8(1) # 4-byte Folded Reload
-; PPC-NEXT: stw 5, 12(1) # 4-byte Folded Spill
+; PPC-NEXT: stw 4, 12(1) # 4-byte Folded Spill
; PPC-NEXT: mr 5, 3
; PPC-NEXT: lwz 3, 12(1) # 4-byte Folded Reload
; PPC-NEXT: xoris 4, 5, 65520
diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
index 9e8a5f331172e3..9c8a3c8e260d3b 100644
--- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-O0.ll
@@ -7,8 +7,6 @@ define <2 x double> @fixed_length(<2 x double> %a, <2 x double> %b) nounwind {
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; CHECK-NEXT: vmv1r.v v10, v9
-; CHECK-NEXT: # kill: def $v11 killed $v10 killed $vtype
-; CHECK-NEXT: # kill: def $v9 killed $v8 killed $vtype
; CHECK-NEXT: # implicit-def: $v9
; CHECK-NEXT: vfadd.vv v9, v8, v10
; CHECK-NEXT: # implicit-def: $v8
diff --git a/llvm/test/CodeGen/SPARC/fp16-promote.ll b/llvm/test/CodeGen/SPARC/fp16-promote.ll
index f26624324c0d56..20ee2905578773 100644
--- a/llvm/test/CodeGen/SPARC/fp16-promote.ll
+++ b/llvm/test/CodeGen/SPARC/fp16-promote.ll
@@ -162,25 +162,14 @@ define void @test_fpextend_fp128(ptr %p, ptr %out) nounwind {
}
define void @test_fptrunc_float(float %f, ptr %p) nounwind {
-; V8-OPT-LABEL: test_fptrunc_float:
-; V8-OPT: ! %bb.0:
-; V8-OPT-NEXT: save %sp, -96, %sp
-; V8-OPT-NEXT: call __truncsfhf2
-; V8-OPT-NEXT: mov %i0, %o0
-; V8-OPT-NEXT: sth %o0, [%i1]
-; V8-OPT-NEXT: ret
-; V8-OPT-NEXT: restore
-;
-; V8-UNOPT-LABEL: test_fptrunc_float:
-; V8-UNOPT: ! %bb.0:
-; V8-UNOPT-NEXT: save %sp, -96, %sp
-; V8-UNOPT-NEXT: mov %i0, %o0
-; V8-UNOPT-NEXT: st %o0, [%fp+-4]
-; V8-UNOPT-NEXT: call __truncsfhf2
-; V8-UNOPT-NEXT: ld [%fp+-4], %f0
-; V8-UNOPT-NEXT: sth %o0, [%i1]
-; V8-UNOPT-NEXT: ret
-; V8-UNOPT-NEXT: restore
+; V8-LABEL: test_fptrunc_float:
+; V8: ! %bb.0:
+; V8-NEXT: save %sp, -96, %sp
+; V8-NEXT: call __truncsfhf2
+; V8-NEXT: mov %i0, %o0
+; V8-NEXT: sth %o0, [%i1]
+; V8-NEXT: ret
+; V8-NEXT: restore
;
; V9-LABEL: test_fptrunc_float:
; V9: ! %bb.0:
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
index b76729d062f1ea..7d062bc8357aa4 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_add.ll
@@ -22,7 +22,6 @@ declare i32 @llvm.vp.reduce.add.v256i32(i32, <256 x i32>, <256 x i1>, i32)
define fastcc i32 @vp_reduce_add_v256i32(i32 %s, <256 x i32> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_add_v256i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
index fef21c5294a809..d47e31f0b8e00a 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_and.ll
@@ -22,8 +22,6 @@ declare i32 @llvm.vp.reduce.and.v256i32(i32, <256 x i32>, <256 x i1>, i32)
define fastcc i32 @vp_reduce_and_v256i32(i32 %s, <256 x i32> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_and_v256i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: and %s2, %s0, (32)0
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 killed $sx2
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
; CHECK-NEXT: lvl %s1
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
index aa47e812693f73..a203d4a161e565 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_or.ll
@@ -22,8 +22,6 @@ declare i32 @llvm.vp.reduce.or.v256i32(i32, <256 x i32>, <256 x i1>, i32)
define fastcc i32 @vp_reduce_or_v256i32(i32 %s, <256 x i32> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_or_v256i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: and %s2, %s0, (32)0
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 killed $sx2
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
; CHECK-NEXT: lvl %s1
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
index 59bdb210a0e54c..54e6ddcac4bfb5 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_smax.ll
@@ -22,7 +22,6 @@ declare i32 @llvm.vp.reduce.smax.v256i32(i32, <256 x i32>, <256 x i1>, i32)
define fastcc i32 @vp_reduce_smax_v256i32(i32 %s, <256 x i32> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_smax_v256i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: and %s0, %s0, (32)0
; CHECK-NEXT: # kill: def $sw0 killed $sw0 killed $sx0
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
diff --git a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
index 9da1eb8db93252..3a417b838cb54e 100644
--- a/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
+++ b/llvm/test/CodeGen/VE/Vector/vp_reduce_xor.ll
@@ -22,8 +22,6 @@ declare i32 @llvm.vp.reduce.xor.v256i32(i32, <256 x i32>, <256 x i1>, i32)
define fastcc i32 @vp_reduce_xor_v256i32(i32 %s, <256 x i32> %v, <256 x i1> %m, i32 %n) {
; CHECK-LABEL: vp_reduce_xor_v256i32:
; CHECK: # %bb.0:
-; CHECK-NEXT: and %s2, %s0, (32)0
-; CHECK-NEXT: # kill: def $sw2 killed $sw2 killed $sx2
; CHECK-NEXT: and %s1, %s1, (32)0
; CHECK-NEXT: # kill: def $sw1 killed $sw1 killed $sx1
; CHECK-NEXT: lvl %s1
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