[llvm-branch-commits] [llvm] AArch64: Move scheduling model definitions to separate file (PR #231888)
Matt Arsenault via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Wed Oct 14 05:23:16 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/231888
Move the SchedMachineModel definitions, and the unsupported feature
lists they use, out of the scheduling files. The processor definitions
can then be parsed without the instruction and scheduling information.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
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>From 26b3eb1775d72b5f07e7219d29acc0f56128bfec Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 13 Oct 2026 10:35:28 -0700
Subject: [PATCH] AArch64: Move scheduling model definitions to separate file
Move the SchedMachineModel definitions, and the unsupported feature
lists they use, out of the scheduling files. The processor definitions
can then be parsed without the instruction and scheduling information.
Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
llvm/lib/Target/AArch64/AArch64.td | 61 +-
llvm/lib/Target/AArch64/AArch64SchedA320.td | 11 -
llvm/lib/Target/AArch64/AArch64SchedA510.td | 14 -
llvm/lib/Target/AArch64/AArch64SchedA53.td | 18 -
llvm/lib/Target/AArch64/AArch64SchedA55.td | 18 -
llvm/lib/Target/AArch64/AArch64SchedA57.td | 17 -
llvm/lib/Target/AArch64/AArch64SchedA64FX.td | 17 -
.../lib/Target/AArch64/AArch64SchedAmpere1.td | 14 -
.../Target/AArch64/AArch64SchedAmpere1B.td | 14 -
llvm/lib/Target/AArch64/AArch64SchedC1Nano.td | 18 -
.../Target/AArch64/AArch64SchedC1Premium.td | 16 -
.../lib/Target/AArch64/AArch64SchedC1Ultra.td | 14 -
.../lib/Target/AArch64/AArch64SchedCyclone.td | 13 -
.../Target/AArch64/AArch64SchedExynosM3.td | 14 -
.../Target/AArch64/AArch64SchedExynosM4.td | 14 -
.../Target/AArch64/AArch64SchedExynosM5.td | 14 -
llvm/lib/Target/AArch64/AArch64SchedFalkor.td | 16 -
llvm/lib/Target/AArch64/AArch64SchedHIP12.td | 14 -
llvm/lib/Target/AArch64/AArch64SchedKryo.td | 19 -
llvm/lib/Target/AArch64/AArch64SchedModels.td | 551 ++++++++++++++++++
.../Target/AArch64/AArch64SchedNeoverseN1.td | 16 -
.../Target/AArch64/AArch64SchedNeoverseN2.td | 13 -
.../Target/AArch64/AArch64SchedNeoverseN3.td | 13 -
.../Target/AArch64/AArch64SchedNeoverseV1.td | 16 -
.../Target/AArch64/AArch64SchedNeoverseV2.td | 17 -
.../Target/AArch64/AArch64SchedNeoverseV3.td | 15 -
.../AArch64/AArch64SchedNeoverseV3AE.td | 15 -
.../lib/Target/AArch64/AArch64SchedOlympus.td | 18 -
llvm/lib/Target/AArch64/AArch64SchedOryon.td | 16 -
llvm/lib/Target/AArch64/AArch64SchedTSV110.td | 16 -
.../Target/AArch64/AArch64SchedThunderX.td | 17 -
.../AArch64/AArch64SchedThunderX2T99.td | 18 -
.../AArch64/AArch64SchedThunderX3T110.td | 18 -
33 files changed, 552 insertions(+), 543 deletions(-)
create mode 100644 llvm/lib/Target/AArch64/AArch64SchedModels.td
diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td
index 9750fa837c1804..11bf91e810563f 100644
--- a/llvm/lib/Target/AArch64/AArch64.td
+++ b/llvm/lib/Target/AArch64/AArch64.td
@@ -61,66 +61,7 @@ include "AArch64LFI.td"
// AArch64 Processors supported.
//
-//===----------------------------------------------------------------------===//
-// Unsupported features to disable for scheduling models
-//===----------------------------------------------------------------------===//
-
-class AArch64Unsupported { list<Predicate> F; }
-
-let F = [HasSVE2p1, HasSVE2p1_or_SME, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in
-def SVE2p1Unsupported : AArch64Unsupported;
-
-def SVE2Unsupported : AArch64Unsupported {
- let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasNonStreamingSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
- HasSSVE_FP8DOT2, HasSSVE_FP8DOT4,
- HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVESM4, HasSVEBitPerm,
- HasSVEB16B16, HasSVEBFSCALE],
- SVE2p1Unsupported.F);
-}
-
-def SVEUnsupported : AArch64Unsupported {
- let F = !listconcat([HasSVE, HasSVE_or_SME],
- SVE2Unsupported.F);
-}
-
-def SME2p3Unsupported : AArch64Unsupported {
- let F = [HasSVE2p3_or_SME2p3, HasSVE_B16MM];
-}
-
-def SME2p2Unsupported : AArch64Unsupported {
- let F = !listconcat([HasSME2p2, HasSVE2p2_or_SME2p2,
- HasNonStreamingSVE_or_SME2p2,
- HasNonStreamingSVE2p2_or_SME2p2],
- SME2p3Unsupported.F);
-}
-
-def SME2p1Unsupported : AArch64Unsupported {
- let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1,
- HasSME_MOP4, HasSME_TMOP, HasNonStreamingSVE_or_SSVE_FEXPA,
- HasNonStreamingSVE_or_SSVE_BitPerm],
- SME2p2Unsupported.F);
-}
-
-def SME2Unsupported : AArch64Unsupported {
- let F = !listconcat([HasSME2, HasNonStreamingSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
- HasSSVE_FP8DOT2, HasSSVE_FP8DOT4,
- HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,
- HasNonStreamingSVE_or_SSVE_AES, HasSVE2p1_or_StreamingSME2, HasSME2andIsNonStreamingSafe],
- SME2p1Unsupported.F);
-}
-
-def SMEUnsupported : AArch64Unsupported {
- let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64,
- HasSMEandIsNonStreamingSafe],
- SME2Unsupported.F);
-}
-
-def MTEUnsupported : AArch64Unsupported {
- let F = [HasMTE];
-}
-
-let F = [HasPAuth, HasPAuthLR] in
-def PAUnsupported : AArch64Unsupported;
+include "AArch64SchedModels.td"
include "AArch64SchedA320.td"
include "AArch64SchedA53.td"
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA320.td b/llvm/lib/Target/AArch64/AArch64SchedA320.td
index 74656fb6ca98c2..6a9e7373f6ff0f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA320.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA320.td
@@ -14,17 +14,6 @@
// The following definitions describe the per-operand machine model.
// This works with MachineScheduler. See MCSchedModel.h for details.
-// Cortex-A320 machine model for scheduling and other instruction cost heuristics.
-def CortexA320Model : SchedMachineModel {
- let MicroOpBufferSize = 0; // Cortex-A320 is an in-order processor
- let IssueWidth = 1; // Cortex-A320 is a single-issue processor
- let LoadLatency = 5;
- let PostRAScheduler = 1; // Enable PostRA scheduler pass.
- let CompleteModel = 0; // Covers instructions applicable to Cortex-A320.
-
- let FullInstRWOverlapCheck = 0;
-}
-
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedWrite types
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA510.td b/llvm/lib/Target/AArch64/AArch64SchedA510.td
index 56ac7141be30f4..1ba3d4949920b0 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA510.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA510.td
@@ -14,20 +14,6 @@
// The following definitions describe the per-operand machine model.
// This works with MachineScheduler. See MCSchedModel.h for details.
-// Cortex-A510 machine model for scheduling and other instruction cost heuristics.
-def CortexA510Model : SchedMachineModel {
- let MicroOpBufferSize = 0; // The Cortex-A510 is an in-order processor
- let IssueWidth = 3; // It dual-issues under most circumstances
- let LoadLatency = 3; // Cycles for loads to access the cache.
- // Most loads have a latency of 2, but some have higher latencies.
- // 3 seems to be a good tradeoff
- let PostRAScheduler = 1; // Enable PostRA scheduler pass.
- let CompleteModel = 0; // Covers instructions applicable to Cortex-A510.
-
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
-}
-
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedWrite types
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td
index 291f78582d94a0..99c41ba133f5df 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA53.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td
@@ -14,24 +14,6 @@
// The following definitions describe the simpler per-operand machine model.
// This works with MachineScheduler. See MCSchedule.h for details.
-// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
-def CortexA53Model : SchedMachineModel {
- let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
- let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
- let LoadLatency = 3; // Optimistic load latency assuming bypass.
- // This is overridden by OperandCycles if the
- // Itineraries are queried instead.
- let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
- // Specification - Instruction Timings"
- // v 1.0 Spreadsheet
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA55.td b/llvm/lib/Target/AArch64/AArch64SchedA55.td
index 26a7d753340e84..32ff123d35db30 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA55.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA55.td
@@ -17,24 +17,6 @@
// The following definitions describe the per-operand machine model.
// This works with MachineScheduler. See MCSchedModel.h for details.
-// Cortex-A55 machine model for scheduling and other instruction cost heuristics.
-def CortexA55Model : SchedMachineModel {
- let MicroOpBufferSize = 0; // The Cortex-A55 is an in-order processor
- let IssueWidth = 2; // It dual-issues under most circumstances
- let LoadLatency = 4; // Cycles for loads to access the cache. The
- // optimisation guide shows that most loads have
- // a latency of 3, but some have a latency of 4
- // or 5. Setting it 4 looked to be good trade-off.
- let MispredictPenalty = 8; // A branch direction mispredict.
- let PostRAScheduler = 1; // Enable PostRA scheduler pass.
- let CompleteModel = 0; // Covers instructions applicable to Cortex-A55.
-
- list<Predicate> UnsupportedFeatures = [HasSVE, HasMTE];
-
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td
index 9260379fb5b270..795fec518cc317 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td
@@ -20,23 +20,6 @@
// Therefore, IssueWidth is set to the narrower of the two at three, while still
// modeling the machine as out-of-order.
-def CortexA57Model : SchedMachineModel {
- let IssueWidth = 3; // 3-way decode and dispatch
- let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
- let LoadLatency = 4; // Optimistic load latency
- let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
-
- // Enable partial & runtime unrolling. The magic number is chosen based on
- // experiments and benchmarking data.
- let LoopMicroOpBufferSize = 16;
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Cortex-A57.
// Cortex A-57 has 8 pipelines that each has its own 8-entry queue where
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index 8ecfa612af63e3..790412e547b915 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -10,23 +10,6 @@
//
//===----------------------------------------------------------------------===//
-def A64FXModel : SchedMachineModel {
- let IssueWidth = 6; // 6 micro-ops dispatched at a time.
- let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
- let LoadLatency = 5; // Optimistic load latency.
- let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
- // Determined via a mix of micro-arch details and experimentation.
- let LoopMicroOpBufferSize = 128;
- let PostRAScheduler = 1; // Using PostRA sched.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F,
- [HasMTE, HasMatMulInt8, HasBF16,
- HasPAuth, HasPAuthLR, HasCPA,
- HasCSSC, HasMOPS, HasMOPS_GO]);
- let FullInstRWOverlapCheck = 0;
-}
-
let SchedModel = A64FXModel in {
// Define the issue ports.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
index 269f4ec5e5fb16..46a2e686a74e3f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
@@ -16,20 +16,6 @@
// mispredicted branch. Instructions coming out of the front end are
// decoded into internal micro-ops (uops).
-def Ampere1Model : SchedMachineModel {
- let IssueWidth = 4; // 4-way decode and dispatch
- let MicroOpBufferSize = 192; // re-order buffer size
- let LoadLatency = 4; // Optimistic load latency
- let MispredictPenalty = 10; // Branch mispredict penalty
- let LoopMicroOpBufferSize = 32; // Instruction queue size
- let CompleteModel = 0;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- SMEUnsupported.F,
- PAUnsupported.F,
- [HasMTE]);
-}
-
let SchedModel = Ampere1Model in {
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
index d77c48126af396..df983601b72257 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
@@ -16,20 +16,6 @@
// mispredicted branch. Instructions coming out of the front end are
// decoded into internal micro-ops (uops).
-def Ampere1BModel : SchedMachineModel {
- let IssueWidth = 12; // Maximum micro-ops dispatch rate.
- let MicroOpBufferSize = 208; // micro-op re-order buffer size
- let LoadLatency = 3; // Optimistic load latency
- let MispredictPenalty = 10; // Branch mispredict penalty
- let LoopMicroOpBufferSize = 32; // Instruction queue size
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- SMEUnsupported.F,
- PAUnsupported.F,
- [HasMOPS, HasMOPS_GO]);
-}
-
let SchedModel = Ampere1BModel in {
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedC1Nano.td b/llvm/lib/Target/AArch64/AArch64SchedC1Nano.td
index 1abbf139323bf0..cd1b19c08dbef1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedC1Nano.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedC1Nano.td
@@ -19,24 +19,6 @@
// ===---------------------------------------------------------------------===//
-// C1-Nano machine model for scheduling and other instruction cost heuristics.
-def C1NanoModel : SchedMachineModel {
- let MicroOpBufferSize = 0; // The C1-Nano is an in-order processor
- let IssueWidth = 3; // It dual-issues under most circumstances
- let LoadLatency = 3; // Cycles for loads to access the cache.
- // 2 is best case, 4 is normal case.
- // 3 seems to be a good tradeoff
- let PostRAScheduler = 1; // Enable PostRA scheduler pass.
- let CompleteModel = 0; // The C1-Nano model is incomplete due
- // SME instruction details that are not
- // available in the SWOG.
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
- SME2Unsupported.F,
- [HasSVEB16B16, HasSVEBFSCALE,
- HasCPA, HasMTE, HasCSSC]);
-}
-
//===----------------------------------------------------------------------===//
// Subtarget-specific SchedWrite types
diff --git a/llvm/lib/Target/AArch64/AArch64SchedC1Premium.td b/llvm/lib/Target/AArch64/AArch64SchedC1Premium.td
index 7c8d219a90fba9..9883f2d96db063 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedC1Premium.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedC1Premium.td
@@ -16,22 +16,6 @@
//
//===----------------------------------------------------------------------===//
-def C1PremiumModel : SchedMachineModel {
- let IssueWidth = 10;
- let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
- let LoopMicroOpBufferSize = 16;
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SME2p1Unsupported.F,
- SVE2p1Unsupported.F,
- [HasSVE2p1, HasSVEB16B16,
- HasSVEBFSCALE,
- HasCPA, HasCSSC,
- HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on C1 Premium.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
index cd6f330178b618..748b1e5c5568a9 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedC1Ultra.td
@@ -17,20 +17,6 @@
//
//===----------------------------------------------------------------------===//
-def C1UltraModel : SchedMachineModel {
- let IssueWidth = 10;
- let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V3
- let LoadLatency = 4; // Optimistic load latency. NOTE: Copied from Neoverse-V3
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N3.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVE2p1Unsupported.F, SME2p1Unsupported.F,
- [HasSVEB16B16, HasCPA, HasMTE,
- HasCSSC, HasMOPS, HasMOPS_GO,
- HasSVEBFSCALE, HasFAMINMAX]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on C1 Ultra.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
index 7929ede8d099b3..7e786dbbdcb2c9 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
@@ -11,19 +11,6 @@
//
//===----------------------------------------------------------------------===//
-def CycloneModel : SchedMachineModel {
- let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.
- let MicroOpBufferSize = 192; // Based on the reorder buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 16; // 14-19 cycles are typical.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Cyclone.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 3644617928dc21..9e39150add68b6 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -16,20 +16,6 @@
// in-order stage for decode and dispatch and a wider issue stage.
// The execution units and loads and stores are out-of-order.
-def ExynosM3Model : SchedMachineModel {
- let IssueWidth = 6; // Up to 6 uops per cycle.
- let MicroOpBufferSize = 228; // ROB size.
- let LoopMicroOpBufferSize = 40; // Based on the instruction queue size.
- let LoadLatency = 4; // Optimistic load cases.
- let MispredictPenalty = 16; // Minimum branch misprediction penalty.
- let CompleteModel = 1; // Use the default model otherwise.
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on the Exynos-M3,
// which has 12 pipelines, each with its own queue with out-of-order dispatch.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
index e72d91101582ab..a22846ce90394f 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -16,20 +16,6 @@
// in-order stage for decode and dispatch and a wider issue stage.
// The execution units and loads and stores are out-of-order.
-def ExynosM4Model : SchedMachineModel {
- let IssueWidth = 6; // Up to 6 uops per cycle.
- let MicroOpBufferSize = 228; // ROB size.
- let LoopMicroOpBufferSize = 48; // Based on the instruction queue size.
- let LoadLatency = 4; // Optimistic load cases.
- let MispredictPenalty = 16; // Minimum branch misprediction penalty.
- let CompleteModel = 1; // Use the default model otherwise.
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on the Exynos-M4.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
index 35a787bdd8fc7e..ed5ce74af02d43 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
@@ -16,20 +16,6 @@
// in-order stage for decode and dispatch and a wider issue stage.
// The execution units and loads and stores are out-of-order.
-def ExynosM5Model : SchedMachineModel {
- let IssueWidth = 6; // Up to 6 uops per cycle.
- let MicroOpBufferSize = 228; // ROB size.
- let LoopMicroOpBufferSize = 60; // Based on the instruction queue size.
- let LoadLatency = 4; // Optimistic load cases.
- let MispredictPenalty = 15; // Minimum branch misprediction penalty.
- let CompleteModel = 1; // Use the default model otherwise.
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on the Exynos-M5.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
index 778a2621618a70..df8a8572e7fa10 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
@@ -15,22 +15,6 @@
// Define the SchedMachineModel and provide basic properties for coarse grained
// instruction cost model.
-def FalkorModel : SchedMachineModel {
- let IssueWidth = 8; // 8 uops are dispatched per cycle.
- let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
- let LoopMicroOpBufferSize = 16;
- let LoadLatency = 3; // Optimistic load latency.
- let MispredictPenalty = 11; // Minimum branch misprediction penalty.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Falkor.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
index 06a139bebcbe87..140f9be863fd95 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
@@ -11,20 +11,6 @@
//
//===----------------------------------------------------------------------===//
-def HIP12Model : SchedMachineModel {
- let IssueWidth = 8; // Micro-ops dispatched at a time.
- let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- SVE2p1Unsupported.F,
- [HasSVEB16B16, HasSVEBFSCALE, HasMTE,
- HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
let SchedModel = HIP12Model in {
// Define the (19) issue ports.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedKryo.td b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
index eec8f37906fd4c..c34bb8dfae6ca6 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedKryo.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedKryo.td
@@ -16,25 +16,6 @@
// uops. Now, the latency spreadsheet has information based on fragmented uops,
// but these do not actually take up an issue queue.
-def KryoModel : SchedMachineModel {
- let IssueWidth = 5; // 5-wide issue for expanded uops
- let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
- let LoadLatency = 4; // Optimistic load latency
- let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
-
- // Enable partial & runtime unrolling. The magic number is chosen based on
- // experiments and benchmarking data.
- let LoopMicroOpBufferSize = 16;
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Kryo.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedModels.td b/llvm/lib/Target/AArch64/AArch64SchedModels.td
new file mode 100644
index 00000000000000..7a5289851a13f7
--- /dev/null
+++ b/llvm/lib/Target/AArch64/AArch64SchedModels.td
@@ -0,0 +1,551 @@
+//=- AArch64SchedModels.td - AArch64 Scheduling Models -------*- tablegen -*-=//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Unsupported features to disable for scheduling models
+//===----------------------------------------------------------------------===//
+
+class AArch64Unsupported { list<Predicate> F; }
+
+let F = [HasSVE2p1, HasSVE2p1_or_SME, HasSVE2p1_or_SME2, HasSVE2p1_or_StreamingSME2, HasSVE2p1_or_SME2p1] in
+def SVE2p1Unsupported : AArch64Unsupported;
+
+def SVE2Unsupported : AArch64Unsupported {
+ let F = !listconcat([HasSVE2, HasSVE2_or_SME, HasNonStreamingSVE2_or_SME2, HasSSVE_FP8FMA, HasSMEF8F16,
+ HasSSVE_FP8DOT2, HasSSVE_FP8DOT4,
+ HasSMEF8F32, HasSVEAES, HasSVESHA3, HasSVESM4, HasSVEBitPerm,
+ HasSVEB16B16, HasSVEBFSCALE],
+ SVE2p1Unsupported.F);
+}
+
+def SVEUnsupported : AArch64Unsupported {
+ let F = !listconcat([HasSVE, HasSVE_or_SME],
+ SVE2Unsupported.F);
+}
+
+def SME2p3Unsupported : AArch64Unsupported {
+ let F = [HasSVE2p3_or_SME2p3, HasSVE_B16MM];
+}
+
+def SME2p2Unsupported : AArch64Unsupported {
+ let F = !listconcat([HasSME2p2, HasSVE2p2_or_SME2p2,
+ HasNonStreamingSVE_or_SME2p2,
+ HasNonStreamingSVE2p2_or_SME2p2],
+ SME2p3Unsupported.F);
+}
+
+def SME2p1Unsupported : AArch64Unsupported {
+ let F = !listconcat([HasSME2p1, HasSVE2p1_or_SME2p1,
+ HasSME_MOP4, HasSME_TMOP, HasNonStreamingSVE_or_SSVE_FEXPA,
+ HasNonStreamingSVE_or_SSVE_BitPerm],
+ SME2p2Unsupported.F);
+}
+
+def SME2Unsupported : AArch64Unsupported {
+ let F = !listconcat([HasSME2, HasNonStreamingSVE2_or_SME2, HasSVE2p1_or_SME2, HasSSVE_FP8FMA,
+ HasSSVE_FP8DOT2, HasSSVE_FP8DOT4,
+ HasSMEF8F16, HasSMEF8F32, HasSMEF16F16_or_SMEF8F16, HasSMEB16B16,
+ HasNonStreamingSVE_or_SSVE_AES, HasSVE2p1_or_StreamingSME2, HasSME2andIsNonStreamingSafe],
+ SME2p1Unsupported.F);
+}
+
+def SMEUnsupported : AArch64Unsupported {
+ let F = !listconcat([HasSME, HasSMEI16I64, HasSMEF16F16, HasSMEF64F64, HasSMEFA64,
+ HasSMEandIsNonStreamingSafe],
+ SME2Unsupported.F);
+}
+
+def MTEUnsupported : AArch64Unsupported {
+ let F = [HasMTE];
+}
+
+let F = [HasPAuth, HasPAuthLR] in
+def PAUnsupported : AArch64Unsupported;
+
+// Cortex-A320 machine model for scheduling and other instruction cost heuristics.
+def CortexA320Model : SchedMachineModel {
+ let MicroOpBufferSize = 0; // Cortex-A320 is an in-order processor
+ let IssueWidth = 1; // Cortex-A320 is a single-issue processor
+ let LoadLatency = 5;
+ let PostRAScheduler = 1; // Enable PostRA scheduler pass.
+ let CompleteModel = 0; // Covers instructions applicable to Cortex-A320.
+
+ let FullInstRWOverlapCheck = 0;
+}
+
+// Cortex-A53 machine model for scheduling and other instruction cost heuristics.
+def CortexA53Model : SchedMachineModel {
+ let MicroOpBufferSize = 0; // Explicitly set to zero since A53 is in-order.
+ let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
+ let LoadLatency = 3; // Optimistic load latency assuming bypass.
+ // This is overridden by OperandCycles if the
+ // Itineraries are queried instead.
+ let MispredictPenalty = 9; // Based on "Cortex-A53 Software Optimisation
+ // Specification - Instruction Timings"
+ // v 1.0 Spreadsheet
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+// Cortex-A55 machine model for scheduling and other instruction cost heuristics.
+def CortexA55Model : SchedMachineModel {
+ let MicroOpBufferSize = 0; // The Cortex-A55 is an in-order processor
+ let IssueWidth = 2; // It dual-issues under most circumstances
+ let LoadLatency = 4; // Cycles for loads to access the cache. The
+ // optimisation guide shows that most loads have
+ // a latency of 3, but some have a latency of 4
+ // or 5. Setting it 4 looked to be good trade-off.
+ let MispredictPenalty = 8; // A branch direction mispredict.
+ let PostRAScheduler = 1; // Enable PostRA scheduler pass.
+ let CompleteModel = 0; // Covers instructions applicable to Cortex-A55.
+
+ list<Predicate> UnsupportedFeatures = [HasSVE, HasMTE];
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
+}
+
+// Cortex-A510 machine model for scheduling and other instruction cost heuristics.
+def CortexA510Model : SchedMachineModel {
+ let MicroOpBufferSize = 0; // The Cortex-A510 is an in-order processor
+ let IssueWidth = 3; // It dual-issues under most circumstances
+ let LoadLatency = 3; // Cycles for loads to access the cache.
+ // Most loads have a latency of 2, but some have higher latencies.
+ // 3 seems to be a good tradeoff
+ let PostRAScheduler = 1; // Enable PostRA scheduler pass.
+ let CompleteModel = 0; // Covers instructions applicable to Cortex-A510.
+
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
+}
+
+def CortexA57Model : SchedMachineModel {
+ let IssueWidth = 3; // 3-way decode and dispatch
+ let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
+ let LoadLatency = 4; // Optimistic load latency
+ let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
+
+ // Enable partial & runtime unrolling. The magic number is chosen based on
+ // experiments and benchmarking data.
+ let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+// C1-Nano machine model for scheduling and other instruction cost heuristics.
+def C1NanoModel : SchedMachineModel {
+ let MicroOpBufferSize = 0; // The C1-Nano is an in-order processor
+ let IssueWidth = 3; // It dual-issues under most circumstances
+ let LoadLatency = 3; // Cycles for loads to access the cache.
+ // 2 is best case, 4 is normal case.
+ // 3 seems to be a good tradeoff
+ let PostRAScheduler = 1; // Enable PostRA scheduler pass.
+ let CompleteModel = 0; // The C1-Nano model is incomplete due
+ // SME instruction details that are not
+ // available in the SWOG.
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
+ SME2Unsupported.F,
+ [HasSVEB16B16, HasSVEBFSCALE,
+ HasCPA, HasMTE, HasCSSC]);
+}
+
+def C1UltraModel : SchedMachineModel {
+ let IssueWidth = 10;
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V3
+ let LoadLatency = 4; // Optimistic load latency. NOTE: Copied from Neoverse-V3
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N3.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVE2p1Unsupported.F, SME2p1Unsupported.F,
+ [HasSVEB16B16, HasCPA, HasMTE,
+ HasCSSC, HasMOPS, HasMOPS_GO,
+ HasSVEBFSCALE, HasFAMINMAX]);
+}
+
+def C1PremiumModel : SchedMachineModel {
+ let IssueWidth = 10;
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SME2p1Unsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasSVEBFSCALE,
+ HasCPA, HasCSSC,
+ HasMOPS, HasMOPS_GO]);
+}
+
+def CycloneModel : SchedMachineModel {
+ let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.
+ let MicroOpBufferSize = 192; // Based on the reorder buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 16; // 14-19 cycles are typical.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def FalkorModel : SchedMachineModel {
+ let IssueWidth = 8; // 8 uops are dispatched per cycle.
+ let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
+ let LoopMicroOpBufferSize = 16;
+ let LoadLatency = 3; // Optimistic load latency.
+ let MispredictPenalty = 11; // Minimum branch misprediction penalty.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
+}
+
+def KryoModel : SchedMachineModel {
+ let IssueWidth = 5; // 5-wide issue for expanded uops
+ let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
+ let LoadLatency = 4; // Optimistic load latency
+ let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
+
+ // Enable partial & runtime unrolling. The magic number is chosen based on
+ // experiments and benchmarking data.
+ let LoopMicroOpBufferSize = 16;
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
+}
+
+def ExynosM3Model : SchedMachineModel {
+ let IssueWidth = 6; // Up to 6 uops per cycle.
+ let MicroOpBufferSize = 228; // ROB size.
+ let LoopMicroOpBufferSize = 40; // Based on the instruction queue size.
+ let LoadLatency = 4; // Optimistic load cases.
+ let MispredictPenalty = 16; // Minimum branch misprediction penalty.
+ let CompleteModel = 1; // Use the default model otherwise.
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def ExynosM4Model : SchedMachineModel {
+ let IssueWidth = 6; // Up to 6 uops per cycle.
+ let MicroOpBufferSize = 228; // ROB size.
+ let LoopMicroOpBufferSize = 48; // Based on the instruction queue size.
+ let LoadLatency = 4; // Optimistic load cases.
+ let MispredictPenalty = 16; // Minimum branch misprediction penalty.
+ let CompleteModel = 1; // Use the default model otherwise.
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def ExynosM5Model : SchedMachineModel {
+ let IssueWidth = 6; // Up to 6 uops per cycle.
+ let MicroOpBufferSize = 228; // ROB size.
+ let LoopMicroOpBufferSize = 60; // Based on the instruction queue size.
+ let LoadLatency = 4; // Optimistic load cases.
+ let MispredictPenalty = 15; // Minimum branch misprediction penalty.
+ let CompleteModel = 1; // Use the default model otherwise.
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+// Cavium ThunderX T8X scheduling machine model.
+def ThunderXT8XModel : SchedMachineModel {
+ let IssueWidth = 2; // 2 micro-ops dispatched per cycle.
+ let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
+ let LoadLatency = 3; // Optimistic load latency.
+ let MispredictPenalty = 8; // Branch mispredict penalty.
+ let PostRAScheduler = 1; // Use PostRA scheduler.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
+}
+
+def ThunderX2T99Model : SchedMachineModel {
+ let IssueWidth = 4; // 4 micro-ops dispatched at a time.
+ let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
+ // Determined via a mix of micro-arch details and experimentation.
+ let LoopMicroOpBufferSize = 128;
+ let PostRAScheduler = 1; // Using PostRA sched.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
+}
+
+def A64FXModel : SchedMachineModel {
+ let IssueWidth = 6; // 6 micro-ops dispatched at a time.
+ let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
+ let LoadLatency = 5; // Optimistic load latency.
+ let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
+ // Determined via a mix of micro-arch details and experimentation.
+ let LoopMicroOpBufferSize = 128;
+ let PostRAScheduler = 1; // Using PostRA sched.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F,
+ [HasMTE, HasMatMulInt8, HasBF16,
+ HasPAuth, HasPAuthLR, HasCPA,
+ HasCSSC, HasMOPS, HasMOPS_GO]);
+ let FullInstRWOverlapCheck = 0;
+}
+
+def ThunderX3T110Model : SchedMachineModel {
+ let IssueWidth = 4; // 4 micro-ops dispatched at a time.
+ let MicroOpBufferSize = 70; // 70 entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
+ // Determined via a mix of micro-arch details and experimentation.
+ let LoopMicroOpBufferSize = 128; // FIXME: might be much bigger in TX3.
+ let PostRAScheduler = 1; // Using PostRA sched.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ // FIXME: Remove when all errors have been fixed.
+ let FullInstRWOverlapCheck = 0;
+}
+
+// Huawei TSV110 scheduling machine model.
+def TSV110Model : SchedMachineModel {
+ let IssueWidth = 4; // 4 micro-ops dispatched per cycle.
+ let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
+ let LoopMicroOpBufferSize = 16;
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ SVE2p1Unsupported.F,
+ PAUnsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def HIP12Model : SchedMachineModel {
+ let IssueWidth = 8; // Micro-ops dispatched at a time.
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVEB16B16, HasSVEBFSCALE, HasMTE,
+ HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def Ampere1Model : SchedMachineModel {
+ let IssueWidth = 4; // 4-way decode and dispatch
+ let MicroOpBufferSize = 192; // re-order buffer size
+ let LoadLatency = 4; // Optimistic load latency
+ let MispredictPenalty = 10; // Branch mispredict penalty
+ let LoopMicroOpBufferSize = 32; // Instruction queue size
+ let CompleteModel = 0;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ SMEUnsupported.F,
+ PAUnsupported.F,
+ [HasMTE]);
+}
+
+def Ampere1BModel : SchedMachineModel {
+ let IssueWidth = 12; // Maximum micro-ops dispatch rate.
+ let MicroOpBufferSize = 208; // micro-op re-order buffer size
+ let LoadLatency = 3; // Optimistic load latency
+ let MispredictPenalty = 10; // Branch mispredict penalty
+ let LoopMicroOpBufferSize = 32; // Instruction queue size
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ SMEUnsupported.F,
+ PAUnsupported.F,
+ [HasMOPS, HasMOPS_GO]);
+}
+
+def NeoverseN1Model : SchedMachineModel {
+ let IssueWidth = 3; // This value comes from the decode bandwidth
+ // and empirical measurements showed that this
+ // value is better.
+ let MicroOpBufferSize = 128; // NOTE: Copied from Cortex-A76.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 11; // Cycles cost of branch mispredicted.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(PAUnsupported.F,
+ SMEUnsupported.F,
+ SVEUnsupported.F,
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def NeoverseN2Model : SchedMachineModel {
+ let IssueWidth = 5; // Micro-ops dispatched at a time.
+ let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVE2p1, HasSVEB16B16, HasSVEBFSCALE, HasPAuthLR, HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def NeoverseN3Model : SchedMachineModel {
+ let IssueWidth = 5; // Micro-ops dispatched at a time.
+ let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVE2p1, HasSVEB16B16, HasSVEBFSCALE, HasPAuthLR, HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def NeoverseV1Model : SchedMachineModel {
+ let IssueWidth = 8; // This value comes from the decode bandwidth
+ // and empirical measurements showed that this
+ // value is better.
+ let MicroOpBufferSize = 256; // Micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 11; // Cycles cost of branch mispredicted.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
+ SMEUnsupported.F,
+ [HasMTE, HasCPA,
+ HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def NeoverseV2Model : SchedMachineModel {
+ let IssueWidth = 6; // This value comes from the decode bandwidth
+ // and empirical measurements showed that a
+ // lower value is better.
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasSVEBFSCALE,
+ HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def NeoverseV3Model : SchedMachineModel {
+ let IssueWidth = 10; // Expect best value to be slightly higher than V2
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V2
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasSVEBFSCALE,
+ HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def NeoverseV3AEModel : SchedMachineModel {
+ let IssueWidth = 10; // Expect best value to be slightly higher than V2
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V2
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasSVEBFSCALE,
+ HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
+
+def OlympusModel : SchedMachineModel {
+ // NOTE: Unless otherwise stated, values unspecified in the Olympus SWOG are
+ // copied from the Neoverse V2 model.
+ let IssueWidth = 10; // Maximum macro-ops dispatched per cycle.
+ let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
+ let LoadLatency = 4; // Optimistic load latency.
+ let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
+ SVE2p1Unsupported.F,
+ [HasSVE2p1, HasSVEB16B16,
+ HasSVEBFSCALE,
+ HasCPA, HasCSSC,
+ HasMatMulFP64, HasMOPS, HasMOPS_GO]);
+}
+
+def OryonModel : SchedMachineModel {
+ let IssueWidth = 14;
+ let MicroOpBufferSize = 376;
+ let LoadLatency = 4;
+ let MispredictPenalty = 13; // 13 cycles for mispredicted branch.
+ let LoopMicroOpBufferSize = 16; // Oryon-1 does not have loop micro op buffer, we enable this pseudo value to allow for aggressive unrolling based on runtime TC.
+ let PostRAScheduler = 1; // Using PostRA sched.
+ let CompleteModel = 1;
+
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ SMEUnsupported.F,
+ MTEUnsupported.F,
+ PAUnsupported.F,
+ [HasPAuth, HasCSSC, HasMOPS, HasMOPS_GO]);
+}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
index c6c945f65e8702..4349034cb3c935 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td
@@ -14,22 +14,6 @@
//
//===----------------------------------------------------------------------===//
-def NeoverseN1Model : SchedMachineModel {
- let IssueWidth = 3; // This value comes from the decode bandwidth
- // and empirical measurements showed that this
- // value is better.
- let MicroOpBufferSize = 128; // NOTE: Copied from Cortex-A76.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 11; // Cycles cost of branch mispredicted.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(PAUnsupported.F,
- SMEUnsupported.F,
- SVEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Neoverse N1.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
index 566e6bd23a6141..3bcf3010117c49 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
@@ -10,19 +10,6 @@
//
//===----------------------------------------------------------------------===//
-def NeoverseN2Model : SchedMachineModel {
- let IssueWidth = 5; // Micro-ops dispatched at a time.
- let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- SVE2p1Unsupported.F,
- [HasSVE2p1, HasSVEB16B16, HasSVEBFSCALE, HasPAuthLR, HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Neoverse N2.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
index efa88afe05139f..6efa727d0da584 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td
@@ -10,19 +10,6 @@
//
//===----------------------------------------------------------------------===//
-def NeoverseN3Model : SchedMachineModel {
- let IssueWidth = 5; // Micro-ops dispatched at a time.
- let MicroOpBufferSize = 160; // Entries in micro-op re-order buffer. NOTE: Copied from N2.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- SVE2p1Unsupported.F,
- [HasSVE2p1, HasSVEB16B16, HasSVEBFSCALE, HasPAuthLR, HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Neoverse N3.
// Instructions are first fetched and then decoded into internal Macro-OPerations
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
index 6b7f1f9b980ef4..7d8420726d35ec 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td
@@ -18,22 +18,6 @@
//
//===----------------------------------------------------------------------===//
-def NeoverseV1Model : SchedMachineModel {
- let IssueWidth = 8; // This value comes from the decode bandwidth
- // and empirical measurements showed that this
- // value is better.
- let MicroOpBufferSize = 256; // Micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 11; // Cycles cost of branch mispredicted.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVE2Unsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCPA,
- HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Neoverse V1.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
index 4875e448cc298a..5275e57e2ec7c1 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td
@@ -13,23 +13,6 @@
//
//===----------------------------------------------------------------------===//
-def NeoverseV2Model : SchedMachineModel {
- let IssueWidth = 6; // This value comes from the decode bandwidth
- // and empirical measurements showed that a
- // lower value is better.
- let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- SVE2p1Unsupported.F,
- [HasSVE2p1, HasSVEB16B16,
- HasSVEBFSCALE,
- HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Neoverse V2.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
index 084101bacea595..e7d0f7d1d4453d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td
@@ -13,21 +13,6 @@
//
//===----------------------------------------------------------------------===//
-def NeoverseV3Model : SchedMachineModel {
- let IssueWidth = 10; // Expect best value to be slightly higher than V2
- let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V2
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- SVE2p1Unsupported.F,
- [HasSVE2p1, HasSVEB16B16,
- HasSVEBFSCALE,
- HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Neoverse V3.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
index a89dc244a980b5..d4f8744f9deb88 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td
@@ -13,21 +13,6 @@
//
//===----------------------------------------------------------------------===//
-def NeoverseV3AEModel : SchedMachineModel {
- let IssueWidth = 10; // Expect best value to be slightly higher than V2
- let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer. NOTE: Copied from Neoverse-V2
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch. NOTE: Copied from N2.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- SVE2p1Unsupported.F,
- [HasSVE2p1, HasSVEB16B16,
- HasSVEBFSCALE,
- HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available on Neoverse V3AE.
// Instructions are first fetched and then decoded into internal macro-ops
diff --git a/llvm/lib/Target/AArch64/AArch64SchedOlympus.td b/llvm/lib/Target/AArch64/AArch64SchedOlympus.td
index 39cda0de137508..505c638c0782cd 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedOlympus.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedOlympus.td
@@ -13,24 +13,6 @@
//
//===----------------------------------------------------------------------===//
-def OlympusModel : SchedMachineModel {
- // NOTE: Unless otherwise stated, values unspecified in the Olympus SWOG are
- // copied from the Neoverse V2 model.
- let IssueWidth = 10; // Maximum macro-ops dispatched per cycle.
- let MicroOpBufferSize = 320; // Entries in micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 10; // Extra cycles for mispredicted branch.
- let LoopMicroOpBufferSize = 16; // NOTE: Copied from Cortex-A57.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
- SVE2p1Unsupported.F,
- [HasSVE2p1, HasSVEB16B16,
- HasSVEBFSCALE,
- HasCPA, HasCSSC,
- HasMatMulFP64, HasMOPS, HasMOPS_GO]);
-}
-
//===----------------------------------------------------------------------===//
// In the Olympus core, instructions are first fetched and decoded into
// internal macro-ops (MOps). Those MOps are then renamed and dispatched to the
diff --git a/llvm/lib/Target/AArch64/AArch64SchedOryon.td b/llvm/lib/Target/AArch64/AArch64SchedOryon.td
index e113bf45252742..e8eaabe7fb067e 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedOryon.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedOryon.td
@@ -14,22 +14,6 @@
//===----------------------------------------------------------------------===//
// Pipeline Description.
-def OryonModel : SchedMachineModel {
- let IssueWidth = 14;
- let MicroOpBufferSize = 376;
- let LoadLatency = 4;
- let MispredictPenalty = 13; // 13 cycles for mispredicted branch.
- let LoopMicroOpBufferSize = 16; // Oryon-1 does not have loop micro op buffer, we enable this pseudo value to allow for aggressive unrolling based on runtime TC.
- let PostRAScheduler = 1; // Using PostRA sched.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- SMEUnsupported.F,
- MTEUnsupported.F,
- PAUnsupported.F,
- [HasPAuth, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
let SchedModel = OryonModel in {
// Issue ports.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
index 2915b69de47efa..e3f2a65fca4412 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedTSV110.td
@@ -15,22 +15,6 @@
// The following definitions describe the simpler per-operand machine model.
// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
-// Huawei TSV110 scheduling machine model.
-def TSV110Model : SchedMachineModel {
- let IssueWidth = 4; // 4 micro-ops dispatched per cycle.
- let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
- let LoopMicroOpBufferSize = 16;
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 14; // Fetch + Decode/Rename/Dispatch + Branch
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- SVE2p1Unsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
-}
-
// Define each kind of processor resource and number available on the TSV110,
// which has 8 pipelines, each with its own queue where micro-ops wait for
// their operands and issue out-of-order to one of eight execution pipelines.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
index e9f2d7618e1997..8ee70f76d730b6 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX.td
@@ -16,23 +16,6 @@
// The following definitions describe the simpler per-operand machine model.
// This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
-// Cavium ThunderX T8X scheduling machine model.
-def ThunderXT8XModel : SchedMachineModel {
- let IssueWidth = 2; // 2 micro-ops dispatched per cycle.
- let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
- let LoadLatency = 3; // Optimistic load latency.
- let MispredictPenalty = 8; // Branch mispredict penalty.
- let PostRAScheduler = 1; // Use PostRA scheduler.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
-}
-
// Modeling each pipeline with BufferSize == 0 since T8X is in-order.
def THXT8XUnitALU : ProcResource<2> { let BufferSize = 0; } // Int ALU
def THXT8XUnitMAC : ProcResource<1> { let BufferSize = 0; } // Int MAC
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
index 5d2adb938d6874..20daad8d7ef675 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td
@@ -15,24 +15,6 @@
//===----------------------------------------------------------------------===//
// 2. Pipeline Description.
-def ThunderX2T99Model : SchedMachineModel {
- let IssueWidth = 4; // 4 micro-ops dispatched at a time.
- let MicroOpBufferSize = 180; // 180 entries in micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
- // Determined via a mix of micro-arch details and experimentation.
- let LoopMicroOpBufferSize = 128;
- let PostRAScheduler = 1; // Using PostRA sched.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
-}
-
let SchedModel = ThunderX2T99Model in {
// Define the issue ports.
diff --git a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
index 80f37d306a48aa..35f45caf3e1a5b 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td
@@ -14,24 +14,6 @@
//===----------------------------------------------------------------------===//
// Pipeline Description.
-def ThunderX3T110Model : SchedMachineModel {
- let IssueWidth = 4; // 4 micro-ops dispatched at a time.
- let MicroOpBufferSize = 70; // 70 entries in micro-op re-order buffer.
- let LoadLatency = 4; // Optimistic load latency.
- let MispredictPenalty = 12; // Extra cycles for mispredicted branch.
- // Determined via a mix of micro-arch details and experimentation.
- let LoopMicroOpBufferSize = 128; // FIXME: might be much bigger in TX3.
- let PostRAScheduler = 1; // Using PostRA sched.
- let CompleteModel = 1;
-
- list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
- PAUnsupported.F,
- SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
- // FIXME: Remove when all errors have been fixed.
- let FullInstRWOverlapCheck = 0;
-}
-
let SchedModel = ThunderX3T110Model in {
// Issue ports.
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