[llvm-branch-commits] [llvm] [AMDGPU][NFC] Extract SIAtomicAddrSpace and fence MMRA parsing from SIMemoryLegalizer (PR #231854)

[Pierre van Houtryve via llvm-branch-commits]

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@@ -113,6 +118,46 @@ bool isReallyAClobber(const Value *Ptr, MemoryDef *Def, AAResults *AA);
 bool isClobberedInFunction(const LoadInst *Load, MemorySSA *MSSA,
                            AAResults *AA);
 
+/// The distinct address spaces supported by the AMDGPU target for
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Pierre-vh wrote:

I am not sure that description is still accurate. e.g. SCRATCH doesn't support atomics unless we have GAS
Also this describes itself as being the AS that support atomic operations, but then there is the ATOMIC value that is different from ALL?

I think this is more like a "memory model address space mask" ? It's a mask of address space that we care about in the memory model. "SIMemoryModelASMask" doesn't roll of the tongue nicely though :D

https://github.com/llvm/llvm-project/pull/231854