[llvm-branch-commits] [clang] [llvm] [AArch64][llvm] Add support for FEAT_FPv2 (PR #231436)
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llvm-branch-commits at lists.llvm.org
Tue Oct 13 03:02:49 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Martin Wehking (MartinWehking)
<details>
<summary>Changes</summary>
Add support for FEAT_FPv2 (IEEE 754-2019 floating-point standard alignment) instructions.
---
Patch is 82.78 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/231436.diff
50 Files Affected:
- (modified) clang/test/Driver/aarch64-vfat.c (+4)
- (modified) clang/test/Driver/print-supported-extensions-aarch64.c (+1)
- (modified) llvm/lib/Target/AArch64/AArch64Features.td (+4)
- (modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (+46-8)
- (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+13)
- (modified) llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td (+26)
- (modified) llvm/lib/Target/AArch64/AArch64SchedA53.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedA57.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedA64FX.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedAmpere1.td (+1-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedCyclone.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedExynosM3.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedExynosM4.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedExynosM5.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedFalkor.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedHIP12.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedKryo.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseN1.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseN3.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV1.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV2.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV3.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedNeoverseV3AE.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedOlympus.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedOryon.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedTSV110.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX2T99.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td (+2-1)
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+1)
- (modified) llvm/lib/Target/AArch64/SVEInstrFormats.td (+100)
- (added) llvm/test/MC/AArch64/FPv2/minmax-diagnostics.s (+31)
- (added) llvm/test/MC/AArch64/FPv2/minmax.s (+247)
- (added) llvm/test/MC/AArch64/FPv2/total-compare.s (+49)
- (modified) llvm/test/MC/AArch64/SVE2p3/directive-arch-negative.s (+6)
- (added) llvm/test/MC/AArch64/SVE2p3/directive-arch.s (+5)
- (modified) llvm/test/MC/AArch64/SVE2p3/directive-arch_extension-negative.s (+7)
- (added) llvm/test/MC/AArch64/SVE2p3/directive-arch_extension.s (+6)
- (added) llvm/test/MC/AArch64/SVE2p3/fcmtl-diagnostics.s (+64)
- (added) llvm/test/MC/AArch64/SVE2p3/minmax-diagnostics.s (+64)
- (added) llvm/test/MC/AArch64/SVE2p3/minmax.s (+514)
- (added) llvm/test/MC/AArch64/SVE2p3/total-compare.s (+51)
- (modified) llvm/test/MC/AArch64/basic-a64-diagnostics.s (+37)
- (modified) llvm/test/MC/AArch64/directive-arch-negative.s (+6)
- (modified) llvm/test/MC/AArch64/directive-arch.s (+4)
- (modified) llvm/test/MC/AArch64/directive-arch_extension-negative.s (+6)
- (modified) llvm/test/MC/AArch64/directive-arch_extension.s (+4)
- (modified) llvm/unittests/TargetParser/TargetParserTest.cpp (+6-1)
``````````diff
diff --git a/clang/test/Driver/aarch64-vfat.c b/clang/test/Driver/aarch64-vfat.c
index 64aabd3cc8c3d..d61db5bca6d7d 100644
--- a/clang/test/Driver/aarch64-vfat.c
+++ b/clang/test/Driver/aarch64-vfat.c
@@ -21,3 +21,7 @@
// RUN: %clang -target aarch64 -march=armv9.8a+sme-f16f8f16 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-SME-F16F8F16 %s
// RUN: %clang -target aarch64 -march=armv9.8-a+sme-f16f8f16 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-SME-F16F8F16 %s
// VFAT-SME-F16F8F16: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+sme-f16f8f16"
+
+// RUN: %clang -target aarch64 -march=armv9.8a+fpv2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-FPV2 %s
+// RUN: %clang -target aarch64 -march=armv9.8-a+fpv2 -### -c %s 2>&1 | FileCheck -check-prefix=VFAT-FPV2 %s
+// VFAT-FPV2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "generic" "-target-feature" "+v9.8a"{{.*}} "-target-feature" "+fpv2"
diff --git a/clang/test/Driver/print-supported-extensions-aarch64.c b/clang/test/Driver/print-supported-extensions-aarch64.c
index 55465def571bb..6ebcc018ac5f8 100644
--- a/clang/test/Driver/print-supported-extensions-aarch64.c
+++ b/clang/test/Driver/print-supported-extensions-aarch64.c
@@ -35,6 +35,7 @@
// CHECK-NEXT: fp8dot4 FEAT_FP8DOT4 Enable FP8 4-way dot instructions
// CHECK-NEXT: fp8fma FEAT_FP8FMA Enable Armv9.5-A FP8 multiply-add instructions
// CHECK-NEXT: fprcvt FEAT_FPRCVT Enable Armv9.6-A base convert instructions for SIMD&FP scalar register operands of different input and output sizes
+// CHECK-NEXT: fpv2 FEAT_FPv2 Enable IEEE 754-2019 floating-point standard alignment instructions
// CHECK-NEXT: fp16 FEAT_FP16 Enable half-precision floating-point data processing
// CHECK-NEXT: gcie FEAT_GCIE Enable GICv5 (Generic Interrupt Controller) CPU Interface Extension
// CHECK-NEXT: gcs FEAT_GCS Enable Armv9.4-A Guarded Call Stack Extension
diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td
index a9e5b4f8f0a58..b4c918ffa80bb 100644
--- a/llvm/lib/Target/AArch64/AArch64Features.td
+++ b/llvm/lib/Target/AArch64/AArch64Features.td
@@ -650,6 +650,10 @@ def FeatureS1POE2: ExtensionWithMArch<"poe2", "POE2", "FEAT_S1POE2",
def FeatureTEV: ExtensionWithMArch<"tev", "TEV", "FEAT_TEV",
"Enable TIndex Exception-like Vector instructions">;
+def FeatureFPv2 : ExtensionWithMArch<"fpv2", "FPv2", "FEAT_FPv2",
+ "Enable IEEE 754-2019 floating-point standard alignment instructions",
+ [FeatureFullFP16]>;
+
def FeatureSMEF16F8F16 : ExtensionWithMArch<"sme-f16f8f16", "SME_F16F8F16", "FEAT_SME_F16F8F16",
"Enable SME half-precision and FP8 sum-of-products accumulating to half-precision instructions",
[FeatureSME2, FeatureFP8]>;
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 3df66fa00fc28..297023ce9449f 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -5980,6 +5980,20 @@ multiclass TwoOperandFPData<bits<4> opcode, string asm,
}
}
+multiclass TwoOperandFPDataFPv2<bits<4> opcode, string asm> {
+ def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm, []> {
+ let Inst{23-22} = 0b11; // 16-bit size flag
+ }
+
+ def Srr : BaseTwoOperandFPData<opcode, FPR32, asm, []> {
+ let Inst{23-22} = 0b00; // 32-bit size flag
+ }
+
+ def Drr : BaseTwoOperandFPData<opcode, FPR64, asm, []> {
+ let Inst{23-22} = 0b01; // 64-bit size flag
+ }
+}
+
multiclass TwoOperandFPDataNeg<bits<4> opcode, string asm,
SDPatternOperator node> {
def Hrr : BaseTwoOperandFPData<opcode, FPR16, asm,
@@ -6127,9 +6141,9 @@ class BaseOneOperandFPComparison<bit signalAllNans,
let PostEncoderMethod = "fixOneOperandFPComparison";
}
-let mayLoad = 0, mayStore = 0, hasSideEffects = 0, mayRaiseFPException = 1, Uses = [FPCR] in
-class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
- string asm, list<dag> pat>
+let mayLoad = 0, mayStore = 0, hasSideEffects = 0, Uses = [FPCR] in
+class BaseTwoOperandFPComparison<bit signalAllNans, bit totalOrder, bit magnitude,
+ RegisterClass regtype, string asm, list<dag> pat>
: I<(outs), (ins regtype:$Rn, regtype:$Rm), asm, "\t$Rn, $Rm", "", pat>,
Sched<[WriteFCmp]> {
bits<5> Rm;
@@ -6137,16 +6151,20 @@ class BaseTwoOperandFPComparison<bit signalAllNans, RegisterClass regtype,
let Inst{31-24} = 0b00011110;
let Inst{21} = 1;
let Inst{20-16} = Rm;
- let Inst{15-10} = 0b001000;
+ let Inst{15} = totalOrder;
+ let Inst{14-10} = 0b01000;
let Inst{9-5} = Rn;
let Inst{4} = signalAllNans;
- let Inst{3-0} = 0b0000;
+ let Inst{3} = magnitude;
+ let Inst{2-0} = 0b000;
+
+ let mayRaiseFPException = !not(totalOrder);
}
multiclass FPComparison<bit signalAllNans, string asm,
SDPatternOperator OpNode = null_frag> {
let Defs = [NZCV] in {
- def Hrr : BaseTwoOperandFPComparison<signalAllNans, FPR16, asm,
+ def Hrr : BaseTwoOperandFPComparison<signalAllNans, 0b0, 0b0, FPR16, asm,
[(set NZCV, (OpNode (f16 FPR16:$Rn), (f16 FPR16:$Rm)))]> {
let Inst{23-22} = 0b11;
let Predicates = [HasFullFP16];
@@ -6158,7 +6176,7 @@ multiclass FPComparison<bit signalAllNans, string asm,
let Predicates = [HasFullFP16];
}
- def Srr : BaseTwoOperandFPComparison<signalAllNans, FPR32, asm,
+ def Srr : BaseTwoOperandFPComparison<signalAllNans, 0b0, 0b0, FPR32, asm,
[(set NZCV, (OpNode FPR32:$Rn, (f32 FPR32:$Rm)))]> {
let Inst{23-22} = 0b00;
}
@@ -6168,7 +6186,7 @@ multiclass FPComparison<bit signalAllNans, string asm,
let Inst{23-22} = 0b00;
}
- def Drr : BaseTwoOperandFPComparison<signalAllNans, FPR64, asm,
+ def Drr : BaseTwoOperandFPComparison<signalAllNans, 0b0, 0b0, FPR64, asm,
[(set NZCV, (OpNode FPR64:$Rn, (f64 FPR64:$Rm)))]> {
let Inst{23-22} = 0b01;
}
@@ -6180,6 +6198,26 @@ multiclass FPComparison<bit signalAllNans, string asm,
} // Defs = [NZCV]
}
+multiclass FPTotalOrderComparison<bit magnitude, string asm> {
+ let Defs = [NZCV] in {
+ let Predicates = [HasFullFP16, HasFPv2] in {
+ def Hrr : BaseTwoOperandFPComparison<0b0, 0b1, magnitude, FPR16, asm, []> {
+ let Inst{23-22} = 0b11;
+ }
+ }
+
+ let Predicates = [HasFPv2] in {
+ def Srr : BaseTwoOperandFPComparison<0b0, 0b1, magnitude, FPR32, asm, []> {
+ let Inst{23-22} = 0b00;
+ }
+
+ def Drr : BaseTwoOperandFPComparison<0b0, 0b1, magnitude, FPR64, asm, []> {
+ let Inst{23-22} = 0b01;
+ }
+ }
+ }
+}
+
//---
// Floating point conditional comparisons
//---
diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0d1152dadfd4b..6c0c152495f42 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -247,6 +247,8 @@ def HasSVE_PERM256 : Predicate<"Subtarget->hasSVE_PERM256()">,
AssemblerPredicateWithAll<(all_of FeatureSVE_PERM256), "sve-perm256">;
def HasSVE_LRCPC : Predicate<"Subtarget->isSVEAvailable() && Subtarget->hasSVE_LRCPC()">,
AssemblerPredicateWithAll<(all_of FeatureSVE_LRCPC), "sve-lrcpc">;
+def HasFPv2 : Predicate<"Subtarget->hasFPv2()">,
+ AssemblerPredicateWithAll<(all_of FeatureFPv2), "fpv2">;
// A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
// they should be enabled if either has been specified.
@@ -5966,6 +5968,15 @@ defm FNMUL : TwoOperandFPDataNeg<0b1000, "fnmul", any_fmul>;
}
defm FSUB : TwoOperandFPData<0b0011, "fsub", any_fsub>;
+let Predicates = [HasFPv2] in {
+defm FMAXINM : TwoOperandFPDataFPv2<0b1010, "fmaxinm">;
+defm FMAXMG : TwoOperandFPDataFPv2<0b1100, "fmaxmg">;
+defm FMAXMGINM : TwoOperandFPDataFPv2<0b1110, "fmaxmginm">;
+defm FMININM : TwoOperandFPDataFPv2<0b1011, "fmininm">;
+defm FMINMG : TwoOperandFPDataFPv2<0b1101, "fminmg">;
+defm FMINMGINM : TwoOperandFPDataFPv2<0b1111, "fminmginm">;
+}
+
multiclass FMULScalarFromIndexedLane0Patterns<string inst,
string inst_f16_suffix,
string inst_f32_suffix,
@@ -6080,6 +6091,8 @@ def : Pat<(f64 (fma (fneg FPR64:$Rn), FPR64:$Rm, (fneg FPR64:$Ra))),
defm FCMPE : FPComparison<1, "fcmpe", AArch64strict_fcmpe>;
defm FCMP : FPComparison<0, "fcmp", AArch64any_fcmp>;
+defm FCMTL : FPTotalOrderComparison<0, "fcmtl">;
+defm FCMTLMG : FPTotalOrderComparison<1, "fcmtlmg">;
//===----------------------------------------------------------------------===//
// Floating point conditional comparison instructions.
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index b407d58ec1dd2..bffdcab44f123 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -5327,6 +5327,32 @@ let Predicates = [HasSVE, HasCPA] in {
def MLA_CPA : sve_int_mla_cpa<"mlapt">;
}
+//===----------------------------------------------------------------------===//
+// (FEAT_SVE2p3 || FEAT_SME2p3) && FEAT_FPv2 Instructions
+//===----------------------------------------------------------------------===//
+let Predicates = [HasSVE2p3_or_SME2p3, HasFPv2], hasNoSchedulingInfo = 1 in {
+ defm FCMTL_PZZ : sve_fp_3op_u_pd_totalcomp<0b100, "fcmtl">;
+ defm FCMTLMG_PZZ : sve_fp_3op_u_pd_totalcomp<0b101, "fcmtlmg">;
+} // End HasSVE_or_SME
+
+
+let Predicates = [HasSVE2p3_or_SME2p3, HasFPv2], hasNoSchedulingInfo = 1 in {
+ defm FMAXINM_ZPmZZ : sve_fp_2op_p_zds_minmax<0b0, 0b00, "fmaxinm">;
+ defm FMININM_ZPmZZ : sve_fp_2op_p_zds_minmax<0b0, 0b01, "fmininm">;
+ defm FMAXMGINM_ZPmZZ : sve_fp_2op_p_zds_minmax<0b1, 0b00, "fmaxmginm">;
+ defm FMINMGINM_ZPmZZ : sve_fp_2op_p_zds_minmax<0b1, 0b01, "fminmginm">;
+ defm FMAXMG_ZPmZZ : sve_fp_2op_p_zds_minmax<0b1, 0b10, "fmaxmg">;
+ defm FMINMG_ZPmZZ : sve_fp_2op_p_zds_minmax<0b1, 0b11, "fminmg">;
+
+ defm FMAXINMV_VPZ : sve_fp_fast_red_minmax<0b00, 0b0, "fmaxinmv">;
+ defm FMININMV_VPZ : sve_fp_fast_red_minmax<0b01, 0b0, "fmininmv">;
+ defm FMAXMGINMV_VPZ : sve_fp_fast_red_minmax<0b00, 0b1, "fmaxmginmv">;
+ defm FMINMGINMV_VPZ : sve_fp_fast_red_minmax<0b01, 0b1, "fminmginmv">;
+ defm FMAXMGV_VPZ : sve_fp_fast_red_minmax<0b10, 0b1, "fmaxmgv">;
+ defm FMINMGV_VPZ : sve_fp_fast_red_minmax<0b11, 0b1, "fminmgv">;
+} // End HasSVE_or_SME
+
+
//===----------------------------------------------------------------------===//
// Load-Acquire/Store-Release octaword (FEAT_SVE_LRCPC)
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA53.td b/llvm/lib/Target/AArch64/AArch64SchedA53.td
index 291f78582d94a..dbc1edc06da19 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA53.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA53.td
@@ -29,7 +29,8 @@ def CortexA53Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA57.td b/llvm/lib/Target/AArch64/AArch64SchedA57.td
index 9260379fb5b27..e4a473ce2a80a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA57.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA57.td
@@ -34,7 +34,8 @@ def CortexA57Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
index 8ecfa612af63e..7f4ed347b89ed 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedA64FX.td
@@ -23,7 +23,8 @@ def A64FXModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F, SVEUnsupported.F,
[HasMTE, HasMatMulInt8, HasBF16,
HasPAuth, HasPAuthLR, HasCPA,
- HasCSSC, HasMOPS, HasMOPS_GO]);
+ HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
index 269f4ec5e5fb1..d013bc559a305 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1.td
@@ -27,7 +27,7 @@ def Ampere1Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
SMEUnsupported.F,
PAUnsupported.F,
- [HasMTE]);
+ [HasMTE, HasFPv2]);
}
let SchedModel = Ampere1Model in {
diff --git a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
index d77c48126af39..347f0e2444c40 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedAmpere1B.td
@@ -27,7 +27,8 @@ def Ampere1BModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
SMEUnsupported.F,
PAUnsupported.F,
- [HasMOPS, HasMOPS_GO]);
+ [HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
let SchedModel = Ampere1BModel in {
diff --git a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
index 7929ede8d099b..4f5616917742d 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedCyclone.td
@@ -21,7 +21,8 @@ def CycloneModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
index 3644617928dc2..12eaf12e6d28c 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM3.td
@@ -27,7 +27,8 @@ def ExynosM3Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
index e72d91101582a..5c8ea5788442a 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM4.td
@@ -27,7 +27,8 @@ def ExynosM4Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
index 35a787bdd8fc7..ef8a1afa50bf8 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedExynosM5.td
@@ -27,7 +27,8 @@ def ExynosM5Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
index 778a2621618a7..9d430da4c1c57 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedFalkor.td
@@ -26,7 +26,8 @@ def FalkorModel : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
PAUnsupported.F,
SMEUnsupported.F,
- [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO]);
+ [HasMTE, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
// FIXME: Remove when all errors have been fixed.
let FullInstRWOverlapCheck = 0;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
index 06a139bebcbe8..ade92141d0621 100644
--- a/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
+++ b/llvm/lib/Target/AArch64/AArch64SchedHIP12.td
@@ -22,7 +22,8 @@ def HIP12Model : SchedMachineModel {
list<Predicate> UnsupportedFeatures = !listconcat(SMEUnsupported.F,
SVE2p1Unsupported.F,
[HasSVEB16B16, HasSVEBFSCALE, HasMTE,
- HasCPA, HasCSSC, HasMOPS, HasMOPS_GO]);
+ HasCPA, HasCSSC, HasMOPS, HasMOPS_GO,
+ HasFPv2]);
}
let SchedModel = HIP12Model in {
diff --git a/llvm/lib/Target/AArc...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/231436
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