[llvm-branch-commits] [llvm] 7909311 - [Mips] Remove experimental warning bits in a few places (#223230)

[Tobias Hieta via llvm-branch-commits]

Author: Brad Smith
Date: 2026-10-13T09:53:57+02:00
New Revision: 7909311aa6f3333ffff7b1d43ce057a89071d27c

URL: https://github.com/llvm/llvm-project/commit/7909311aa6f3333ffff7b1d43ce057a89071d27c
DIFF: https://github.com/llvm/llvm-project/commit/7909311aa6f3333ffff7b1d43ce057a89071d27c.diff

LOG: [Mips] Remove experimental warning bits in a few places (#223230)

- Remove the warning message "warning: MIPS-I support is experimental" from
  MipsSubtarget.cpp. The warning can interfere with build systems that do not
  expect diagnostic output on stderr.
- Remove experimental / highly experimental from a few MIPS processors.
  MIPS I is on track and the rest I wouldn't consider experimental anymore.

(cherry picked from commit 73641283fc038d819b5a0d3e5fd1315d501ff9e1)

Added: 
    

Modified: 
    llvm/lib/Target/Mips/Mips.td
    llvm/lib/Target/Mips/MipsSubtarget.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/Mips/Mips.td b/llvm/lib/Target/Mips/Mips.td
index 41d38f10da816..fd987789ea68f 100644
--- a/llvm/lib/Target/Mips/Mips.td
+++ b/llvm/lib/Target/Mips/Mips.td
@@ -81,9 +81,9 @@ def FeatureNoOddSPReg  : SubtargetFeature<"nooddspreg", "UseOddSPReg", "false",
 def FeatureVFPU        : SubtargetFeature<"vfpu", "HasVFPU",
                                 "true", "Enable vector FPU instructions">;
 def FeatureMips1       : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1",
-                                "Mips I ISA Support [highly experimental]">;
+                                "Mips I ISA Support">;
 def FeatureMips2       : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2",
-                                "Mips II ISA Support [highly experimental]",
+                                "Mips II ISA Support",
                                 [FeatureMips1]>;
 def FeatureMips3_32    : SubtargetFeature<"mips3_32", "HasMips3_32", "true",
                                 "Subset of MIPS-III that is also in MIPS32 "
@@ -92,7 +92,7 @@ def FeatureMips3_32r2  : SubtargetFeature<"mips3_32r2", "HasMips3_32r2", "true",
                                 "Subset of MIPS-III that is also in MIPS32r2 "
                                 "[highly experimental]">;
 def FeatureMips3       : SubtargetFeature<"mips3", "MipsArchVersion", "Mips3",
-                                "MIPS III ISA Support [highly experimental]",
+                                "MIPS III ISA Support",
                                 [FeatureMips2, FeatureMips3_32,
                                  FeatureMips3_32r2, FeatureGP64Bit,
                                  FeatureFP64Bit]>;

diff  --git a/llvm/lib/Target/Mips/MipsSubtarget.cpp b/llvm/lib/Target/Mips/MipsSubtarget.cpp
index 287a4cbbf5af4..14d507848f2f6 100644
--- a/llvm/lib/Target/Mips/MipsSubtarget.cpp
+++ b/llvm/lib/Target/Mips/MipsSubtarget.cpp
@@ -74,7 +74,6 @@ bool MipsSubtarget::MSAWarningPrinted = false;
 bool MipsSubtarget::VirtWarningPrinted = false;
 bool MipsSubtarget::CRCWarningPrinted = false;
 bool MipsSubtarget::GINVWarningPrinted = false;
-bool MipsSubtarget::MIPS1WarningPrinted = false;
 
 void MipsSubtarget::anchor() {}
 
@@ -104,12 +103,6 @@ MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
   if (MipsArchVersion == MipsDefault)
     MipsArchVersion = Mips32;
 
-  // MIPS-I has not been tested.
-  if (MipsArchVersion == Mips1 && !MIPS1WarningPrinted) {
-    errs() << "warning: MIPS-I support is experimental\n";
-    MIPS1WarningPrinted = true;
-  }
-
   // Don't even attempt to generate code for MIPS-V. It has not
   // been tested and currently exists for the integrated assembler only.
   if (MipsArchVersion == Mips5)