[llvm-branch-commits] [llvm] [AMDGPU] Let llvm.amdgcn.raw.ptr.buffer.load.format also return any type (PR #231308)
Krzysztof Drewniak via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Mon Oct 12 15:54:35 PDT 2026
https://github.com/krzysz00 updated https://github.com/llvm/llvm-project/pull/231308
>From bf37f648d12ad9b1ad271ccf1958f202a5fc2c14 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Fri, 9 Oct 2026 16:20:14 +0000
Subject: [PATCH 1/2] [AMDGPU] Let llvm.amdgcn.raw.ptr.buffer.load.format also
return any type
While llvm.amdgcn.raw.buffer.load.format can handle any type, and so
can llvm.amdgcn.struct.ptr.buffer.load.format,
llvm.amdgcn.raw.ptr.buffer.format is restricted to floats for some
reason, probably somebody forgetting to loosen it.
This commit fixes the issue so integer-format typed loads can migrate
off of the non-pointer intrinsic.
AI disclosure: Claude noticed it when I asked it draft up a stronger
deprecation for the non-ptr intrinsics, and I wrote the commit message.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
---
llvm/include/llvm/IR/IntrinsicsAMDGPU.td | 2 +-
...dgcn.raw.ptr.buffer.load.format.integer.ll | 73 +++++++++++++++++--
2 files changed, 69 insertions(+), 6 deletions(-)
diff --git a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
index d2671c67b3414..dfefee58acc72 100644
--- a/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
+++ b/llvm/include/llvm/IR/IntrinsicsAMDGPU.td
@@ -1679,7 +1679,7 @@ class AMDGPURawPtrBufferLoad<LLVMType data_ty = llvm_any_ty> : DefaultAttrsIntri
[IntrArgMemOnly, IntrReadMem, ReadOnly<ArgIndex<0>>, NoCapture<ArgIndex<0>>,
ImmArg<ArgIndex<3>>], "", [SDNPMemOperand]>,
AMDGPURsrcIntrinsic<0>;
-def int_amdgcn_raw_ptr_buffer_load_format : AMDGPURawPtrBufferLoad<llvm_anyfloat_ty>;
+def int_amdgcn_raw_ptr_buffer_load_format : AMDGPURawPtrBufferLoad;
def int_amdgcn_raw_ptr_buffer_load : AMDGPURawPtrBufferLoad;
class AMDGPURawPtrAtomicBufferLoad<LLVMType data_ty = llvm_any_ty> : Intrinsic <
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
index 9e925ded23409..81ac68064c8a9 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
@@ -1,10 +1,35 @@
-; RUN: not llc -global-isel=0 -mtriple=amdgpu9.00-amd-mesa3d -filetype=null < %s 2>&1 | FileCheck %s
-; RUN: not llc -global-isel=1 -mtriple=amdgpu9.00-amd-mesa3d -filetype=null < %s 2>&1 | FileCheck %s
-
-; Only the first offending declaration is reported, so do not pin the type.
-; CHECK: error: intrinsic return type (overload type 0) expected any fp or fp vector
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -o - %s | FileCheck -check-prefix=SDAG %s
+; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-mesa3d -o - %s | FileCheck -check-prefix=GISEL %s
define amdgpu_ps <4 x float> @raw_ptr_buffer_load_format_v4i32(ptr addrspace(8) inreg %rsrc) {
+; SDAG-LABEL: raw_ptr_buffer_load_format_v4i32:
+; SDAG: ; %bb.0: ; %main_body
+; SDAG-NEXT: s_mov_b32 s7, s5
+; SDAG-NEXT: s_mov_b32 s6, s4
+; SDAG-NEXT: s_mov_b32 s5, s3
+; SDAG-NEXT: s_mov_b32 s4, s2
+; SDAG-NEXT: buffer_load_format_xyzw v[0:3], off, s[4:7], 0
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: ; return to shader part epilog
+;
+; GISEL-LABEL: raw_ptr_buffer_load_format_v4i32:
+; GISEL: ; %bb.0: ; %main_body
+; GISEL-NEXT: s_mov_b32 s0, s2
+; GISEL-NEXT: s_mov_b32 s1, s3
+; GISEL-NEXT: s_mov_b32 s2, s4
+; GISEL-NEXT: s_mov_b32 s3, s5
+; GISEL-NEXT: buffer_load_format_xyzw v[0:3], off, s[0:3], 0
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: v_readfirstlane_b32 s0, v0
+; GISEL-NEXT: v_readfirstlane_b32 s1, v1
+; GISEL-NEXT: v_readfirstlane_b32 s2, v2
+; GISEL-NEXT: v_readfirstlane_b32 s3, v3
+; GISEL-NEXT: v_mov_b32_e32 v0, s0
+; GISEL-NEXT: v_mov_b32_e32 v1, s1
+; GISEL-NEXT: v_mov_b32_e32 v2, s2
+; GISEL-NEXT: v_mov_b32_e32 v3, s3
+; GISEL-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.format.v4i32(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
%fdata = bitcast <4 x i32> %data to <4 x float>
@@ -12,6 +37,25 @@ main_body:
}
define amdgpu_ps <4 x float> @raw_ptr_buffer_load_format_ofs_v4i32(ptr addrspace(8) inreg %rsrc, i32 %voffset) {
+; SDAG-LABEL: raw_ptr_buffer_load_format_ofs_v4i32:
+; SDAG: ; %bb.0: ; %main_body
+; SDAG-NEXT: s_mov_b32 s7, s5
+; SDAG-NEXT: s_mov_b32 s6, s4
+; SDAG-NEXT: s_mov_b32 s5, s3
+; SDAG-NEXT: s_mov_b32 s4, s2
+; SDAG-NEXT: buffer_load_format_xyzw v[0:3], v0, s[4:7], 0 offen
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: ; return to shader part epilog
+;
+; GISEL-LABEL: raw_ptr_buffer_load_format_ofs_v4i32:
+; GISEL: ; %bb.0: ; %main_body
+; GISEL-NEXT: s_mov_b32 s0, s2
+; GISEL-NEXT: s_mov_b32 s1, s3
+; GISEL-NEXT: s_mov_b32 s2, s4
+; GISEL-NEXT: s_mov_b32 s3, s5
+; GISEL-NEXT: buffer_load_format_xyzw v[0:3], v0, s[0:3], 0 offen
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: ; return to shader part epilog
main_body:
%data = call <4 x i32> @llvm.amdgcn.raw.ptr.buffer.load.format.v4i32(ptr addrspace(8) %rsrc, i32 %voffset, i32 0, i32 0)
%fdata = bitcast <4 x i32> %data to <4 x float>
@@ -19,6 +63,25 @@ main_body:
}
define amdgpu_ps float @raw_ptr_buffer_load_format_i32(ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) {
+; SDAG-LABEL: raw_ptr_buffer_load_format_i32:
+; SDAG: ; %bb.0: ; %main_body
+; SDAG-NEXT: s_mov_b32 s11, s5
+; SDAG-NEXT: s_mov_b32 s10, s4
+; SDAG-NEXT: s_mov_b32 s9, s3
+; SDAG-NEXT: s_mov_b32 s8, s2
+; SDAG-NEXT: buffer_load_format_x v0, v0, s[8:11], s6 offen
+; SDAG-NEXT: s_waitcnt vmcnt(0)
+; SDAG-NEXT: ; return to shader part epilog
+;
+; GISEL-LABEL: raw_ptr_buffer_load_format_i32:
+; GISEL: ; %bb.0: ; %main_body
+; GISEL-NEXT: s_mov_b32 s0, s2
+; GISEL-NEXT: s_mov_b32 s1, s3
+; GISEL-NEXT: s_mov_b32 s2, s4
+; GISEL-NEXT: s_mov_b32 s3, s5
+; GISEL-NEXT: buffer_load_format_x v0, v0, s[0:3], s6 offen
+; GISEL-NEXT: s_waitcnt vmcnt(0)
+; GISEL-NEXT: ; return to shader part epilog
main_body:
%data = call i32 @llvm.amdgcn.raw.ptr.buffer.load.format.i32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 0)
%fdata = bitcast i32 %data to float
>From 3e9f499b8d8ff632f613555db31b251585148263 Mon Sep 17 00:00:00 2001
From: Krzysztof Drewniak <Krzysztof.Drewniak at amd.com>
Date: Mon, 12 Oct 2026 22:35:33 +0000
Subject: [PATCH 2/2] [AI fixup] Test nits
Address review nits from PR #231308:
- Use `< %s` instead of `-o - %s`.
- Spell `-global-isel=0` on the SDAG run line and `-global-isel=1` on
the GlobalISel one, rather than leaving the SDAG line implicit.
Re-running utils/update_llc_test_checks.py produces no check changes,
so this is a run-line-only cleanup.
Co-Authored-By: Claude Opus 5 (1M context) <noreply at anthropic.com>
---
.../AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
index 81ac68064c8a9..34d2e47804c58 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.format.integer.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
-; RUN: llc -mtriple=amdgpu9.00-amd-mesa3d -o - %s | FileCheck -check-prefix=SDAG %s
-; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-mesa3d -o - %s | FileCheck -check-prefix=GISEL %s
+; RUN: llc -global-isel=0 -mtriple=amdgpu9.00-amd-mesa3d < %s | FileCheck -check-prefix=SDAG %s
+; RUN: llc -global-isel=1 -mtriple=amdgpu9.00-amd-mesa3d < %s | FileCheck -check-prefix=GISEL %s
define amdgpu_ps <4 x float> @raw_ptr_buffer_load_format_v4i32(ptr addrspace(8) inreg %rsrc) {
; SDAG-LABEL: raw_ptr_buffer_load_format_v4i32:
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