[llvm-branch-commits] [llvm] [X86] keep upper-16-bit f32 extractions in XMM for f16/v8i16 (PR #230698)

[Emilio Cota via llvm-branch-commits]

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@@ -52344,6 +52360,22 @@ static SDValue combineVectorInsert(SDNode *N, SelectionDAG &DAG,
       return SDValue(N, 0);
   }
 
+  if (Opcode == X86ISD::PINSRW) {
+    using namespace SDPatternMatch;
+    SDValue FpOp;
+    if (sd_match(Scl, m_OneUse(m_Srl(m_OneUse(m_BitCast(m_Value(
+                                         FpOp, m_SpecificVT(MVT::f32)))),
+                                     m_SpecificInt(16)))) &&
+        !ISD::isNormalLoad(FpOp.getNode())) {
+      SDLoc DL(N);
+      SDValue SrcVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, MVT::v4f32, FpOp);
+      SDValue Extract = DAG.getNode(X86ISD::PEXTRW, DL, MVT::i32,
+                                    DAG.getBitcast(MVT::v8i16, SrcVec),
+                                    DAG.getTargetConstant(1, DL, MVT::i8));
+      return DAG.getNode(X86ISD::PINSRW, DL, VT, Vec, Extract, Idx);
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cota wrote:

Done both, thanks

https://github.com/llvm/llvm-project/pull/230698