[llvm-branch-commits] [llvm] AMDGPU: Use TargetSubtarget.td in TargetDef tablegen tests (PR #231018)

[Matt Arsenault via llvm-branch-commits]

https://github.com/arsenm updated https://github.com/llvm/llvm-project/pull/231018

>From a498980906cb859958372e0530f0363f2be4e680 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Sun, 11 Oct 2026 02:33:30 -0700
Subject: [PATCH] AMDGPU: Use TargetSubtarget.td in TargetDef tablegen tests

The -gen-amdgpu-target-def tests only need the subtarget and processor
classes. Include TargetSubtarget.td instead of Target.td, which also
checks that it works standalone, and drop the unneeded dummy Target.

The 14 llvm-tblgen RUN lines each parsed Target.td, which costs 1.29 G
instructions:u (Release+asserts); TargetSubtarget.td costs 0.005 G.

Co-authored-by: Claude Opus 5.5 <noreply at anthropic.com>
---
 llvm/test/TableGen/AMDGPUTargetDefErrors.td   | 30 +++++++------------
 .../AMDGPUTargetDefLDSAllocGranularity.td     |  3 +-
 .../AMDGPUTargetDefSubArchSpelling.td         |  3 +-
 3 files changed, 12 insertions(+), 24 deletions(-)

diff --git a/llvm/test/TableGen/AMDGPUTargetDefErrors.td b/llvm/test/TableGen/AMDGPUTargetDefErrors.td
index 9722c8cce9d44..1672a7e986f59 100644
--- a/llvm/test/TableGen/AMDGPUTargetDefErrors.td
+++ b/llvm/test/TableGen/AMDGPUTargetDefErrors.td
@@ -23,8 +23,7 @@
 // Verify the validation performed by the -gen-amdgpu-target-def backend.
 
 //--- bad-alias.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -37,8 +36,7 @@ def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0, 0]>;
 def : ProcessorAlias<"foo", "gfx-missing">;
 
 //--- dup-processor.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -51,8 +49,7 @@ def DupA : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0, 0]>;
 def DupB : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0, 0]>;
 
 //--- alias-shadows-processor.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -65,8 +62,7 @@ def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0, 0]>;
 def : ProcessorAlias<"gfx900", "gfx900">;
 
 //--- bad-isa-version.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -78,8 +74,7 @@ class AMDGPUGPUInfo<list<int> isa = []> {
 def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0]>;
 
 //--- oversized-major.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -91,8 +86,7 @@ class AMDGPUGPUInfo<list<int> isa = []> {
 def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[256, 0, 0]>;
 
 //--- oversized-minor.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -103,8 +97,7 @@ class AMDGPUGPUInfo<list<int> isa = []> {
 def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 256, 0]>;
 
 //--- oversized-stepping.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -116,8 +109,7 @@ class AMDGPUGPUInfo<list<int> isa = []> {
 def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0, 256]>;
 
 //--- negative-component.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -128,8 +120,7 @@ class AMDGPUGPUInfo<list<int> isa = []> {
 def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0, -1]>;
 
 //--- bad-stepping.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
@@ -141,8 +132,7 @@ class AMDGPUGPUInfo<list<int> isa = []> {
 def : ProcessorModel<"gfx900", NoSchedModel, []>, AMDGPUGPUInfo<[9, 0, 16]>;
 
 //--- generic-feature-superset.td
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];
diff --git a/llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td b/llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td
index b5e4337081a7d..1d3abe1db8ff9 100644
--- a/llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td
+++ b/llvm/test/TableGen/AMDGPUTargetDefLDSAllocGranularity.td
@@ -7,9 +7,8 @@
 // RUN:   | FileCheck %t/missing-encoding.td -DFILE=%t/missing-encoding.td --implicit-check-not="error:"
 
 //--- common.td
-include "llvm/Target/Target.td"
+include "llvm/Target/TargetSubtarget.td"
 include "AMDGPUFeatures.td"
-def MyTarget : Target;
 
 def AMDGPUFrontendVisibleFeatures {
   list<SubtargetFeature> Features = [FeatureLDSAllocGranularity512,
diff --git a/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td b/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
index 69cf05499845f..4c73cb6cff67c 100644
--- a/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
+++ b/llvm/test/TableGen/AMDGPUTargetDefSubArchSpelling.td
@@ -2,8 +2,7 @@
 
 // Verify the -gen-amdgpu-target-def backend's handling of SubArchSpelling.
 
-include "llvm/Target/Target.td"
-def MyTarget : Target;
+include "llvm/Target/TargetSubtarget.td"
 class AMDGPUGPUInfo<list<int> isa = []> {
   list<int> IsaVersion = isa;
   list<Processor> CoveredGPUs = [];