[llvm-branch-commits] [llvm] AMDGPU: Move GCN subtarget features to GCNFeatures.td (PR #230996)
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llvm-branch-commits at lists.llvm.org
Sun Oct 11 08:37:53 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
Move the GCN SubtargetFeature definitions, the FeatureISAVersion lists
and AMDGPUFrontendVisibleFeatures out of AMDGPU.td, so they can be used
without parsing the instruction, register and intrinsic definitions.
Co-authored-by: Claude Opus 5.5 <noreply@<!-- -->anthropic.com>
---
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---
Patch is 190.21 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/230996.diff
2 Files Affected:
- (modified) llvm/lib/Target/AMDGPU/AMDGPU.td (+1-2832)
- (added) llvm/lib/Target/AMDGPU/GCNFeatures.td (+2840)
``````````diff
diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td
index 73464a89544cc..71927e471680f 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPU.td
+++ b/llvm/lib/Target/AMDGPU/AMDGPU.td
@@ -21,2777 +21,7 @@ def p5 : PtrValueType<i32, 5>;
def p6 : PtrValueType<i32, 6>;
def p15 : PtrValueType<i32, 15>;
-//===-----------------------------------------------------------------------===//
-// AMDGPU Subtarget Feature (device properties)
-//===----------------------------------------------------------------------===//
-
-// Multiclass to define a SubtargetFeature along with optional predicates.
-// Parameters:
-// - FeatureString: The feature string used in the SubtargetFeature.
-// - Description: The description of the feature.
-// - GenPredicate: If 1 (default), generates a Has#NAME predicate.
-// - GenAssemblerPredicate: If 1 (default), the predicate includes AssemblerPredicate.
-// - Deps: List of dependent SubtargetFeatures (default empty).
-//
-// Usage:
-// defm MadMixInsts : AMDGPUSubtargetFeature<"mad-mix-insts", "description">;
-// This generates:
-// - FeatureMadMixInsts : SubtargetFeature<"mad-mix-insts", "HasMadMixInsts", "true", "description">
-// - HasMadMixInsts : Predicate<"Subtarget->hasMadMixInsts()">,
-// AssemblerPredicate<(any_of FeatureMadMixInsts)>
-//
-// With GenAssemblerPredicate=0:
-// defm Foo : AMDGPUSubtargetFeature<"foo", "desc", 1, 0>;
-// This generates:
-// - FeatureFoo : SubtargetFeature<...>
-// - HasFoo : Predicate<"Subtarget->hasFoo()"> (no AssemblerPredicate)
-//
-// With dependencies:
-// defm Bar : AMDGPUSubtargetFeature<"bar", "desc", 1, 1, [FeatureFoo]>;
-// This generates:
-// - FeatureBar : SubtargetFeature<"bar", "HasBar", "true", "desc", [FeatureFoo]>
-// - HasBar : Predicate + AssemblerPredicate
-multiclass AMDGPUSubtargetFeature<string FeatureString,
- string Description,
- bit GenPredicate = 1,
- bit GenAssemblerPredicate = 1,
- list<SubtargetFeature> Deps = [],
- InlineBehavior IB = InlineDefault> {
- def Feature#NAME : SubtargetFeature<FeatureString,
- "Has"#NAME,
- "true",
- Description,
- Deps,
- IB
- >;
-
- if GenPredicate then
- if GenAssemblerPredicate then
- def Has#NAME
- : Predicate<"Subtarget->has"#NAME#"()">,
- AssemblerPredicate<(any_of !cast<SubtargetFeature>("Feature"#NAME))>;
- else
- def Has#NAME : Predicate<"Subtarget->has"#NAME#"()">;
-}
-
-// Like AMDGPUSubtargetFeature, but a generic target only needs one covered GPU
-// to support the feature.
-multiclass AMDGPUGenericAnySubtargetFeature<string FeatureString,
- string Description,
- bit GenPredicate = 1,
- bit GenAssemblerPredicate = 1,
- list<SubtargetFeature> Deps = [],
- InlineBehavior IB = InlineDefault> {
- def Feature#NAME : AMDGPUGenericAnyFeature<FeatureString,
- "Has"#NAME,
- "true",
- Description,
- Deps,
- IB
- >;
-
- if GenPredicate then
- if GenAssemblerPredicate then
- def Has#NAME
- : Predicate<"Subtarget->has"#NAME#"()">,
- AssemblerPredicate<(any_of !cast<SubtargetFeature>("Feature"#NAME))>;
- else
- def Has#NAME : Predicate<"Subtarget->has"#NAME#"()">;
-}
-
-defm FastFMAF32 : AMDGPUSubtargetFeature<"fast-fmaf",
- "Assuming f32 fma is at least as fast as mul + add",
- /*GenPredicate=*/0, /*GenAssemblerPredicate=*/1, [], InlineIgnore
->;
-
-defm FastDenormalF32 : AMDGPUSubtargetFeature<"fast-denormal-f32",
- "Enabling denormals does not cause f32 instructions to run at f64 rates",
- /*GenPredicate=*/0
->;
-
-defm MIMG_R128 : AMDGPUSubtargetFeature<"mimg-r128",
- "Support 128-bit texture resources",
- /*GenPredicate=*/0
->;
-
-defm HalfRate64Ops : AMDGPUSubtargetFeature<"half-rate-64-ops",
- "Most fp64 instructions are half rate instead of quarter",
- /*GenPredicate=*/0, /*GenAssemblerPredicate=*/1, [], InlineIgnore
->;
-
-defm FullRate64Ops : AMDGPUSubtargetFeature<"full-rate-64-ops",
- "Most fp64 instructions are full rate",
- /*GenPredicate=*/0
->;
-
-defm FlatAddressSpace : AMDGPUSubtargetFeature<"flat-address-space",
- "Support flat address space"
->;
-
-defm FlatInstOffsets : AMDGPUSubtargetFeature<"flat-inst-offsets",
- "Flat instructions have immediate offset addressing mode"
->;
-
-defm FlatGlobalInsts : AMDGPUSubtargetFeature<"flat-global-insts",
- "Have global_* flat memory instructions",
- /*GenPredicate=*/1,
- /*GenAssemblerPredicate=*/1,
- [FeatureFlatAddressSpace]
->;
-
-defm FlatScratchInsts : AMDGPUSubtargetFeature<"flat-scratch-insts",
- "Have scratch_* flat memory instructions",
- /*GenPredicate=*/1,
- /*GenAssemblerPredicate=*/1,
- [FeatureFlatAddressSpace]
->;
-
-defm ScalarFlatScratchInsts : AMDGPUSubtargetFeature<"scalar-flat-scratch-insts",
- "Have s_scratch_* flat memory instructions"
->;
-
-def FeatureEnableFlatScratch : SubtargetFeature<"enable-flat-scratch",
- "EnableFlatScratch",
- "true",
- "Use scratch_* flat memory instructions to access scratch"
->;
-
-defm FlatGVSMode : AMDGPUSubtargetFeature<"flat-gvs-mode",
- "Have GVS addressing mode with flat_* instructions",
- /*GenPredicate=*/1,
- /*GenAssemblerPredicate=*/1,
- [FeatureFlatAddressSpace]
->;
-
-defm AddNoCarryInsts : AMDGPUSubtargetFeature<"add-no-carry-insts",
- "Have VALU add/sub instructions without carry out"
->;
-
-defm UnalignedBufferAccess : AMDGPUSubtargetFeature<"unaligned-buffer-access",
- "Hardware supports unaligned global loads and stores"
->;
-
-defm TrapHandler: AMDGPUSubtargetFeature<"trap-handler",
- "Trap handler support",
- /*GenPredicate=*/0, /*GenAssemblerPredicate=*/1, [], InlineIgnore
->;
-
-defm UnalignedScratchAccess : AMDGPUSubtargetFeature<"unaligned-scratch-access",
- "Support unaligned scratch loads and stores",
- /*GenPredicate=*/1, /*GenAssemblerPredicate=*/1, [], InlineIgnore
->;
-
-defm UnalignedDSAccess : AMDGPUSubtargetFeature<"unaligned-ds-access",
- "Hardware supports unaligned local and region loads and stores"
->;
-
-defm DX10ClampAndIEEEMode : AMDGPUSubtargetFeature<"dx10-clamp-and-ieee-mode",
- "Target has DX10_CLAMP and IEEE_MODE kernel descriptor bits"
->;
-
-defm ApertureRegs : AMDGPUSubtargetFeature<"aperture-regs",
- "Has Memory Aperture Base and Size Registers",
- /*GenPredicate=*/0
->;
-
-defm GetDoorbellID : AMDGPUSubtargetFeature<"get-doorbell-id",
- "Supports reading the doorbell ID through S_GETREG",
- /*GenPredicate=*/0, /*GenAssemblerPredicate=*/false, [], InlineIgnore
->;
-
-defm AGPRAlloc : AMDGPUSubtargetFeature<"agpr-alloc",
- "Supports allocation of AGPRs",
- /*GenPredicate=*/0, /*GenAssemblerPredicate=*/false, [], InlineIgnore
->;
-
-defm MadMixInsts : AMDGPUSubtargetFeature<"mad-mix-insts",
- "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
->;
-
-defm FmaMixInsts : AMDGPUSubtargetFeature<"fma-mix-insts",
- "Has v_fma_mix_f32, v_fma_mixlo_f16, v_fma_mixhi_f16 instructions"
->;
-
-defm FmaMixBF16Insts : AMDGPUSubtargetFeature<"fma-mix-bf16-insts",
- "Has v_fma_mix_f32_bf16, v_fma_mixlo_bf16, v_fma_mixhi_bf16 instructions"
->;
-
-defm FmaLegacy32Insts : AMDGPUSubtargetFeature<"fma-legacy32-insts",
- "Has single-precision legacy FMA instructions"
->;
-
-defm IEEEMinimumMaximumInsts : AMDGPUSubtargetFeature<"ieee-minimum-maximum-insts",
- "Has v_minimum/maximum_f16/f32/f64, v_minimummaximum/maximumminimum_f16/f32,"
- "v_pk_minmax/maxmin_num_f16, v_min/max_num_f16/f32/f64 and"
- "v_pk_min/max_num_f16 instructions"
->;
-
-defm SALUMinimumMaximumInsts : AMDGPUSubtargetFeature<"salu-minimum-maximum-insts",
- "Has s_minimum/maximum_f16/f32 instructions"
->;
-
-defm Minimum3Maximum3F32 : AMDGPUSubtargetFeature<"minimum3-maximum3-f32",
- "Has v_minimum3_f32 and v_maximum3_f32 instructions"
->;
-
-defm Minimum3Maximum3F16 : AMDGPUSubtargetFeature<"minimum3-maximum3-f16",
- "Has v_minimum3_f16 and v_maximum3_f16 instructions"
->;
-
-defm Min3Max3PKF16 : AMDGPUSubtargetFeature<"min3-max3-pkf16",
- "Has v_pk_min3_num_f16 and v_pk_max3_num_f16 instructions"
->;
-
-defm Minimum3Maximum3PKF16 : AMDGPUSubtargetFeature<"minimum3-maximum3-pkf16",
- "Has v_pk_minimum3_f16 and v_pk_maximum3_f16 instructions"
->;
-
-def FeatureSupportsXNACK : SubtargetFeature<"xnack-support",
- "SupportsXNACK",
- "true",
- "Hardware supports XNACK",
- [], InlineIgnore
->;
-
-defm XNACKOnOffModes : AMDGPUSubtargetFeature<"xnack-on-off-modes",
- "Target supports XNACK on/off modes",
- /*GenPredicate=*/1,
- /*GenAssemblerPredicate=*/0,
- [FeatureSupportsXNACK],
- InlineIgnore
->;
-
-// Whether the hardware supports WGP (work-group processor) execution
-// mode, as opposed to the per-kernel CU-mode selection
-// (FeatureCuMode).
-defm SupportsWGP : AMDGPUSubtargetFeature<"supports-wgp",
- "Hardware supports WGP mode",
- /*GenPredicate=*/false, /*GenAssemblerPredicate=*/false,
- [], InlineIgnore
->;
-
-def FeatureCuMode : SubtargetFeature<"cumode",
- "EnableCuMode",
- "true",
- "Enable CU wavefront execution mode"
->;
-
-def FeaturePreciseMemory
- : SubtargetFeature<"precise-memory", "EnablePreciseMemory",
- "true", "Enable precise memory mode">;
-
-defm SGPRInitBug : AMDGPUSubtargetFeature<"sgpr-init-bug",
- "VI SGPR initialization bug requiring a fixed SGPR allocation size",
- /*GenPredicate=*/1, /*GenAssemblerPredicate=*/1, [], InlineIgnore
->;
-
-defm UserSGPRInit16Bug : AMDGPUGenericAnySubtargetFeature<"user-sgpr-init16-bug",
- "Bug requiring at least 16 user+system SGPRs to be enabled",
- /*GenPredicate=*/0
->;
-
-defm LDSMisalignedBug : AMDGPUSubtargetFeature<"lds-misaligned-bug",
- "Some GFX10 bug with multi-dword LDS and flat access that is not naturally aligned in WGP mode",
- /*GenPredicate=*/0
->;
-
-// Set where a work-group can address only half of the physical LDS block:
-// gfx6 has 64 KiB physical and 32 KiB addressable, while gfx10/11/12 have
-// 128 KiB physical and 64 KiB addressable.
-defm HalfAddressablePhysicalLocalMemory : AMDGPUSubtargetFeature<"half-addressable-physical-local-memory",
- "A work-group can address only half of the physical LDS block",
- /*GenPredicate=*/0
->;
-
-defm MFMAInlineLiteralBug : AMDGPUSubtargetFeature<"mfma-inline-literal-bug",
- "MFMA cannot use inline literal as SrcC",
- /*GenPredicate=*/0
->;
-
-defm VcmpxPermlaneHazard : AMDGPUSubtargetFeature<"vcmpx-permlane-hazard",
- "TODO: describe me",
- /*GenPredicate=*/0
->;
-
-defm VMEMtoScalarWriteHazard : AMDGPUSubtargetFeature<"vmem-to-scalar-write-hazard",
- "VMEM instruction followed by scalar writing to EXEC mask, M0 or SGPR leads to incorrect execution.",
- /*GenPredicate=*/0
->;
-
-defm SMEMtoVectorWriteHazard : AMDGPUSubtargetFeature<"smem-to-vector-write-hazard",
- "s_load_dword followed by v_cmp page faults",
- /*GenPredicate=*/0
->;
-
-defm InstFwdPrefetchBug : AMDGPUSubtargetFeature<"inst-fwd-prefetch-bug",
- "S_INST_PREFETCH instruction causes shader to hang",
- /*GenPredicate=*/0
->;
-
-defm VmemPrefInsts : AMDGPUSubtargetFeature<"vmem-pref-insts",
- "Has flat_prefect_b8 and global_prefetch_b8 instructions"
->;
-
-defm SmemPrefetchInsts : AMDGPUSubtargetFeature<"smem-prefetch-insts",
- "Has s_prefetch_inst, s_prefetch_inst_pc_rel, s_prefetch_data and s_prefetch_data_pc_rel instructions"
->;
-
-defm SafeSmemPrefetch : AMDGPUSubtargetFeature<"safe-smem-prefetch",
- "SMEM prefetches do not fail on illegal address",
- /*GenPredicate=*/0
->;
-
-defm SafeCUPrefetch : AMDGPUSubtargetFeature<"safe-cu-prefetch",
- "VMEM CU scope prefetches do not fail on illegal address",
- /*GenPredicate=*/0
->;
-
-defm VcmpxExecWARHazard : AMDGPUSubtargetFeature<"vcmpx-exec-war-hazard",
- "V_CMPX WAR hazard on EXEC (V_CMPX issue ONLY)",
- /*GenPredicate=*/0
->;
-
-defm LdsBranchVmemWARHazard : AMDGPUSubtargetFeature<"lds-branch-vmem-war-hazard",
- "Switching between LDS and VMEM-tex not waiting VM_VSRC=0",
- /*GenPredicate=*/0
->;
-
-class FeatureMaxHardClauseLength<int size> : SubtargetFeature<
- "max-hard-clause-length-"#size,
- "MaxHardClauseLength",
- !cast<string>(size),
- "Maximum number of instructions in an explicit S_CLAUSE is "#size
->;
-
-/// Work around a hardware bug on some chips that can be triggered
-/// under certain circumstances when clauses are longer than 32 operations.
-def FeatureMaxHardClauseLength32 : FeatureMaxHardClauseLength<32>;
-/// While the S_CLAUSE instruction permits encoding clause lengths up to 64,
-/// hardware documentation for gfx10+ indicates that 63 is the maximum
-/// permitted clause length.
-def FeatureMaxHardClauseLength63 : FeatureMaxHardClauseLength<63>;
-
-defm NSAtoVMEMBug : AMDGPUSubtargetFeature<"nsa-to-vmem-bug",
- "MIMG-NSA followed by VMEM fail if EXEC_LO or EXEC_HI equals zero",
- /*GenPredicate=*/0
->;
-
-defm NSAClauseBug : AMDGPUSubtargetFeature<"nsa-clause-bug",
- "MIMG-NSA in a hard clause has unpredictable results on GFX10.1",
- /*GenPredicate=*/0
->;
-
-defm FlatSegmentOffsetBug : AMDGPUSubtargetFeature<"flat-segment-offset-bug",
- "GFX10 bug where inst_offset is ignored when flat instructions access global memory",
- /*GenPredicate=*/0
->;
-
-defm NegativeScratchOffsetBug : AMDGPUSubtargetFeature<"negative-scratch-offset-bug",
- "Negative immediate offsets in scratch instructions with an SGPR offset page fault on GFX9"
->;
-
-defm NegativeUnalignedScratchOffsetBug : AMDGPUSubtargetFeature<"negative-unaligned-scratch-offset-bug",
- "Scratch instructions with a VGPR offset and a negative immediate offset that"
- "is not a multiple of 4 read wrong memory on GFX10",
- /*GenPredicate=*/0
->;
-
-defm Offset3fBug : AMDGPUSubtargetFeature<"offset-3f-bug",
- "Branch offset of 3f hardware bug",
- /*GenPredicate=*/0
->;
-
-defm ImageStoreD16Bug : AMDGPUSubtargetFeature<"image-store-d16-bug",
- "Image Store D16 hardware bug",
- /*GenPredicate=*/0
->;
-
-defm ImageGather4D16Bug : AMDGPUSubtargetFeature<"image-gather4-d16-bug",
- "Image Gather4 D16 hardware bug",
- /*GenPredicate=*/0
->;
-
-defm MADIntraFwdBug : AMDGPUGenericAnySubtargetFeature<"mad-intra-fwd-bug",
- "MAD_U64/I64 intra instruction forwarding bug",
- /*GenPredicate=*/1,
- /*GenAssemblerPredicate=*/0
->;
-
-defm MSAALoadDstSelBug : AMDGPUGenericAnySubtargetFeature<"msaa-load-dst-sel-bug",
- "MSAA loads not honoring dst_sel bug",
- /*GenPredicate=*/0
->;
-
-defm PrivEnabledTrap2NopBug : AMDGPUGenericAnySubtargetFeature<"priv-enabled-trap2-nop-bug",
- "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug",
- /*GenPredicate=*/0
->;
-
-// A generic target may use an LDS bank count from one of its covered GPUs.
-class SubtargetFeatureLDSBankCount <int Value> : AMDGPUGenericAnyFeature <
- "ldsbankcount"#Value,
- "LDSBankCount",
- !cast<string>(Value),
- "The number of LDS banks per compute unit."
->;
-
-def FeatureLDSBankCount16 : SubtargetFeatureLDSBankCount<16>;
-def FeatureLDSBankCount32 : SubtargetFeatureLDSBankCount<32>;
-def FeatureLDSBankCount64 : SubtargetFeatureLDSBankCount<64>;
-
-class SubtargetFeatureMaxWavesPerEU <int Value> : SubtargetFeature <
- "max-waves-per-eu-"#Value,
- "MaxWavesPerEU",
- !cast<string>(Value),
- "Maximum number of waves an execution unit can hold."
->;
-
-def FeatureMaxWavesPerEU8 : SubtargetFeatureMaxWavesPerEU<8>;
-def FeatureMaxWavesPerEU10 : SubtargetFeatureMaxWavesPerEU<10>;
-def FeatureMaxWavesPerEU16 : SubtargetFeatureMaxWavesPerEU<16>;
-def FeatureMaxWavesPerEU20 : SubtargetFeatureMaxWavesPerEU<20>;
-
-class SubtargetFeatureInstCacheLineSize <int Value> : SubtargetFeature <
- "instcachelinesize"#Value,
- "InstCacheLineSize",
- !cast<string>(Value),
- "Instruction cache line size in bytes."
->;
-
-def FeatureInstCacheLineSize64 : SubtargetFeatureInstCacheLineSize<64>;
-def FeatureInstCacheLineSize128 : SubtargetFeatureInstCacheLineSize<128>;
-
-class SubtargetFeatureDataCacheLineSize <int Value> : SubtargetFeature <
- "datacachelinesize"#Value,
- "DataCacheLineSize",
- !cast<string>(Value),
- "Data (VMEM) cache line size in bytes."
->;
-
-def FeatureDataCacheLineSize128 : SubtargetFeatureDataCacheLineSize<128>;
-
-defm GCN3Encoding : AMDGPUSubtargetFeature<"gcn3-encoding",
- "Encoding format for VI",
- /*GenPredicate=*/0
->;
-
-defm CIInsts : AMDGPUSubtargetFeature<"ci-insts",
- "Additional instructions for CI+",
- /*GenPredicate=*/0
->;
-
-defm GFX8Insts : AMDGPUSubtargetFeature<"gfx8-insts",
- "Additional instructions for GFX8+",
- /*GenPredicate=*/0
->;
-
-defm GFX9Insts : AMDGPUSubtargetFeature<"gfx9-insts",
- "Additional instructions for GFX9+",
- /*GenPredicate=*/0
->;
-
-def FeatureRequiresAlignedVGPRs : SubtargetFeature<"vgpr-align2",
- "RequiresAlignVGPR",
- "true",
- "VGPR and AGPR tuple operands require even alignment"
->;
-
-defm GFX90AInsts : AMDGPUSubtargetFeature<"gfx90a-insts",
- "Additional instructions for GFX90A+",
- /*GenPredicate=*/0
->;
-
-defm TgSplitSupport : AMDGPUSubtargetFeature<"tgsplit-support",
- "Hardware support for threadgroup split execution mode"
->;
-
-defm GFX940Insts : AMDGPUSubtargetFeature<"gfx940-insts",
- "Additional instructions for GFX940+",
- /*GenPredicate=*/0
->;
-
-defm BufferInvInst : AMDGPUSubtargetFeature<"buffer-inv-inst",
- "Has buffer_inv instruction"
->;
-
-defm Permlane16Insts : AMDGPUSubtargetFeature<"permlane16-insts",
- "Has v_permlane16_b32/v_permlanex16_b32 instructions"
->;
-
-defm Permlane16Swap : AMDGPUSubtargetFeature<"permlane16-swap",
- "Has v_permlane16_swap_b32 instructions"
->;
-
-defm Permlane32Swap : AMDGPUSubtargetFeature<"permlane32-swap",
- "Has v_permlane32_swap_b32 instructions"
->;
-
-defm FP8ConversionScaleInsts : AMDGPUSubtargetFeature<"fp8-cvt-scale-insts",
- "Has fp8 conversion scale instructions"
->;
-
-defm BF8ConversionScaleInsts : AMDGPUSubtargetFeature<"bf8-cvt-scale-insts",
- "Has bf8 conversion scale instructions"
->;
-
-defm FP4ConversionScaleInsts : AMDGPUSubtargetFeature<"fp4-cvt-scale-insts",
- "Has fp4 conversion scale instructions"
->;
-
-defm FP6BF6ConversionScaleInsts : AMDGPUSubtargetFeature<"fp6bf6-cvt-scale-insts",
- "Has fp6 and bf6 conversion scale instructions"
->;
-
-defm F16BF16ToFP6BF6ConversionScaleInsts : AMDGPUSubtargetFeature<"f16bf16-to-fp6bf6-cvt-scale-insts",
- "Has f16bf16 to fp6bf6 conversion scale instructions"
->;
-
-defm F32ToFP6BF6ConversionScaleInsts : AMDGPUSubtargetFeature<"f32-to-fp6bf6-cvt-scale-insts",
- "Has f32 to fp6bf6 conversion scale instructions"
->;
-
-defm F32ToF16BF16ConversionSRInsts : AMDGPUSubtargetFeature<"f32-to-f16bf16-cvt-sr-insts",
- "Has f32 to f16bf16 conversion scale instructions"
->;
-
-defm FP6BF6ToF16BF16F32ConversionScaleInsts : AMDGPUSubtargetFeature<"fp6bf6-to-f16bf16f32-cvt-scale-insts",
- "Has fp6bf6 to f16bf16f32 conversion scale instructions"
->;
-
-defm Block16ConversionScaleInsts : AMDGPUSubtargetFeature<"block16-cvt-scale-insts",
- "Has block16 conversion scale instructions"
->;
-
-defm AshrPkInsts : AMDGPUSubtargetFeature<"ashr-pk-insts",
- "Has Arithmetic Shift Pack instructions"
->;
-
-defm ExclusiveScanInsts : AMDGPUSubtargetFeature<"exclusive-scan-insts",
- "Has exclusive scan instructions"
->;
-
-defm CvtPkF16F32Inst : AMDGPUSubtargetFeature<"cvt-pk-f16-f32-inst",
- "Has cvt_pk_f16_f32 instruction"
->;
-
-defm CvtSrPkBF16F32Inst : AMDGPUSubtargetFeature<"cvt-sr-pk-bf16-f32-inst",
- "Has cvt_sr_pk_bf16_f32 instruction"
->;
-
-defm McastLoadInsts : AMDGPUSubtargetFeature<"mcast-load-insts",
- "Has multicast load instructions"
->;
-
-defm AsyncLoadToLDSInsts : AMDGPUSubtargetFeature<"async-load-to-lds-insts",
- "Has global async load to LDS instructions"
->;
-
-defm AsyncStoreFromLDSInsts : AMDGPUSubtargetFeature<"async-store-from-lds-insts",
- "Has global async store from LDS instructions"
->;
-
-defm SWakeupImm : AMDGPUSubtargetFeature<"s-wakeup-imm",
- "s_wakeup takes an immediate operand"
->;
-
-defm SBarrierLeaveImm : AMDGPUSubtargetFeature<"s-barrier-leave-imm",
- "s_barrier_leave takes an immediate operand"
->;
-
-defm MTBUFInsts : AMDGPUSubtargetFeature<"mtbuf-insts",
- "Has memory typed buffer instructions."
->;
-
-defm FormattedMUBUFInsts : AMDGPUSubtargetFeature<"formatted-mubuf-insts...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/230996
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