[llvm-branch-commits] [llvm] [AArch64][llvm] Improve diagnostics for invalid operands (PR #230436)
via llvm-branch-commits
llvm-branch-commits at lists.llvm.org
Fri Oct 9 03:14:06 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-aarch64
Author: Jonathan Thackray (jthackray)
<details>
<summary>Changes</summary>
Return `DiagnosticPredicate` from `isSImm()`, `isImmInRange()`, and
`isUImm12Offset()` so invalid operand types do not produce misleading
immediate range errors, while out-of-range constants retain their
range diagnostics.
Keep the load/store fallback predicate boolean and remove the
CFLT-specific diagnostic workaround. Update affected diagnostic
tests and add prefetch and CFLT regression testcases.
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---
Patch is 25.48 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/230436.diff
27 Files Affected:
- (modified) llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp (+14-15)
- (modified) llvm/test/MC/AArch64/CMPBR/cmpbr_aliases-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/addspl-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/addsvl-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/ld1b-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/ld1d-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/ld1h-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/ld1q-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/ld1w-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/st1b-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/st1d-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/st1h-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/st1q-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME/st1w-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SME2p1/zero-diagnostics.s (+3-3)
- (modified) llvm/test/MC/AArch64/SVE/addpl-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SVE/addvl-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/SVE/index-diagnostics.s (+2-2)
- (modified) llvm/test/MC/AArch64/SVE/rdvl-diagnostics.s (+1-1)
- (modified) llvm/test/MC/AArch64/arm64-diags.s (+1-1)
- (modified) llvm/test/MC/AArch64/arm64-spsel-sysreg.s (+1-1)
- (modified) llvm/test/MC/AArch64/armv8.1a-pan.s (+1-1)
- (modified) llvm/test/MC/AArch64/armv8.5a-mte-error.s (+2-2)
- (modified) llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s (+9)
- (modified) llvm/test/MC/AArch64/basic-a64-diagnostics.s (+14-14)
- (modified) llvm/test/MC/AArch64/neon-diagnostics.s (+5-5)
``````````diff
diff --git a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index 79e39424097e07..6639f2f6cf1758 100644
--- a/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -776,8 +776,8 @@ class AArch64Operand : public MCParsedAsmOperand {
return (Val >= 0 && Val < 64);
}
- template <int Width> bool isSImm() const {
- return bool(isSImmScaled<Width, 1>());
+ template <int Width> DiagnosticPredicate isSImm() const {
+ return isSImmScaled<Width, 1>();
}
template <int Bits, int Scale> DiagnosticPredicate isSImmScaled() const {
@@ -882,27 +882,31 @@ class AArch64Operand : public MCParsedAsmOperand {
return false;
}
- template <int Scale> bool isUImm12Offset() const {
+ template <int Scale> DiagnosticPredicate isUImm12Offset() const {
if (!isImm())
- return false;
+ return DiagnosticPredicate::NoMatch;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
- return isSymbolicUImm12Offset(getImm());
+ return DiagnosticPredicate(isSymbolicUImm12Offset(getImm()));
int64_t Val = MCE->getValue();
- return (Val % Scale) == 0 && Val >= 0 && (Val / Scale) < 0x1000;
+ if ((Val % Scale) == 0 && Val >= 0 && (Val / Scale) < 0x1000)
+ return DiagnosticPredicate::Match;
+ return DiagnosticPredicate::NearMatch;
}
template <int N, int M>
- bool isImmInRange() const {
+ DiagnosticPredicate isImmInRange() const {
if (!isImm())
- return false;
+ return DiagnosticPredicate::NoMatch;
const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(getImm());
if (!MCE)
- return false;
+ return DiagnosticPredicate::NoMatch;
int64_t Val = MCE->getValue();
- return (Val >= N && Val <= M);
+ if (Val >= N && Val <= M)
+ return DiagnosticPredicate::Match;
+ return DiagnosticPredicate::NearMatch;
}
bool isHinteUImm16() const {
@@ -7075,11 +7079,6 @@ bool AArch64AsmParser::matchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
case Match_MRS: {
if (ErrorInfo >= Operands.size())
return Error(IDLoc, "too few operands for instruction", SMRange(IDLoc, (*Operands.back()).getEndLoc()));
- // CFLT has both register and immediate forms. The matcher may select an
- // immediate-form failure for an invalid register operand.
- if (Tok.starts_with("cflt") &&
- static_cast<AArch64Operand &>(*Operands[ErrorInfo]).isScalarReg())
- MatchResult = Match_InvalidOperand;
// Any time we get here, there's nothing fancy to do. Just get the
// operand SMLoc and display the diagnostic.
SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
diff --git a/llvm/test/MC/AArch64/CMPBR/cmpbr_aliases-diagnostics.s b/llvm/test/MC/AArch64/CMPBR/cmpbr_aliases-diagnostics.s
index c4135d0fadfc09..c27be7fb9be860 100644
--- a/llvm/test/MC/AArch64/CMPBR/cmpbr_aliases-diagnostics.s
+++ b/llvm/test/MC/AArch64/CMPBR/cmpbr_aliases-diagnostics.s
@@ -22,4 +22,4 @@ L:
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [-1, 62]
cbls x3, w5, L
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [-1, 62]
\ No newline at end of file
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
diff --git a/llvm/test/MC/AArch64/SME/addspl-diagnostics.s b/llvm/test/MC/AArch64/SME/addspl-diagnostics.s
index 02b8f6ca765aa7..96e926e327b36a 100644
--- a/llvm/test/MC/AArch64/SME/addspl-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/addspl-diagnostics.s
@@ -8,6 +8,6 @@ addspl x19, x14, #32
// addspl requires an immediate, not a register.
addspl x19, x14, x15
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addspl x19, x14, x15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/addsvl-diagnostics.s b/llvm/test/MC/AArch64/SME/addsvl-diagnostics.s
index d420894bc174c1..0a3867952fc25a 100644
--- a/llvm/test/MC/AArch64/SME/addsvl-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/addsvl-diagnostics.s
@@ -8,6 +8,6 @@ addsvl x3, x5, #32
// addsvl requires an immediate, not a register.
addsvl x3, x5, x6
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addsvl x3, x5, x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
index 242cd1df739b3b..57bc9f46ee9173 100644
--- a/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1b-diagnostics.s
@@ -35,7 +35,7 @@ ld1b {za0h.b[w16, 0]}, p0/z, [x0]
// Invalid vector select offset (expected: 0-15)
ld1b {za0h.b[w12]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld1b {za0h.b[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
index ad3d85aa3a0453..b68e2d564dc8a9 100644
--- a/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1d-diagnostics.s
@@ -35,7 +35,7 @@ ld1d {za0h.d[w16, 0]}, p0/z, [x0]
// Invalid vector select offset (expected: 0-1)
ld1d {za0h.d[w12]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld1d {za0h.d[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
index fd8849c3cb3013..2c068ad1856b78 100644
--- a/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1h-diagnostics.s
@@ -35,7 +35,7 @@ ld1h {za0h.h[w16, 0]}, p0/z, [x0]
// Invalid vector select offset (expected: 0-7)
ld1h {za0h.h[w12]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld1h {za0h.h[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
index 654d7b10383757..c4944421c4051d 100644
--- a/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1q-diagnostics.s
@@ -35,7 +35,7 @@ ld1q {za0h.q[w16, 0]}, p0/z, [x0]
// Invalid vector select offset (expected: 0)
ld1q {za0h.q[w12]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld1q {za0h.q[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s b/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
index e382e94323900d..a3e7e0180acba0 100644
--- a/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/ld1w-diagnostics.s
@@ -35,7 +35,7 @@ ld1w {za0h.s[w16, 0]}, p0/z, [x0]
// Invalid vector select offset (expected: 0-3)
ld1w {za0h.s[w12]}, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: ld1w {za0h.s[w12]}, p0/z, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s b/llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s
index 0ea7d9beaef3bc..8e5e85b089102b 100644
--- a/llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/rdsvl-diagnostics.s
@@ -8,6 +8,6 @@ rdsvl x9, #32
// rdsvl requires an immediate, not a register.
rdsvl x9, x10
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: rdsvl x9, x10
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1b-diagnostics.s b/llvm/test/MC/AArch64/SME/st1b-diagnostics.s
index 05ac2301041ff3..da367cbc8f67f3 100644
--- a/llvm/test/MC/AArch64/SME/st1b-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1b-diagnostics.s
@@ -35,7 +35,7 @@ st1b {za0h.b[w16, 0]}, p0, [x0]
// Invalid vector select offset (expected: 0-15)
st1b {za0h.b[w12]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 15].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st1b {za0h.b[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1d-diagnostics.s b/llvm/test/MC/AArch64/SME/st1d-diagnostics.s
index ad6a5ab6f59cc1..16f3a361e9d32f 100644
--- a/llvm/test/MC/AArch64/SME/st1d-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1d-diagnostics.s
@@ -35,7 +35,7 @@ st1d {za0h.d[w16, 0]}, p0, [x0]
// Invalid vector select offset (expected: 0-1)
st1d {za0h.d[w12]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 1].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st1d {za0h.d[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1h-diagnostics.s b/llvm/test/MC/AArch64/SME/st1h-diagnostics.s
index 8493729570bce6..0c2a5a66e6876f 100644
--- a/llvm/test/MC/AArch64/SME/st1h-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1h-diagnostics.s
@@ -35,7 +35,7 @@ st1h {za0h.h[w16, 0]}, p0, [x0]
// Invalid vector select offset (expected: 0-7)
st1h {za0h.h[w12]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st1h {za0h.h[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1q-diagnostics.s b/llvm/test/MC/AArch64/SME/st1q-diagnostics.s
index dae09a9bcc557a..13b942acf79e27 100644
--- a/llvm/test/MC/AArch64/SME/st1q-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1q-diagnostics.s
@@ -35,7 +35,7 @@ st1q {za0h.q[w16, 0]}, p0, [x0]
// Invalid vector select offset (expected: 0)
st1q {za0h.q[w12]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be 0.
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st1q {za0h.q[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME/st1w-diagnostics.s b/llvm/test/MC/AArch64/SME/st1w-diagnostics.s
index 4edca02855504d..1cd4315db5900b 100644
--- a/llvm/test/MC/AArch64/SME/st1w-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME/st1w-diagnostics.s
@@ -35,7 +35,7 @@ st1w {za0h.s[w16, 0]}, p0, [x0]
// Invalid vector select offset (expected: 0-3)
st1w {za0h.s[w12]}, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 3].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: st1w {za0h.s[w12]}, p0, [x0]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SME2p1/zero-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/zero-diagnostics.s
index ee6010af993955..66cdbbe42442d7 100644
--- a/llvm/test/MC/AArch64/SME2p1/zero-diagnostics.s
+++ b/llvm/test/MC/AArch64/SME2p1/zero-diagnostics.s
@@ -24,17 +24,17 @@ zero za.d[w11, 5:8, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
zero za.d[w11, 0:4, vgx4]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zero za.d[w11, 0:4, vgx4]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
zero za.d[w11, 0:4, vgx2]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zero za.d[w11, 0:4, vgx2]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
zero za.d[w11, 11:15]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: immediate must be an integer in range [0, 7].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: zero za.d[w11, 11:15]
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/addpl-diagnostics.s b/llvm/test/MC/AArch64/SVE/addpl-diagnostics.s
index eb5a80aa4ea9ff..266d58abdca33e 100644
--- a/llvm/test/MC/AArch64/SVE/addpl-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/addpl-diagnostics.s
@@ -8,6 +8,6 @@ addpl x19, x14, #32
// addpl requires an immediate, not a register.
addpl x19, x14, x15
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addpl x19, x14, x15
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/addvl-diagnostics.s b/llvm/test/MC/AArch64/SVE/addvl-diagnostics.s
index 6c04176d0bd1b9..1dc540f501e43b 100644
--- a/llvm/test/MC/AArch64/SVE/addvl-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/addvl-diagnostics.s
@@ -8,6 +8,6 @@ addvl x3, x5, #32
// addvl requires an immediate, not a register.
addvl x3, x5, x6
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addvl x3, x5, x6
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/index-diagnostics.s b/llvm/test/MC/AArch64/SVE/index-diagnostics.s
index 3b2a4aa656fd3b..2600089cd01c0e 100644
--- a/llvm/test/MC/AArch64/SVE/index-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/index-diagnostics.s
@@ -48,12 +48,12 @@ index z17.d, x9, #16
// Invalid register
index z17.s, x9, w7
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: index z17.s, x9, w7
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
index z17.d, w9, w7
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-16, 15].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: index z17.d, w9, w7
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE/rdvl-diagnostics.s b/llvm/test/MC/AArch64/SVE/rdvl-diagnostics.s
index 0af37a60e38b0a..e78b5f1292bd4a 100644
--- a/llvm/test/MC/AArch64/SVE/rdvl-diagnostics.s
+++ b/llvm/test/MC/AArch64/SVE/rdvl-diagnostics.s
@@ -8,6 +8,6 @@ rdvl x9, #32
// rdvl requires an immediate, not a register.
rdvl x9, x10
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: index must be an integer in range [-32, 31].
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: rdvl x9, x10
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/arm64-diags.s b/llvm/test/MC/AArch64/arm64-diags.s
index 41b98e79537e39..0581703b2f9bfd 100644
--- a/llvm/test/MC/AArch64/arm64-diags.s
+++ b/llvm/test/MC/AArch64/arm64-diags.s
@@ -121,7 +121,7 @@ ldr q1, [x3, w3, sxtw #1]
; CHECK-ERRORS: error: expected 'uxtw' or 'sxtw' with optional shift of #0 or #3
; CHECK-ERRORS: str d1, [x3, w3, sxtx #3]
; CHECK-ERRORS: ^
-; CHECK-ERRORS: error: index must be an integer in range [-256, 255].
+; CHECK-ERRORS: error: invalid operand for instruction
; CHECK-ERRORS: ldr s1, [x3, d3, sxtx #2]
; CHECK-ERRORS: ^
diff --git a/llvm/test/MC/AArch64/arm64-spsel-sysreg.s b/llvm/test/MC/AArch64/arm64-spsel-sysreg.s
index f1c675f6edf496..02ff33bbc934a8 100644
--- a/llvm/test/MC/AArch64/arm64-spsel-sysreg.s
+++ b/llvm/test/MC/AArch64/arm64-spsel-sysreg.s
@@ -19,6 +19,6 @@ mrs x0, ESR_EL1
msr DAIFSet, x0
msr ESR_EL1, #0
mrs x0, DAIFSet
-// CHECK-ERRORS: error: immediate must be an integer in range [0, 15]
+// CHECK-ERRORS: error: invalid operand for instruction
// CHECK-ERRORS: error: invalid operand for instruction
// CHECK-ERRORS: error: expected readable system register
diff --git a/llvm/test/MC/AArch64/armv8.1a-pan.s b/llvm/test/MC/AArch64/armv8.1a-pan.s
index d39542c30abe5d..129ee8eba85475 100644
--- a/llvm/test/MC/AArch64/armv8.1a-pan.s
+++ b/llvm/test/MC/AArch64/armv8.1a-pan.s
@@ -24,7 +24,7 @@
// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
// CHECK-ERROR: msr pan, #16
// CHECK-ERROR: ^
-// CHECK-ERROR: error: immediate must be an integer in range [0, 15].
+// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR: msr pan, w0
// CHECK-ERROR: ^
// CHECK-ERROR: error: invalid operand for instruction
diff --git a/llvm/test/MC/AArch64/armv8.5a-mte-error.s b/llvm/test/MC/AArch64/armv8.5a-mte-error.s
index 07b4a19660d489..b5d5ebdeb10fa7 100644
--- a/llvm/test/MC/AArch64/armv8.5a-mte-error.s
+++ b/llvm/test/MC/AArch64/armv8.5a-mte-error.s
@@ -107,7 +107,7 @@ subg x0, x1, #16, #2, #99
// CHECK-NEXT: addg x0, #0, #0, #0
// CHECK: invalid operand for instruction
// CHECK-NEXT: addg x0, x1, x0, #0
-// CHECK: immediate must be an integer in range [0, 15]
+// CHECK: invalid operand for instruction
// CHECK-NEXT: addg x0, x1, #0, x0
// CHECK: invalid operand for instruction
// CHECK-NEXT: addg x0, x1, #16, #2, #99
@@ -142,7 +142,7 @@ subg x0, x1, #16, #2, #99
// CHECK-NEXT: subg x0, #0, #0, #0
// CHECK: invalid operand for instruction
// CHECK-NEXT: subg x0, x1, x0, #0
-// CHECK: immediate must be an integer in range [0, 15]
+// CHECK: invalid operand for instruction
// CHECK-NEXT: subg x0, x1, #0, x0
// CHECK: invalid operand for instruction
// CHECK-NEXT: subg x0, x1, #16, #2, #99
diff --git a/llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s b/llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s
index b9c6683a99d226..d27cc5d41ce03d 100644
--- a/llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s
+++ b/llvm/test/MC/AArch64/armv9.8a-cflt-diagnostics.s
@@ -70,6 +70,15 @@ cflteq #0, w0, wzr
cflteq #0, x0, xzr
// CHECK: [[@LINE-1]]:16: error: invalid operand for instruction
+cflteq #0, w0, label
+// CHECK: [[@LINE-1]]:16: error: invalid operand for instruction
+
+cflthi #0, w0, wzr
+// CHECK: [[@LINE-1]]:16: error: invalid operand for instruction
+
+cflths #0, x0, xzr
+// CHECK: [[@LINE-1]]:16: error: invalid operand for instruction
+
cfltz #0, wsp
// CHECK: [[@LINE-1]]:11: error: invalid operand for instruction
diff --git a/llvm/test/MC/AArch64/basic-a64-diagnostics.s b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
index 823a37dc54f2c9..7fd65f9b38d367 100644
--- a/llvm/test/MC/AArch64/basic-a64-diagnostics.s
+++ b/llvm/test/MC/AArch64/basic-a64-diagnostics.s
@@ -1274,7 +1274,7 @@ cbz w1, lsl
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ccmp wsp, w4, #2, ne
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31]
+// CHECK-ERROR-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ccmp w3, wsp, #0, ge
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15]
@@ -1291,7 +1291,7 @@ cbz w1, lsl
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ccmp sp, x4, #2, ne
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31]
+// CHECK-ERROR-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ccmp x25, sp, #15, hs
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 15]
@@ -1308,7 +1308,7 @@ cbz w1, lsl
// CHECK-ERROR: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ccmn wsp, w4, #2, ne
// CHECK-ERROR-NEXT: ^
-// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range [0, 31]
+// CHECK-ERROR-NEXT: error: invalid operand for instruction
// CHECK-ERROR-NEXT: ccmn w25, wsp, #15, hs
// CHECK-ERROR-NEXT: ^
// CHECK-ERROR-NEXT: error: {{expected|immediate must be an}} integer in range ...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/230436
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